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Changed more code to dict<> and pool<>
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parent
f3a97b75c7
commit
137f35373f
5 changed files with 17 additions and 17 deletions
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@ -231,7 +231,7 @@ namespace AST
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// for expressions the resulting signal vector is returned
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// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
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RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);
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RTLIL::SigSpec genWidthRTLIL(int width, const std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
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RTLIL::SigSpec genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
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// compare AST nodes
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bool operator==(const AstNode &other) const;
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@ -293,7 +293,7 @@ namespace AST_INTERNAL
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extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
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extern AST::AstNode *current_ast, *current_ast_mod;
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extern std::map<std::string, AST::AstNode*> current_scope;
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extern const std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
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extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
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extern RTLIL::SigSpec ignoreThisSignalsInInitial;
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extern AST::AstNode *current_top_block, *current_block, *current_block_child;
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extern AST::AstModule *current_module;
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