From 137f35373f4ef0d1ddf212187e537e48d077b1f4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 28 Dec 2014 19:24:24 +0100
Subject: [PATCH] Changed more code to dict<> and pool<>
---
frontends/ast/ast.cc | 2 +-
frontends/ast/ast.h | 4 ++--
frontends/ast/genrtlil.cc | 6 +++---
kernel/celltypes.h | 12 ++++++------
kernel/utils.h | 10 +++++-----
5 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 0f79352f7..8ef60079b 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -56,7 +56,7 @@ namespace AST_INTERNAL {
bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope;
- const std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
+ const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr = NULL;
RTLIL::SigSpec ignoreThisSignalsInInitial;
AstNode *current_top_block, *current_block, *current_block_child;
AstModule *current_module;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 27cf0ef3d..1a7ac576b 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -231,7 +231,7 @@ namespace AST
// for expressions the resulting signal vector is returned
// all generated cell instances, etc. are written to the RTLIL::Module pointed to by AST_INTERNAL::current_module
RTLIL::SigSpec genRTLIL(int width_hint = -1, bool sign_hint = false);
- RTLIL::SigSpec genWidthRTLIL(int width, const std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
+ RTLIL::SigSpec genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr = NULL);
// compare AST nodes
bool operator==(const AstNode &other) const;
@@ -293,7 +293,7 @@ namespace AST_INTERNAL
extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
extern AST::AstNode *current_ast, *current_ast_mod;
extern std::map<std::string, AST::AstNode*> current_scope;
- extern const std::map<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
+ extern const dict<RTLIL::SigBit, RTLIL::SigBit> *genRTLIL_subst_ptr;
extern RTLIL::SigSpec ignoreThisSignalsInInitial;
extern AST::AstNode *current_top_block, *current_block, *current_block_child;
extern AST::AstModule *current_module;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 238da2634..a86d08d56 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -254,7 +254,7 @@ struct AST_INTERNAL::ProcessGenerator
// create initial assignments for the temporary signals
if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
- subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
+ subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
} else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
}
@@ -1391,9 +1391,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
// signals must be substituted before beeing used as input values (used by ProcessGenerator)
// note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
-RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const std::map<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
+RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
{
- const std::map<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
+ const dict<RTLIL::SigBit, RTLIL::SigBit> *backup_subst_ptr = genRTLIL_subst_ptr;
if (new_subst_ptr)
genRTLIL_subst_ptr = new_subst_ptr;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 5ba4dd88b..32e144194 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -27,13 +27,13 @@ YOSYS_NAMESPACE_BEGIN
struct CellType
{
RTLIL::IdString type;
- std::set<RTLIL::IdString> inputs, outputs;
+ pool<RTLIL::IdString> inputs, outputs;
bool is_evaluable;
};
struct CellTypes
{
- std::map<RTLIL::IdString, CellType> cell_types;
+ dict<RTLIL::IdString, CellType> cell_types;
CellTypes()
{
@@ -55,7 +55,7 @@ struct CellTypes
setup_stdcells_mem();
}
- void setup_type(RTLIL::IdString type, const std::set<RTLIL::IdString> &inputs, const std::set<RTLIL::IdString> &outputs, bool is_evaluable = false)
+ void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
{
CellType ct = {type, inputs, outputs, is_evaluable};
cell_types[ct.type] = ct;
@@ -63,7 +63,7 @@ struct CellTypes
void setup_module(RTLIL::Module *module)
{
- std::set<RTLIL::IdString> inputs, outputs;
+ pool<RTLIL::IdString> inputs, outputs;
for (RTLIL::IdString wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
@@ -109,7 +109,7 @@ struct CellTypes
setup_type("$alu", {"\\A", "\\B", "\\CI", "\\BI"}, {"\\X", "\\Y", "\\CO"}, true);
setup_type("$fa", {"\\A", "\\B", "\\C"}, {"\\X", "\\Y"}, true);
- setup_type("$assert", {"\\A", "\\EN"}, std::set<RTLIL::IdString>(), true);
+ setup_type("$assert", {"\\A", "\\EN"}, pool<RTLIL::IdString>(), true);
}
void setup_internals_mem()
@@ -123,7 +123,7 @@ struct CellTypes
setup_type("$dlatchsr", {"\\EN", "\\SET", "\\CLR", "\\D"}, {"\\Q"});
setup_type("$memrd", {"\\CLK", "\\ADDR"}, {"\\DATA"});
- setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, std::set<RTLIL::IdString>());
+ setup_type("$memwr", {"\\CLK", "\\EN", "\\ADDR", "\\DATA"}, pool<RTLIL::IdString>());
setup_type("$mem", {"\\RD_CLK", "\\RD_ADDR", "\\WR_CLK", "\\WR_EN", "\\WR_ADDR", "\\WR_DATA"}, {"\\RD_DATA"});
setup_type("$fsm", {"\\CLK", "\\ARST", "\\CTRL_IN"}, {"\\CTRL_OUT"});
diff --git a/kernel/utils.h b/kernel/utils.h
index 479effdc9..2ec6182ea 100644
--- a/kernel/utils.h
+++ b/kernel/utils.h
@@ -31,17 +31,17 @@ YOSYS_NAMESPACE_BEGIN
// A map-like container, but you can save and restore the state
// ------------------------------------------------
-template<typename Key, typename T, typename Compare = std::less<Key>>
+template<typename Key, typename T, typename OPS = hash_ops<Key>>
struct stackmap
{
private:
- std::vector<std::map<Key, T*, Compare>> backup_state;
- std::map<Key, T, Compare> current_state;
+ std::vector<dict<Key, T*, OPS>> backup_state;
+ dict<Key, T, OPS> current_state;
static T empty_tuple;
public:
stackmap() { }
- stackmap(const std::map<Key, T, Compare> &other) : current_state(other) { }
+ stackmap(const dict<Key, T, OPS> &other) : current_state(other) { }
template<typename Other>
void operator=(const Other &other)
@@ -94,7 +94,7 @@ public:
current_state.erase(k);
}
- const std::map<Key, T, Compare> &stdmap()
+ const dict<Key, T, OPS> &stdmap()
{
return current_state;
}