mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Improve comments for xilinx_dsp_CREG

Browse source
This commit is contained in:
Eddie Hung 2019-10-04 22:24:15 -07:00
parent 14e4aeece6
commit 12fd2ec4f0
1 changed files with 7 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

13
passes/pmgen/xilinx_dsp_CREG.pmg
View file

@ -7,11 +7,12 @@
// (attached to at most two $mux cells that implement clock-enable or
// reset functionality, using a subpattern discussed below)
// Notes:
// - Separating out CREG packing is necessary since there is no guarantee
// that the cell ordering corresponds to the "expected" case (i.e. the order
// in which they appear in the source) thus the possiblity existed that a
// register got packed as a CREG into a downstream DSP that should have
// otherwise been a PREG of an upstream DSP that had not been visited yet
// - Running CREG packing after xilinx_dsp_pack is necessary since there is no
// guarantee that the cell ordering corresponds to the "expected" case (i.e.
// the order in which they appear in the source) thus the possiblity existed
// that a register got packed as a CREG into a downstream DSP that should
// have otherwise been a PREG of an upstream DSP that had not been visited
// yet
// - The reason this is separated out from the xilinx_dsp.pmg file is
// for efficiency --- each *.pmg file creates a class of the same basename,
// which when constructed, creates a custom database tailored to the
@ -28,7 +29,7 @@ state <SigSpec> sigC sigP
state <bool> ffCcepol ffCrstpol
state <Cell*> ffC ffCcemux ffCrstmux
// subpattern
// Variables used for subpatterns
state <SigSpec> argQ argD
state <bool> ffcepol ffrstpol
state <int> ffoffset