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	Improve comments for xilinx_dsp_CREG
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					 1 changed files with 7 additions and 6 deletions
				
			
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					@ -7,11 +7,12 @@
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//       (attached to at most two $mux cells that implement clock-enable or
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					//       (attached to at most two $mux cells that implement clock-enable or
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//        reset functionality, using a subpattern discussed below)
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					//        reset functionality, using a subpattern discussed below)
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// Notes:
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					// Notes:
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//   - Separating out CREG packing is necessary since there is no guarantee
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					//   - Running CREG packing after xilinx_dsp_pack is necessary since there is no
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//     that the cell ordering corresponds to the "expected" case (i.e. the order
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					//     guarantee that the cell ordering corresponds to the "expected" case (i.e.
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//     in which they appear in the source) thus the possiblity existed that a
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					//     the order in which they appear in the source) thus the possiblity existed
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//     register got packed as a CREG into a downstream DSP that should have
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					//     that a register got packed as a CREG into a downstream DSP that should
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//     otherwise been a PREG of an upstream DSP that had not been visited yet
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					//     have otherwise been a PREG of an upstream DSP that had not been visited
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					//     yet
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//   - The reason this is separated out from the xilinx_dsp.pmg file is
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					//   - The reason this is separated out from the xilinx_dsp.pmg file is
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//     for efficiency --- each *.pmg file creates a class of the same basename,
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					//     for efficiency --- each *.pmg file creates a class of the same basename,
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//     which when constructed, creates a custom database tailored to the
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					//     which when constructed, creates a custom database tailored to the
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					@ -28,7 +29,7 @@ state <SigSpec> sigC sigP
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state <bool> ffCcepol ffCrstpol
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					state <bool> ffCcepol ffCrstpol
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state <Cell*> ffC ffCcemux ffCrstmux
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					state <Cell*> ffC ffCcemux ffCrstmux
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// subpattern
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					// Variables used for subpatterns
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state <SigSpec> argQ argD
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					state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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					state <bool> ffcepol ffrstpol
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state <int> ffoffset
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					state <int> ffoffset
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