mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-30 13:19:05 +00:00
Code Activity

Add $input_port and $connect cell types

Browse source
This commit is contained in:
Jannis Harder 2025-09-03 15:26:33 +02:00
parent c4f435569f
commit 1251e92e3a
4 changed files with 63 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

25
techlibs/common/techmap.v
View file

@ -647,3 +647,28 @@ module _90_lut;
endmodule
`endif
// --------------------------------------------------------
// Bufnorm helpers
// --------------------------------------------------------
(* techmap_celltype = "$connect" *)
module \$connect (A, B);
parameter WIDTH = 0;
inout [WIDTH-1:0] A;
inout [WIDTH-1:0] B;
assign A = B; // RTLIL assignments are not inherently directed
endmodule
(* techmap_celltype = "$input_port" *)
module \$input_port (Y);
parameter WIDTH = 0;
inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
endmodule