From 1251e92e3a988b33f2075118071f4454247041d6 Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Wed, 3 Sep 2025 15:26:33 +0200
Subject: [PATCH] Add `$input_port` and `$connect` cell types

---
 kernel/celltypes.h        |  2 ++
 kernel/rtlil.cc           | 13 +++++++++++++
 techlibs/common/simlib.v  | 23 +++++++++++++++++++++++
 techlibs/common/techmap.v | 25 +++++++++++++++++++++++++
 4 files changed, 63 insertions(+)

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 34592192f..2c3535eac 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -111,6 +111,8 @@ struct CellTypes
 		setup_type(ID($original_tag), {ID::A}, {ID::Y});
 		setup_type(ID($future_ff), {ID::A}, {ID::Y});
 		setup_type(ID($scopeinfo), {}, {});
+		setup_type(ID($input_port), {}, {ID::Y});
+		setup_type(ID($connect), {ID::A, ID::B}, {});
 	}
 
 	void setup_internals_eval()
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 5f8e6ad66..3858a3372 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2451,6 +2451,19 @@ namespace {
 				check_expected();
 				return;
 			}
+			if (cell->type.in(ID($input_port))) {
+				param(ID::WIDTH);
+				port(ID::Y, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
+			if (cell->type.in(ID($connect))) {
+				param(ID::WIDTH);
+				port(ID::A, param(ID::WIDTH));
+				port(ID::B, param(ID::WIDTH));
+				check_expected();
+				return;
+			}
 			/*
 			 * Checklist for adding internal cell types
 			 * ========================================
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 6e39aa60a..096df07b9 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -3216,3 +3216,26 @@ module \$scopeinfo ();
 parameter TYPE = "";
 
 endmodule
+
+// --------------------------------------------------------
+//* group wire
+module \$connect (A, B);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] A;
+inout [WIDTH-1:0] B;
+
+tran connect[WIDTH-1:0] (A, B);
+
+endmodule
+
+// --------------------------------------------------------
+//* group wire
+module \$input_port (Y);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] Y;
+
+endmodule
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index fdf11904b..7a9ad7693 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -647,3 +647,28 @@ module _90_lut;
 endmodule
 `endif
 
+
+// --------------------------------------------------------
+// Bufnorm helpers
+// --------------------------------------------------------
+
+(* techmap_celltype = "$connect" *)
+module \$connect (A, B);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] A;
+inout [WIDTH-1:0] B;
+
+assign A = B; // RTLIL assignments are not inherently directed
+
+endmodule
+
+(* techmap_celltype = "$input_port" *)
+module \$input_port (Y);
+
+parameter WIDTH = 0;
+
+inout [WIDTH-1:0] Y; // This cell is just a maker, so we leave Y undriven
+
+endmodule