mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-09-30 05:09:04 +00:00
Code Activity

Add $input_port and $connect cell types

Browse source
This commit is contained in:
Jannis Harder 2025-09-03 15:26:33 +02:00
parent c4f435569f
commit 1251e92e3a
4 changed files with 63 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

23
techlibs/common/simlib.v
View file

@ -3216,3 +3216,26 @@ module \$scopeinfo ();
parameter TYPE = "";
endmodule
// --------------------------------------------------------
//* group wire
module \$connect (A, B);
parameter WIDTH = 0;
inout [WIDTH-1:0] A;
inout [WIDTH-1:0] B;
tran connect[WIDTH-1:0] (A, B);
endmodule
// --------------------------------------------------------
//* group wire
module \$input_port (Y);
parameter WIDTH = 0;
inout [WIDTH-1:0] Y;
endmodule