From 104d39057ec356fb39d21fd1db19a105e352da69 Mon Sep 17 00:00:00 2001 From: Alain Dargelas Date: Tue, 4 Mar 2025 10:31:20 -0800 Subject: [PATCH] unique names --- passes/silimate/annotate_cell_fanout.cc | 88 +++++++++++++++---------- 1 file changed, 52 insertions(+), 36 deletions(-) diff --git a/passes/silimate/annotate_cell_fanout.cc b/passes/silimate/annotate_cell_fanout.cc index 71f3ccfca..c93eb2292 100644 --- a/passes/silimate/annotate_cell_fanout.cc +++ b/passes/silimate/annotate_cell_fanout.cc @@ -5,14 +5,24 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -RTLIL::IdString generateSigSpecName(const RTLIL::SigSpec &sigspec) +// Return substring up to a delimiter or full string if not found +std::string substringuntil(const std::string &str, char delimiter) +{ + size_t pos = str.find(delimiter); + if (pos != std::string::npos) { + return str.substr(0, pos); + } else { + return str; + } +} + +// Generate a human readable name for a sigspec, uniquify if necessary +RTLIL::IdString generateSigSpecName(Module* module, const RTLIL::SigSpec &sigspec, bool makeUnique = false, std::string postfix = "", bool cellName = false) { if (sigspec.empty()) { return RTLIL::IdString(); // Empty SigSpec, return empty IdString } - std::stringstream ss; - if (sigspec.is_wire()) { // Handle wires ss << sigspec.as_wire()->name.str(); @@ -22,33 +32,47 @@ RTLIL::IdString generateSigSpecName(const RTLIL::SigSpec &sigspec) if (sigspec[0].wire->width != 1) { ss << "[" << sigspec[0].offset << "]"; } - } else if (sigspec.is_chunk()) { - // Handle slices - RTLIL::Wire *parent_wire = sigspec[0].wire; - SigChunk chunk = sigspec.as_chunk(); - if (parent_wire) { - ss << parent_wire->name.str() << "[" << chunk.offset + chunk.width - 1 << ":" << chunk.offset << "]"; - } } else if (!sigspec.is_chunk()) { // Handle vector of chunks int max = 0; int min = INT_MAX; RTLIL::Wire *parent_wire = sigspec[0].wire; + int width = 0; for (SigChunk chunk : sigspec.chunks()) { + width += chunk.width; max = std::max(max, chunk.offset); min = std::min(min, chunk.offset); } + if (max == 0) { + max = width - 1; + } if (parent_wire) { - ss << parent_wire->name.str() << "[" << max << ":" << min << "]"; + if (max != min) { + ss << substringuntil(parent_wire->name.str(), '[') << "[" << max << ":" << min << "]"; + } else { + ss << parent_wire->name.str(); + } } else { ss << "\\sigspec_[" << max << ":" << min << "]"; } - } else { - // Handle other cases (e.g., constants) - ss << "\\sigspec_"; + } + ss << postfix; + if (makeUnique) { + RTLIL::IdString base_name = RTLIL::IdString(ss.str()); + // Ensure uniqueness + int counter = 0; + if (cellName) { + while (module->cells_.count(RTLIL::IdString(ss.str()))) { + ss.str(""); + ss << base_name.str() << "_" << counter++; + } + } else { + while (module->wires_.count(RTLIL::IdString(ss.str()))) { + ss.str(""); + ss << base_name.str() << "_" << counter++; + } + } } - - RTLIL::IdString base_name = RTLIL::IdString(ss.str()); return RTLIL::IdString(ss.str()); } @@ -111,6 +135,7 @@ void lhs2rhs_rhs2lhs(RTLIL::Module *module, SigMap &sigmap, dict &bufferIndexes, +SigSpec updateToBuffer(Module* module, std::map &bufferIndexes, std::map>> &buffer_outputs, dict> &sig2CellsInFanout, std::map &bufferActualFanout, std::map &usedBuffers, int max_output_per_buffer, Cell *fanoutcell, SigSpec sigToReplace, @@ -229,7 +254,7 @@ SigSpec updateToBuffer(std::map &bufferIndexes, std::map::iterator itrBuffer = usedBuffers.find(sigToReplace); if (itrBuffer != usedBuffers.end()) { if (debug) - std::cout << "REUSE CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(sigToReplace).c_str() + std::cout << "REUSE CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(module, sigToReplace).c_str() << std::endl; return itrBuffer->second; } @@ -259,8 +284,8 @@ SigSpec updateToBuffer(std::map &bufferIndexes, } // Cache result if (debug) - std::cout << "CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(sigToReplace).c_str() << " BY " - << generateSigSpecName(newSig).c_str() << std::endl; + std::cout << "CACHE:" << fanoutcell->name.c_str() << " SIG: " << generateSigSpecName(module, sigToReplace).c_str() << " BY " + << generateSigSpecName(module, newSig).c_str() << std::endl; usedBuffers.emplace(sigToReplace, newSig); // Return buffer's output @@ -279,7 +304,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict> buffer_chunk_outputs; for (int i = 0; i < num_buffers; ++i) { - RTLIL::Cell *buffer = module->addCell(signame + "_fbuf" + std::to_string(index_buffer), ID($pos)); + std::string wireName = generateSigSpecName(module, sigToBuffer, true, "_wbuf" + std::to_string(index_buffer)).c_str(); + std::string cellName = generateSigSpecName(module, sigToBuffer, true, "_fbuf" + std::to_string(index_buffer), true).c_str(); + RTLIL::Cell *buffer = module->addCell(cellName, ID($pos)); bufferActualFanout[buffer] = 0; - RTLIL::SigSpec buffer_output = module->addWire(signame + "_wbuf" + std::to_string(index_buffer), chunk.size()); + RTLIL::SigSpec buffer_output = module->addWire(wireName, chunk.size()); buffer->setPort(ID(A), chunk); buffer->setPort(ID(Y), sigmap(buffer_output)); buffer->fixup_parameters(); @@ -359,7 +386,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dictsetPort(portName, newSig); @@ -376,7 +403,7 @@ void fixfanout(RTLIL::Module *module, SigMap &sigmap, dict &netsToSplitS, RTLIL::SigSpec &sigToSplit, bool formalFriendly, bool inputPort = false) { Wire *parentWire = getParentWire(sigToSplit);