tracy: init, zones per pass execute method, pointer-colored

.gitmodules

@@ -1,3 +1,6 @@
 [submodule "abc"]
 	path = abc
 	url = https://github.com/YosysHQ/abc
+[submodule "tracy"]
+	path = tracy
+	url = git@github.com:wolfpld/tracy.git

Makefile

@@ -91,7 +91,7 @@ YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST)))
 VPATH := $(YOSYS_SRC)
 
 CXXSTD ?= c++11
-CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
+CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -Itracy/public -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include
 LIBS := $(LIBS) -lstdc++ -lm
 PLUGIN_LINKFLAGS :=
 PLUGIN_LIBS :=
@@ -595,6 +595,8 @@ $(eval $(call add_include_file,frontends/ast/ast_binding.h))
 $(eval $(call add_include_file,frontends/blif/blifparse.h))
 $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h))
 
+OBJS += tracy/public/TracyClient.o
+CXXFLAGS += -DTRACY_ENABLE
 OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o
 OBJS += kernel/binding.o
 OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o

flake.nix

@@ -15,10 +15,10 @@
         # TODO: don't override src when ./abc is empty
         # which happens when the command used is `nix build` and not `nix build ?submodules=1`
         abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;});
-        yosys = pkgs.clangStdenv.mkDerivation {
+        yosys = pkgs.llvmPackages.libcxxStdenv.mkDerivation {
           name = "yosys";
           src = ./. ;
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ];
+          buildInputs = with pkgs; [ bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream tracy ];
           checkInputs = with pkgs; [ gtest ];
           propagatedBuildInputs = [ abc-verifier ];
           preConfigure = "make config-clang";
@@ -41,7 +41,7 @@
         packages.default = yosys;
         defaultPackage = yosys;
         devShell = pkgs.mkShell {
-          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ];
+          buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier tracy ];
         };
       }
     );

kernel/register.h

@@ -23,6 +23,8 @@
 #include "kernel/yosys_common.h"
 #include "kernel/yosys.h"
 
+#include "tracy/public/tracy/Tracy.hpp"
+
 YOSYS_NAMESPACE_BEGIN
 
 struct Pass

passes/cmds/add.cc

@@ -152,6 +152,9 @@ struct AddPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string command;
 		std::string arg_name;
 		std::string enable_name = "";

passes/cmds/autoname.cc

@@ -101,6 +101,9 @@ struct AutonamePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{

passes/cmds/blackbox.cc

@@ -36,6 +36,9 @@ struct BlackboxPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{

passes/cmds/bugpoint.cc

@@ -399,6 +399,9 @@ struct BugpointPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		string yosys_cmd = "yosys", yosys_arg, grep, runner;
 		bool fast = false, clean = false;
 		bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, wires = false, has_part = false;

passes/cmds/check.cc

@@ -62,6 +62,9 @@ struct CheckPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		int counter = 0;
 		bool noinit = false;
 		bool initdrv = false;

passes/cmds/chformal.cc

@@ -128,6 +128,9 @@ struct ChformalPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool assert2assume = false;
 		bool assume2assert = false;
 		bool live2fair = false;

passes/cmds/chtype.cc

@@ -42,6 +42,9 @@ struct ChtypePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		IdString set_type;
 		dict<IdString, IdString> map_types;
 

passes/cmds/clean_zerowidth.cc

@@ -52,6 +52,9 @@ struct CleanZeroWidthPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{

passes/cmds/connect.cc

@@ -80,6 +80,9 @@ struct ConnectPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_nounset = false, flag_nomap = false, flag_assert = false;
 		std::string set_lhs, set_rhs, unset_expr;
 		std::string port_cell, port_port, port_expr;

passes/cmds/connwrappers.cc

@@ -167,6 +167,9 @@ struct ConnwrappersPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		ConnwrappersWorker worker;
 
 		size_t argidx;

passes/cmds/copy.cc

@@ -38,6 +38,9 @@ struct CopyPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		if (args.size() != 3)
 			log_cmd_error("Invalid number of arguments!\n");
 

passes/cmds/cover.cc

@@ -85,6 +85,9 @@ struct CoverPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::vector<FILE*> out_files;
 		std::vector<std::string> patterns;
 		bool do_log = true;

passes/cmds/delete.cc

@@ -42,6 +42,9 @@ struct DeletePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_input = false;
 		bool flag_output = false;
 

passes/cmds/design.cc

@@ -107,6 +107,9 @@ struct DesignPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool got_mode = false;
 		bool reset_mode = false;
 		bool reset_vlog_mode = false;

passes/cmds/dft_tag.cc

@@ -972,6 +972,9 @@ struct DftTagPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		DftTagOptions options;
 
 		log_header(design, "Executing DFT_TAG pass.\n");

passes/cmds/edgetypes.cc

@@ -37,6 +37,9 @@ struct EdgetypePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			// if (args[argidx] == "-ltr") {

passes/cmds/exec.cc

@@ -73,6 +73,9 @@ struct ExecPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string cmd = "";
 		char buf[1024] = {};
 		std::string linebuf = "";

passes/cmds/future.cc

@@ -119,6 +119,9 @@ struct FuturePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		FutureOptions options;
 
 		log_header(design, "Executing FUTURE pass.\n");

passes/cmds/glift.cc

@@ -517,6 +517,9 @@ struct GliftPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool opt_create_precise_model = false, opt_create_imprecise_model = false, opt_create_instrumented_model = false;
 		bool opt_taintconstants = false, opt_keepoutputs = false, opt_simplecostmodel = false, opt_nocostmodel = false;
 		bool opt_instrumentmore = false;

passes/cmds/logcmd.cc

@@ -65,6 +65,9 @@ struct LogPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design* design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		bool to_stdout = false;
 		bool to_stderr = false;

passes/cmds/logger.cc

@@ -73,6 +73,9 @@ struct LoggerPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design * design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{

passes/cmds/ltp.cc

@@ -156,6 +156,9 @@ struct LtpPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool noff = false;
 
 		log_header(design, "Executing LTP pass (find longest path).\n");

passes/cmds/plugin.cc

@@ -142,6 +142,9 @@ struct PluginPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string plugin_filename;
 		std::vector<std::string> plugin_aliases;
 		bool list_mode = false;

passes/cmds/portlist.cc

@@ -41,6 +41,9 @@ struct PortlistPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool m_mode = false;
 
 		size_t argidx;

passes/cmds/printattrs.cc

@@ -50,6 +50,9 @@ struct PrintAttrsPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
 

passes/cmds/qwp.cc

@@ -810,6 +810,9 @@ struct QwpPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		QwpConfig config;
 		xorshift32_state = 123456789;
 

passes/cmds/rename.cc

@@ -256,6 +256,9 @@ struct RenamePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string pattern_prefix = "_", pattern_suffix = "_";
 		std::string cell_suffix = "";
 		bool flag_src = false;

passes/cmds/scatter.cc

@@ -43,6 +43,9 @@ struct ScatterPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		CellTypes ct(design);
 		extra_args(args, 1, design);
 

passes/cmds/scc.cc

@@ -294,6 +294,9 @@ struct SccPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		dict<std::string, std::string> setAttr;
 		bool allCellTypes = false;
 		bool selectMode = false;

passes/cmds/scratchpad.cc

@@ -66,6 +66,9 @@ struct ScratchpadPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{

passes/cmds/select.cc

@@ -1254,6 +1254,9 @@ struct SelectPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool add_mode = false;
 		bool del_mode = false;
 		bool clear_mode = false;
@@ -1622,6 +1625,9 @@ struct CdPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		if (args.size() != 1 && args.size() != 2)
 			log_cmd_error("Invalid number of arguments.\n");
 
@@ -1713,6 +1719,9 @@ struct LsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
 

passes/cmds/setattr.cc

@@ -71,6 +71,9 @@ struct SetattrPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::vector<setunset_t> setunset_list;
 		bool flag_mod = false;
 
@@ -140,6 +143,9 @@ struct WbflipPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -181,6 +187,9 @@ struct SetparamPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		vector<setunset_t> setunset_list;
 		string new_cell_type;
 
@@ -236,6 +245,9 @@ struct ChparamPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::vector<setunset_t> setunset_list;
 		dict<RTLIL::IdString, RTLIL::Const> new_parameters;
 		bool list_mode = false;

passes/cmds/setundef.cc

@@ -150,6 +150,9 @@ struct SetundefPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		int got_value = 0;
 		bool undriven_mode = false;
 		bool expose_mode = false;

passes/cmds/show.cc

@@ -752,6 +752,9 @@ struct ShowPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Generating Graphviz representation of design.\n");
 		log_push();
 

passes/cmds/splice.cc

@@ -289,6 +289,9 @@ struct SplicePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool sel_by_cell = false;
 		bool sel_by_wire = false;
 		bool sel_any_bit = false;

passes/cmds/splitcells.cc

@@ -220,6 +220,9 @@ struct SplitcellsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string format;
 
 		log_header(design, "Executing SPLITCELLS pass (splitting up multi-bit cells).\n");

passes/cmds/splitnets.cc

@@ -119,6 +119,9 @@ struct SplitnetsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_ports = false;
 		bool flag_driver = false;
 		std::string format = "[]:";

passes/cmds/sta.cc

@@ -287,6 +287,9 @@ struct StaPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing STA pass (static timing analysis).\n");
 
 		/*

passes/cmds/stat.cc

@@ -404,6 +404,9 @@ struct StatPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool width_mode = false, json_mode = false;
 		RTLIL::Module *top_mod = nullptr;
 		std::map<RTLIL::IdString, statdata_t> mod_stat;

passes/cmds/tee.cc

@@ -54,6 +54,9 @@ struct TeePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::vector<FILE*> backup_log_files, files_to_close;
 		std::vector<std::ostream*> backup_log_streams;
 		std::vector<std::string> backup_log_scratchpads;

passes/cmds/torder.cc

@@ -45,6 +45,9 @@ struct TorderPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool noautostop = false;
 		dict<IdString, pool<IdString>> stop_db;
 

passes/cmds/trace.cc

@@ -72,6 +72,9 @@ struct TracePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
@@ -107,6 +110,9 @@ struct DebugPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{

passes/cmds/viz.cc

@@ -889,6 +889,9 @@ struct VizPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Generating Graphviz representation of design.\n");
 		log_push();
 

passes/cmds/write_file.cc

@@ -46,6 +46,9 @@ struct WriteFileFrontend : public Frontend {
 	}
 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool append_mode = false;
 		std::string output_filename;
 

passes/cmds/xprop.cc

@@ -1154,6 +1154,9 @@ struct XpropPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		XpropOptions options;
 
 		log_header(design, "Executing XPROP pass.\n");

passes/equiv/equiv_add.cc

@@ -41,6 +41,9 @@ struct EquivAddPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool try_mode = false;
 
 		if (design->selected_active_module.empty())

passes/equiv/equiv_induct.cc

@@ -199,6 +199,9 @@ struct EquivInductPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		int success_counter = 0;
 		bool model_undef = false;
 		int max_seq = 4;

passes/equiv/equiv_make.cc

@@ -457,6 +457,9 @@ struct EquivMakePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		EquivMakeWorker worker;
 		worker.ct.setup(design);
 		worker.inames = false;

passes/equiv/equiv_mark.cc

@@ -218,6 +218,9 @@ struct EquivMarkPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing EQUIV_MARK pass.\n");
 
 		size_t argidx;

passes/equiv/equiv_miter.cc

@@ -284,6 +284,9 @@ struct EquivMiterPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		EquivMiterWorker worker;
 		worker.ct.setup(design);
 		worker.mode_trigger = false;

passes/equiv/equiv_opt.cc

@@ -85,6 +85,9 @@ struct EquivOptPass:public ScriptPass
 
 	void execute(std::vector < std::string > args, RTLIL::Design * design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		string run_from, run_to;
 		clear_flags();
 

passes/equiv/equiv_purge.cc

@@ -189,6 +189,9 @@ struct EquivPurgePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing EQUIV_PURGE pass.\n");
 
 		size_t argidx;

passes/equiv/equiv_remove.cc

@@ -42,6 +42,9 @@ struct EquivRemovePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool mode_gold = false;
 		bool mode_gate = false;
 		int remove_count = 0;

passes/equiv/equiv_simple.cc

@@ -304,6 +304,9 @@ struct EquivSimplePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool verbose = false, short_cones = false, model_undef = false, nogroup = false;
 		int success_counter = 0;
 		int max_seq = 1;

passes/equiv/equiv_status.cc

@@ -38,6 +38,9 @@ struct EquivStatusPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool assert_mode = false;
 		int unproven_count = 0;
 

passes/equiv/equiv_struct.cc

@@ -316,6 +316,9 @@ struct EquivStructPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		pool<IdString> fwonly_cells({ ID($equiv) });
 		bool mode_icells = false;
 		bool mode_fwd = false;

passes/fsm/fsm.cc

@@ -79,6 +79,9 @@ struct FsmPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_nomap = false;
 		bool flag_norecode = false;
 		bool flag_nodetect = false;

passes/fsm/fsm_detect.cc

@@ -287,6 +287,9 @@ struct FsmDetectPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
 
 		bool ignore_self_reset = false;

passes/fsm/fsm_expand.cc

@@ -281,6 +281,9 @@ struct FsmExpandPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool full_mode = false;
 
 		log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n");

passes/fsm/fsm_export.cc

@@ -145,6 +145,9 @@ struct FsmExportPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
 		std::string arg;
 		bool flag_noauto = false;

passes/fsm/fsm_extract.cc

@@ -419,6 +419,9 @@ struct FsmExtractPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
 		extra_args(args, 1, design);
 

passes/fsm/fsm_info.cc

@@ -43,6 +43,9 @@ struct FsmInfoPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
 		extra_args(args, 1, design);
 

passes/fsm/fsm_map.cc

@@ -333,6 +333,9 @@ struct FsmMapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
 		extra_args(args, 1, design);
 

passes/fsm/fsm_opt.cc

@@ -337,6 +337,9 @@ struct FsmOptPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
 		extra_args(args, 1, design);
 

passes/fsm/fsm_recode.cc

@@ -153,6 +153,9 @@ struct FsmRecodePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		FILE *fm_set_fsm_file = NULL;
 		FILE *encfile = NULL;
 		std::string default_encoding;

passes/hierarchy/hierarchy.cc

@@ -819,6 +819,9 @@ struct HierarchyPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
 
 		bool flag_check = false;

passes/hierarchy/submod.cc

@@ -354,6 +354,9 @@ struct SubmodPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
 		log_push();
 

passes/hierarchy/uniquify.cc

@@ -43,6 +43,9 @@ struct UniquifyPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");
 
 		size_t argidx;

passes/memory/memory.cc

@@ -55,6 +55,9 @@ struct MemoryPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_norom = false;
 		bool flag_nomap = false;
 		bool flag_nordff = false;

passes/memory/memory_bmux2rom.cc

@@ -37,6 +37,9 @@ struct MemoryBmux2RomPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n");
 
 		size_t argidx;

passes/memory/memory_bram.cc

@@ -1306,6 +1306,9 @@ struct MemoryBramPass : public Pass {
 	}
 	void execute(vector<string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		rules_t rules;
 
 		log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");

passes/memory/memory_collect.cc

@@ -37,6 +37,9 @@ struct MemoryCollectPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 		for (auto module : design->selected_modules()) {
 			if (module->has_processes_warn())

passes/memory/memory_dff.cc

@@ -643,6 +643,9 @@ struct MemoryDffPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_no_rw_check = false;
 		log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n");
 

passes/memory/memory_libmap.cc

@@ -2182,6 +2182,9 @@ struct MemoryLibMapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::vector<std::string> lib_files;
 		pool<std::string> defines;
 		PassOptions opts;

passes/memory/memory_map.cc

@@ -432,6 +432,9 @@ struct MemoryMapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool attr_icase = false;
 		bool rom_only = false;
 		bool keepdc = false;

passes/memory/memory_memx.cc

@@ -51,6 +51,9 @@ struct MemoryMemxPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules())

passes/memory/memory_narrow.cc

@@ -37,6 +37,9 @@ struct MemoryNarrowPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
 
 		size_t argidx;

passes/memory/memory_nordff.cc

@@ -38,6 +38,9 @@ struct MemoryNordffPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from memories).\n");
 
 		size_t argidx;

passes/memory/memory_share.cc

@@ -538,6 +538,9 @@ struct MemorySharePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		bool flag_widen = true;
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool flag_sat = true;
 		log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
 		size_t argidx;

passes/memory/memory_unpack.cc

@@ -37,6 +37,9 @@ struct MemoryUnpackPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 		for (auto module : design->selected_modules()) {
 			for (auto &mem : Mem::get_selected_memories(module)) {

passes/opt/muxpack.cc

@@ -343,6 +343,9 @@ struct MuxpackPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
 
 		size_t argidx;

passes/opt/opt.cc

@@ -66,6 +66,9 @@ struct OptPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string opt_clean_args;
 		std::string opt_expr_args;
 		std::string opt_reduce_args;

passes/opt/opt_clean.cc

@@ -646,6 +646,9 @@ struct OptCleanPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool purge_mode = false;
 
 		log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
@@ -711,6 +714,9 @@ struct CleanPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool purge_mode = false;
 
 		size_t argidx;

passes/opt/opt_demorgan.cc

@@ -181,6 +181,9 @@ struct OptDemorganPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
 
 		int argidx = 1;

passes/opt/opt_dff.cc

@@ -882,6 +882,9 @@ struct OptDffPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_DFF pass (perform DFF optimizations).\n");
 		OptDffOptions opt;
 		opt.nodffe = false;

passes/opt/opt_expr.cc

@@ -2252,6 +2252,9 @@ struct OptExprPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool mux_undef = false;
 		bool mux_bool = false;
 		bool undriven = false;

passes/opt/opt_ffinv.cc

@@ -245,6 +245,9 @@ struct OptFfInvPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_FFINV pass (push inverters through FFs).\n");
 
 		size_t argidx;

passes/opt/opt_lut.cc

@@ -543,6 +543,9 @@ struct OptLutPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
 
 		std::vector<dlogic_t> dlogic;

passes/opt/opt_lut_ins.cc

@@ -44,6 +44,9 @@ struct OptLutInsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_LUT_INS pass (discard unused LUT inputs).\n");
 		string techname;
 

passes/opt/opt_mem.cc

@@ -38,6 +38,9 @@ struct OptMemPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MEM pass (optimize memories).\n");
 
 		size_t argidx;

passes/opt/opt_mem_feedback.cc

@@ -338,6 +338,9 @@ struct OptMemFeedbackPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 		OptMemFeedbackWorker worker(design);
 

passes/opt/opt_mem_priority.cc

@@ -42,6 +42,9 @@ struct OptMemPriorityPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 
 		ModWalker modwalker(design);

passes/opt/opt_mem_widen.cc

@@ -37,6 +37,9 @@ struct OptMemWidenPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n");
 
 		size_t argidx;

passes/opt/opt_merge.cc

@@ -336,6 +336,9 @@ struct OptMergePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
 
 		bool mode_nomux = false;

passes/opt/opt_muxtree.cc

@@ -487,6 +487,9 @@ struct OptMuxtreePass : public Pass {
 	}
 	void execute(vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
 		extra_args(args, 1, design);
 

passes/opt/opt_reduce.cc

@@ -630,6 +630,9 @@ struct OptReducePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool do_fine = false;
 
 		log_header(design, "Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");