diff --git a/.gitmodules b/.gitmodules index d88d4b1e5..849e97484 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,6 @@ [submodule "abc"] path = abc url = https://github.com/YosysHQ/abc +[submodule "tracy"] + path = tracy + url = git@github.com:wolfpld/tracy.git diff --git a/Makefile b/Makefile index 15ab4766c..19b639fba 100644 --- a/Makefile +++ b/Makefile @@ -91,7 +91,7 @@ YOSYS_SRC := $(dir $(firstword $(MAKEFILE_LIST))) VPATH := $(YOSYS_SRC) CXXSTD ?= c++11 -CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include +CXXFLAGS := $(CXXFLAGS) -Wall -Wextra -ggdb -I. -Itracy/public -I"$(YOSYS_SRC)" -MD -MP -D_YOSYS_ -fPIC -I$(PREFIX)/include LIBS := $(LIBS) -lstdc++ -lm PLUGIN_LINKFLAGS := PLUGIN_LIBS := @@ -595,6 +595,8 @@ $(eval $(call add_include_file,frontends/ast/ast_binding.h)) $(eval $(call add_include_file,frontends/blif/blifparse.h)) $(eval $(call add_include_file,backends/rtlil/rtlil_backend.h)) +OBJS += tracy/public/TracyClient.o +CXXFLAGS += -DTRACY_ENABLE OBJS += kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o OBJS += kernel/binding.o OBJS += kernel/cellaigs.o kernel/celledges.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o diff --git a/flake.nix b/flake.nix index 1e2023246..b0194ce80 100644 --- a/flake.nix +++ b/flake.nix @@ -15,10 +15,10 @@ # TODO: don't override src when ./abc is empty # which happens when the command used is `nix build` and not `nix build ?submodules=1` abc-verifier = pkgs.abc-verifier.overrideAttrs(x: y: {src = ./abc;}); - yosys = pkgs.clangStdenv.mkDerivation { + yosys = pkgs.llvmPackages.libcxxStdenv.mkDerivation { name = "yosys"; src = ./. ; - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream ]; + buildInputs = with pkgs; [ bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git pkg-configUpstream tracy ]; checkInputs = with pkgs; [ gtest ]; propagatedBuildInputs = [ abc-verifier ]; preConfigure = "make config-clang"; @@ -41,7 +41,7 @@ packages.default = yosys; defaultPackage = yosys; devShell = pkgs.mkShell { - buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier ]; + buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier tracy ]; }; } ); diff --git a/kernel/register.h b/kernel/register.h index 25ea9f232..6dd761286 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -23,6 +23,8 @@ #include "kernel/yosys_common.h" #include "kernel/yosys.h" +#include "tracy/public/tracy/Tracy.hpp" + YOSYS_NAMESPACE_BEGIN struct Pass diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index c09517254..63061d0d2 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -152,6 +152,9 @@ struct AddPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string command; std::string arg_name; std::string enable_name = ""; diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 737bd3e58..7740a74d0 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -101,6 +101,9 @@ struct AutonamePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc index 43670efaf..d0b9aff6a 100644 --- a/passes/cmds/blackbox.cc +++ b/passes/cmds/blackbox.cc @@ -36,6 +36,9 @@ struct BlackboxPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc index c398afffa..dad83ed70 100644 --- a/passes/cmds/bugpoint.cc +++ b/passes/cmds/bugpoint.cc @@ -399,6 +399,9 @@ struct BugpointPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); string yosys_cmd = "yosys", yosys_arg, grep, runner; bool fast = false, clean = false; bool modules = false, ports = false, cells = false, connections = false, processes = false, assigns = false, updates = false, wires = false, has_part = false; diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 255c32fba..64b7e469b 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -62,6 +62,9 @@ struct CheckPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int counter = 0; bool noinit = false; bool initdrv = false; diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc index e027103bb..03187d014 100644 --- a/passes/cmds/chformal.cc +++ b/passes/cmds/chformal.cc @@ -128,6 +128,9 @@ struct ChformalPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool assert2assume = false; bool assume2assert = false; bool live2fair = false; diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc index 6f9ca9a45..dc8786dde 100644 --- a/passes/cmds/chtype.cc +++ b/passes/cmds/chtype.cc @@ -42,6 +42,9 @@ struct ChtypePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); IdString set_type; dict map_types; diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc index bac6b1521..d525be5a8 100644 --- a/passes/cmds/clean_zerowidth.cc +++ b/passes/cmds/clean_zerowidth.cc @@ -52,6 +52,9 @@ struct CleanZeroWidthPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 65292ef92..24aed247f 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -80,6 +80,9 @@ struct ConnectPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_nounset = false, flag_nomap = false, flag_assert = false; std::string set_lhs, set_rhs, unset_expr; std::string port_cell, port_port, port_expr; diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index dbe23ccf1..054a40e4d 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -167,6 +167,9 @@ struct ConnwrappersPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); ConnwrappersWorker worker; size_t argidx; diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index e3fb3a0e6..f6753edd3 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -38,6 +38,9 @@ struct CopyPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); if (args.size() != 3) log_cmd_error("Invalid number of arguments!\n"); diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index 1db3e2ca0..8d7b73482 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -85,6 +85,9 @@ struct CoverPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector out_files; std::vector patterns; bool do_log = true; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index e341f29d6..e3c56cf65 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -42,6 +42,9 @@ struct DeletePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_input = false; bool flag_output = false; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 168d38563..c4f1bc161 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -107,6 +107,9 @@ struct DesignPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool got_mode = false; bool reset_mode = false; bool reset_vlog_mode = false; diff --git a/passes/cmds/dft_tag.cc b/passes/cmds/dft_tag.cc index 2b2340dab..5ea55de44 100644 --- a/passes/cmds/dft_tag.cc +++ b/passes/cmds/dft_tag.cc @@ -972,6 +972,9 @@ struct DftTagPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); DftTagOptions options; log_header(design, "Executing DFT_TAG pass.\n"); diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc index 5b53f50cc..1eaccd1d8 100644 --- a/passes/cmds/edgetypes.cc +++ b/passes/cmds/edgetypes.cc @@ -37,6 +37,9 @@ struct EdgetypePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { // if (args[argidx] == "-ltr") { diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index e5fa4fb41..94c7e1f92 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -73,6 +73,9 @@ struct ExecPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string cmd = ""; char buf[1024] = {}; std::string linebuf = ""; diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc index b03613c9b..9bd8f5229 100644 --- a/passes/cmds/future.cc +++ b/passes/cmds/future.cc @@ -119,6 +119,9 @@ struct FuturePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); FutureOptions options; log_header(design, "Executing FUTURE pass.\n"); diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index 8553b02a5..b30ff8f42 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -517,6 +517,9 @@ struct GliftPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool opt_create_precise_model = false, opt_create_imprecise_model = false, opt_create_instrumented_model = false; bool opt_taintconstants = false, opt_keepoutputs = false, opt_simplecostmodel = false, opt_nocostmodel = false; bool opt_instrumentmore = false; diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc index 8e51af4b3..9f1a0292a 100644 --- a/passes/cmds/logcmd.cc +++ b/passes/cmds/logcmd.cc @@ -65,6 +65,9 @@ struct LogPass : public Pass { } void execute(std::vector args, RTLIL::Design* design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; bool to_stdout = false; bool to_stderr = false; diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index 9e45e86af..a0f14dd1f 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -73,6 +73,9 @@ struct LoggerPass : public Pass { void execute(std::vector args, RTLIL::Design * design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc index 22bdaab44..7e51a2605 100644 --- a/passes/cmds/ltp.cc +++ b/passes/cmds/ltp.cc @@ -156,6 +156,9 @@ struct LtpPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool noff = false; log_header(design, "Executing LTP pass (find longest path).\n"); diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 4ad7c165b..e615165c7 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -142,6 +142,9 @@ struct PluginPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string plugin_filename; std::vector plugin_aliases; bool list_mode = false; diff --git a/passes/cmds/portlist.cc b/passes/cmds/portlist.cc index 03048422d..e7916ab9a 100644 --- a/passes/cmds/portlist.cc +++ b/passes/cmds/portlist.cc @@ -41,6 +41,9 @@ struct PortlistPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool m_mode = false; size_t argidx; diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc index 7973ac262..991b68aef 100644 --- a/passes/cmds/printattrs.cc +++ b/passes/cmds/printattrs.cc @@ -50,6 +50,9 @@ struct PrintAttrsPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx = 1; extra_args(args, argidx, design); diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc index 2da612441..21839ccb8 100644 --- a/passes/cmds/qwp.cc +++ b/passes/cmds/qwp.cc @@ -810,6 +810,9 @@ struct QwpPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); QwpConfig config; xorshift32_state = 123456789; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 3f8d807b3..147ff1e96 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -256,6 +256,9 @@ struct RenamePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string pattern_prefix = "_", pattern_suffix = "_"; std::string cell_suffix = ""; bool flag_src = false; diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 017600a46..60b8b63fd 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -43,6 +43,9 @@ struct ScatterPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); CellTypes ct(design); extra_args(args, 1, design); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 197bd9319..bc7891064 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -294,6 +294,9 @@ struct SccPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); dict setAttr; bool allCellTypes = false; bool selectMode = false; diff --git a/passes/cmds/scratchpad.cc b/passes/cmds/scratchpad.cc index aecc4c17d..24999d721 100644 --- a/passes/cmds/scratchpad.cc +++ b/passes/cmds/scratchpad.cc @@ -66,6 +66,9 @@ struct ScratchpadPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 03d00816e..b1637bd35 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -1254,6 +1254,9 @@ struct SelectPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool add_mode = false; bool del_mode = false; bool clear_mode = false; @@ -1622,6 +1625,9 @@ struct CdPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); if (args.size() != 1 && args.size() != 2) log_cmd_error("Invalid number of arguments.\n"); @@ -1713,6 +1719,9 @@ struct LsPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx = 1; extra_args(args, argidx, design); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 710fa9ab4..216acbf1f 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -71,6 +71,9 @@ struct SetattrPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector setunset_list; bool flag_mod = false; @@ -140,6 +143,9 @@ struct WbflipPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -181,6 +187,9 @@ struct SetparamPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); vector setunset_list; string new_cell_type; @@ -236,6 +245,9 @@ struct ChparamPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector setunset_list; dict new_parameters; bool list_mode = false; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 7293002f3..4f18f6ffd 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -150,6 +150,9 @@ struct SetundefPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int got_value = 0; bool undriven_mode = false; bool expose_mode = false; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 82b5c6bcf..a052af333 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -752,6 +752,9 @@ struct ShowPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Generating Graphviz representation of design.\n"); log_push(); diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 4ad0d2b25..9509a358b 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -289,6 +289,9 @@ struct SplicePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool sel_by_cell = false; bool sel_by_wire = false; bool sel_any_bit = false; diff --git a/passes/cmds/splitcells.cc b/passes/cmds/splitcells.cc index 82ed49074..c8f24231b 100644 --- a/passes/cmds/splitcells.cc +++ b/passes/cmds/splitcells.cc @@ -220,6 +220,9 @@ struct SplitcellsPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string format; log_header(design, "Executing SPLITCELLS pass (splitting up multi-bit cells).\n"); diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 927cefca3..ca7740e30 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -119,6 +119,9 @@ struct SplitnetsPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_ports = false; bool flag_driver = false; std::string format = "[]:"; diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc index 4ad0e96be..7a4202bd6 100644 --- a/passes/cmds/sta.cc +++ b/passes/cmds/sta.cc @@ -287,6 +287,9 @@ struct StaPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing STA pass (static timing analysis).\n"); /* diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index c2bb72f3b..8ae2c397d 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -404,6 +404,9 @@ struct StatPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool width_mode = false, json_mode = false; RTLIL::Module *top_mod = nullptr; std::map mod_stat; diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index 39ed4a7a8..6fe60dce3 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -54,6 +54,9 @@ struct TeePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector backup_log_files, files_to_close; std::vector backup_log_streams; std::vector backup_log_scratchpads; diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc index 1620c0bca..feadd5d9e 100644 --- a/passes/cmds/torder.cc +++ b/passes/cmds/torder.cc @@ -45,6 +45,9 @@ struct TorderPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool noautostop = false; dict> stop_db; diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc index 400542776..69b36789f 100644 --- a/passes/cmds/trace.cc +++ b/passes/cmds/trace.cc @@ -72,6 +72,9 @@ struct TracePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { @@ -107,6 +110,9 @@ struct DebugPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index 3655f3f49..22f25cb63 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -889,6 +889,9 @@ struct VizPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Generating Graphviz representation of design.\n"); log_push(); diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc index ea9b3f556..85f0532ec 100644 --- a/passes/cmds/write_file.cc +++ b/passes/cmds/write_file.cc @@ -46,6 +46,9 @@ struct WriteFileFrontend : public Frontend { } void execute(std::istream *&f, std::string filename, std::vector args, RTLIL::Design*) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool append_mode = false; std::string output_filename; diff --git a/passes/cmds/xprop.cc b/passes/cmds/xprop.cc index 310d6d773..b48325d92 100644 --- a/passes/cmds/xprop.cc +++ b/passes/cmds/xprop.cc @@ -1154,6 +1154,9 @@ struct XpropPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); XpropOptions options; log_header(design, "Executing XPROP pass.\n"); diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 1bcd4a887..1e099c465 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -41,6 +41,9 @@ struct EquivAddPass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool try_mode = false; if (design->selected_active_module.empty()) diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc index 8d882ae83..ab0c87e0d 100644 --- a/passes/equiv/equiv_induct.cc +++ b/passes/equiv/equiv_induct.cc @@ -199,6 +199,9 @@ struct EquivInductPass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int success_counter = 0; bool model_undef = false; int max_seq = 4; diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index e15e510be..d2dfd5f01 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -457,6 +457,9 @@ struct EquivMakePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); EquivMakeWorker worker; worker.ct.setup(design); worker.inames = false; diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc index 97a2a38dd..1e2a30ae2 100644 --- a/passes/equiv/equiv_mark.cc +++ b/passes/equiv/equiv_mark.cc @@ -218,6 +218,9 @@ struct EquivMarkPass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing EQUIV_MARK pass.\n"); size_t argidx; diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 6acfe85a9..a50df229e 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -284,6 +284,9 @@ struct EquivMiterPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); EquivMiterWorker worker; worker.ct.setup(design); worker.mode_trigger = false; diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index f5eb75730..2cc872182 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -85,6 +85,9 @@ struct EquivOptPass:public ScriptPass void execute(std::vector < std::string > args, RTLIL::Design * design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); string run_from, run_to; clear_flags(); diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index 5b0696d9b..a41e20c8b 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -189,6 +189,9 @@ struct EquivPurgePass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing EQUIV_PURGE pass.\n"); size_t argidx; diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc index 5d1823e12..8e5e3a288 100644 --- a/passes/equiv/equiv_remove.cc +++ b/passes/equiv/equiv_remove.cc @@ -42,6 +42,9 @@ struct EquivRemovePass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool mode_gold = false; bool mode_gate = false; int remove_count = 0; diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc index 59974a1e6..994eec09a 100644 --- a/passes/equiv/equiv_simple.cc +++ b/passes/equiv/equiv_simple.cc @@ -304,6 +304,9 @@ struct EquivSimplePass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool verbose = false, short_cones = false, model_undef = false, nogroup = false; int success_counter = 0; int max_seq = 1; diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc index b221be27c..e46b47506 100644 --- a/passes/equiv/equiv_status.cc +++ b/passes/equiv/equiv_status.cc @@ -38,6 +38,9 @@ struct EquivStatusPass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool assert_mode = false; int unproven_count = 0; diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc index 39604994a..9d87e203a 100644 --- a/passes/equiv/equiv_struct.cc +++ b/passes/equiv/equiv_struct.cc @@ -316,6 +316,9 @@ struct EquivStructPass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); pool fwonly_cells({ ID($equiv) }); bool mode_icells = false; bool mode_fwd = false; diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc index 8e7e09d4c..c8db5274c 100644 --- a/passes/fsm/fsm.cc +++ b/passes/fsm/fsm.cc @@ -79,6 +79,9 @@ struct FsmPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_nomap = false; bool flag_norecode = false; bool flag_nodetect = false; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 86d654cc4..9f85c6a31 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -287,6 +287,9 @@ struct FsmDetectPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n"); bool ignore_self_reset = false; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 239f17f36..fa0d970a6 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -281,6 +281,9 @@ struct FsmExpandPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool full_mode = false; log_header(design, "Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n"); diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 65dda1267..cd415d65d 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -145,6 +145,9 @@ struct FsmExportPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); dict::iterator attr_it; std::string arg; bool flag_noauto = false; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 62a9d309e..96bc032ad 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -419,6 +419,9 @@ struct FsmExtractPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index ff3714021..5670e3d91 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -43,6 +43,9 @@ struct FsmInfoPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index df31dbb7a..266f4d8e3 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -333,6 +333,9 @@ struct FsmMapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index f2eb06760..94800bd2d 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -337,6 +337,9 @@ struct FsmOptPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 3dc29b5a0..65e762c86 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -153,6 +153,9 @@ struct FsmRecodePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); FILE *fm_set_fsm_file = NULL; FILE *encfile = NULL; std::string default_encoding; diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 3ef04616f..1a7fbb5dc 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -819,6 +819,9 @@ struct HierarchyPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n"); bool flag_check = false; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 8476d392c..8a63c2a07 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -354,6 +354,9 @@ struct SubmodPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n"); log_push(); diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc index 49b59c8df..94f2d9dfd 100644 --- a/passes/hierarchy/uniquify.cc +++ b/passes/hierarchy/uniquify.cc @@ -43,6 +43,9 @@ struct UniquifyPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n"); size_t argidx; diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc index d5dec6198..c7c3e6ca7 100644 --- a/passes/memory/memory.cc +++ b/passes/memory/memory.cc @@ -55,6 +55,9 @@ struct MemoryPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_norom = false; bool flag_nomap = false; bool flag_nordff = false; diff --git a/passes/memory/memory_bmux2rom.cc b/passes/memory/memory_bmux2rom.cc index a3fc5a7fc..01aaf18f3 100644 --- a/passes/memory/memory_bmux2rom.cc +++ b/passes/memory/memory_bmux2rom.cc @@ -37,6 +37,9 @@ struct MemoryBmux2RomPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n"); size_t argidx; diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc index 1cb50b3ea..d0611325d 100644 --- a/passes/memory/memory_bram.cc +++ b/passes/memory/memory_bram.cc @@ -1306,6 +1306,9 @@ struct MemoryBramPass : public Pass { } void execute(vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); rules_t rules; log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n"); diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index 157042c9c..eca0c9b4f 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -37,6 +37,9 @@ struct MemoryCollectPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n"); + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); extra_args(args, 1, design); for (auto module : design->selected_modules()) { if (module->has_processes_warn()) diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index 75c6e6a3a..9e71b930b 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -643,6 +643,9 @@ struct MemoryDffPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_no_rw_check = false; log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n"); diff --git a/passes/memory/memory_libmap.cc b/passes/memory/memory_libmap.cc index 77a4eb81b..4172a44ab 100644 --- a/passes/memory/memory_libmap.cc +++ b/passes/memory/memory_libmap.cc @@ -2182,6 +2182,9 @@ struct MemoryLibMapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector lib_files; pool defines; PassOptions opts; diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index d1dd0fd88..30f22ae45 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -432,6 +432,9 @@ struct MemoryMapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool attr_icase = false; bool rom_only = false; bool keepdc = false; diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc index 22aebb43f..09d884c66 100644 --- a/passes/memory/memory_memx.cc +++ b/passes/memory/memory_memx.cc @@ -51,6 +51,9 @@ struct MemoryMemxPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n"); + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); extra_args(args, 1, design); for (auto module : design->selected_modules()) diff --git a/passes/memory/memory_narrow.cc b/passes/memory/memory_narrow.cc index 46c538bab..2b11be7ba 100644 --- a/passes/memory/memory_narrow.cc +++ b/passes/memory/memory_narrow.cc @@ -37,6 +37,9 @@ struct MemoryNarrowPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n"); size_t argidx; diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc index 3253c8f60..2a97ad35a 100644 --- a/passes/memory/memory_nordff.cc +++ b/passes/memory/memory_nordff.cc @@ -38,6 +38,9 @@ struct MemoryNordffPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from memories).\n"); size_t argidx; diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index e06989f4a..055aebf2e 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -538,6 +538,9 @@ struct MemorySharePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { bool flag_widen = true; + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_sat = true; log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n"); size_t argidx; diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 422d6fe15..093bb18b5 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -37,6 +37,9 @@ struct MemoryUnpackPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); extra_args(args, 1, design); for (auto module : design->selected_modules()) { for (auto &mem : Mem::get_selected_memories(module)) { diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc index b5e151098..fd40a2a9c 100644 --- a/passes/opt/muxpack.cc +++ b/passes/opt/muxpack.cc @@ -343,6 +343,9 @@ struct MuxpackPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n"); size_t argidx; diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc index dc88563c2..ca2ecd43e 100644 --- a/passes/opt/opt.cc +++ b/passes/opt/opt.cc @@ -66,6 +66,9 @@ struct OptPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string opt_clean_args; std::string opt_expr_args; std::string opt_reduce_args; diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index ba39b9c80..b6933eb0f 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -646,6 +646,9 @@ struct OptCleanPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool purge_mode = false; log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n"); @@ -711,6 +714,9 @@ struct CleanPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool purge_mode = false; size_t argidx; diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc index 4db3a8101..a33b452db 100644 --- a/passes/opt/opt_demorgan.cc +++ b/passes/opt/opt_demorgan.cc @@ -181,6 +181,9 @@ struct OptDemorganPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n"); int argidx = 1; diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc index b77be4515..de4bfb5aa 100644 --- a/passes/opt/opt_dff.cc +++ b/passes/opt/opt_dff.cc @@ -882,6 +882,9 @@ struct OptDffPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_DFF pass (perform DFF optimizations).\n"); OptDffOptions opt; opt.nodffe = false; diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 3eadd35c6..ecf0d2c99 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -2252,6 +2252,9 @@ struct OptExprPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool mux_undef = false; bool mux_bool = false; bool undriven = false; diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc index d982ef2d2..a945fe109 100644 --- a/passes/opt/opt_ffinv.cc +++ b/passes/opt/opt_ffinv.cc @@ -245,6 +245,9 @@ struct OptFfInvPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_FFINV pass (push inverters through FFs).\n"); size_t argidx; diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index d0fc60781..56496e288 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -543,6 +543,9 @@ struct OptLutPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n"); std::vector dlogic; diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 652fce1e2..296fccb5a 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -44,6 +44,9 @@ struct OptLutInsPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_LUT_INS pass (discard unused LUT inputs).\n"); string techname; diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index 9a2d8e6a5..39d959d98 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -38,6 +38,9 @@ struct OptMemPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_MEM pass (optimize memories).\n"); size_t argidx; diff --git a/passes/opt/opt_mem_feedback.cc b/passes/opt/opt_mem_feedback.cc index 20a2a79ed..a7560253a 100644 --- a/passes/opt/opt_mem_feedback.cc +++ b/passes/opt/opt_mem_feedback.cc @@ -338,6 +338,9 @@ struct OptMemFeedbackPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n"); + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); extra_args(args, 1, design); OptMemFeedbackWorker worker(design); diff --git a/passes/opt/opt_mem_priority.cc b/passes/opt/opt_mem_priority.cc index a9b145bea..fbbd2b8b9 100644 --- a/passes/opt/opt_mem_priority.cc +++ b/passes/opt/opt_mem_priority.cc @@ -42,6 +42,9 @@ struct OptMemPriorityPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n"); + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); extra_args(args, 1, design); ModWalker modwalker(design); diff --git a/passes/opt/opt_mem_widen.cc b/passes/opt/opt_mem_widen.cc index 95e01088c..f7bc35f7a 100644 --- a/passes/opt/opt_mem_widen.cc +++ b/passes/opt/opt_mem_widen.cc @@ -37,6 +37,9 @@ struct OptMemWidenPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n"); size_t argidx; diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc index eb3aa462e..c9fd56ac1 100644 --- a/passes/opt/opt_merge.cc +++ b/passes/opt/opt_merge.cc @@ -336,6 +336,9 @@ struct OptMergePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n"); bool mode_nomux = false; diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 100b1b495..faf448bc9 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -487,6 +487,9 @@ struct OptMuxtreePass : public Pass { } void execute(vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n"); extra_args(args, 1, design); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index c36a38dae..e3e77b6e3 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -630,6 +630,9 @@ struct OptReducePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool do_fine = false; log_header(design, "Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n"); diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index bf9569d99..2c0a5574a 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -354,6 +354,9 @@ struct OptSharePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing OPT_SHARE pass.\n"); diff --git a/passes/opt/pmux2shiftx.cc b/passes/opt/pmux2shiftx.cc index 90ddf8dd7..3adef2fc2 100644 --- a/passes/opt/pmux2shiftx.cc +++ b/passes/opt/pmux2shiftx.cc @@ -218,6 +218,9 @@ struct Pmux2ShiftxPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int min_density = 50; int min_choices = 3; bool allow_onehot = false; @@ -742,6 +745,9 @@ struct OnehotPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool verbose = false; bool verbose_onehot = false; diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc index 9fa9f5c2d..232e95c3c 100644 --- a/passes/opt/rmports.cc +++ b/passes/opt/rmports.cc @@ -41,6 +41,9 @@ struct RmportsPassPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n"); size_t argidx = 1; diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 586bd9dfe..090a48f5d 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -1442,6 +1442,9 @@ struct SharePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); ShareWorkerConfig config; config.limit = -1; diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 87a5cb56d..e91446a82 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -495,6 +495,9 @@ struct WreducePass : public Pass { } void execute(std::vector args, Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); WreduceConfig config; bool opt_memx = false; diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc index 5720c9b1e..caf684495 100644 --- a/passes/pmgen/ice40_dsp.cc +++ b/passes/pmgen/ice40_dsp.cc @@ -298,6 +298,9 @@ struct Ice40DspPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ICE40_DSP pass (map multipliers).\n"); size_t argidx; diff --git a/passes/pmgen/ice40_wrapcarry.cc b/passes/pmgen/ice40_wrapcarry.cc index c936d02dc..3cccff6da 100644 --- a/passes/pmgen/ice40_wrapcarry.cc +++ b/passes/pmgen/ice40_wrapcarry.cc @@ -93,6 +93,9 @@ struct Ice40WrapCarryPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool unwrap = false; log_header(design, "Executing ICE40_WRAPCARRY pass (wrap carries).\n"); diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index edd3b18a8..fc317d7d1 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -54,6 +54,9 @@ struct PeepoptPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n"); size_t argidx; diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index beff59778..ce8536a7d 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -241,6 +241,9 @@ struct TestPmgenPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); if (GetSize(args) > 1) { if (args[1] == "-reduce_chain") diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 72b4522d8..f00529f4f 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -770,6 +770,9 @@ struct XilinxDspPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing XILINX_DSP pass (pack resources into DSPs).\n"); std::string family = "xc7"; diff --git a/passes/pmgen/xilinx_srl.cc b/passes/pmgen/xilinx_srl.cc index eebd30017..237c56412 100644 --- a/passes/pmgen/xilinx_srl.cc +++ b/passes/pmgen/xilinx_srl.cc @@ -214,6 +214,9 @@ struct XilinxSrlPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing XILINX_SRL pass (Xilinx shift register extraction).\n"); bool fixed = false; diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index c18651d5e..4d34703c4 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -72,6 +72,9 @@ struct ProcPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string global_arst; bool ifxmode = false; bool nomux = false; diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index f01682957..251a92bf4 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -265,6 +265,9 @@ struct ProcArstPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string global_arst; bool global_arst_neg = false; diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 95cb0e88c..48b7ea930 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -192,6 +192,9 @@ struct ProcCleanPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int total_count = 0; bool quiet = false; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index fd56786f2..0b695094d 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -361,6 +361,9 @@ struct ProcDffPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n"); extra_args(args, 1, design); diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 5b392ce51..b9b0414c9 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -460,6 +460,9 @@ struct ProcDlatchPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n"); extra_args(args, 1, design); diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 4da20c395..cfea7d810 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -87,6 +87,9 @@ struct ProcInitPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PROC_INIT pass (extract init attributes).\n"); extra_args(args, 1, design); diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index cf10bd4b2..024c9c19a 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -95,6 +95,9 @@ struct ProcMemWrPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PROC_MEMWR pass (convert process memory writes to cells).\n"); extra_args(args, 1, design); diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index b209057fe..c49f35b9b 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -454,6 +454,9 @@ struct ProcMuxPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool ifxmode = false; log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n"); diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index 3433557ee..2b463d850 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -122,6 +122,9 @@ struct ProcPrunePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int total_removed_count = 0, total_promoted_count = 0; log_header(design, "Executing PROC_PRUNE pass (remove redundant assignments in processes).\n"); diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 2ec11415a..612d7d8da 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -142,6 +142,9 @@ struct ProcRmdeadPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n"); extra_args(args, 1, design); diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index ebc2377aa..c240b3d84 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -232,6 +232,9 @@ struct ProcRomPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int total_count = 0; log_header(design, "Executing PROC_ROM pass (convert switches to ROMs).\n"); diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index abdcb2240..8cbbb59d8 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -201,6 +201,9 @@ struct AssertpmuxPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_noinit = false; bool flag_always = false; diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc index 93c7e96c8..f18f63816 100644 --- a/passes/sat/async2sync.cc +++ b/passes/sat/async2sync.cc @@ -47,6 +47,9 @@ struct Async2syncPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_nolower = false; log_header(design, "Executing ASYNC2SYNC pass.\n"); diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc index bcefa7d8f..5271ec006 100644 --- a/passes/sat/clk2fflogic.cc +++ b/passes/sat/clk2fflogic.cc @@ -120,6 +120,9 @@ struct Clk2fflogicPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_nolower = false; log_header(design, "Executing CLK2FFLOGIC pass (convert clocked FFs to generic $ff cells).\n"); diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc index bca6a5ec6..009ab5ff8 100644 --- a/passes/sat/cutpoint.cc +++ b/passes/sat/cutpoint.cc @@ -40,6 +40,9 @@ struct CutpointPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_undef = false; log_header(design, "Executing CUTPOINT pass.\n"); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index acebea6c5..f2636c0b2 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -384,6 +384,9 @@ struct EvalPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector> sets; std::vector shows, tables; bool set_undef = false; diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index e7ec29ee4..bb6ed4746 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -256,6 +256,9 @@ struct ExposePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_shared = false; bool flag_evert = false; bool flag_dff = false; diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc index 220cf5c52..0820ec6b2 100644 --- a/passes/sat/fmcombine.cc +++ b/passes/sat/fmcombine.cc @@ -276,6 +276,9 @@ struct FmcombinePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); opts_t opts; Module *module = nullptr; Cell *gold_cell = nullptr; diff --git a/passes/sat/fminit.cc b/passes/sat/fminit.cc index 5f4ec0068..afa9d3cc9 100644 --- a/passes/sat/fminit.cc +++ b/passes/sat/fminit.cc @@ -49,6 +49,9 @@ struct FminitPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); vector>> initdata; vector> setdata; string clocksignal; diff --git a/passes/sat/formalff.cc b/passes/sat/formalff.cc index 0eadb69e0..e7ab62c03 100644 --- a/passes/sat/formalff.cc +++ b/passes/sat/formalff.cc @@ -542,6 +542,9 @@ struct FormalFfPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool flag_clk2ff = false; bool flag_ff2anyinit = false; bool flag_anyinit2ff = false; diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 52e80f667..5a44048d6 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -794,6 +794,9 @@ struct FreducePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); reduce_counter = 0; reduce_stop_at = 0; verbose_level = 0; diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 8f27c4c6f..ce1cf83b3 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -450,6 +450,9 @@ struct MiterPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); if (args.size() > 1 && args[1] == "-equiv") { create_miter_equiv(this, args, design); return; diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 02174be53..3bb2f5d1f 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -794,6 +794,9 @@ struct MutatePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); mutate_opts_t opts; string filename; string srcsfile; diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index db6836ea1..63b629355 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -584,6 +584,9 @@ struct QbfSatPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing QBFSAT pass (solving QBF-SAT problems in the circuit).\n"); QbfSolveOptions opt = parse_args(args); extra_args(args, opt.argidx, design); diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc index 4870e2cac..56fab5c73 100644 --- a/passes/sat/recover_names.cc +++ b/passes/sat/recover_names.cc @@ -698,6 +698,9 @@ struct RecoverNamesPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing RECOVER_NAMES pass (run mapping and recover original names).\n"); string command; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 69f81e3df..e8f2998c3 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1074,6 +1074,9 @@ struct SatPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::vector> sets, sets_init, prove, prove_x; std::map>> sets_at; std::map> unsets_at, sets_def_at, sets_any_undef_at, sets_all_undef_at; diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index aeed16b97..b3d1fbc4e 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2688,6 +2688,9 @@ struct SimPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); SimWorker worker; int numcycles = 20; int append = 0; @@ -2932,6 +2935,9 @@ struct Fst2TbPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); SimWorker worker; int numcycles = 20; bool stop_set = false; diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc index 38dbd3cf9..48260d802 100644 --- a/passes/sat/supercover.cc +++ b/passes/sat/supercover.cc @@ -37,6 +37,9 @@ struct SupercoverPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); // bool flag_noinit = false; log_header(design, "Executing SUPERCOVER pass.\n"); diff --git a/passes/sat/synthprop.cc b/passes/sat/synthprop.cc index 25416b6c4..457b8698b 100644 --- a/passes/sat/synthprop.cc +++ b/passes/sat/synthprop.cc @@ -220,6 +220,9 @@ struct SyntProperties : public Pass { virtual void execute(std::vector args, RTLIL::Design* design) { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing SYNTHPROP pass.\n"); SynthPropWorker worker(design); size_t argidx; diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index b33e1a17d..edb5d4485 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1648,6 +1648,9 @@ struct AbcPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ABC pass (technology mapping using ABC).\n"); log_push(); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index 876917e56..865ada174 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -203,6 +203,9 @@ struct Abc9Pass : public ScriptPass void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); std::string run_from, run_to; clear_flags(); diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 8e02e25a4..59a41f7e7 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -408,6 +408,9 @@ struct Abc9ExePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n"); std::string exe_file = yosys_abc_executable; diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 4eaed1f75..a2c74dd26 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -1654,6 +1654,9 @@ struct Abc9OpsPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n"); bool check_mode = false; diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc index 4836ebe34..8d3480e6f 100644 --- a/passes/techmap/aigmap.cc +++ b/passes/techmap/aigmap.cc @@ -45,6 +45,9 @@ struct AigmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool nand_mode = false, select_mode = false; log_header(design, "Executing AIGMAP pass (map logic to AIG).\n"); diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc index e4e70004c..e16256707 100644 --- a/passes/techmap/alumacc.cc +++ b/passes/techmap/alumacc.cc @@ -562,6 +562,9 @@ struct AlumaccPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n"); size_t argidx; diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc index 96e65ff2e..b801c2b3f 100644 --- a/passes/techmap/attrmap.cc +++ b/passes/techmap/attrmap.cc @@ -243,6 +243,9 @@ struct AttrmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n"); bool modattr_mode = false; @@ -319,6 +322,9 @@ struct ParamapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n"); vector> actions; diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc index 65b63daf1..43fee052e 100644 --- a/passes/techmap/attrmvcp.cc +++ b/passes/techmap/attrmvcp.cc @@ -55,6 +55,9 @@ struct AttrmvcpPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n"); bool copy_mode = false; diff --git a/passes/techmap/bmuxmap.cc b/passes/techmap/bmuxmap.cc index 7aa67d3c0..e60cdfaf0 100644 --- a/passes/techmap/bmuxmap.cc +++ b/passes/techmap/bmuxmap.cc @@ -39,6 +39,9 @@ struct BmuxmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool pmux_mode = false; log_header(design, "Executing BMUXMAP pass.\n"); diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc index 09c20b507..62a09a924 100644 --- a/passes/techmap/booth.cc +++ b/passes/techmap/booth.cc @@ -1155,6 +1155,9 @@ struct BoothPass : public Pass { } void execute(vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n"); size_t argidx; diff --git a/passes/techmap/bwmuxmap.cc b/passes/techmap/bwmuxmap.cc index 7fe1cded7..fc6fc2e08 100644 --- a/passes/techmap/bwmuxmap.cc +++ b/passes/techmap/bwmuxmap.cc @@ -35,6 +35,9 @@ struct BwmuxmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing BWMUXMAP pass.\n"); size_t argidx; diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index a21a4fbad..047bdfad3 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -158,6 +158,9 @@ struct CellmatchPass : Pass { } void execute(std::vector args, RTLIL::Design *d) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(d, "Executing CELLMATCH pass. (match cells)\n"); size_t argidx; diff --git a/passes/techmap/clkbufmap.cc b/passes/techmap/clkbufmap.cc index a7b96a9c6..5bea83a31 100644 --- a/passes/techmap/clkbufmap.cc +++ b/passes/techmap/clkbufmap.cc @@ -79,6 +79,9 @@ struct ClkbufmapPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing CLKBUFMAP pass (inserting clock buffers).\n"); std::string buf_celltype, buf_portname, buf_portname2; diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc index 5245331f8..ca1c35a73 100644 --- a/passes/techmap/deminout.cc +++ b/passes/techmap/deminout.cc @@ -35,6 +35,9 @@ struct DeminoutPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n"); size_t argidx; diff --git a/passes/techmap/demuxmap.cc b/passes/techmap/demuxmap.cc index 292b18bad..650cf570d 100644 --- a/passes/techmap/demuxmap.cc +++ b/passes/techmap/demuxmap.cc @@ -36,6 +36,9 @@ struct DemuxmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing DEMUXMAP pass.\n"); size_t argidx; diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc index 9cfe55947..ae383b3a8 100644 --- a/passes/techmap/dffinit.cc +++ b/passes/techmap/dffinit.cc @@ -57,6 +57,9 @@ struct DffinitPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n"); dict> ff_types; diff --git a/passes/techmap/dfflegalize.cc b/passes/techmap/dfflegalize.cc index 64f07b708..6acf2374c 100644 --- a/passes/techmap/dfflegalize.cc +++ b/passes/techmap/dfflegalize.cc @@ -1013,6 +1013,9 @@ struct DffLegalizePass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n"); diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 78bfe1586..98fb827a2 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -467,6 +467,9 @@ struct DfflibmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n"); log_push(); diff --git a/passes/techmap/dffunmap.cc b/passes/techmap/dffunmap.cc index 8703bf1a0..20b4e93c5 100644 --- a/passes/techmap/dffunmap.cc +++ b/passes/techmap/dffunmap.cc @@ -45,6 +45,9 @@ struct DffunmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs).\n"); bool ce_only = false; diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 137d22170..c3f83bb5f 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -436,6 +436,9 @@ struct ExtractPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n"); log_push(); diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index b780f7df0..08dac523c 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -788,6 +788,9 @@ struct ExtractCounterPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n"); pool _parallel_cells; diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index ec1979f3b..f1a171325 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -563,6 +563,9 @@ struct ExtractFaPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); ExtractFaConfig config; log_header(design, "Executing EXTRACT_FA pass (find and extract full/half adders).\n"); diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc index 892e9a364..e8838f010 100644 --- a/passes/techmap/extract_reduce.cc +++ b/passes/techmap/extract_reduce.cc @@ -65,6 +65,9 @@ struct ExtractReducePass : public Pass void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing EXTRACT_REDUCE pass.\n"); log_push(); diff --git a/passes/techmap/extractinv.cc b/passes/techmap/extractinv.cc index 48d9600fa..51072dd5f 100644 --- a/passes/techmap/extractinv.cc +++ b/passes/techmap/extractinv.cc @@ -59,6 +59,9 @@ struct ExtractinvPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n"); std::string inv_celltype, inv_portname, inv_portname2; diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc index ea5855a09..5d62345ac 100644 --- a/passes/techmap/flatten.cc +++ b/passes/techmap/flatten.cc @@ -348,6 +348,9 @@ struct FlattenPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing FLATTEN pass (flatten design).\n"); log_push(); diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 579503a0b..1e2c363ae 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1514,6 +1514,9 @@ struct FlowmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); int order = 3; int minlut = 1; vector cells; diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index c1b947221..6fedfb562 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -76,6 +76,9 @@ struct HilomapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n"); hicell_celltype = std::string(); diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc index f288987a1..db683fbaf 100644 --- a/passes/techmap/insbuf.cc +++ b/passes/techmap/insbuf.cc @@ -42,6 +42,9 @@ struct InsbufPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n"); IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y; diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 322eb7779..d40dfcef4 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -101,6 +101,9 @@ struct IopadmapPass : public Pass { void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n"); std::string inpad_celltype, inpad_portname_o, inpad_portname_pad; diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc index ef76e0deb..8364f2636 100644 --- a/passes/techmap/lut2mux.cc +++ b/passes/techmap/lut2mux.cc @@ -67,6 +67,9 @@ struct Lut2muxPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n"); size_t argidx; diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc index 2235bdef9..b458091b2 100644 --- a/passes/techmap/maccmap.cc +++ b/passes/techmap/maccmap.cc @@ -377,6 +377,9 @@ struct MaccmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool unmap_mode = false; log_header(design, "Executing MACCMAP pass (map $macc cells).\n"); diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc index 2656f30ce..22773b911 100644 --- a/passes/techmap/muxcover.cc +++ b/passes/techmap/muxcover.cc @@ -655,6 +655,9 @@ struct MuxcoverPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n"); bool use_mux4 = false; diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc index 016789157..bf2873e13 100644 --- a/passes/techmap/nlutmap.cc +++ b/passes/techmap/nlutmap.cc @@ -151,6 +151,9 @@ struct NlutmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); NlutmapConfig config; log_header(design, "Executing NLUTMAP pass (mapping to constant drivers).\n"); diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc index ff6bb549b..c166c8478 100644 --- a/passes/techmap/pmuxtree.cc +++ b/passes/techmap/pmuxtree.cc @@ -78,6 +78,9 @@ struct PmuxtreePass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing PMUXTREE pass.\n"); size_t argidx; diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc index 928182970..b50c20ad0 100644 --- a/passes/techmap/shregmap.cc +++ b/passes/techmap/shregmap.cc @@ -434,6 +434,9 @@ struct ShregmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); ShregmapOptions opts; string clkpol, enpol; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 7461460fe..5c5f56f43 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -490,6 +490,9 @@ struct SimplemapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n"); extra_args(args, 1, design); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 64de3a1ca..2eec37dfa 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -1152,6 +1152,9 @@ struct TechmapPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); log_header(design, "Executing TECHMAP pass (map to technology primitives).\n"); log_push(); diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc index b45cd268a..9f58727e4 100644 --- a/passes/techmap/tribuf.cc +++ b/passes/techmap/tribuf.cc @@ -201,6 +201,9 @@ struct TribufPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); TribufConfig config; log_header(design, "Executing TRIBUF pass.\n"); diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc index cc208c516..655b0fd32 100644 --- a/passes/techmap/zinit.cc +++ b/passes/techmap/zinit.cc @@ -41,6 +41,9 @@ struct ZinitPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { + ZoneScoped; + ZoneText(pass_name.c_str(), pass_name.length()); + ZoneColor((uint32_t)(size_t)pass_name.c_str()); bool all_mode = false; log_header(design, "Executing ZINIT pass (make all FFs zero-initialized).\n"); diff --git a/tracy b/tracy new file mode 160000 index 000000000..37aff70df --- /dev/null +++ b/tracy @@ -0,0 +1 @@ +Subproject commit 37aff70dfa50cf6307b3fee6074d627dc2929143