tracy: init, zones per pass execute method, pointer-colored

passes/techmap/abc.cc

@@ -1648,6 +1648,9 @@ struct AbcPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
 		log_push();
 

passes/techmap/abc9.cc

@@ -203,6 +203,9 @@ struct Abc9Pass : public ScriptPass
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string run_from, run_to;
 		clear_flags();
 

passes/techmap/abc9_exe.cc

@@ -408,6 +408,9 @@ struct Abc9ExePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing ABC9_EXE pass (technology mapping using ABC9).\n");
 
 		std::string exe_file = yosys_abc_executable;

passes/techmap/abc9_ops.cc

@@ -1654,6 +1654,9 @@ struct Abc9OpsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing ABC9_OPS pass (helper functions for ABC9).\n");
 
 		bool check_mode = false;

passes/techmap/aigmap.cc

@@ -45,6 +45,9 @@ struct AigmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool nand_mode = false, select_mode = false;
 
 		log_header(design, "Executing AIGMAP pass (map logic to AIG).\n");

passes/techmap/alumacc.cc

@@ -562,6 +562,9 @@ struct AlumaccPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
 
 		size_t argidx;

passes/techmap/attrmap.cc

@@ -243,6 +243,9 @@ struct AttrmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n");
 
 		bool modattr_mode = false;
@@ -319,6 +322,9 @@ struct ParamapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing PARAMAP pass (move or copy cell parameters).\n");
 
 		vector<std::unique_ptr<AttrmapAction>> actions;

passes/techmap/attrmvcp.cc

@@ -55,6 +55,9 @@ struct AttrmvcpPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
 
 		bool copy_mode = false;

passes/techmap/bmuxmap.cc

@@ -39,6 +39,9 @@ struct BmuxmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool pmux_mode = false;
 
 		log_header(design, "Executing BMUXMAP pass.\n");

passes/techmap/booth.cc

@@ -1155,6 +1155,9 @@ struct BoothPass : public Pass {
 	}
 	void execute(vector<string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n");
 
 		size_t argidx;

passes/techmap/bwmuxmap.cc

@@ -35,6 +35,9 @@ struct BwmuxmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing BWMUXMAP pass.\n");
 
 		size_t argidx;

passes/techmap/cellmatch.cc

@@ -158,6 +158,9 @@ struct CellmatchPass : Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *d) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(d, "Executing CELLMATCH pass. (match cells)\n");
 
 		size_t argidx;

passes/techmap/clkbufmap.cc

@@ -79,6 +79,9 @@ struct ClkbufmapPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing CLKBUFMAP pass (inserting clock buffers).\n");
 
 		std::string buf_celltype, buf_portname, buf_portname2;

passes/techmap/deminout.cc

@@ -35,6 +35,9 @@ struct DeminoutPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n");
 
 		size_t argidx;

passes/techmap/demuxmap.cc

@@ -36,6 +36,9 @@ struct DemuxmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing DEMUXMAP pass.\n");
 
 		size_t argidx;

passes/techmap/dffinit.cc

@@ -57,6 +57,9 @@ struct DffinitPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
 
 		dict<IdString, dict<IdString, IdString>> ff_types;

passes/techmap/dfflegalize.cc

@@ -1013,6 +1013,9 @@ struct DffLegalizePass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 
 		log_header(design, "Executing DFFLEGALIZE pass (convert FFs to types supported by the target).\n");
 

passes/techmap/dfflibmap.cc

@@ -467,6 +467,9 @@ struct DfflibmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
 		log_push();
 

passes/techmap/dffunmap.cc

@@ -45,6 +45,9 @@ struct DffunmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs).\n");
 
 		bool ce_only = false;

passes/techmap/extract.cc

@@ -436,6 +436,9 @@ struct ExtractPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
 		log_push();
 

passes/techmap/extract_counter.cc

@@ -788,6 +788,9 @@ struct ExtractCounterPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n");
 
 		pool<RTLIL::IdString> _parallel_cells;

passes/techmap/extract_fa.cc

@@ -563,6 +563,9 @@ struct ExtractFaPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		ExtractFaConfig config;
 
 		log_header(design, "Executing EXTRACT_FA pass (find and extract full/half adders).\n");

passes/techmap/extract_reduce.cc

@@ -65,6 +65,9 @@ struct ExtractReducePass : public Pass
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing EXTRACT_REDUCE pass.\n");
 		log_push();
 

passes/techmap/extractinv.cc

@@ -59,6 +59,9 @@ struct ExtractinvPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing EXTRACTINV pass (extracting pin inverters).\n");
 
 		std::string inv_celltype, inv_portname, inv_portname2;

passes/techmap/flatten.cc

@@ -348,6 +348,9 @@ struct FlattenPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing FLATTEN pass (flatten design).\n");
 		log_push();
 

passes/techmap/flowmap.cc

@@ -1514,6 +1514,9 @@ struct FlowmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		int order = 3;
 		int minlut = 1;
 		vector<string> cells;

passes/techmap/hilomap.cc

@@ -76,6 +76,9 @@ struct HilomapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
 
 		hicell_celltype = std::string();

passes/techmap/insbuf.cc

@@ -42,6 +42,9 @@ struct InsbufPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
 
 		IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;

passes/techmap/iopadmap.cc

@@ -101,6 +101,9 @@ struct IopadmapPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
 
 		std::string inpad_celltype, inpad_portname_o, inpad_portname_pad;

passes/techmap/lut2mux.cc

@@ -67,6 +67,9 @@ struct Lut2muxPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
 
 		size_t argidx;

passes/techmap/maccmap.cc

@@ -377,6 +377,9 @@ struct MaccmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool unmap_mode = false;
 
 		log_header(design, "Executing MACCMAP pass (map $macc cells).\n");

passes/techmap/muxcover.cc

@@ -655,6 +655,9 @@ struct MuxcoverPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n");
 
 		bool use_mux4 = false;

passes/techmap/nlutmap.cc

@@ -151,6 +151,9 @@ struct NlutmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		NlutmapConfig config;
 
 		log_header(design, "Executing NLUTMAP pass (mapping to constant drivers).\n");

passes/techmap/pmuxtree.cc

@@ -78,6 +78,9 @@ struct PmuxtreePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing PMUXTREE pass.\n");
 
 		size_t argidx;

passes/techmap/shregmap.cc

@@ -434,6 +434,9 @@ struct ShregmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		ShregmapOptions opts;
 		string clkpol, enpol;
 

passes/techmap/simplemap.cc

@@ -490,6 +490,9 @@ struct SimplemapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 		extra_args(args, 1, design);
 

passes/techmap/techmap.cc

@@ -1152,6 +1152,9 @@ struct TechmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
 		log_push();
 

passes/techmap/tribuf.cc

@@ -201,6 +201,9 @@ struct TribufPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		TribufConfig config;
 
 		log_header(design, "Executing TRIBUF pass.\n");

passes/techmap/zinit.cc

@@ -41,6 +41,9 @@ struct ZinitPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool all_mode = false;
 
 		log_header(design, "Executing ZINIT pass (make all FFs zero-initialized).\n");