tracy: init, zones per pass execute method, pointer-colored

passes/opt/muxpack.cc

@@ -343,6 +343,9 @@ struct MuxpackPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
 
 		size_t argidx;

passes/opt/opt.cc

@@ -66,6 +66,9 @@ struct OptPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		std::string opt_clean_args;
 		std::string opt_expr_args;
 		std::string opt_reduce_args;

passes/opt/opt_clean.cc

@@ -646,6 +646,9 @@ struct OptCleanPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool purge_mode = false;
 
 		log_header(design, "Executing OPT_CLEAN pass (remove unused cells and wires).\n");
@@ -711,6 +714,9 @@ struct CleanPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool purge_mode = false;
 
 		size_t argidx;

passes/opt/opt_demorgan.cc

@@ -181,6 +181,9 @@ struct OptDemorganPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
 
 		int argidx = 1;

passes/opt/opt_dff.cc

@@ -882,6 +882,9 @@ struct OptDffPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_DFF pass (perform DFF optimizations).\n");
 		OptDffOptions opt;
 		opt.nodffe = false;

passes/opt/opt_expr.cc

@@ -2252,6 +2252,9 @@ struct OptExprPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool mux_undef = false;
 		bool mux_bool = false;
 		bool undriven = false;

passes/opt/opt_ffinv.cc

@@ -245,6 +245,9 @@ struct OptFfInvPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_FFINV pass (push inverters through FFs).\n");
 
 		size_t argidx;

passes/opt/opt_lut.cc

@@ -543,6 +543,9 @@ struct OptLutPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
 
 		std::vector<dlogic_t> dlogic;

passes/opt/opt_lut_ins.cc

@@ -44,6 +44,9 @@ struct OptLutInsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_LUT_INS pass (discard unused LUT inputs).\n");
 		string techname;
 

passes/opt/opt_mem.cc

@@ -38,6 +38,9 @@ struct OptMemPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MEM pass (optimize memories).\n");
 
 		size_t argidx;

passes/opt/opt_mem_feedback.cc

@@ -338,6 +338,9 @@ struct OptMemFeedbackPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 		OptMemFeedbackWorker worker(design);
 

passes/opt/opt_mem_priority.cc

@@ -42,6 +42,9 @@ struct OptMemPriorityPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override {
 		log_header(design, "Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).\n");
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		extra_args(args, 1, design);
 
 		ModWalker modwalker(design);

passes/opt/opt_mem_widen.cc

@@ -37,6 +37,9 @@ struct OptMemWidenPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n");
 
 		size_t argidx;

passes/opt/opt_merge.cc

@@ -336,6 +336,9 @@ struct OptMergePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
 
 		bool mode_nomux = false;

passes/opt/opt_muxtree.cc

@@ -487,6 +487,9 @@ struct OptMuxtreePass : public Pass {
 	}
 	void execute(vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
 		extra_args(args, 1, design);
 

passes/opt/opt_reduce.cc

@@ -630,6 +630,9 @@ struct OptReducePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool do_fine = false;
 
 		log_header(design, "Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");

passes/opt/opt_share.cc

@@ -354,6 +354,9 @@ struct OptSharePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 
 		log_header(design, "Executing OPT_SHARE pass.\n");
 

passes/opt/pmux2shiftx.cc

@@ -218,6 +218,9 @@ struct Pmux2ShiftxPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		int min_density = 50;
 		int min_choices = 3;
 		bool allow_onehot = false;
@@ -742,6 +745,9 @@ struct OnehotPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		bool verbose = false;
 		bool verbose_onehot = false;
 

passes/opt/rmports.cc

@@ -41,6 +41,9 @@ struct RmportsPassPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
 
 		size_t argidx = 1;

passes/opt/share.cc

@@ -1442,6 +1442,9 @@ struct SharePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		ShareWorkerConfig config;
 
 		config.limit = -1;

passes/opt/wreduce.cc

@@ -495,6 +495,9 @@ struct WreducePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, Design *design) override
 	{
+		ZoneScoped;
+		ZoneText(pass_name.c_str(), pass_name.length());
+		ZoneColor((uint32_t)(size_t)pass_name.c_str());
 		WreduceConfig config;
 		bool opt_memx = false;