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tracy: init, zones per pass execute method, pointer-colored

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This commit is contained in:
Emil J. Tywoniak 2024-05-28 23:51:17 +02:00
parent 5579685673
commit 0fb3f3a78e
180 changed files with 567 additions and 4 deletions
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3
passes/memory/memory.cc
View file

@ -55,6 +55,9 @@ struct MemoryPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
bool flag_norom = false;
bool flag_nomap = false;
bool flag_nordff = false;

3
passes/memory/memory_bmux2rom.cc
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@ -37,6 +37,9 @@ struct MemoryBmux2RomPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n");
size_t argidx;

3
passes/memory/memory_bram.cc
View file

@ -1306,6 +1306,9 @@ struct MemoryBramPass : public Pass {
}
void execute(vector<string> args, Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
rules_t rules;
log_header(design, "Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");

3
passes/memory/memory_collect.cc
View file

@ -37,6 +37,9 @@ struct MemoryCollectPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
extra_args(args, 1, design);
for (auto module : design->selected_modules()) {
if (module->has_processes_warn())

3
passes/memory/memory_dff.cc
View file

@ -643,6 +643,9 @@ struct MemoryDffPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
bool flag_no_rw_check = false;
log_header(design, "Executing MEMORY_DFF pass (merging $dff cells to $memrd).\n");

3
passes/memory/memory_libmap.cc
View file

@ -2182,6 +2182,9 @@ struct MemoryLibMapPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
std::vector<std::string> lib_files;
pool<std::string> defines;
PassOptions opts;

3
passes/memory/memory_map.cc
View file

@ -432,6 +432,9 @@ struct MemoryMapPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
bool attr_icase = false;
bool rom_only = false;
bool keepdc = false;

3
passes/memory/memory_memx.cc
View file

@ -51,6 +51,9 @@ struct MemoryMemxPass : public Pass {
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_MEMX pass (emit soft logic for out-of-bounds handling).\n");
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
extra_args(args, 1, design);
for (auto module : design->selected_modules())

3
passes/memory/memory_narrow.cc
View file

@ -37,6 +37,9 @@ struct MemoryNarrowPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
size_t argidx;

3
passes/memory/memory_nordff.cc
View file

@ -38,6 +38,9 @@ struct MemoryNordffPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from memories).\n");
size_t argidx;

3
passes/memory/memory_share.cc
View file

@ -538,6 +538,9 @@ struct MemorySharePass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
bool flag_widen = true;
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
bool flag_sat = true;
log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
size_t argidx;

3
passes/memory/memory_unpack.cc
View file

@ -37,6 +37,9 @@ struct MemoryUnpackPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
ZoneScoped;
ZoneText(pass_name.c_str(), pass_name.length());
ZoneColor((uint32_t)(size_t)pass_name.c_str());
extra_args(args, 1, design);
for (auto module : design->selected_modules()) {
for (auto &mem : Mem::get_selected_memories(module)) {