3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-01-20 17:14:44 +00:00

fix indentation

This commit is contained in:
Dhaval Chaudhari 2026-01-04 02:01:50 +05:30
parent 2c5d79d441
commit 0f279eef41

View file

@ -3695,9 +3695,9 @@ struct VerificPass : public Pass {
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") {
for (argidx++; argidx < GetSize(args); argidx++) {
#ifdef VERIFIC_VHDL_SUPPORT
#ifdef VERIFIC_VHDL_SUPPORT
vhdl_file::SetDefaultLibraryPath(args[argidx].c_str());
#endif
#endif
}
goto check_error;
}