3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00

Merge pull request #17 from alaindargelas/rtlil_dump

RTLIL Module dump and hash
This commit is contained in:
Akash Levy 2024-11-06 16:41:37 -08:00 committed by GitHub
commit 0d57928548
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 19 additions and 0 deletions

View file

@ -27,6 +27,7 @@
#include "backends/rtlil/rtlil_backend.h"
#include <string.h>
#include <strstream>
#include <algorithm>
#include <optional>
@ -2508,6 +2509,21 @@ void RTLIL::Module::swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2)
wires_[w2->name] = w2;
}
// Returns the RTLIL dump of a module
std::string RTLIL::Module::rtlil_dump() {
// Sorting the module to have a canonical RTLIL
sort();
// Dumping the RTLIL in an in-memory stringstream
std::stringstream stream;
RTLIL_BACKEND::dump_module(stream, " ", this, design, false, true, false);
return stream.str();
}
// Returns a hash of the RTLIL dump
unsigned int RTLIL::Module::rtlil_hash() {
return hash_ops<std::string>::hash(rtlil_dump());
}
void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
{
log_assert(cells_[c1->name] == c1);

View file

@ -1591,6 +1591,9 @@ public:
RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const std::string &src = "");
RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, const std::string &src = "");
std::string rtlil_dump();
unsigned int rtlil_hash();
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Module*> *get_all_modules(void);
#endif