3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-27 10:35:40 +00:00

Merge pull request #5564 from rocallahan/pass-fuzz

Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
This commit is contained in:
Emil J 2026-01-06 20:07:31 +01:00 committed by GitHub
commit 0ab967b036
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
9 changed files with 733 additions and 20 deletions

View file

@ -3039,6 +3039,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
}
}
void RTLIL::Module::remove(RTLIL::Memory *memory)
{
log_assert(memories.count(memory->name) != 0);
memories.erase(memory->name);
delete memory;
}
void RTLIL::Module::remove(RTLIL::Process *process)
{
log_assert(processes.count(process->name) != 0);

View file

@ -2137,6 +2137,8 @@ public:
}
RTLIL::ObjRange<RTLIL::Wire*> wires() { return RTLIL::ObjRange<RTLIL::Wire*>(&wires_, &refcount_wires_); }
int wires_size() const { return wires_.size(); }
RTLIL::Wire* wire_at(int index) const { return wires_.element(index)->second; }
RTLIL::ObjRange<RTLIL::Cell*> cells() { return RTLIL::ObjRange<RTLIL::Cell*>(&cells_, &refcount_cells_); }
void add(RTLIL::Binding *binding);
@ -2144,6 +2146,7 @@ public:
// Removing wires is expensive. If you have to remove wires, remove them all at once.
void remove(const pool<RTLIL::Wire*> &wires);
void remove(RTLIL::Cell *cell);
void remove(RTLIL::Memory *memory);
void remove(RTLIL::Process *process);
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);