From 0a15a23e8fc2d9c31673005c06b8e205bcdbbb5c Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Thu, 20 Mar 2025 12:31:59 +0100
Subject: [PATCH] opt_expr: neater variable names, avoid shadowing

---
 passes/opt/opt_expr.cc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index fad01ef10..d9da82d4e 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -491,11 +491,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 	}
 
 	std::vector<Cell*> module_cells = module->cells();
-	auto iterator = [&](auto&& replace_cell) {
+	auto visitor = [&](auto&& do_action) {
 		if (sort_fails >= effort) {
 			for (auto cell : module_cells)
 				if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type))
-					replace_cell(cell);
+				do_action(cell);
 		} else {
 			TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
 			dict<RTLIL::SigBit, Cell*> outbit_to_cell;
@@ -529,11 +529,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						effort, log_id(module));
 			}
 			for (auto cell : cells.sorted) {
-				replace_cell(cell);
+				do_action(cell);
 			}
 		}
 	};
-	iterator([&](auto& cell)
+	visitor([&](auto& cell)
 	{
 #define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
 #define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))