From f67d4bcfa4893c51d1f314bc60a1d4923e5de3f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Mar 2024 15:19:17 +0100 Subject: [PATCH 1/3] verilog: Do not set `module_not_derived` on internal cells --- frontends/ast/genrtlil.cc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 86ea70b51..d9eb51a9c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -2085,8 +2085,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) check_unique_id(current_module, id, this, "cell"); RTLIL::Cell *cell = current_module->addCell(id, ""); set_src_attr(cell, this); - // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass - cell->set_bool_attribute(ID::module_not_derived); for (auto it = children.begin(); it != children.end(); it++) { auto* child = it->get(); @@ -2149,6 +2147,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) } log_abort(); } + + // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass + if (cell->type.isPublic()) + cell->set_bool_attribute(ID::module_not_derived); + for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) input_error("Attribute `%s' with non-constant value.\n", attr.first); From 90673cb0a261c0a8032cab8d2e44a5f4c16945d3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 7 Mar 2024 15:20:15 +0100 Subject: [PATCH 2/3] techmap: Use `-icells` mode of frontend instead of type fixup --- passes/techmap/techmap.cc | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index b49a40704..cf7ce56e2 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -333,9 +333,6 @@ struct TechmapWorker RTLIL::Cell *c = module->addCell(c_name, tpl_cell); design->select(module, c); - - if (c->type.begins_with("\\$")) - c->type = c->type.substr(1); if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype)) { c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype)); @@ -436,13 +433,9 @@ struct TechmapWorker if (handled_cells.count(cell) > 0) continue; - std::string cell_type = cell->type.str(); - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - if (celltypeMap.count(cell_type) == 0) { - if (assert_mode && cell_type.back() != '_') - log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell_type)); + if (celltypeMap.count(cell->type) == 0) { + if (assert_mode && !cell->type.ends_with("_")) + log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type)); continue; } @@ -454,7 +447,7 @@ struct TechmapWorker if (GetSize(sig) == 0) continue; - for (auto &tpl_name : celltypeMap.at(cell_type)) { + for (auto &tpl_name : celltypeMap.at(cell->type)) { RTLIL::Module *tpl = map->module(tpl_name); RTLIL::Wire *port = tpl->wire(conn.first); if (port && port->port_input) @@ -481,12 +474,7 @@ struct TechmapWorker log_assert(cell == module->cell(cell->name)); bool mapped_cell = false; - std::string cell_type = cell->type.str(); - - if (in_recursion && cell->type.begins_with("\\$")) - cell_type = cell_type.substr(1); - - for (auto &tpl_name : celltypeMap.at(cell_type)) + for (auto &tpl_name : celltypeMap.at(cell->type)) { IdString derived_name = tpl_name; RTLIL::Module *tpl = map->module(tpl_name); @@ -508,8 +496,6 @@ struct TechmapWorker if (!extmapper_name.empty()) { - cell->type = cell_type; - if ((extern_mode && !in_recursion) || extmapper_name == "wrap") { std::string m_name = stringf("$extern:%s:%s", extmapper_name, log_id(cell->type)); @@ -935,11 +921,6 @@ struct TechmapWorker RTLIL::Module *m = design->addModule(m_name); tpl->cloneInto(m); - for (auto cell : m->cells()) { - if (cell->type.begins_with("\\$")) - cell->type = cell->type.substr(1); - } - module_queue.insert(m); } @@ -1168,7 +1149,7 @@ struct TechmapPass : public Pass { std::vector map_files; std::vector dont_map; - std::string verilog_frontend = "verilog -nooverwrite -noblackbox"; + std::string verilog_frontend = "verilog -nooverwrite -noblackbox -icells"; int max_iter = -1; size_t argidx; From 491276983ee1bd1004acd4e6fea71c2976b83732 Mon Sep 17 00:00:00 2001 From: Gus Smith Date: Mon, 19 Jan 2026 18:34:55 -0800 Subject: [PATCH 3/3] Add test --- tests/techmap/module_not_derived.ys | 31 +++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 tests/techmap/module_not_derived.ys diff --git a/tests/techmap/module_not_derived.ys b/tests/techmap/module_not_derived.ys new file mode 100644 index 000000000..299e4b75b --- /dev/null +++ b/tests/techmap/module_not_derived.ys @@ -0,0 +1,31 @@ +# Test 1: internal cells from alumacc/techmap must not keep module_not_derived. +read_verilog <