Move rename logic to abc_ops_reintegrate

tests/various/abc9.v

@@ -1,15 +1,3 @@
-module abc9_test027(output reg o);
-initial o = 1'b0;
-always @*
-    o <= ~o;
-endmodule
-
-module abc9_test028(input i, output o);
-wire w;
-unknown u(~i, w);
-unknown2 u2(w, o);
-endmodule
-
 module abc9_test032(input clk, d, r, output reg q);
 initial q = 1'b0;
 always @(negedge clk or negedge r)

tests/various/abc9.ys

@@ -1,31 +1,4 @@
 read_verilog abc9.v
-design -save read
-hierarchy -top abc9_test027
-proc
-design -save gold
-
-abc9 -lut 4
-check
-design -stash gate
-
-design -import gold -as gold
-design -import gate -as gate
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
-
-
-design -load read
-hierarchy -top abc9_test028
-proc
-
-abc9 -lut 4
-select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
-select -assert-count 1 t:unknown
-select -assert-none t:$lut t:unknown %% t: %D
-
-
-design -load read
 hierarchy -top abc9_test032
 proc
 clk2fflogic