mirror of
https://github.com/YosysHQ/yosys
synced 2026-06-26 18:48:51 +00:00
6 lines
155 B
Verilog
6 lines
155 B
Verilog
module abc9_test032(input clk, d, r, output reg q);
|
|
initial q = 1'b0;
|
|
always @(negedge clk or negedge r)
|
|
if (!r) q <= 1'b0;
|
|
else q <= d;
|
|
endmodule
|