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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
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5 changed files with 376 additions and 5 deletions
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@ -1,3 +1,4 @@
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# ================================ RAM ================================
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# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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@ -46,6 +47,13 @@ setattr -set ram_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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setattr -set logic_block 1 m:memory
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@ -67,6 +75,7 @@ synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested BROM but this is a RAM
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select -assert-min 1 t:SB_DFFE
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# ================================ ROM ================================
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# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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@ -110,6 +119,13 @@ setattr -set rom_block 1 m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
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select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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setattr -set logic_block 1 m:memory
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