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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.

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This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
  * LSE supports both `syn_ramstyle` and `syn_romstyle`.
  * Synplify only supports `syn_ramstyle`, with same values as LSE.
  * Synplify also supports `syn_rw_conflict_logic`, which is not
    documented as supported for LSE.

Limitations of the Yosys implementation:
  * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
    syntax to turn off insertion of transparency logic. There is
    currently no way to support multiple valued attributes in
    memory_bram. It is also not clear if that is a good idea, since
    it can cause sim/synth mismatches.
  * LSE/Synplify/1364.1 support block ROM inference from full case
    statements. Yosys does not currently perform this transformation.
  * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
    from the module to the inner memories. There is currently no way
    to do this in Yosys (attrmvcp only works on cells and wires).
This commit is contained in:
whitequark 2020-01-01 08:27:47 +00:00
parent 3f4460a186
commit 081d9318bc
5 changed files with 376 additions and 5 deletions
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62
techlibs/ecp5/brams.txt
View file

@ -37,7 +37,17 @@ bram $__ECP5_DP16KD
clkpol 2 3
endbram
# The syn_* attributes are described in:
# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
attr_icase 1
match $__ECP5_PDPW16KD
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 2048
min efficiency 5
shuffle_enable A
@ -45,8 +55,60 @@ match $__ECP5_PDPW16KD
or_next_if_better
endmatch
match $__ECP5_PDPW16KD
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__ECP5_PDPW16KD
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
make_transp
or_next_if_better
endmatch
match $__ECP5_DP16KD
# implicitly requested RAM or ROM
attribute !syn_ramstyle syn_ramstyle=auto
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
min bits 2048
min efficiency 5
shuffle_enable A
or_next_if_better
endmatch
match $__ECP5_DP16KD
# explicitly requested RAM
attribute syn_ramstyle=block_ram ram_block
attribute !syn_romstyle
attribute !rom_block
attribute !logic_block
min wports 1
shuffle_enable A
or_next_if_better
endmatch
match $__ECP5_DP16KD
# explicitly requested ROM
attribute syn_romstyle=ebr rom_block
attribute !syn_ramstyle
attribute !ram_block
attribute !logic_block
max wports 0
shuffle_enable A
endmatch

9
techlibs/ecp5/lutrams.txt
View file

@ -11,7 +11,16 @@ bram $__TRELLIS_DPR16X4
clkpol 0 2
endbram
# The syn_* attributes are described in:
# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
attr_icase 1
match $__TRELLIS_DPR16X4
attribute !syn_ramstyle syn_ramstyle=auto syn_ramstyle=distributed
attribute !syn_romstyle syn_romstyle=auto
attribute !ram_block
attribute !rom_block
attribute !logic_block
make_outreg
min wports 1
endmatch