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Add "read -undef"

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-06-28 23:43:38 +02:00
parent fe2ee833e1
commit 07e616900c
1 changed files with 32 additions and 0 deletions
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32
frontends/verific/verific.cc
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@ -1715,6 +1715,11 @@ struct VerificPass : public Pass {
log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n"); log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
log("\n"); log("\n");
log("\n"); log("\n");
log(" verific -vlog-undef <macro>..\n");
log("\n");
log("Remove Verilog defines previously set with -vlog-define.\n");
log("\n");
log("\n");
log(" verific -import [options] <top-module>..\n"); log(" verific -import [options] <top-module>..\n");
log("\n"); log("\n");
log("Elaborate the design for the specified top modules, import to Yosys and\n"); log("Elaborate the design for the specified top modules, import to Yosys and\n");
@ -1828,6 +1833,14 @@ struct VerificPass : public Pass {
goto check_error; goto check_error;
} }
if (GetSize(args) > argidx && args[argidx] == "-vlog-undef") {
for (argidx++; argidx < GetSize(args); argidx++) {
string name = args[argidx];
veri_file::UndefineMacro(name.c_str());
}
goto check_error;
}
if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" || if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv")) args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv"))
{ {
@ -2139,6 +2152,11 @@ struct ReadPass : public Pass {
log("\n"); log("\n");
log("Set global Verilog/SystemVerilog defines.\n"); log("Set global Verilog/SystemVerilog defines.\n");
log("\n"); log("\n");
log("\n");
log(" read -undef <macro>..\n");
log("\n");
log("Unset global Verilog/SystemVerilog defines.\n");
log("\n");
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
@ -2200,6 +2218,20 @@ struct ReadPass : public Pass {
return; return;
} }
if (args[1] == "-undef") {
if (use_verific) {
args[0] = "verific";
args[1] = "-vlog-undef";
Pass::call(design, args);
}
args[0] = "verilog_defines";
args.erase(args.begin()+1, args.begin()+2);
for (int i = 1; i < GetSize(args); i++)
args[i] = "-U" + args[i];
Pass::call(design, args);
return;
}
log_cmd_error("Missing or unsupported mode parameter.\n"); log_cmd_error("Missing or unsupported mode parameter.\n");
} }
} ReadPass; } ReadPass;