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Merge pull request #5543 from YosysHQ/krys/check_iverilog

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Tests: Don't mention iverilog if the error wasn't from iverilog
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Miodrag Milanović 2025-12-16 07:59:48 +01:00 • committed by GitHub
commit 07c9d575fd
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1 changed files with 7 additions and 1 deletions
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8
tests/tools/autotest.sh
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@ -162,20 +162,24 @@ do
cp ../${bn}_tb.v ${bn}_tb.v
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
touch ${bn}.iverilog
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v
rm ${bn}.iverilog
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0
test_passes() {
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
touch ${bn}.iverilog
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
"$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
rm ${bn}.iverilog
test_count=$(( test_count + 1 ))
}
@ -227,7 +231,9 @@ do
else
echo "${status_prefix}${did_firrtl}-> ERROR!"
if $warn_iverilog_git; then
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
if [ -f ${bn}.out/${bn}.iverilog ]; then
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
fi
fi
$keeprunning || exit 1
fi