From 24f4902156220c39a91c2783f038c14ec0130a23 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 15 Dec 2025 10:17:19 +1300 Subject: [PATCH 1/2] Don't mention iverilog if the error wasn't from iverilog --- tests/tools/autotest.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 47b06d575..1afe304a5 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -170,12 +170,14 @@ do test_count=0 test_passes() { "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" + touch ${bn}.iverilog compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \ "$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi "$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count} + rm ${bn}.iverilog test_count=$(( test_count + 1 )) } @@ -227,7 +229,9 @@ do else echo "${status_prefix}${did_firrtl}-> ERROR!" if $warn_iverilog_git; then - echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." + if [ -f ${bn}.out/${bn}.iverilog ]; then + echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog." + fi fi $keeprunning || exit 1 fi From c69be9d7678031eea7696bd11e91869ef3495a11 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 15 Dec 2025 10:31:17 +1300 Subject: [PATCH 2/2] Missed an iverilog Should now still report an iverilog issue if `iverilog` doesn't exist. --- tests/tools/autotest.sh | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 1afe304a5..c9a12b66b 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -162,9 +162,11 @@ do cp ../${bn}_tb.v ${bn}_tb.v fi if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi + touch ${bn}.iverilog compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \ "$toolsdir"/../../techlibs/common/simlib.v \ "$toolsdir"/../../techlibs/common/simcells.v + rm ${bn}.iverilog if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi test_count=0