mirror of
https://github.com/YosysHQ/yosys
synced 2025-12-20 19:23:45 +00:00
Merge pull request #5543 from YosysHQ/krys/check_iverilog
Tests: Don't mention iverilog if the error wasn't from iverilog
This commit is contained in:
commit
07c9d575fd
1 changed files with 7 additions and 1 deletions
|
|
@ -162,20 +162,24 @@ do
|
||||||
cp ../${bn}_tb.v ${bn}_tb.v
|
cp ../${bn}_tb.v ${bn}_tb.v
|
||||||
fi
|
fi
|
||||||
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
|
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
|
||||||
|
touch ${bn}.iverilog
|
||||||
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
|
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} "${libs[@]}" \
|
||||||
"$toolsdir"/../../techlibs/common/simlib.v \
|
"$toolsdir"/../../techlibs/common/simlib.v \
|
||||||
"$toolsdir"/../../techlibs/common/simcells.v
|
"$toolsdir"/../../techlibs/common/simcells.v
|
||||||
|
rm ${bn}.iverilog
|
||||||
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
|
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
|
||||||
|
|
||||||
test_count=0
|
test_count=0
|
||||||
test_passes() {
|
test_passes() {
|
||||||
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
|
"$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@"
|
||||||
|
touch ${bn}.iverilog
|
||||||
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
|
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
|
||||||
${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
|
${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \
|
||||||
"$toolsdir"/../../techlibs/common/simlib.v \
|
"$toolsdir"/../../techlibs/common/simlib.v \
|
||||||
"$toolsdir"/../../techlibs/common/simcells.v
|
"$toolsdir"/../../techlibs/common/simcells.v
|
||||||
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
|
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
|
||||||
"$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
|
"$toolsdir/cmp_tbdata" ${bn}_out_ref ${bn}_out_syn${test_count}
|
||||||
|
rm ${bn}.iverilog
|
||||||
test_count=$(( test_count + 1 ))
|
test_count=$(( test_count + 1 ))
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -227,7 +231,9 @@ do
|
||||||
else
|
else
|
||||||
echo "${status_prefix}${did_firrtl}-> ERROR!"
|
echo "${status_prefix}${did_firrtl}-> ERROR!"
|
||||||
if $warn_iverilog_git; then
|
if $warn_iverilog_git; then
|
||||||
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
|
if [ -f ${bn}.out/${bn}.iverilog ]; then
|
||||||
|
echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
|
||||||
|
fi
|
||||||
fi
|
fi
|
||||||
$keeprunning || exit 1
|
$keeprunning || exit 1
|
||||||
fi
|
fi
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue