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This pass identifies arithmetic operators that share an operand and whose results are used in mutually exclusive cases controlled by a multiplexer, and merges them together by multiplexing the other operands
20 lines
366 B
Verilog
20 lines
366 B
Verilog
module add_sub(
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input [15:0] a,
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input [15:0] b,
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input [15:0] c,
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input [1:0] sel,
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output reg [15:0] res
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);
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always @* begin
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case(sel)
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0: res = a + b;
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1: res = a - b;
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2: res = a + c;
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default: res = 16'bx;
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endcase
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end
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endmodule
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