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opt_mem: Use Mem helpers.

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This commit is contained in:
Marcelina Kościelnicka 2020-10-17 22:21:05 +02:00
parent 21896e2a02
commit 06141db233
1 changed files with 6 additions and 81 deletions
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87
passes/opt/opt_mem.cc
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@ -19,82 +19,11 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/mem.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct OptMemWorker
{
RTLIL::Design *design;
RTLIL::Module *module;
SigMap sigmap;
bool restart;
dict<IdString, vector<IdString>> memrd, memwr, meminit;
pool<IdString> remove_mem, remove_cells;
OptMemWorker(RTLIL::Module *module) : design(module->design), module(module), sigmap(module), restart(false)
{
for (auto &it : module->memories)
{
memrd[it.first];
memwr[it.first];
meminit[it.first];
}
for (auto cell : module->cells())
{
if (cell->type == ID($memrd)) {
IdString id = cell->getParam(ID::MEMID).decode_string();
memrd.at(id).push_back(cell->name);
}
if (cell->type == ID($memwr)) {
IdString id = cell->getParam(ID::MEMID).decode_string();
memwr.at(id).push_back(cell->name);
}
if (cell->type == ID($meminit)) {
IdString id = cell->getParam(ID::MEMID).decode_string();
meminit.at(id).push_back(cell->name);
}
}
}
~OptMemWorker()
{
for (auto it : remove_mem)
{
for (auto cell_name : memrd[it])
module->remove(module->cell(cell_name));
for (auto cell_name : memwr[it])
module->remove(module->cell(cell_name));
for (auto cell_name : meminit[it])
module->remove(module->cell(cell_name));
delete module->memories.at(it);
module->memories.erase(it);
}
for (auto cell_name : remove_cells)
module->remove(module->cell(cell_name));
}
int run(RTLIL::Memory *mem)
{
if (restart || remove_mem.count(mem->name))
return 0;
if (memwr.at(mem->name).empty() && meminit.at(mem->name).empty()) {
log("Removing memory %s.%s with no write ports or init data.\n", log_id(module), log_id(mem));
remove_mem.insert(mem->name);
return 1;
}
return 0;
}
};
struct OptMemPass : public Pass {
OptMemPass() : Pass("opt_mem", "optimize memories") { }
void help() override
@ -122,15 +51,11 @@ struct OptMemPass : public Pass {
int total_count = 0;
for (auto module : design->selected_modules()) {
while (1) {
int cnt = 0;
OptMemWorker worker(module);
for (auto &it : module->memories)
if (module->selected(it.second))
cnt += worker.run(it.second);
if (!cnt && !worker.restart)
break;
total_count += cnt;
for (auto &mem : Mem::get_selected_memories(module)) {
if (mem.wr_ports.empty() && mem.inits.empty()) {
mem.remove();
total_count++;
}
}
}