Merge 411daa16cf into 22c15a7ecd

passes/opt/muxpack.cc

@@ -294,6 +294,7 @@ struct MuxpackWorker
 					s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
 				}
 				remove_cells.insert(cursor_cell);
+				first_cell->add_strpool_attribute(ID::src, cursor_cell->get_strpool_attribute(ID::src));
 			}
 
 			first_cell->setPort(ID::B, b_sig);

passes/opt/opt_share.cc

@@ -196,7 +196,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 	for (auto &operand : muxed_operands) {
 		operand.sig.extend_u0(max_width, operand.is_signed);
 		if (operand.sign != muxed_operands[0].sign)
-			operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
+			operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed, mux->get_src_attribute()));
 	}
 
 	for (const auto& p : ports) {
@@ -241,9 +241,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 
 	SigSpec mux_to_oper;
 	if (GetSize(shared_pmux_s) == 1) {
-		mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
+		mux_to_oper = module->Mux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s, mux->get_src_attribute());
 	} else {
-		mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
+		mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s, mux->get_src_attribute());
 	}
 
 	if (shared_op->type.in(ID($alu))) {

tests/opt/muxpack_src.ys

@@ -0,0 +1,57 @@
+read_rtlil <<EOT
+module \top
+  wire width 2 input 1 \a
+  wire width 2 input 2 \b
+  wire width 2 input 3 \c
+  wire input 4 \sel
+  wire \eq0_y
+  wire \eq1_y
+  wire width 2 \mux0_y
+  wire width 2 output 5 \y
+
+  cell $eq \eq0
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \sel
+    connect \B 1'0
+    connect \Y \eq0_y
+  end
+
+  cell $eq \eq1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \sel
+    connect \B 1'1
+    connect \Y \eq1_y
+  end
+
+  attribute \src "muxpack_src_a"
+  cell $mux \mux0
+    parameter \WIDTH 2
+    connect \A \a
+    connect \B \b
+    connect \S \eq0_y
+    connect \Y \mux0_y
+  end
+
+  attribute \src "muxpack_src_b"
+  cell $mux \mux1
+    parameter \WIDTH 2
+    connect \A \mux0_y
+    connect \B \c
+    connect \S \eq1_y
+    connect \Y \y
+  end
+end
+EOT
+
+muxpack
+
+select -assert-count 1 t:$pmux
+select -assert-count 1 t:$pmux a:src=muxpack_src_b|muxpack_src_a %i

tests/opt/opt_share_src.ys

@@ -0,0 +1,47 @@
+read_rtlil <<EOT
+module \top
+  wire width 4 input 1 \a
+  wire width 4 input 2 \b
+  wire width 4 input 3 \c
+  wire input 4 \sel
+  wire width 4 \add0_y
+  wire width 4 \add1_y
+  wire width 4 output 5 \y
+
+  cell $add \add0
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \a
+    connect \B \b
+    connect \Y \add0_y
+  end
+
+  cell $add \add1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \a
+    connect \B \c
+    connect \Y \add1_y
+  end
+
+  attribute \src "opt_share_mux_src"
+  cell $mux \mux
+    parameter \WIDTH 4
+    connect \A \add0_y
+    connect \B \add1_y
+    connect \S \sel
+    connect \Y \y
+  end
+end
+EOT
+
+opt_share
+
+select -assert-count 1 t:$add
+select -assert-count 2 t:$mux a:src=opt_share_mux_src %i