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analogdevices: DSP inference

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Lofty 2025-10-16 23:33:59 +01:00
parent aab52403f1
commit 059925a56a
4 changed files with 122 additions and 788 deletions
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84
techlibs/analogdevices/dsp_map.v
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@ -1,4 +1,4 @@
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
module \$__MUL22X22 (input [21:0] A, input [21:0] B, output [43:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
@ -6,45 +6,55 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
parameter Y_WIDTH = 0;
wire [47:0] P_48;
DSP48E1 #(
RBBDSP #(
// Disable all registers
.ACASCREG(0),
.ADREG(0),
.A_INPUT("DIRECT"),
.ALUMODEREG(0),
.AREG(0),
.BCASCREG(0),
.B_INPUT("DIRECT"),
.BREG(0),
.CARRYINREG(0),
.CARRYINSELREG(0),
.CREG(0),
.DREG(0),
.INMODEREG(0),
.MREG(0),
.OPMODEREG(0),
.PREG(0),
.USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48"),
.USE_DPORT("FALSE")
.AI_SEL_IN(1'b0),
.BC_CI(2'b00),
.BI_SEL(1'b0),
.BI_SEL_IN(1'b0),
.CE_A(1'b0),
.CE_ADD(1'b0),
.CE_B(1'b0),
.CE_C(1'b0),
.CE_CRY(1'b0),
.CE_D(2'b0),
.CE_M(1'b0),
.CE_OPCODE(1'b0),
.CE_PADD(1'b0),
.CE_RST(1'b1),
.CE_SEL(1'b0),
.CE_SFT(1'b0),
.CI_SEL(4'd3),
.DI_SEL(1'b0),
.DI_SEL_IN(1'b0),
.OPCODE_SEL(1'b0),
.OP_ADD(10'b0),
.OP_CPLX(1'b0),
.OP_MULT(2'b11),
.OP_PADD(10'b0000000000),
.OP_SFT(6'b000000),
.OP_X(4'b1010),
.OP_Y(4'b0101),
.OP_Z(4'b0000),
.PO_LOC_SEL(1'b1),
.PO_NWK_SEL(1'b1),
.REG_A(1'b0),
.REG_ADD(1'b0),
.REG_B(1'b0),
.REG_C(1'b0),
.REG_CRY(1'b0),
.REG_D(2'b0),
.REG_M(1'b0),
.REG_OPCODE(1'b0),
.REG_PADD(1'b0),
.REG_SFT(1'b0),
.RST_SEL(1'b0),
.FF_SYNC_RST(1'b0),
) _TECHMAP_REPLACE_ (
//Data path
.A({{5{A[24]}}, A}),
.B(B),
.C(48'b0),
.D(25'b0),
.CARRYIN(1'b0),
.P(P_48),
.INMODE(5'b00000),
.ALUMODE(4'b0000),
.OPMODE(7'b000101),
.CARRYINSEL(3'b000),
.ACIN(30'b0),
.BCIN(18'b0),
.PCIN(48'b0),
.CARRYIN(1'b0)
.A(A),
.B(B),
.D(48'b0)
);
assign Y = P_48;
endmodule