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Tests.
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1 changed files with 6 additions and 6 deletions
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@ -3,9 +3,9 @@ design -reset
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read_verilog -sv opt_dff_eqbits_small.sv
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hierarchy -top test_case
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techmap
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opt_dff -sat
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opt_dff -sat -eqbits
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synth
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opt_dff -sat
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opt_dff -sat -eqbits
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opt_clean -purge
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select -assert-count 2 t:$_SDFF_PN0_
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@ -17,7 +17,7 @@ hierarchy -top test_case
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prep
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design -save gold
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opt_dff -sat
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opt_dff -sat -eqbits
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design -save gate
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design -copy-from gold -as gold test_case
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@ -32,9 +32,9 @@ design -reset
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read_verilog -sv opt_dff_eqbits_large.sv
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hierarchy -top test_case
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techmap
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opt_dff -sat
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opt_dff -sat -eqbits
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synth
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opt_dff -sat
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opt_dff -sat -eqbits
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opt_clean -purge
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select -assert-count 6 t:$_SDFFE_PN0P_
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@ -46,7 +46,7 @@ hierarchy -top test_case
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prep
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design -save gold
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opt_dff -sat
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opt_dff -sat -eqbits
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design -save gate
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design -copy-from gold -as gold test_case
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