diff --git a/tests/opt/opt_dff_eqbits.ys b/tests/opt/opt_dff_eqbits.ys
index 10e9045e4..181b5d0a7 100644
--- a/tests/opt/opt_dff_eqbits.ys
+++ b/tests/opt/opt_dff_eqbits.ys
@@ -3,9 +3,9 @@ design -reset
 read_verilog -sv opt_dff_eqbits_small.sv
 hierarchy -top test_case
 techmap
-opt_dff -sat
+opt_dff -sat -eqbits
 synth
-opt_dff -sat
+opt_dff -sat -eqbits
 opt_clean -purge
 
 select -assert-count 2 t:$_SDFF_PN0_
@@ -17,7 +17,7 @@ hierarchy -top test_case
 prep
 design -save gold
 
-opt_dff -sat
+opt_dff -sat -eqbits
 design -save gate
 
 design -copy-from gold -as gold test_case
@@ -32,9 +32,9 @@ design -reset
 read_verilog -sv opt_dff_eqbits_large.sv
 hierarchy -top test_case
 techmap
-opt_dff -sat
+opt_dff -sat -eqbits
 synth
-opt_dff -sat
+opt_dff -sat -eqbits
 opt_clean -purge
 
 select -assert-count 6 t:$_SDFFE_PN0P_
@@ -46,7 +46,7 @@ hierarchy -top test_case
 prep
 design -save gold
 
-opt_dff -sat
+opt_dff -sat -eqbits
 design -save gate
 
 design -copy-from gold -as gold test_case