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Merge remote-tracking branch 'origin/master' into feature/python_bindings
This commit is contained in:
commit
03d1606b42
428 changed files with 23388 additions and 2479 deletions
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@ -33,6 +33,8 @@ std::vector<int> RTLIL::IdString::global_refcount_storage_;
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std::vector<char*> RTLIL::IdString::global_id_storage_;
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dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
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std::vector<int> RTLIL::IdString::global_free_idx_list_;
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int RTLIL::IdString::last_created_idx_[8];
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int RTLIL::IdString::last_created_idx_ptr_;
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RTLIL::Const::Const()
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{
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@ -676,6 +678,11 @@ std::map<unsigned int, RTLIL::Module*> *RTLIL::Module::get_all_modules(void)
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}
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#endif
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void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
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{
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log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
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}
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RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
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{
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if (mayfail)
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@ -683,6 +690,14 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLI
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log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
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}
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RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
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{
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if (mayfail)
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return RTLIL::IdString();
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log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
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}
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size_t RTLIL::Module::count_id(RTLIL::IdString id)
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{
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return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
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@ -782,7 +797,7 @@ namespace {
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void check()
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{
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if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
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if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
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cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
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return;
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@ -2423,7 +2438,7 @@ void RTLIL::Cell::check()
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void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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{
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if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
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if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
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type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
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return;
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@ -2475,6 +2490,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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if (connections_.count("\\Y"))
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parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
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if (connections_.count("\\Q"))
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parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
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check();
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}
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@ -3305,7 +3323,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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remove(width, width_ - width);
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if (width_ < width) {
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RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
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RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
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if (!is_signed)
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padding = RTLIL::State::S0;
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while (width_ < width)
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@ -3866,6 +3884,11 @@ RTLIL::CaseRule::~CaseRule()
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delete *it;
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}
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bool RTLIL::CaseRule::empty() const
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{
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return actions.empty() && switches.empty();
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}
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RTLIL::CaseRule *RTLIL::CaseRule::clone() const
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{
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RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
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@ -3882,6 +3905,11 @@ RTLIL::SwitchRule::~SwitchRule()
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delete *it;
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}
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bool RTLIL::SwitchRule::empty() const
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{
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return cases.empty();
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}
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RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
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{
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RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
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