From 2b9c75f8e372f6886e073743d1df11bcd1c58281 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Fri, 9 Mar 2018 10:35:33 +0200
Subject: [PATCH 001/528] This PR should be the base for discussion, do not
 merge it yet!

It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
---
 frontends/ast/ast.cc               |  7 +++++-
 frontends/ast/ast.h                |  2 +-
 frontends/ast/simplify.cc          | 10 ++++++++
 frontends/verilog/verilog_lexer.l  |  2 +-
 frontends/verilog/verilog_parser.y |  6 ++++-
 tests/simple/reg_wire_error.v      | 40 ++++++++++++++++++++++++++++++
 6 files changed, 63 insertions(+), 4 deletions(-)
 create mode 100644 tests/simple/reg_wire_error.v

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 037a9f3ee..25267775a 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -191,6 +191,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
 	is_input = false;
 	is_output = false;
 	is_reg = false;
+	is_logic = false;
 	is_signed = false;
 	is_string = false;
 	range_valid = false;
@@ -285,7 +286,9 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
 		fprintf(f, " input");
 	if (is_output)
 		fprintf(f, " output");
-	if (is_reg)
+	if (is_logic)
+		fprintf(f, " logic");
+	if (is_reg) // this is an AST dump, not Verilog - if we see "logic reg" that's fine.
 		fprintf(f, " reg");
 	if (is_signed)
 		fprintf(f, " signed");
@@ -652,6 +655,8 @@ bool AstNode::operator==(const AstNode &other) const
 		return false;
 	if (is_output != other.is_output)
 		return false;
+	if (is_logic != other.is_logic)
+		return false;
 	if (is_reg != other.is_reg)
 		return false;
 	if (is_signed != other.is_signed)
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index d1e2c78d1..9b7124934 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -168,7 +168,7 @@ namespace AST
 		// node content - most of it is unused in most node types
 		std::string str;
 		std::vector<RTLIL::State> bits;
-		bool is_input, is_output, is_reg, is_signed, is_string, range_valid, range_swapped;
+		bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped;
 		int port_id, range_left, range_right;
 		uint32_t integer;
 		double realvalue;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index a16fdfeeb..c9c5e5263 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -327,6 +327,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			if (node->type == AST_WIRE) {
 				if (this_wire_scope.count(node->str) > 0) {
 					AstNode *first_node = this_wire_scope[node->str];
+					if (first_node->is_input && node->is_reg)
+						goto wires_are_incompatible;
 					if (!node->is_input && !node->is_output && node->is_reg && node->children.size() == 0)
 						goto wires_are_compatible;
 					if (first_node->children.size() == 0 && node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
@@ -361,6 +363,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 						first_node->is_output = true;
 					if (node->is_reg)
 						first_node->is_reg = true;
+					if (node->is_logic)
+						first_node->is_logic = true;
 					if (node->is_signed)
 						first_node->is_signed = true;
 					for (auto &it : node->attributes) {
@@ -440,6 +444,12 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		children[1]->detectSignWidth(width_hint, sign_hint);
 		width_hint = max(width_hint, backup_width_hint);
 		child_0_is_self_determined = true;
+		if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
+			children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
+		if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
+			log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
+		if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
+			log_error("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
 		break;
 
 	case AST_PARAMETER:
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index d6d00c371..8aa123e1e 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -189,7 +189,7 @@ YOSYS_NAMESPACE_END
 "const"      { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
 "checker"    { if (formal_mode) return TOK_CHECKER; SV_KEYWORD(TOK_CHECKER); }
 "endchecker" { if (formal_mode) return TOK_ENDCHECKER; SV_KEYWORD(TOK_ENDCHECKER); }
-"logic"      { SV_KEYWORD(TOK_REG); }
+"logic"      { SV_KEYWORD(TOK_LOGIC); }
 "bit"        { SV_KEYWORD(TOK_REG); }
 
 "eventually"   { if (formal_mode) return TOK_EVENTUALLY; SV_KEYWORD(TOK_EVENTUALLY); }
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ba2fc036e..722febf13 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -105,7 +105,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
-%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
+%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
 %token TOK_DPI_FUNCTION TOK_POSEDGE TOK_NEGEDGE TOK_OR TOK_AUTOMATIC
@@ -394,6 +394,9 @@ wire_type_token:
 	TOK_REG {
 		astbuf3->is_reg = true;
 	} |
+	TOK_LOGIC {
+		astbuf3->is_logic = true;
+	} |
 	TOK_INTEGER {
 		astbuf3->is_reg = true;
 		astbuf3->range_left = 31;
@@ -827,6 +830,7 @@ wire_name:
 				node->port_id = current_function_or_task_port_id++;
 		}
 		ast_stack.back()->children.push_back(node);
+
 		delete $1;
 	};
 
diff --git a/tests/simple/reg_wire_error.v b/tests/simple/reg_wire_error.v
new file mode 100644
index 000000000..ab461b95a
--- /dev/null
+++ b/tests/simple/reg_wire_error.v
@@ -0,0 +1,40 @@
+module sub_mod(input i_in, output o_out);
+assign o_out = i_in;
+endmodule
+
+module test(i_clk, i_reg, o_reg, o_wire);
+input i_clk;
+input i_reg;
+output o_reg;
+output o_wire;
+
+// Enable this to see how it doesn't fail on yosys although it should
+//reg o_wire;
+// Enable this instead of the above to see how logic can be mapped to a wire
+logic o_wire;
+// Enable this to see how it doesn't fail on yosys although it should
+//reg i_reg;
+// Disable this to see how it doesn't fail on yosys although it should
+reg o_reg;
+
+logic l_reg;
+
+// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
+//assign l_reg = !o_reg;
+initial o_reg = 1'b0;
+always @(posedge i_clk)
+begin
+  o_reg <= !o_reg;
+  l_reg <= !o_reg;
+end
+
+assign o_wire = !o_reg;
+// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
+//assign l_reg = !o_reg;
+
+sub_mod sm_inst (
+  .i_in(1'b1),
+  .o_out(o_reg)
+);
+endmodule
+

From 9286acb6870876f27771c039704ded7d9ffef3a9 Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Sun, 13 May 2018 16:53:35 -0400
Subject: [PATCH 002/528] Add option -expose to setundef pass

Option -expose converts undriven wires to inputs.

Example usage: setundef -undriven -expose [selection]
---
 passes/cmds/setundef.cc | 32 ++++++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index c11ddbdc1..172b1c3f8 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -81,6 +81,9 @@ struct SetundefPass : public Pass {
 		log("    -undriven\n");
 		log("        also set undriven nets to constant values\n");
 		log("\n");
+		log("    -expose\n");
+		log("        also expose undriven nets as inputs\n");
+		log("\n");
 		log("    -zero\n");
 		log("        replace with bits cleared (0)\n");
 		log("\n");
@@ -105,6 +108,7 @@ struct SetundefPass : public Pass {
 	{
 		bool got_value = false;
 		bool undriven_mode = false;
+		bool expose_mode = false;
 		bool init_mode = false;
 		SetundefWorker worker;
 
@@ -117,6 +121,11 @@ struct SetundefPass : public Pass {
 				undriven_mode = true;
 				continue;
 			}
+			if (args[argidx] == "-expose") {
+				got_value = true;
+				expose_mode = true;
+				continue;
+			}
 			if (args[argidx] == "-zero") {
 				got_value = true;
 				worker.next_bit_mode = 0;
@@ -157,6 +166,8 @@ struct SetundefPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		if (expose_mode && !undriven_mode)
+			log_cmd_error("Option -expose must be used with option -undriven.\n");
 		if (!got_value)
 			log_cmd_error("One of the options -zero, -one, -anyseq, or -random <seed> must be specified.\n");
 
@@ -184,12 +195,21 @@ struct SetundefPass : public Pass {
 						undriven_signals.del(sigmap(conn.second));
 
 				RTLIL::SigSpec sig = undriven_signals.export_all();
-				for (auto &c : sig.chunks()) {
-					RTLIL::SigSpec bits;
-					for (int i = 0; i < c.width; i++)
-						bits.append(worker.next_bit());
-					module->connect(RTLIL::SigSig(c, bits));
-				}
+        if (expose_mode) {
+          for (auto &c : sig.chunks()) {
+            c.wire->port_input = true;
+            log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name));
+          }
+          module->fixup_ports();
+        }
+        else {
+          for (auto &c : sig.chunks()) {
+            RTLIL::SigSpec bits;
+            for (int i = 0; i < c.width; i++)
+              bits.append(worker.next_bit());
+            module->connect(RTLIL::SigSig(c, bits));
+          }
+        }
 			}
 
 			if (init_mode)

From b4a303a1b7a9986881efa1040bf54c5f583d87a0 Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Sun, 13 May 2018 20:13:54 -0400
Subject: [PATCH 003/528] Corrections to option -expose in setundef pass

---
 passes/cmds/setundef.cc | 163 +++++++++++++++++++++++++++++++++++-----
 1 file changed, 144 insertions(+), 19 deletions(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 172b1c3f8..0825cf83e 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -26,6 +26,70 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
+{
+  RTLIL::Wire *wire = NULL;
+  name = RTLIL::escape_id(name);
+
+  if (module->count_id(name) != 0)
+  {
+    if (module->wires_.count(name) > 0)
+      wire = module->wires_.at(name);
+
+    if (wire != NULL && wire->width != width)
+      wire = NULL;
+
+    if (wire != NULL && wire->port_input != flag_input)
+      wire = NULL;
+
+    if (wire != NULL && wire->port_output != flag_output)
+      wire = NULL;
+
+    if (wire == NULL) {
+      return wire;
+      log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str());
+    }
+
+    log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
+  }
+  else
+  {
+    wire = module->addWire(name, width);
+    wire->port_input = flag_input;
+    wire->port_output = flag_output;
+
+    if (flag_input || flag_output) {
+      wire->port_id = module->wires_.size();
+      module->fixup_ports();
+    }
+
+    log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
+  }
+
+  if (!flag_global)
+    return wire;
+
+  for (auto &it : module->cells_)
+  {
+    if (design->modules_.count(it.second->type) == 0)
+      continue;
+
+    RTLIL::Module *mod = design->modules_.at(it.second->type);
+    if (!design->selected_whole_module(mod->name))
+      continue;
+    if (mod->get_bool_attribute("\\blackbox"))
+      continue;
+    if (it.second->hasPort(name))
+      continue;
+
+    it.second->setPort(name, wire);
+    log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
+  }
+
+  return wire;
+}
+
+
 struct SetundefWorker
 {
 	int next_bit_mode;
@@ -178,31 +242,92 @@ struct SetundefPass : public Pass {
 				if (!module->processes.empty())
 					log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
 
-				SigMap sigmap(module);
-				SigPool undriven_signals;
-
-				for (auto &it : module->wires_)
-					undriven_signals.add(sigmap(it.second));
-
-				for (auto &it : module->wires_)
-					if (it.second->port_input)
-						undriven_signals.del(sigmap(it.second));
-
-				CellTypes ct(design);
-				for (auto &it : module->cells_)
-				for (auto &conn : it.second->connections())
-					if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
-						undriven_signals.del(sigmap(conn.second));
-
-				RTLIL::SigSpec sig = undriven_signals.export_all();
         if (expose_mode) {
+          SigMap sigmap(module);
+          dict<SigBit, bool> wire_drivers;
+          pool<SigBit> used_wires;
+          SigPool undriven_signals;
+
+          for (auto cell : module->cells())
+          for (auto &conn : cell->connections()) {
+            SigSpec sig = sigmap(conn.second);
+            if (cell->input(conn.first))
+              for (auto bit : sig)
+                if (bit.wire) {
+                  used_wires.insert(bit);
+                }
+            if (cell->output(conn.first))
+              for (int i = 0; i < GetSize(sig); i++) {
+                if (sig[i].wire)
+                  wire_drivers[sig[i]] = true;
+              }
+          }
+
+          for (auto wire : module->wires()) {
+            if (wire->port_input) {
+              SigSpec sig = sigmap(wire);
+              for (int i = 0; i < GetSize(sig); i++)
+                wire_drivers[sig[i]] = true;
+            }
+            if (wire->port_output)
+              for (auto bit : sigmap(wire))
+                if (bit.wire) used_wires.insert(bit);
+          }
+
+          pool<RTLIL::Wire*> undriven_wires;
+          for (auto bit : used_wires) {
+            if (!wire_drivers.count(bit)) {
+              undriven_wires.insert(bit.wire);
+            }
+          }
+
+          for (auto &it : undriven_wires)
+            undriven_signals.add(sigmap(it));
+
+          for (auto &it : undriven_wires)
+            if (it->port_input)
+              undriven_signals.del(sigmap(it));
+
+          CellTypes ct(design);
+          for (auto &it : module->cells_)
+          for (auto &conn : it.second->connections())
+            if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+              undriven_signals.del(sigmap(conn.second));
+
+          RTLIL::SigSpec sig = undriven_signals.export_all();
           for (auto &c : sig.chunks()) {
-            c.wire->port_input = true;
-            log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(c.wire->name));
+            RTLIL::Wire * wire;
+            if (c.wire->width == c.width) {
+              wire = c.wire;
+              wire->port_input = true;
+            }
+            else {
+              string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
+              wire = add_wire(design, module, name, c.width, true, false, false);
+              module->connect(RTLIL::SigSig(c.wire, wire));
+            }
+            log("Exposing undriven wire %s as input.\n", wire->name.c_str());
           }
           module->fixup_ports();
         }
         else {
+          SigMap sigmap(module);
+          SigPool undriven_signals;
+
+          for (auto &it : module->wires_)
+            undriven_signals.add(sigmap(it.second));
+
+          for (auto &it : module->wires_)
+            if (it.second->port_input)
+              undriven_signals.del(sigmap(it.second));
+
+          CellTypes ct(design);
+          for (auto &it : module->cells_)
+          for (auto &conn : it.second->connections())
+            if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+              undriven_signals.del(sigmap(conn.second));
+
+          RTLIL::SigSpec sig = undriven_signals.export_all();
           for (auto &c : sig.chunks()) {
             RTLIL::SigSpec bits;
             for (int i = 0; i < c.width; i++)

From 8b9a8c7f9115e691dc832b3be3d82b55be507e99 Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Mon, 14 May 2018 18:58:49 -0400
Subject: [PATCH 004/528] Minor correction

Minor typo error correction in -expose with setundef
---
 passes/cmds/setundef.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 0825cf83e..9b0c30cae 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -89,7 +89,6 @@ static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std:
   return wire;
 }
 
-
 struct SetundefWorker
 {
 	int next_bit_mode;
@@ -304,7 +303,7 @@ struct SetundefPass : public Pass {
             else {
               string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
               wire = add_wire(design, module, name, c.width, true, false, false);
-              module->connect(RTLIL::SigSig(c.wire, wire));
+              module->connect(RTLIL::SigSig(c, wire));
             }
             log("Exposing undriven wire %s as input.\n", wire->name.c_str());
           }

From 6e63df6dd08fe424f46039d26f9f238ac1cb4494 Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Tue, 15 May 2018 13:06:23 -0400
Subject: [PATCH 005/528] Correction to -expose with setundef

---
 passes/cmds/setundef.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 9b0c30cae..c67953976 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -308,6 +308,7 @@ struct SetundefPass : public Pass {
             log("Exposing undriven wire %s as input.\n", wire->name.c_str());
           }
           module->fixup_ports();
+          continue;
         }
         else {
           SigMap sigmap(module);

From 80d9d15f1c4b73ee73172b06fd2c8c55703aea54 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 5 Jun 2018 12:15:59 +0300
Subject: [PATCH 006/528] reg_wire_error test needs the -sv flag so it is run
 via a script so it had to be moved out of the tests/simple dir that only runs
 Verilog files

---
 tests/{simple/reg_wire_error.v => various/reg_wire_error.sv} | 0
 tests/various/reg_wire_error.ys                              | 1 +
 2 files changed, 1 insertion(+)
 rename tests/{simple/reg_wire_error.v => various/reg_wire_error.sv} (100%)
 create mode 100644 tests/various/reg_wire_error.ys

diff --git a/tests/simple/reg_wire_error.v b/tests/various/reg_wire_error.sv
similarity index 100%
rename from tests/simple/reg_wire_error.v
rename to tests/various/reg_wire_error.sv
diff --git a/tests/various/reg_wire_error.ys b/tests/various/reg_wire_error.ys
new file mode 100644
index 000000000..b9d03155d
--- /dev/null
+++ b/tests/various/reg_wire_error.ys
@@ -0,0 +1 @@
+read_verilog -sv reg_wire_error.sv

From 73d426bc879087ca522ca595a8ba921b647fae27 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 5 Jun 2018 17:44:24 +0300
Subject: [PATCH 007/528] Modified errors into warnings No longer false
 warnings for memories and assertions

---
 frontends/ast/ast.cc               |  1 +
 frontends/ast/ast.h                |  2 +-
 frontends/ast/simplify.cc          | 44 ++++++++++++++++++++++++++----
 frontends/verilog/verilog_parser.y |  1 +
 tests/various/reg_wire_error.sv    | 42 +++++++++++++++++++++++++---
 5 files changed, 79 insertions(+), 11 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 25267775a..b8f25e53e 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -194,6 +194,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch
 	is_logic = false;
 	is_signed = false;
 	is_string = false;
+	was_checked = false;
 	range_valid = false;
 	range_swapped = false;
 	port_id = 0;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 9b7124934..8a640b1cc 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -168,7 +168,7 @@ namespace AST
 		// node content - most of it is unused in most node types
 		std::string str;
 		std::vector<RTLIL::State> bits;
-		bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped;
+		bool is_input, is_output, is_reg, is_logic, is_signed, is_string, range_valid, range_swapped, was_checked;
 		int port_id, range_left, range_right;
 		uint32_t integer;
 		double realvalue;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index c9c5e5263..a9608369c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -444,12 +444,16 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		children[1]->detectSignWidth(width_hint, sign_hint);
 		width_hint = max(width_hint, backup_width_hint);
 		child_0_is_self_determined = true;
-		if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
-			children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
-		if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
-			log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
-		if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
-			log_error("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
+		// test only once, before optimizations and memory mappings but after assignment LHS was mapped to an identifier
+		if (children[0]->id2ast && !children[0]->was_checked) {
+			if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && children[0]->id2ast->is_logic)
+				children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
+			if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
+				log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
+			if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
+				log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
+			children[0]->was_checked = true;
+		}
 		break;
 
 	case AST_PARAMETER:
@@ -959,6 +963,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 		AstNode *assign = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), data);
 		assign->children[0]->str = wire_id;
+		assign->children[0]->was_checked = true;
 
 		if (current_block)
 		{
@@ -1425,16 +1430,19 @@ skip_dynamic_range_lvalue_expansion:;
 
 		AstNode *wire_check = new AstNode(AST_WIRE);
 		wire_check->str = id_check;
+		wire_check->was_checked = true;
 		current_ast_mod->children.push_back(wire_check);
 		current_scope[wire_check->str] = wire_check;
 		while (wire_check->simplify(true, false, false, 1, -1, false, false)) { }
 
 		AstNode *wire_en = new AstNode(AST_WIRE);
 		wire_en->str = id_en;
+		wire_en->was_checked = true;
 		current_ast_mod->children.push_back(wire_en);
 		if (current_always_clocked) {
 			current_ast_mod->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), AstNode::mkconst_int(0, false, 1)))));
 			current_ast_mod->children.back()->children[0]->children[0]->children[0]->str = id_en;
+			current_ast_mod->children.back()->children[0]->children[0]->children[0]->was_checked = true;
 		}
 		current_scope[wire_en->str] = wire_en;
 		while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
@@ -1444,9 +1452,11 @@ skip_dynamic_range_lvalue_expansion:;
 
 		AstNode *assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bit, false));
 		assign_check->children[0]->str = id_check;
+		assign_check->children[0]->was_checked = true;
 
 		AstNode *assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, 1));
 		assign_en->children[0]->str = id_en;
+		assign_en->children[0]->was_checked = true;
 
 		AstNode *default_signals = new AstNode(AST_BLOCK);
 		default_signals->children.push_back(assign_check);
@@ -1455,6 +1465,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 		assign_check = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), new AstNode(AST_REDUCE_BOOL, children[0]->clone()));
 		assign_check->children[0]->str = id_check;
+		assign_check->children[0]->was_checked = true;
 
 		if (current_always == nullptr || current_always->type != AST_INITIAL) {
 			assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(1, false, 1));
@@ -1463,6 +1474,7 @@ skip_dynamic_range_lvalue_expansion:;
 			assign_en->children[1]->str = "\\$initstate";
 		}
 		assign_en->children[0]->str = id_en;
+		assign_en->children[0]->was_checked = true;
 
 		newNode = new AstNode(AST_BLOCK);
 		newNode->children.push_back(assign_check);
@@ -1571,12 +1583,14 @@ skip_dynamic_range_lvalue_expansion:;
 
 		AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
 		wire_addr->str = id_addr;
+		wire_addr->was_checked = true;
 		current_ast_mod->children.push_back(wire_addr);
 		current_scope[wire_addr->str] = wire_addr;
 		while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
 
 		AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
 		wire_data->str = id_data;
+		wire_data->was_checked = true;
 		wire_data->is_signed = mem_signed;
 		current_ast_mod->children.push_back(wire_data);
 		current_scope[wire_data->str] = wire_data;
@@ -1586,6 +1600,7 @@ skip_dynamic_range_lvalue_expansion:;
 		if (current_always->type != AST_INITIAL) {
 			wire_en = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
 			wire_en->str = id_en;
+			wire_en->was_checked = true;
 			current_ast_mod->children.push_back(wire_en);
 			current_scope[wire_en->str] = wire_en;
 			while (wire_en->simplify(true, false, false, 1, -1, false, false)) { }
@@ -1601,14 +1616,17 @@ skip_dynamic_range_lvalue_expansion:;
 
 		AstNode *assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_addr, false));
 		assign_addr->children[0]->str = id_addr;
+		assign_addr->children[0]->was_checked = true;
 
 		AstNode *assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(x_bits_data, false));
 		assign_data->children[0]->str = id_data;
+		assign_data->children[0]->was_checked = true;
 
 		AstNode *assign_en = nullptr;
 		if (current_always->type != AST_INITIAL) {
 			assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_int(0, false, mem_width));
 			assign_en->children[0]->str = id_en;
+			assign_en->children[0]->was_checked = true;
 		}
 
 		AstNode *default_signals = new AstNode(AST_BLOCK);
@@ -1620,6 +1638,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 		assign_addr = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
 		assign_addr->children[0]->str = id_addr;
+		assign_addr->children[0]->was_checked = true;
 
 		if (children[0]->children.size() == 2)
 		{
@@ -1634,12 +1653,14 @@ skip_dynamic_range_lvalue_expansion:;
 				assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
 						new AstNode(AST_CONCAT, mkconst_bits(padding_x, false), children[1]->clone()));
 				assign_data->children[0]->str = id_data;
+				assign_data->children[0]->was_checked = true;
 
 				if (current_always->type != AST_INITIAL) {
 					for (int i = 0; i < mem_width; i++)
 						set_bits_en[i] = offset <= i && i < offset+width ? RTLIL::State::S1 : RTLIL::State::S0;
 					assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
 					assign_en->children[0]->str = id_en;
+					assign_en->children[0]->was_checked = true;
 				}
 			}
 			else
@@ -1661,6 +1682,7 @@ skip_dynamic_range_lvalue_expansion:;
 				assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
 						new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone()));
 				assign_data->children[0]->str = id_data;
+				assign_data->children[0]->was_checked = true;
 
 				if (current_always->type != AST_INITIAL) {
 					for (int i = 0; i < mem_width; i++)
@@ -1668,6 +1690,7 @@ skip_dynamic_range_lvalue_expansion:;
 					assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
 							new AstNode(AST_SHIFT_LEFT, mkconst_bits(set_bits_en, false), offset_ast->clone()));
 					assign_en->children[0]->str = id_en;
+					assign_en->children[0]->was_checked = true;
 				}
 
 				delete left_at_zero_ast;
@@ -1679,10 +1702,12 @@ skip_dynamic_range_lvalue_expansion:;
 		{
 			assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), children[1]->clone());
 			assign_data->children[0]->str = id_data;
+			assign_data->children[0]->was_checked = true;
 
 			if (current_always->type != AST_INITIAL) {
 				assign_en = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER), mkconst_bits(set_bits_en, false));
 				assign_en->children[0]->str = id_en;
+				assign_en->children[0]->was_checked = true;
 			}
 		}
 
@@ -3018,6 +3043,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
 		wire_addr->str = id_addr;
 		wire_addr->is_reg = true;
+		wire_addr->was_checked = true;
 		wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
 		mod->children.push_back(wire_addr);
 		while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
@@ -3025,6 +3051,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
 		wire_data->str = id_data;
 		wire_data->is_reg = true;
+		wire_data->was_checked = true;
 		wire_data->is_signed = mem_signed;
 		wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
 		mod->children.push_back(wire_data);
@@ -3093,6 +3120,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			AstNode *wire_addr = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(addr_bits-1, true), mkconst_int(0, true)));
 			wire_addr->str = id_addr;
 			wire_addr->is_reg = true;
+			wire_addr->was_checked = true;
 			if (block)
 				wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
 			mod->children.push_back(wire_addr);
@@ -3101,6 +3129,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			AstNode *wire_data = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(mem_width-1, true), mkconst_int(0, true)));
 			wire_data->str = id_data;
 			wire_data->is_reg = true;
+			wire_data->was_checked = true;
 			wire_data->is_signed = mem_signed;
 			if (block)
 				wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
@@ -3109,6 +3138,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 
 			AstNode *assign_addr = new AstNode(block ? AST_ASSIGN_EQ : AST_ASSIGN, new AstNode(AST_IDENTIFIER), children[0]->children[0]->clone());
 			assign_addr->children[0]->str = id_addr;
+			assign_addr->children[0]->was_checked = true;
 
 			AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
 			case_node->children[0]->str = id_addr;
@@ -3119,6 +3149,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 				AstNode *cond_node = new AstNode(AST_COND, AstNode::mkconst_int(i, false, addr_bits), new AstNode(AST_BLOCK));
 				AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), new AstNode(AST_IDENTIFIER));
 				assign_reg->children[0]->str = id_data;
+				assign_reg->children[0]->was_checked = true;
 				assign_reg->children[1]->str = stringf("%s[%d]", str.c_str(), i);
 				cond_node->children[1]->children.push_back(assign_reg);
 				case_node->children.push_back(cond_node);
@@ -3131,6 +3162,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 			AstNode *cond_node = new AstNode(AST_COND, new AstNode(AST_DEFAULT), new AstNode(AST_BLOCK));
 			AstNode *assign_reg = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), AstNode::mkconst_bits(x_bits, false));
 			assign_reg->children[0]->str = id_data;
+			assign_reg->children[0]->was_checked = true;
 			cond_node->children[1]->children.push_back(assign_reg);
 			case_node->children.push_back(cond_node);
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 722febf13..dfdeabbdb 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -548,6 +548,7 @@ task_func_decl:
 		AstNode *outreg = new AstNode(AST_WIRE);
 		outreg->str = *$6;
 		outreg->is_signed = $4;
+		outreg->is_reg = true;
 		if ($5 != NULL) {
 			outreg->children.push_back($5);
 			outreg->is_signed = $4 || $5->is_signed;
diff --git a/tests/various/reg_wire_error.sv b/tests/various/reg_wire_error.sv
index ab461b95a..fe5ff3abd 100644
--- a/tests/various/reg_wire_error.sv
+++ b/tests/various/reg_wire_error.sv
@@ -2,11 +2,13 @@ module sub_mod(input i_in, output o_out);
 assign o_out = i_in;
 endmodule
 
-module test(i_clk, i_reg, o_reg, o_wire);
+module test(i_clk, i, i_reg, o_reg, o_wire, o_mr, o_mw, o_ml);
 input i_clk;
+input i;
 input i_reg;
 output o_reg;
 output o_wire;
+output o_mr, o_mw, o_ml;
 
 // Enable this to see how it doesn't fail on yosys although it should
 //reg o_wire;
@@ -15,12 +17,12 @@ logic o_wire;
 // Enable this to see how it doesn't fail on yosys although it should
 //reg i_reg;
 // Disable this to see how it doesn't fail on yosys although it should
-reg o_reg;
+//reg o_reg;
 
 logic l_reg;
 
 // Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
-//assign l_reg = !o_reg;
+assign l_reg = !o_reg;
 initial o_reg = 1'b0;
 always @(posedge i_clk)
 begin
@@ -30,11 +32,43 @@ end
 
 assign o_wire = !o_reg;
 // Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
-//assign l_reg = !o_reg;
+assign l_reg = !o_reg;
 
 sub_mod sm_inst (
   .i_in(1'b1),
   .o_out(o_reg)
 );
+
+wire   mw1[0:1];
+wire   mw2[0:1];
+wire   mw3[0:1];
+reg    mr1[0:1];
+reg    mr2[0:1];
+reg    mr3[0:1];
+logic  ml1[0:1];
+logic  ml2[0:1];
+logic  ml3[0:1];
+
+assign o_mw = mw1[i];
+assign o_mr = mr1[i];
+assign o_ml = ml1[i];
+
+assign mw1[1] = 1'b1;
+//assign mr1[1] = 1'b1;
+assign ml1[1] = 1'b1;
+always @(posedge i_clk)
+begin
+  mr2[0] = 1'b0;
+  mw2[0] = 1'b0;
+  ml2[0] = 1'b0;
+end
+
+always @(posedge i_clk)
+begin
+  mr3[0] <= 1'b0;
+  mw3[0] <= 1'b0;
+  ml3[0] <= 1'b0;
+end
+
 endmodule
 

From 8b7580b0a152ec937abb1510abf5f2d7cd3b7acb Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Wed, 6 Jun 2018 22:27:25 +0300
Subject: [PATCH 008/528] Detect illegal port declaration, e.g
 input/output/inout keyword must be the first.

---
 frontends/verilog/verilog_parser.y | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index e803d8072..72a501d11 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -376,9 +376,10 @@ wire_type:
 	};
 
 wire_type_token_list:
-	wire_type_token | wire_type_token_list wire_type_token;
+	wire_type_token | wire_type_token_list wire_type_token |
+	wire_type_token_io ;
 
-wire_type_token:
+wire_type_token_io:
 	TOK_INPUT {
 		astbuf3->is_input = true;
 	} |
@@ -388,7 +389,9 @@ wire_type_token:
 	TOK_INOUT {
 		astbuf3->is_input = true;
 		astbuf3->is_output = true;
-	} |
+	};
+
+wire_type_token:
 	TOK_WIRE {
 	} |
 	TOK_REG {

From 848c3c5c889945f64ddefc8fe45342a4338dc769 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 22 Jun 2018 20:40:22 +0200
Subject: [PATCH 009/528] Add YOSYS_NOVERIFIC env variable for temporarily
 disabling verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 62 +++++++++++++++++++++++-------------
 1 file changed, 40 insertions(+), 22 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 3c6566f62..fb27810dd 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1669,6 +1669,16 @@ YOSYS_NAMESPACE_END
 
 PRIVATE_NAMESPACE_BEGIN
 
+bool check_noverific_env()
+{
+	const char *e = getenv("YOSYS_NOVERIFIC");
+	if (e == nullptr)
+		return false;
+	if (atoi(e) == 0)
+		return false;
+	return true;
+}
+
 struct VerificPass : public Pass {
 	VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
 	virtual void help()
@@ -1759,6 +1769,9 @@ struct VerificPass : public Pass {
 #ifdef YOSYS_ENABLE_VERIFIC
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
+		if (check_noverific_env())
+			log_cmd_error("This version of Yosys is built without Verific support.\n");
+
 		log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
 
 		Message::SetConsoleOutput(0);
@@ -2135,44 +2148,50 @@ struct ReadPass : public Pass {
 		if (args.size() < 3)
 			log_cmd_error("Missing file name parameter.\n");
 
-		if (args[1] == "-vlog95" || args[1] == "-vlog2k") {
 #ifdef YOSYS_ENABLE_VERIFIC
-			args[0] = "verific";
+		bool use_verific = !check_noverific_env();
 #else
-			args[0] = "read_verilog";
-			args.erase(args.begin()+1, args.begin()+2);
+		bool use_verific = false;
 #endif
+
+		if (args[1] == "-vlog95" || args[1] == "-vlog2k") {
+			if (use_verific) {
+				args[0] = "verific";
+			} else {
+				args[0] = "read_verilog";
+				args.erase(args.begin()+1, args.begin()+2);
+			}
 			Pass::call(design, args);
 			return;
 		}
 
 		if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv") {
-#ifdef YOSYS_ENABLE_VERIFIC
-			args[0] = "verific";
-#else
-			args[0] = "read_verilog";
-			args[1] = "-sv";
-#endif
+			if (use_verific) {
+				args[0] = "verific";
+			} else {
+				args[0] = "read_verilog";
+				args[1] = "-sv";
+			}
 			Pass::call(design, args);
 			return;
 		}
 
 		if (args[1] == "-vhdl87" || args[1] == "-vhdl93" || args[1] == "-vhdl2k" || args[1] == "-vhdl2008" || args[1] == "-vhdl") {
-#ifdef YOSYS_ENABLE_VERIFIC
-			args[0] = "verific";
-#else
-			log_cmd_error("This version of Yosys is built without Verific support.\n");
-#endif
-			Pass::call(design, args);
+			if (use_verific) {
+				args[0] = "verific";
+				Pass::call(design, args);
+			} else {
+				log_cmd_error("This version of Yosys is built without Verific support.\n");
+			}
 			return;
 		}
 
 		if (args[1] == "-define") {
-#ifdef YOSYS_ENABLE_VERIFIC
-			args[0] = "verific";
-			args[1] = "-vlog-define";
-			Pass::call(design, args);
-#endif
+			if (use_verific) {
+				args[0] = "verific";
+				args[1] = "-vlog-define";
+				Pass::call(design, args);
+			}
 			args[0] = "verilog_defines";
 			args.erase(args.begin()+1, args.begin()+2);
 			for (int i = 1; i < GetSize(args); i++)
@@ -2186,4 +2205,3 @@ struct ReadPass : public Pass {
 } ReadPass;
 
 PRIVATE_NAMESPACE_END
-

From ee7164b87902313fe7a4af616891340b449db900 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 27 Jun 2018 16:26:36 -0400
Subject: [PATCH 010/528] Use msys2-provided pthreads instead of abc's.

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 11803ec0a..e8d7addf5 100644
--- a/Makefile
+++ b/Makefile
@@ -217,7 +217,7 @@ CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := $(filter-out -lrt,$(LDLIBS))
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=0
+ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
 else ifneq ($(CONFIG),none)

From 7e5801beedf63a713386433672429dbc607819c7 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 27 Jun 2018 16:33:34 -0400
Subject: [PATCH 011/528] Add support for 64-bit builds using msys2
 environment.

---
 Makefile | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index e8d7addf5..35759d559 100644
--- a/Makefile
+++ b/Makefile
@@ -5,6 +5,7 @@ CONFIG := clang
 # CONFIG := emcc
 # CONFIG := mxe
 # CONFIG := msys2
+# CONFIG := msys2-64
 
 # features (the more the better)
 ENABLE_TCL := 1
@@ -220,8 +221,19 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC
 ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="i686-w64-mingw32-gcc" CXX="$(CXX)"
 EXE = .exe
 
+else ifeq ($(CONFIG),msys2-64)
+CXX = x86_64-w64-mingw32-g++
+LD = x86_64-w64-mingw32-g++
+CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_WIN32_UNIX_DIR
+CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
+LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
+LDLIBS := $(filter-out -lrt,$(LDLIBS))
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
+ABCMKARGS += LIBS="-lpthread -s" ABC_USE_NO_READLINE=0 CC="x86_64-w64-mingw32-gcc" CXX="$(CXX)"
+EXE = .exe
+
 else ifneq ($(CONFIG),none)
-$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2)
+$(error Invalid CONFIG setting '$(CONFIG)'. Valid values: clang, gcc, gcc-4.8, emcc, mxe, msys2, msys2-64)
 endif
 
 ifeq ($(ENABLE_LIBYOSYS),1)
@@ -676,6 +688,9 @@ config-mxe: clean
 config-msys2: clean
 	echo 'CONFIG := msys2' > Makefile.conf
 
+config-msys2-64: clean
+	echo 'CONFIG := msys2-64' > Makefile.conf
+
 config-gprof: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 	echo 'ENABLE_GPROF := 1' >> Makefile.conf

From fe2ee833e154691ef61cc72833b86e02266039a2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Jun 2018 16:57:03 +0200
Subject: [PATCH 012/528] Fix handling of signed memories

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 40cbbc2a3..d9f0039af 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1300,6 +1300,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0);
 			cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0);
 
+			if (!sign_hint)
+				is_signed = false;
+
 			return RTLIL::SigSpec(wire);
 		}
 

From 07e616900c2d6ddf021644f9687954d92ac8109a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Jun 2018 23:43:38 +0200
Subject: [PATCH 013/528] Add "read -undef"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index fb27810dd..4fa74df3d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1715,6 +1715,11 @@ struct VerificPass : public Pass {
 		log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
 		log("\n");
 		log("\n");
+		log("    verific -vlog-undef <macro>..\n");
+		log("\n");
+		log("Remove Verilog defines previously set with -vlog-define.\n");
+		log("\n");
+		log("\n");
 		log("    verific -import [options] <top-module>..\n");
 		log("\n");
 		log("Elaborate the design for the specified top modules, import to Yosys and\n");
@@ -1828,6 +1833,14 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+		if (GetSize(args) > argidx && args[argidx] == "-vlog-undef") {
+			for (argidx++; argidx < GetSize(args); argidx++) {
+				string name = args[argidx];
+				veri_file::UndefineMacro(name.c_str());
+			}
+			goto check_error;
+		}
+
 		if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
 				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv"))
 		{
@@ -2139,6 +2152,11 @@ struct ReadPass : public Pass {
 		log("\n");
 		log("Set global Verilog/SystemVerilog defines.\n");
 		log("\n");
+		log("\n");
+		log("    read -undef <macro>..\n");
+		log("\n");
+		log("Unset global Verilog/SystemVerilog defines.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
@@ -2200,6 +2218,20 @@ struct ReadPass : public Pass {
 			return;
 		}
 
+		if (args[1] == "-undef") {
+			if (use_verific) {
+				args[0] = "verific";
+				args[1] = "-vlog-undef";
+				Pass::call(design, args);
+			}
+			args[0] = "verilog_defines";
+			args.erase(args.begin()+1, args.begin()+2);
+			for (int i = 1; i < GetSize(args); i++)
+				args[i] = "-U" + args[i];
+			Pass::call(design, args);
+			return;
+		}
+
 		log_cmd_error("Missing or unsupported mode parameter.\n");
 	}
 } ReadPass;

From afedb2d03ee07738025ae77d73d280044c29ec2f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Jun 2018 23:58:15 +0200
Subject: [PATCH 014/528] Add "read -sv -D" support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 27 +++++++++++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 4fa74df3d..c9a071f70 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1693,6 +1693,9 @@ struct VerificPass : public Pass {
 		log("Files passed to different calls to this command are treated as belonging to\n");
 		log("different compilation units.\n");
 		log("\n");
+		log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
+		log("the language version (and before file names) to set additional verilog defines.\n");
+		log("\n");
 		log("\n");
 		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
 		log("\n");
@@ -1860,8 +1863,25 @@ struct VerificPass : public Pass {
 			else
 				log_abort();
 
-			for (argidx++; argidx < GetSize(args); argidx++)
-				file_names.Insert(args[argidx].c_str());
+			for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) {
+				std::string name = args[argidx].substr(2);
+				if (args[argidx] == "-D") {
+					if (++argidx >= GetSize(args))
+						break;
+					name = args[argidx];
+				}
+				size_t equal = name.find('=');
+				if (equal != std::string::npos) {
+					string value = name.substr(equal+1);
+					name = name.substr(0, equal);
+					veri_file::DefineMacro(name.c_str(), value.c_str());
+				} else {
+					veri_file::DefineMacro(name.c_str());
+				}
+			}
+
+			while (argidx < GetSize(args))
+				file_names.Insert(args[argidx++].c_str());
 
 			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU))
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
@@ -2142,6 +2162,9 @@ struct ReadPass : public Pass {
 		log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
 		log("is only available via Verific.)\n");
 		log("\n");
+		log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
+		log("the language version (and before file names) to set additional verilog defines.\n");
+		log("\n");
 		log("\n");
 		log("    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
 		log("\n");

From ebf0f003d3e8d219b396d4c6a3943e1ce54d2879 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 29 Jun 2018 10:02:27 +0200
Subject: [PATCH 015/528] Add "verific -formal" and "read -formal"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c9a071f70..62a8028b8 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1695,8 +1695,13 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("Additional -D<macro>[=<value>] options may be added after the option indicating\n");
 		log("the language version (and before file names) to set additional verilog defines.\n");
+		log("The macros SYNTHESIS and VERIFIC are defined implicitly.\n");
 		log("\n");
 		log("\n");
+		log("    verific -formal <verilog-file>..\n");
+		log("\n");
+		log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
+		log("\n");
 		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files into Verific.\n");
@@ -1715,7 +1720,7 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("    verific -vlog-define <macro>[=<value>]..\n");
 		log("\n");
-		log("Add Verilog defines. (The macros SYNTHESIS and VERIFIC are defined implicitly.)\n");
+		log("Add Verilog defines.\n");
 		log("\n");
 		log("\n");
 		log("    verific -vlog-undef <macro>..\n");
@@ -1790,8 +1795,6 @@ struct VerificPass : public Pass {
 		RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 		RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
 		RuntimeFlags::SetVar("db_infer_wide_operators", 1);
-		veri_file::DefineCmdLineMacro("VERIFIC");
-		veri_file::DefineCmdLineMacro("SYNTHESIS");
 
 		verific_verbose = 0;
 
@@ -1845,7 +1848,7 @@ struct VerificPass : public Pass {
 		}
 
 		if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
-				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv"))
+				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
 		{
 			Array file_names;
 			unsigned verilog_mode;
@@ -1858,11 +1861,14 @@ struct VerificPass : public Pass {
 				verilog_mode = veri_file::SYSTEM_VERILOG_2005;
 			else if (args[argidx] == "-sv2009")
 				verilog_mode = veri_file::SYSTEM_VERILOG_2009;
-			else if (args[argidx] == "-sv2012" || args[argidx] == "-sv")
+			else if (args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal")
 				verilog_mode = veri_file::SYSTEM_VERILOG;
 			else
 				log_abort();
 
+			veri_file::DefineMacro("VERIFIC");
+			veri_file::DefineMacro(args[argidx] == "-formal" ? "FORMAL" : "SYNTHESIS");
+
 			for (argidx++; argidx < GetSize(args) && GetSize(args[argidx]) >= 2 && args[argidx].substr(0, 2) == "-D"; argidx++) {
 				std::string name = args[argidx].substr(2);
 				if (args[argidx] == "-D") {
@@ -2157,7 +2163,7 @@ struct ReadPass : public Pass {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..\n");
+		log("    read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..\n");
 		log("\n");
 		log("Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support\n");
 		log("is only available via Verific.)\n");
@@ -2206,11 +2212,13 @@ struct ReadPass : public Pass {
 			return;
 		}
 
-		if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv") {
+		if (args[1] == "-sv2005" || args[1] == "-sv2009" || args[1] == "-sv2012" || args[1] == "-sv" || args[1] == "-formal") {
 			if (use_verific) {
 				args[0] = "verific";
 			} else {
 				args[0] = "read_verilog";
+				if (args[1] == "-formal")
+					args.insert(args.begin()+1, std::string());
 				args[1] = "-sv";
 			}
 			Pass::call(design, args);

From 0404cf61d5f230de70bc6e6e6bf907bf7b112e0d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 29 Jun 2018 19:21:04 +0200
Subject: [PATCH 016/528] Add verific support for eventually properties

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verificsva.cc | 110 ++++++++++++++++++++++++++++++--
 1 file changed, 105 insertions(+), 5 deletions(-)

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 4e440b4ca..9312fd6e6 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -980,7 +980,6 @@ struct VerificSvaImporter
 	bool mode_assume = false;
 	bool mode_cover = false;
 	bool mode_trigger = false;
-	bool eventually = false;
 
 	Instance *net_to_ast_driver(Net *n)
 	{
@@ -1487,6 +1486,69 @@ struct VerificSvaImporter
 			fsm.getFirstAcceptReject(accept_p, reject_p);
 	}
 
+	bool eventually_property(Net *&net, SigBit &trig)
+	{
+		if (clocking.cond_net != nullptr)
+			trig = importer->net_map_at(clocking.cond_net);
+		else
+			trig = State::S1;
+
+		Instance *inst = net_to_ast_driver(net);
+
+		if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY)
+		{
+			if (mode_cover || mode_trigger)
+				parser_error(inst);
+
+			net = inst->GetInput();
+			clocking.cond_net = nullptr;
+
+			return true;
+		}
+
+		if (inst->Type() == PRIM_SVA_OVERLAPPED_IMPLICATION ||
+				inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION)
+		{
+			Net *antecedent_net = inst->GetInput1();
+			Net *consequent_net = inst->GetInput2();
+
+			Instance *consequent_inst = net_to_ast_driver(consequent_net);
+
+			if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY) {
+				return false;
+			}
+
+			if (mode_cover || mode_trigger)
+				parser_error(consequent_inst);
+
+			int node;
+
+			log_dump(trig);
+			SvaFsm antecedent_fsm(clocking, trig);
+			node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net);
+			if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) {
+				int next_node = antecedent_fsm.createNode();
+				antecedent_fsm.createEdge(node, next_node);
+				node = next_node;
+			}
+			antecedent_fsm.createLink(node, antecedent_fsm.acceptNode);
+
+			trig = antecedent_fsm.getAccept();
+			net = consequent_inst->GetInput();
+			clocking.cond_net = nullptr;
+
+			if (verific_verbose) {
+				log("    Eventually Antecedent FSM:\n");
+				antecedent_fsm.dump();
+				log_dump(trig);
+			}
+
+			return true;
+		}
+
+		return false;
+	}
+
 	void parse_property(Net *net, SigBit *accept_p, SigBit *reject_p)
 	{
 		Instance *inst = net_to_ast_driver(net);
@@ -1620,10 +1682,48 @@ struct VerificSvaImporter
 			}
 			else
 			{
-				if (mode_assert || mode_assume) {
-					parse_property(clocking.body_net, nullptr, &reject_bit);
-				} else {
-					parse_property(clocking.body_net, &accept_bit, nullptr);
+				Net *net = clocking.body_net;
+				SigBit trig;
+
+				if (eventually_property(net, trig))
+				{
+					SigBit sig_a, sig_en = trig;
+					parse_property(net, &sig_a, nullptr);
+
+					log_dump(trig, sig_a, sig_en);
+
+					// add final FF stage
+
+					SigBit sig_a_q, sig_en_q;
+
+					if (clocking.body_net == nullptr) {
+						sig_a_q = sig_a;
+						sig_en_q = sig_en;
+					} else {
+						sig_a_q = module->addWire(NEW_ID);
+						sig_en_q = module->addWire(NEW_ID);
+						clocking.addDff(NEW_ID, sig_a, sig_a_q, State::S0);
+						clocking.addDff(NEW_ID, sig_en, sig_en_q, State::S0);
+					}
+
+					// generate fair/live cell
+
+					RTLIL::Cell *c = nullptr;
+
+					if (mode_assert) c = module->addLive(root_name, sig_a_q, sig_en_q);
+					if (mode_assume) c = module->addFair(root_name, sig_a_q, sig_en_q);
+
+					importer->import_attributes(c->attributes, root);
+
+					return;
+				}
+				else
+				{
+					if (mode_assert || mode_assume) {
+						parse_property(net, nullptr, &reject_bit);
+					} else {
+						parse_property(net, &accept_bit, nullptr);
+					}
 				}
 			}
 

From 8b92ddb9d2635c30636b17ff3d24bc09a44b8551 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 29 Jun 2018 19:24:58 +0200
Subject: [PATCH 017/528] Fix verific eventually handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verificsva.cc | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 9312fd6e6..8e985c3a6 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1488,13 +1488,16 @@ struct VerificSvaImporter
 
 	bool eventually_property(Net *&net, SigBit &trig)
 	{
+		Instance *inst = net_to_ast_driver(net);
+
+		if (inst == nullptr)
+			return false;
+
 		if (clocking.cond_net != nullptr)
 			trig = importer->net_map_at(clocking.cond_net);
 		else
 			trig = State::S1;
 
-		Instance *inst = net_to_ast_driver(net);
-
 		if (inst->Type() == PRIM_SVA_S_EVENTUALLY || inst->Type() == PRIM_SVA_EVENTUALLY)
 		{
 			if (mode_cover || mode_trigger)
@@ -1523,7 +1526,6 @@ struct VerificSvaImporter
 
 			int node;
 
-			log_dump(trig);
 			SvaFsm antecedent_fsm(clocking, trig);
 			node = parse_sequence(antecedent_fsm, antecedent_fsm.createStartNode(), antecedent_net);
 			if (inst->Type() == PRIM_SVA_NON_OVERLAPPED_IMPLICATION) {
@@ -1540,7 +1542,6 @@ struct VerificSvaImporter
 			if (verific_verbose) {
 				log("    Eventually Antecedent FSM:\n");
 				antecedent_fsm.dump();
-				log_dump(trig);
 			}
 
 			return true;
@@ -1690,8 +1691,6 @@ struct VerificSvaImporter
 					SigBit sig_a, sig_en = trig;
 					parse_property(net, &sig_a, nullptr);
 
-					log_dump(trig, sig_a, sig_en);
-
 					// add final FF stage
 
 					SigBit sig_a_q, sig_en_q;

From 0caa62802ccb3ee67e05c948a9e334504cae9cc4 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 6 Jul 2018 01:36:41 -0400
Subject: [PATCH 018/528] Gate POSIX-only signals and resource module to only
 run on POSIX Python implementations.

---
 backends/smt2/smtio.py | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 1a8d2484c..3fc823e3e 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -17,7 +17,9 @@
 #
 
 import sys, re, os, signal
-import resource, subprocess
+import subprocess
+if os.name == "posix":
+    import resource
 from copy import deepcopy
 from select import select
 from time import time
@@ -27,12 +29,13 @@ from threading import Thread
 
 # This is needed so that the recursive SMT2 S-expression parser
 # does not run out of stack frames when parsing large expressions
-smtio_reclimit = 64 * 1024
-smtio_stacksize = 128 * 1024 * 1024
-if sys.getrecursionlimit() < smtio_reclimit:
-    sys.setrecursionlimit(smtio_reclimit)
-if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize:
-    resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1))
+if os.name == "posix":
+    smtio_reclimit = 64 * 1024
+    smtio_stacksize = 128 * 1024 * 1024
+    if sys.getrecursionlimit() < smtio_reclimit:
+        sys.setrecursionlimit(smtio_reclimit)
+    if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize:
+        resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1))
 
 
 # currently running solvers (so we can kill them)
@@ -51,8 +54,9 @@ def force_shutdown(signum, frame):
             os.kill(p.pid, signal.SIGTERM)
     sys.exit(1)
 
+if os.name == "posix":
+    signal.signal(signal.SIGHUP, force_shutdown)
 signal.signal(signal.SIGINT, force_shutdown)
-signal.signal(signal.SIGHUP, force_shutdown)
 signal.signal(signal.SIGTERM, force_shutdown)
 
 def except_hook(exctype, value, traceback):
@@ -1053,4 +1057,3 @@ class MkVcd:
                     print("b0 %s" % self.nets[path][0], file=self.f)
                 else:
                     print("b1 %s" % self.nets[path][0], file=self.f)
-

From cd65eeb3b3a2410e6e42f35e8ab58be4276fd104 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 13:09:18 +0200
Subject: [PATCH 019/528] ice40: Add CIN_CONST and CIN_SET parameters to
 ICESTORM_LC

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ice40/cells_sim.v | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 45a02111f..9f73aeb07 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -657,7 +657,12 @@ module ICESTORM_LC (
 	parameter [0:0] SET_NORESET  = 0;
 	parameter [0:0] ASYNC_SR     = 0;
 
-	assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && CIN) : 1'bx;
+	parameter [0:0] CIN_CONST    = 0;
+	parameter [0:0] CIN_SET      = 0;
+
+	wire mux_cin = CIN_CONST ? CIN_SET : CIN;
+
+	assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx;
 
 	wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
 	wire [3:0] lut_s2 = I2 ?   lut_s3[ 7:4] :   lut_s3[3:0];
@@ -1226,4 +1231,3 @@ module SB_IO_OD (
 	endgenerate
 `endif
 endmodule
-

From b1b9e23f949410fe7c337491a5813f2741a5d9a1 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 13:27:24 +0200
Subject: [PATCH 020/528] ecp5: Adding basic cells_sim and mapper for LUTs up
 to LUT7

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v |  86 +++++++++
 techlibs/ecp5/cells_sim.v | 387 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 473 insertions(+)
 create mode 100644 techlibs/ecp5/cells_map.v
 create mode 100644 techlibs/ecp5/cells_sim.v

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
new file mode 100644
index 000000000..399697c14
--- /dev/null
+++ b/techlibs/ecp5/cells_map.v
@@ -0,0 +1,86 @@
+`ifndef NO_LUT
+module \$lut (A, Y);
+    parameter WIDTH = 0;
+    parameter LUT = 0;
+
+    input [WIDTH-1:0] A;
+    output Y;
+
+    generate
+        if (WIDTH == 1) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(1'b0), .C(1'b0), .D(1'b0));
+        end else
+        if (WIDTH == 2) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(1'b0), .D(1'b0));
+        end else
+        if (WIDTH == 3) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(1'b0));
+        end else
+        if (WIDTH == 4) begin
+            LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+        `ifndef NO_PFUMUX
+        end else
+        if (WIDTH == 5) begin
+            wire f0, f1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            PFUMX mux5(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(Y));
+        end else
+        if (WIDTH == 6) begin
+            wire f0, f1, f2, f3, g0, g1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
+            L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
+        end else
+        if (WIDTH == 7) begin
+            wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
+            LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+            LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
+                .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
+            PFUMX mux52(.ALUT(f5), .BLUT(f4), .SD(A[4]), .Z(g2));
+            PFUMX mux53(.ALUT(f7), .BLUT(f6), .SD(A[4]), .Z(g3));
+            L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
+            L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
+            L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
+        `endif
+        end else begin
+            wire _TECHMAP_FAIL_ = 1;
+        end
+    endgenerate
+endmodule
+`endif
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
new file mode 100644
index 000000000..54006218f
--- /dev/null
+++ b/techlibs/ecp5/cells_sim.v
@@ -0,0 +1,387 @@
+// ---------------------------------------
+
+module LUT4(input A, B, C, D, output Z);
+	parameter [15:0] INIT = 16'h0000;
+	assign Z = INIT[{D, C, B, A}];
+endmodule
+
+// ---------------------------------------
+
+module L6MUX21 (input D0, D1, SD, output Z);
+	assign Z = SD ? D1 : D0;
+endmodule
+
+// ---------------------------------------
+
+module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
+	           output S0, S1, COUT);
+
+	parameter [15:0] INIT0 = 16'h0000;
+	parameter [15:0] INIT1 = 16'h0000;
+	parameter INJECT1_0 = "YES";
+	parameter INJECT1_1 = "YES";
+
+	// First half
+	wire LUT4_0 = INIT0[{D0, C0, B0, A0}];
+	wire LUT2_0 = INIT0[{2'b00, B0, A0}];
+
+	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
+	assign S0 = LUT4_0 ^ gated_cin_0;
+
+	wire gated_lut2_0 = (INJECT1_0 == "YES") ? 1'b0 : LUT2_0;
+	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
+
+	// Second half
+	wire LUT4_1 = INIT1[{D1, C1, B1, A1}];
+	wire LUT2_1 = INIT1[{2'b00, B1, A1}];
+
+	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
+	assign S1 = LUT4_1 ^ gated_cin_1;
+
+	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
+	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
+
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_RAM16X2 (
+	input DI0, DI1,
+	input WAD0, WAD1, WAD2, WAD3,
+	input WRE, WCK,
+	input RAD0, RAD1, RAD2, RAD3,
+	output DO0, DO1
+);
+  parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter INITVAL_0 = 16'h0000;
+	parameter INITVAL_1 = 16'h0000;
+
+	reg [1:0] mem[15:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
+	end
+
+	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+	wire muxwre = (WREMUX == "1") ? 1'b1 :
+							  (WREMUX == "0") ? 1'b0 :
+							  (WREMUX == "INV") ? ~WRE :
+							  WRE;
+
+	always @(posedge muxwck)
+		if (muxwre)
+			mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
+
+	assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
+endmodule
+
+// ---------------------------------------
+
+module PFUMX (input ALUT, BLUT, C0, output Z);
+	assign Z = C0 ? ALUT : BLUT;
+endmodule
+
+// ---------------------------------------
+
+module DPR16X4C (
+		input [3:0] DI,
+		input WCK, WRE,
+		input [3:0] RAD,
+		input [3:0] WAD,
+		output [3:0] DO
+);
+	// For legacy Lattice compatibility, INITIVAL is a hex
+	// string rather than a numeric parameter
+	parameter INITVAL = "0x0000000000000000";
+
+	function [63:0] convert_initval;
+		input [143:0] hex_initval;
+		reg done;
+		reg [63:0] temp;
+		reg [7:0] char;
+		integer i;
+		begin
+			done = 1'b0;
+			temp = 0;
+			for (i = 0; i < 16; i = i + 1) begin
+				if (!done) begin
+					char = hex_initval[8*i +: 8];
+					if (char == "x") begin
+						done = 1'b1;
+					end else begin
+						if (char >= "0" && char <= "9")
+							temp[4*i +: 4] = char - "0";
+						else if (char >= "A" && char <= "F")
+							temp[4*i +: 4] = 10 + char - "A";
+						else if (char >= "a" && char <= "f")
+							temp[4*i +: 4] = 10 + char - "a";
+					end
+				end
+			end
+			convert_initval = temp;
+		end
+	endfunction
+
+	localparam conv_initval = convert_initval(INITVAL);
+
+	reg [3:0] ram[0:15];
+	integer i;
+	initial begin
+		for (i = 0; i < 15; i = i + 1) begin
+			ram[i] = conv_initval[4*i +: 4];
+		end
+	end
+
+	always @(posedge WCK)
+		if (WRE)
+			ram[WAD] <= DI;
+
+	assign DO = ram[RAD];
+
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
+	parameter GSR = "ENABLED";
+	parameter [127:0] CEMUX = "1";
+	parameter CLKMUX = "CLK";
+	parameter LSRMUX = "LSR";
+	parameter SRMODE = "LSR_OVER_CE";
+	parameter REGSET = "RESET";
+
+	wire muxce = (CEMUX == "1") ? 1'b1 :
+	             (CEMUX == "0") ? 1'b0 :
+							 (CEMUX == "INV") ? ~CE :
+							 CE;
+
+	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
+	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+
+	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+
+	initial Q = 1'b0;
+
+	generate
+		if (SRMODE == "ASYNC") begin
+			always @(posedge muxclk, posedge muxlsr)
+				if (muxlsr)
+					Q <= srval;
+				else
+					Q <= DI;
+		end else begin
+			always @(posedge muxclk)
+				if (muxlsr)
+					Q <= srval;
+				else
+					Q <= DI;
+		end
+	endgenerate
+endmodule
+
+// ---------------------------------------
+
+module OBZ(input I, T, output O);
+assign O = T ? 1'bz : I;
+endmodule
+
+// ---------------------------------------
+
+module IB(input I, output O);
+assign O = I;
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_IO(
+	inout B,
+	input I,
+	input T,
+	output O
+);
+	parameter DIR = "INPUT";
+
+	generate
+		if (DIR == "INPUT") begin
+			assign B = 1'bz;
+			assign O = B;
+		end else if (DIR == "OUTPUT") begin
+			assign B = T ? 1'bz : I;
+			assign O = 1'bx;
+		end else if (DIR == "INOUT") begin
+			assign B = T ? 1'bz : I;
+			assign O = B;
+		end else begin
+			ERROR_UNKNOWN_IO_MODE error();
+		end
+	endgenerate
+
+endmodule
+
+// ---------------------------------------
+
+module OB(input I, output O);
+assign O = I;
+endmodule
+
+// ---------------------------------------
+
+module BB(input I, T, output O, inout B);
+assign B = T ? 1'bz : I;
+assign O = B;
+endmodule
+
+// ---------------------------------------
+
+module INV(input A, output Z);
+	assign Z = !A;
+endmodule
+
+// ---------------------------------------
+
+module TRELLIS_SLICE(
+	input A0, B0, C0, D0,
+	input A1, B1, C1, D1,
+	input M0, M1,
+	input FCI, FXA, FXB,
+
+	input CLK, LSR, CE,
+	input DI0, DI1,
+
+	input WD0, WD1,
+	input WAD0, WAD1, WAD2, WAD3,
+	input WRE, WCK,
+
+	output F0, Q0,
+	output F1, Q1,
+	output FCO, OFX0, OFX1,
+
+	output WDO0, WDO1, WDO2, WDO3,
+	output WADO0, WADO1, WADO2, WADO3
+);
+
+	parameter MODE = "LOGIC";
+	parameter GSR = "ENABLED";
+	parameter SRMODE = "LSR_OVER_CE";
+	parameter [127:0] CEMUX = "1";
+	parameter CLKMUX = "CLK";
+	parameter LSRMUX = "LSR";
+	parameter LUT0_INITVAL = 16'h0000;
+	parameter LUT1_INITVAL = 16'h0000;
+	parameter REG0_SD = "0";
+	parameter REG1_SD = "0";
+	parameter REG0_REGSET = "RESET";
+	parameter REG1_REGSET = "RESET";
+	parameter [127:0] CCU2_INJECT1_0 = "NO";
+	parameter [127:0] CCU2_INJECT1_1 = "NO";
+	parameter WREMUX = "WRE";
+
+	function [15:0] permute_initval;
+		input [15:0] initval;
+		integer i;
+		begin
+			for (i = 0; i < 16; i = i + 1) begin
+				permute_initval[{i[0], i[2], i[1], i[3]}] = initval[i];
+			end
+		end
+	endfunction
+
+	generate
+		if (MODE == "LOGIC") begin
+			// LUTs
+			LUT4 #(
+				.INIT(LUT0_INITVAL)
+			) lut4_0 (
+				.A(A0), .B(B0), .C(C0), .D(D0),
+				.Z(F0)
+			);
+			LUT4 #(
+				.INIT(LUT1_INITVAL)
+			) lut4_1 (
+				.A(A1), .B(B1), .C(C1), .D(D1),
+				.Z(F1)
+			);
+			// LUT expansion muxes
+			PFUMX lut5_mux (.ALUT(F1), .BLUT(F0), .C0(M0), .Z(OFX0));
+			L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M1), .Z(OFX1));
+		end else if (MODE == "CCU2") begin
+			CCU2C #(
+				.INIT0(LUT0_INITVAL),
+				.INIT1(LUT1_INITVAL),
+				.INJECT1_0(CCU2_INJECT1_0),
+				.INJECT1_1(CCU2_INJECT1_1)
+		  ) ccu2c_i (
+				.CIN(FCI),
+				.A0(A0), .B0(B0), .C0(C0), .D0(D0),
+				.A1(A1), .B1(B1), .C1(C1), .D1(D1),
+				.S0(F0), .S1(F1),
+				.COUT(FCO)
+			);
+		end else if (MODE == "RAMW") begin
+			assign WDO0 = C1;
+			assign WDO1 = A1;
+			assign WDO2 = D1;
+			assign WDO3 = B1;
+			assign WADO0 = D0;
+			assign WADO1 = B0;
+			assign WADO2 = C0;
+			assign WADO3 = A0;
+		end else if (MODE == "DPRAM") begin
+			TRELLIS_RAM16X2 #(
+				.INITVAL_0(permute_initval(LUT0_INITVAL)),
+				.INITVAL_1(permute_initval(LUT1_INITVAL)),
+				.WREMUX(WREMUX)
+			) ram_i (
+				.DI0(WD0), .DI1(WD1),
+				.WAD0(WAD0), .WAD1(WAD1), .WAD2(WAD2), .WAD3(WAD3),
+				.WRE(WRE), .WCK(WCK),
+				.RAD0(D0), .RAD1(B0), .RAD2(C0), .RAD3(A0),
+				.DO0(F0), .DO1(F1)
+			);
+			// TODO: confirm RAD and INITVAL ordering
+			// DPRAM mode contract?
+			always @(*) begin
+				assert(A0==A1);
+				assert(B0==B1);
+				assert(C0==C1);
+				assert(D0==D1);
+			end
+		end else begin
+			ERROR_UNKNOWN_SLICE_MODE error();
+		end
+	endgenerate
+
+	// FF input selection muxes
+	wire muxdi0 = (REG0_SD == "1") ? DI0 : M0;
+	wire muxdi1 = (REG1_SD == "1") ? DI1 : M1;
+	// Flipflops
+	TRELLIS_FF #(
+		.GSR(GSR),
+		.CEMUX(CEMUX),
+		.CLKMUX(CLKMUX),
+		.LSRMUX(LSRMUX),
+		.SRMODE(SRMODE),
+		.REGSET(REG0_REGSET)
+	) ff_0 (
+		.CLK(CLK), .LSR(LSR), .CE(CE),
+		.DI(muxdi0),
+		.Q(Q0)
+	);
+	TRELLIS_FF #(
+		.GSR(GSR),
+		.CEMUX(CEMUX),
+		.CLKMUX(CLKMUX),
+		.LSRMUX(LSRMUX),
+		.SRMODE(SRMODE),
+		.REGSET(REG1_REGSET)
+	) ff_1 (
+		.CLK(CLK), .LSR(LSR), .CE(CE),
+		.DI(muxdi1),
+		.Q(Q1)
+	);
+endmodule
+

From 1def34f2a64603a3186dc50460fe964f1f197a43 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 14:08:42 +0200
Subject: [PATCH 021/528] ecp5: Adding DRAM map

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_sim.v | 37 ++++++++++++++++++++++++++++++++++++-
 techlibs/ecp5/dram.txt    | 12 ++++++++++++
 techlibs/ecp5/drams_map.v | 28 ++++++++++++++++++++++++++++
 3 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ecp5/dram.txt
 create mode 100644 techlibs/ecp5/drams_map.v

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 54006218f..06e6133a7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -52,7 +52,7 @@ module TRELLIS_RAM16X2 (
 	input RAD0, RAD1, RAD2, RAD3,
 	output DO0, DO1
 );
-  parameter WCKMUX = "WCK";
+  	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter INITVAL_0 = 16'h0000;
 	parameter INITVAL_1 = 16'h0000;
@@ -87,6 +87,41 @@ endmodule
 
 // ---------------------------------------
 
+module TRELLIS_DPR16X4 (
+	input [3:0] DI,
+	input [3:0] WAD,
+	input WRE, WCK,
+	input [3:0] RAD,
+	output [3:0] DO
+);
+  	parameter WCKMUX = "WCK";
+	parameter WREMUX = "WRE";
+	parameter [63:0] INITVAL = 64'h0000000000000000;
+
+	reg [3:0] mem[15:0];
+
+	integer i;
+	initial begin
+		for (i = 0; i < 16; i = i + 1)
+			mem[i] <= INITVAL[4*i :+ 4];
+	end
+
+	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
+
+	wire muxwre = (WREMUX == "1") ? 1'b1 :
+							  (WREMUX == "0") ? 1'b0 :
+							  (WREMUX == "INV") ? ~WRE :
+							  WRE;
+
+	always @(posedge muxwck)
+		if (muxwre)
+			mem[WAD] <= DI;
+
+	assign DO = mem[RAD];
+endmodule
+
+// ---------------------------------------
+
 module DPR16X4C (
 		input [3:0] DI,
 		input WCK, WRE,
diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
new file mode 100644
index 000000000..a13111f0c
--- /dev/null
+++ b/techlibs/ecp5/dram.txt
@@ -0,0 +1,12 @@
+bram $__TRELLIS_DPR16X4
+  init 1
+  abits 4
+  dbits 4
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 2
+endbram
diff --git a/techlibs/ecp5/drams_map.v b/techlibs/ecp5/drams_map.v
new file mode 100644
index 000000000..3b3de831f
--- /dev/null
+++ b/techlibs/ecp5/drams_map.v
@@ -0,0 +1,28 @@
+module \$__TRELLIS_DPR16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0] INIT = 64'bx;
+	parameter CLKPOL2 = 1;
+	input CLK1;
+
+	input [3:0] A1ADDR;
+	output [3:0] A1DATA;
+
+	input [3:0] B1ADDR;
+	input [3:0] B1DATA;
+	input B1EN;
+
+	localparam WCKMUX = CLKPOL2 ? "WCK" : "INV";
+
+	TRELLIS_DPR16X4 #(
+		.INITVAL(INIT),
+		.WCKMUX(WCKMUX),
+		.WREMUX("WRE")
+	) _TECHMAP_REPLACE_ (
+		.RAD(A1ADDR),
+		.DO(A1DATA),
+
+		.WAD(B1ADDR),
+		.DI(B1DATA),
+		.WCK(CLK1),
+		.WRE(B1EN)
+	);
+endmodule

From eb8f3f7dc467156ffaec0ed1a471fe5e610709c7 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 14:32:23 +0200
Subject: [PATCH 022/528] ecp5: Adding DFF maps

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v | 29 +++++++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v |  2 +-
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 399697c14..05874ec09 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -1,3 +1,32 @@
+module  \$_DFF_N_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFFE_NN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("INV"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 06e6133a7..32aec4e93 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -199,7 +199,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 
 	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
-	initial Q = 1'b0;
+	initial Q = srval;
 
 	generate
 		if (SRMODE == "ASYNC") begin

From c2d7be140a2b40ecb553f87437c6f958786030ad Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 14:52:25 +0200
Subject: [PATCH 023/528] ecp5: Adding basic synth_ecp5 based on synth_ice40

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/Makefile.inc  |   7 +
 techlibs/ecp5/cells_map.v   |  14 +-
 techlibs/ecp5/synth_ecp5.cc | 331 ++++++++++++++++++++++++++++++++++++
 3 files changed, 345 insertions(+), 7 deletions(-)
 create mode 100644 techlibs/ecp5/Makefile.inc
 create mode 100644 techlibs/ecp5/synth_ecp5.cc

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
new file mode 100644
index 000000000..e0900f8f4
--- /dev/null
+++ b/techlibs/ecp5/Makefile.inc
@@ -0,0 +1,7 @@
+
+OBJS += techlibs/ecp5/synth_ecp5.o
+
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 05874ec09..6bce03755 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -59,7 +59,7 @@ module \$lut (A, Y);
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
             LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
-            PFUMX mux5(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(Y));
+            PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
         end else
         if (WIDTH == 6) begin
             wire f0, f1, f2, f3, g0, g1;
@@ -73,8 +73,8 @@ module \$lut (A, Y);
             LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
 
-            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
-            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
             L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
         end else
         if (WIDTH == 7) begin
@@ -99,10 +99,10 @@ module \$lut (A, Y);
             LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
                 .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
 
-            PFUMX mux50(.ALUT(f1), .BLUT(f0), .SD(A[4]), .Z(g0));
-            PFUMX mux51(.ALUT(f3), .BLUT(f2), .SD(A[4]), .Z(g1));
-            PFUMX mux52(.ALUT(f5), .BLUT(f4), .SD(A[4]), .Z(g2));
-            PFUMX mux53(.ALUT(f7), .BLUT(f6), .SD(A[4]), .Z(g3));
+            PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
+            PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
+            PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
+            PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
             L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
             L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
             L6MUX21 mux7  (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
new file mode 100644
index 000000000..219496738
--- /dev/null
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -0,0 +1,331 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018 Clifford Wolf <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthEcp5Pass : public ScriptPass
+{
+	SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
+
+	virtual void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_ecp5 [options]\n");
+		log("\n");
+		log("This command runs synthesis for ECP5 FPGAs.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -blif <file>\n");
+		log("        write the design to the specified BLIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        write the design to the specified EDIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("    -noccu2\n");
+		log("        do not use CCU2 cells in output netlist\n");
+		log("\n");
+		log("    -nodffe\n");
+		log("        do not use flipflops with CE in output netlist\n");
+		log("\n");
+		log("    -nobram\n");
+		log("        do not use BRAM cells in output netlist\n");
+		log("\n");
+		log("    -nodram\n");
+		log("        do not use distributed RAM cells in output netlist\n");
+		log("\n");
+		log("    -nomux\n");
+		log("        do not use PFU muxes to implement LUTs larger than LUT4s\n");
+		log("\n");
+		log("    -abc2\n");
+		log("        run two passes of 'abc' for slightly improved logic density\n");
+		log("\n");
+		log("    -vpr\n");
+		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
+		log("        (this feature is experimental and incomplete)\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, blif_file, edif_file, json_file;
+	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
+
+	virtual void clear_flags() YS_OVERRIDE
+	{
+		top_opt = "-auto-top";
+		blif_file = "";
+		edif_file = "";
+		json_file = "";
+		noccu2 = false;
+		nodffe = false;
+		nobram = false;
+		nodram = false;
+		nomux = false;
+		flatten = true;
+		retime = false;
+		abc2 = false;
+		vpr = false;
+	}
+
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-blif" && argidx+1 < args.size()) {
+				blif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-flatten") {
+				flatten = true;
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			if (args[argidx] == "-noccu2") {
+				noccu2 = true;
+				continue;
+			}
+			if (args[argidx] == "-nodffe") {
+				nodffe = true;
+				continue;
+			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
+			if (args[argidx] == "-nodram") {
+				nodram = true;
+				continue;
+			}
+			if (args[argidx] == "-abc2") {
+				abc2 = true;
+				continue;
+			}
+			if (args[argidx] == "-vpr") {
+				vpr = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+		log_header(design, "Executing SYNTH_ECP5 pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	virtual void script() YS_OVERRIDE
+	{
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib +/ecp5/cells_sim.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		{
+			run("proc");
+			run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+		}
+
+		if (check_label("coarse"))
+		{
+			run("synth -run coarse");
+		}
+
+		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		{
+			//TODO
+#if 0
+			run("memory_bram -rules +/ecp5/brams.txt");
+			run("techmap -map +/ecp5/brams_map.v");
+#endif
+		}
+
+		if (!nodram && check_label("dram", "(skip if -nodram)"))
+		{
+			run("memory_bram -rules +/ecp5/dram.txt");
+			run("techmap -map +/ecp5/drams_map.v");
+		}
+
+		if (check_label("fine"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine");
+			//TODO
+#if 0
+			if (nocarry)
+				run("techmap");
+			else
+				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
+#else
+				run("techmap");
+#endif
+			if (retime || help_mode)
+				run("abc -dff", "(only if -retime)");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("dffsr2dff");
+			if (!nodffe)
+				run("dff2dffe -direct-match $_DFF_*");
+			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
+			run("opt_expr -mux_undef");
+			run("simplemap");
+			// TODO
+#if 0
+			run("ecp5_ffinit");
+			run("ecp5_ffssr");
+#endif
+		}
+
+		if (check_label("map_luts"))
+		{
+			if (abc2 || help_mode) {
+				run("abc", "      (only if -abc2)");
+			}
+			//TODO
+#if 0
+			run("techmap -map +/ecp5/latches_map.v");
+#endif
+			if (nomux)
+				run("abc -lut 4");
+			else
+				run("abc -lut 4:7");
+			run("clean");
+		}
+
+		if (check_label("map_cells"))
+		{
+			if (vpr)
+				run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
+			else
+				run("techmap -map +/ecp5/cells_map.v", "(with -D NO_LUT in vpr mode)");
+
+			run("clean");
+		}
+
+		if (check_label("check"))
+		{
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+		}
+
+		if (check_label("blif"))
+		{
+			if (!blif_file.empty() || help_mode) {
+				if (vpr || help_mode) {
+					run(stringf("opt_clean -purge"),
+							"                                 (vpr mode)");
+					run(stringf("write_blif -attr -cname -conn -param %s",
+							help_mode ? "<file-name>" : blif_file.c_str()),
+							" (vpr mode)");
+				}
+				if (!vpr)
+					run(stringf("write_blif -gates -attr -param %s",
+							help_mode ? "<file-name>" : blif_file.c_str()),
+							"       (non-vpr mode)");
+			}
+		}
+
+		if (check_label("edif"))
+		{
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthEcp5Pass;
+
+PRIVATE_NAMESPACE_END

From 11c916840d127d7e32fd9689f1c86cdc847352e0 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 15:46:12 +0200
Subject: [PATCH 024/528] ecp5: Initial arith_map implementation

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/Makefile.inc  |  1 +
 techlibs/ecp5/arith_map.v   | 78 +++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |  7 +---
 3 files changed, 80 insertions(+), 6 deletions(-)
 create mode 100644 techlibs/ecp5/arith_map.v

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index e0900f8f4..9d3247347 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -5,3 +5,4 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
new file mode 100644
index 000000000..3c2b86deb
--- /dev/null
+++ b/techlibs/ecp5/arith_map.v
@@ -0,0 +1,78 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	output [Y_WIDTH-1:0] CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	function integer round_up2;
+		input integer N;
+		begin
+			round_up2 = ((N / 2) + 1) * 2;
+		end
+	endfunction
+
+	localparam Y_WIDTH2 = round_up2(Y_WIDTH);
+
+	wire [Y_WIDTH2-1:0] AA = A_buf;
+	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
+	wire [Y_WIDTH2-1:0] C = {CO, CI};
+	wire [Y_WIDTH2-1:0] FCO;
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
+		CCU2C #(
+			.INIT0(16'b0110011010101010),
+			.INIT1(16'b0110011010101010),
+			.INJECT1_0(1'b0),
+			.INJECT1_1(1'b0)
+	   ) ccu2c_i (
+			.CIN(C[i]),
+			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
+			.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
+			.S0(F0), .S1(F1),
+			.COUT(FCO[i])
+		);
+
+		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
+		if (i < Y_WIDTH)
+			assign CO[i+1] = FCO[i];
+
+	end endgenerate
+
+	assign X = AA ^ BB;
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 219496738..86d2027de 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -236,15 +236,10 @@ struct SynthEcp5Pass : public ScriptPass
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
-			//TODO
-#if 0
-			if (nocarry)
+			if (noccu2)
 				run("techmap");
 			else
 				run("techmap -map +/techmap.v -map +/ecp5/arith_map.v");
-#else
-				run("techmap");
-#endif
 			if (retime || help_mode)
 				run("abc -dff", "(only if -retime)");
 		}

From b0fea67cc66ceac64e2cb71874c36cde21aa34df Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 15:49:59 +0200
Subject: [PATCH 025/528] ecp5: Fixing arith_map

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/arith_map.v | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 3c2b86deb..cf21ee80e 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -51,7 +51,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	wire [Y_WIDTH2-1:0] AA = A_buf;
 	wire [Y_WIDTH2-1:0] BB = BI ? ~B_buf : B_buf;
 	wire [Y_WIDTH2-1:0] C = {CO, CI};
-	wire [Y_WIDTH2-1:0] FCO;
+	wire [Y_WIDTH2-1:0] FCO, Y1;
 
 	genvar i;
 	generate for (i = 0; i < Y_WIDTH2; i = i + 2) begin:slice
@@ -64,14 +64,15 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 			.CIN(C[i]),
 			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
 			.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
-			.S0(F0), .S1(F1),
+			.S0(Y[i]), .S1(Y1[i]),
 			.COUT(FCO[i])
 		);
 
 		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
-		if (i < Y_WIDTH)
+		if (i < Y_WIDTH) begin
 			assign CO[i+1] = FCO[i];
-
+			assign Y[i+1] = Y1[i];
+		end
 	end endgenerate
 
 	assign X = AA ^ BB;

From 4a60bc83ab47b76632b38fcaec4cefffa152f507 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 16:14:08 +0200
Subject: [PATCH 026/528] ecp5: Cells and mappings fixes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/arith_map.v | 6 +++---
 techlibs/ecp5/cells_sim.v | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index cf21ee80e..05d44b9b4 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -58,12 +58,12 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 		CCU2C #(
 			.INIT0(16'b0110011010101010),
 			.INIT1(16'b0110011010101010),
-			.INJECT1_0(1'b0),
-			.INJECT1_1(1'b0)
+			.INJECT1_0("NO"),
+			.INJECT1_1("NO")
 	   ) ccu2c_i (
 			.CIN(C[i]),
 			.A0(AA[i]), .B0(BB[i]), .C0(1'b0), .D0(1'b1),
-			.A1(AA[i+1]), .B1(BB[i]), .C1(1'b0), .D1(1'b1),
+			.A1(AA[i+1]), .B1(BB[i+1]), .C1(1'b0), .D1(1'b1),
 			.S0(Y[i]), .S1(Y1[i]),
 			.COUT(FCO[i])
 		);
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 32aec4e93..6c53a78eb 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -103,7 +103,7 @@ module TRELLIS_DPR16X4 (
 	integer i;
 	initial begin
 		for (i = 0; i < 16; i = i + 1)
-			mem[i] <= INITVAL[4*i :+ 4];
+			mem[i] <= {INITVAL[i+3], INITVAL[i+2], INITVAL[i+1], INITVAL[i]};
 	end
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
@@ -197,7 +197,7 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
 
-	wire srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 
 	initial Q = srval;
 

From 241429abac67de34b073db46550b1c2b4a42d425 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Fri, 13 Jul 2018 16:25:52 +0200
Subject: [PATCH 027/528] ecp5: Add DRAM match rule

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/dram.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
index a13111f0c..b3252fa9a 100644
--- a/techlibs/ecp5/dram.txt
+++ b/techlibs/ecp5/dram.txt
@@ -10,3 +10,7 @@ bram $__TRELLIS_DPR16X4
   clocks 0 1
   clkpol 0 2
 endbram
+
+match $__TRELLIS_DPR16X4
+  make_outreg
+endmatch

From 459d3679134d4e30d9b4bfbc7007368d229c9e9f Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sat, 14 Jul 2018 15:54:30 +0200
Subject: [PATCH 028/528] ecp5: Adding synchronous set/reset support

Signed-off-by: David Shah <davey1576@gmail.com>
---
 passes/techmap/Makefile.inc |   2 +-
 passes/techmap/dff2dffe.cc  |  14 +++-
 passes/techmap/dff2dffs.cc  | 142 ++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/cells_map.v   |  52 +++++++++----
 techlibs/ecp5/synth_ecp5.cc |   5 +-
 5 files changed, 194 insertions(+), 21 deletions(-)
 create mode 100644 passes/techmap/dff2dffs.cc

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 140a9f892..4faa0ab00 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -35,6 +35,7 @@ OBJS += passes/techmap/insbuf.o
 OBJS += passes/techmap/attrmvcp.o
 OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
+OBJS += passes/techmap/dff2dffs.o
 endif
 
 GENFILES += passes/techmap/techmap.inc
@@ -57,4 +58,3 @@ yosys-filterlib$(EXE): passes/techmap/filterlib.o
 	$(Q) mkdir -p $(dir $@)
 	$(P) $(LD) -o yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS)
 endif
-
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 1b8920bb7..4d515f174 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -279,8 +279,9 @@ struct Dff2dffePass : public Pass {
 		log("    -direct-match <pattern>\n");
 		log("        like -direct for all DFF cell types matching the expression.\n");
 		log("        this will use $__DFFE_* as <external_gate_type> matching the\n");
-		log("        internal gate type $_DFF_*_, except for $_DFF_[NP]_, which is\n");
-		log("        converted to $_DFFE_[NP]_.\n");
+		log("        internal gate type $_DFF_*_, and $__DFFSE_* for those matching\n");
+		log("        $_DFFS_*_, except for $_DFF_[NP]_, which is converted to \n");
+		log("        $_DFFE_[NP]_.\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
@@ -315,6 +316,15 @@ struct Dff2dffePass : public Pass {
 				if (patmatch(pattern, "$_DFF_PN1_")) found_match = true, direct_dict["$_DFF_PN1_"] = "$__DFFE_PN1";
 				if (patmatch(pattern, "$_DFF_PP0_")) found_match = true, direct_dict["$_DFF_PP0_"] = "$__DFFE_PP0";
 				if (patmatch(pattern, "$_DFF_PP1_")) found_match = true, direct_dict["$_DFF_PP1_"] = "$__DFFE_PP1";
+
+				if (patmatch(pattern, "$__DFFS_NN0_")) found_match = true, direct_dict["$__DFFS_NN0_"] = "$__DFFSE_NN0";
+				if (patmatch(pattern, "$__DFFS_NN1_")) found_match = true, direct_dict["$__DFFS_NN1_"] = "$__DFFSE_NN1";
+				if (patmatch(pattern, "$__DFFS_NP0_")) found_match = true, direct_dict["$__DFFS_NP0_"] = "$__DFFSE_NP0";
+				if (patmatch(pattern, "$__DFFS_NP1_")) found_match = true, direct_dict["$__DFFS_NP1_"] = "$__DFFSE_NP1";
+				if (patmatch(pattern, "$__DFFS_PN0_")) found_match = true, direct_dict["$__DFFS_PN0_"] = "$__DFFSE_PN0";
+				if (patmatch(pattern, "$__DFFS_PN1_")) found_match = true, direct_dict["$__DFFS_PN1_"] = "$__DFFSE_PN1";
+				if (patmatch(pattern, "$__DFFS_PP0_")) found_match = true, direct_dict["$__DFFS_PP0_"] = "$__DFFSE_PP0";
+				if (patmatch(pattern, "$__DFFS_PP1_")) found_match = true, direct_dict["$__DFFS_PP1_"] = "$__DFFSE_PP1";
 				if (!found_match)
 					log_cmd_error("No cell types matched pattern '%s'.\n", pattern);
 				continue;
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
new file mode 100644
index 000000000..0bfbdc965
--- /dev/null
+++ b/passes/techmap/dff2dffs.cc
@@ -0,0 +1,142 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Dff2dffsPass : public Pass {
+	Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
+	virtual void help()
+	{
+		log("\n");
+		log("    dff2dffs [options] [selection]\n");
+		log("\n");
+		log("Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before\n");
+		log("dff2dffe for SR over CE priority.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		pool<IdString> dff_types;
+		dff_types.insert("$_DFF_N_");
+		dff_types.insert("$_DFF_P_");
+
+		for (auto module : design->selected_modules())
+		{
+			log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+			dict<SigBit, Cell*> sr_muxes;
+			vector<Cell*> ff_cells;
+
+			for (auto cell : module->selected_cells())
+			{
+				if (dff_types.count(cell->type)) {
+					ff_cells.push_back(cell);
+					continue;
+				}
+
+				if (cell->type != "$_MUX_")
+					continue;
+
+				SigBit bit_a = sigmap(cell->getPort("\\A"));
+				SigBit bit_b = sigmap(cell->getPort("\\B"));
+
+				if (bit_a.wire == nullptr || bit_b.wire == nullptr)
+					sr_muxes[sigmap(cell->getPort("\\Y"))] = cell;
+			}
+
+			for (auto cell : ff_cells)
+			{
+				SigSpec sig_d = cell->getPort("\\D");
+
+				if (GetSize(sig_d) < 1)
+					continue;
+
+				SigBit bit_d = sigmap(sig_d[0]);
+
+				if (sr_muxes.count(bit_d) == 0)
+					continue;
+
+				Cell *mux_cell = sr_muxes.at(bit_d);
+				SigBit bit_a = sigmap(mux_cell->getPort("\\A"));
+				SigBit bit_b = sigmap(mux_cell->getPort("\\B"));
+				SigBit bit_s = sigmap(mux_cell->getPort("\\S"));
+
+				log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
+						log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));
+
+				SigBit sr_val, sr_sig;
+				bool invert_sr;
+				sr_sig = bit_s;
+				if (bit_a.wire == nullptr) {
+					bit_d = bit_b;
+					sr_val = bit_a;
+					invert_sr = true;
+				} else {
+					log_assert(bit_b.wire == nullptr);
+					bit_d = bit_a;
+					sr_val = bit_b;
+					invert_sr = false;
+				}
+
+				if (sr_val == State::S1) {
+					if (cell->type == "$_DFF_N_") {
+						if (invert_sr) cell->type = "$__DFFS_NN1_";
+						else cell->type = "$__DFFS_NP1_";
+					} else {
+						log_assert(cell->type == "$_DFF_P_");
+						if (invert_sr) cell->type = "$__DFFS_PN1_";
+						else cell->type = "$__DFFS_PP1_";
+					}
+				} else {
+					if (cell->type == "$_DFF_N_") {
+						if (invert_sr) cell->type = "$__DFFS_NN0_";
+						else cell->type = "$__DFFS_NP0_";
+					} else {
+						log_assert(cell->type == "$_DFF_P_");
+						if (invert_sr) cell->type = "$__DFFS_PN0_";
+						else cell->type = "$__DFFS_PP0_";
+					}
+				}
+				cell->setPort("\\R", sr_sig);
+				cell->setPort("\\D", bit_d);
+			}
+		}
+	}
+} Dff2dffsPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 6bce03755..48162a4dc 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -7,25 +7,45 @@ module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C
 module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+
+module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
 `ifndef NO_LUT
 module \$lut (A, Y);
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 86d2027de..b54bf4204 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -247,15 +247,16 @@ struct SynthEcp5Pass : public ScriptPass
 		if (check_label("map_ffs"))
 		{
 			run("dffsr2dff");
+			run("dff2dffs");
+			run("opt_clean");
 			if (!nodffe)
-				run("dff2dffe -direct-match $_DFF_*");
+				run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 			// TODO
 #if 0
 			run("ecp5_ffinit");
-			run("ecp5_ffssr");
 #endif
 		}
 

From b2c62ff8efb9650ac3eefab4e7756b7ba303962e Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 14:33:13 +0200
Subject: [PATCH 029/528] ecp5: ECP5 synthesis fixes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/arith_map.v   |  4 ++--
 techlibs/ecp5/cells_sim.v   | 39 ++++++++++++++++++++++++-------------
 techlibs/ecp5/synth_ecp5.cc |  4 ++++
 3 files changed, 32 insertions(+), 15 deletions(-)

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 05d44b9b4..1094c5f8a 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -42,7 +42,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	function integer round_up2;
 		input integer N;
 		begin
-			round_up2 = ((N / 2) + 1) * 2;
+			round_up2 = ((N + 1) / 2) * 2;
 		end
 	endfunction
 
@@ -69,7 +69,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 		);
 
 		assign CO[i] = (AA[i] && BB[i]) || (C[i] && (AA[i] || BB[i]));
-		if (i < Y_WIDTH) begin
+		if (i+1 < Y_WIDTH) begin
 			assign CO[i+1] = FCO[i];
 			assign Y[i+1] = Y1[i];
 		end
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 6c53a78eb..1755da24b 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -67,10 +67,15 @@ module TRELLIS_RAM16X2 (
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 
-	wire muxwre = (WREMUX == "1") ? 1'b1 :
-							  (WREMUX == "0") ? 1'b0 :
-							  (WREMUX == "INV") ? ~WRE :
-							  WRE;
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
+
 
 	always @(posedge muxwck)
 		if (muxwre)
@@ -108,10 +113,14 @@ module TRELLIS_DPR16X4 (
 
 	wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
 
-	wire muxwre = (WREMUX == "1") ? 1'b1 :
-							  (WREMUX == "0") ? 1'b0 :
-							  (WREMUX == "INV") ? ~WRE :
-							  WRE;
+	reg muxwre;
+	always @(*)
+		case (WREMUX)
+			"1": muxwre = 1'b1;
+			"0": muxwre = 1'b0;
+			"INV": muxwre = ~WRE;
+			default: muxwre = WRE;
+		endcase
 
 	always @(posedge muxwck)
 		if (muxwre)
@@ -167,7 +176,7 @@ module DPR16X4C (
 	integer i;
 	initial begin
 		for (i = 0; i < 15; i = i + 1) begin
-			ram[i] = conv_initval[4*i +: 4];
+			ram[i] <= conv_initval[4*i +: 4];
 		end
 	end
 
@@ -189,10 +198,14 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	parameter SRMODE = "LSR_OVER_CE";
 	parameter REGSET = "RESET";
 
-	wire muxce = (CEMUX == "1") ? 1'b1 :
-	             (CEMUX == "0") ? 1'b0 :
-							 (CEMUX == "INV") ? ~CE :
-							 CE;
+	reg muxce;
+	always @(*)
+		case (CEMUX)
+			"1": muxce = 1'b1;
+			"0": muxce = 1'b0;
+			"INV": muxce = ~CE;
+			default: muxce = CE;
+		endcase
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index b54bf4204..76051d1a2 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -172,6 +172,10 @@ struct SynthEcp5Pass : public ScriptPass
 				nodram = true;
 				continue;
 			}
+			if (args[argidx] == "-nomux") {
+				nomux = true;
+				continue;
+			}
 			if (args[argidx] == "-abc2") {
 				abc2 = true;
 				continue;

From e9ef077266652b4a76773287199a0b7f18b94a3d Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 15:20:34 +0200
Subject: [PATCH 030/528] ecp5: Fixing 'X' issues with LUT simulation models

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_sim.v | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 1755da24b..cf1446a52 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -1,8 +1,11 @@
 // ---------------------------------------
 
 module LUT4(input A, B, C, D, output Z);
-	parameter [15:0] INIT = 16'h0000;
-	assign Z = INIT[{D, C, B, A}];
+    parameter [15:0] INIT = 16'h0000;
+    wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
+    wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
+    wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
+    assign Z =      A ?          s1[1] :         s1[0];
 endmodule
 
 // ---------------------------------------
@@ -22,8 +25,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
 	parameter INJECT1_1 = "YES";
 
 	// First half
-	wire LUT4_0 = INIT0[{D0, C0, B0, A0}];
-	wire LUT2_0 = INIT0[{2'b00, B0, A0}];
+	wire LUT4_0, LUT2_0;
+	LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
+	LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
 
 	wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
 	assign S0 = LUT4_0 ^ gated_cin_0;
@@ -32,8 +36,9 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
 	wire cout_0 = (~LUT4_0 & gated_lut2_0) | (LUT4_0 & CIN);
 
 	// Second half
-	wire LUT4_1 = INIT1[{D1, C1, B1, A1}];
-	wire LUT2_1 = INIT1[{2'b00, B1, A1}];
+	wire LUT4_1, LUT2_1;
+	LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
+	LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
 
 	wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
 	assign S1 = LUT4_1 ^ gated_cin_1;
@@ -190,6 +195,14 @@ endmodule
 
 // ---------------------------------------
 
+module LUT2(input A, B, output Z);
+    parameter [3:0] INIT = 4'h0;
+    wire [1:0] s1 = B ?     INIT[ 3:2] :     INIT[1:0];
+    assign Z =      A ?          s1[1] :         s1[0];
+endmodule
+
+// ---------------------------------------
+
 module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";

From f39b897545c0f9b4d02c77cc7b6cd2a3bfc6082f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 16 Jul 2018 15:32:26 +0200
Subject: [PATCH 031/528] Add "read -incdir"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 62a8028b8..ab752b96d 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2186,6 +2186,11 @@ struct ReadPass : public Pass {
 		log("\n");
 		log("Unset global Verilog/SystemVerilog defines.\n");
 		log("\n");
+		log("\n");
+		log("    read -incdir <directory>\n");
+		log("\n");
+		log("Add directory to global Verilog/SystemVerilog include directories.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
@@ -2263,6 +2268,20 @@ struct ReadPass : public Pass {
 			return;
 		}
 
+		if (args[1] == "-incdir") {
+			if (use_verific) {
+				args[0] = "verific";
+				args[1] = "-vlog-incdir";
+				Pass::call(design, args);
+			}
+			args[0] = "verilog_defaults";
+			args[1] = "-add";
+			for (int i = 1; i < GetSize(args); i++)
+				args[i] = "-I" + args[i];
+			Pass::call(design, args);
+			return;
+		}
+
 		log_cmd_error("Missing or unsupported mode parameter.\n");
 	}
 } ReadPass;

From 3a3558acce25807d6ce75280cc3f43aeb52974df Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 16 Jul 2018 15:56:12 +0200
Subject: [PATCH 032/528] ecp5: Fixing miscellaneous sim model issues

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_sim.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index cf1446a52..1700694e8 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 			always @(posedge muxclk, posedge muxlsr)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end else begin
 			always @(posedge muxclk)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end
 	endgenerate

From f897af626dc8f84c79dc9274a5a5fa868018480f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 16 Jul 2018 16:48:09 +0200
Subject: [PATCH 033/528] Fix "read -incdir"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index ab752b96d..54b682082 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2276,7 +2276,7 @@ struct ReadPass : public Pass {
 			}
 			args[0] = "verilog_defaults";
 			args[1] = "-add";
-			for (int i = 1; i < GetSize(args); i++)
+			for (int i = 2; i < GetSize(args); i++)
 				args[i] = "-I" + args[i];
 			Pass::call(design, args);
 			return;

From 5041ed2f7df1e932eed6bc4ad38fb0f0973700af Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 16 Jul 2018 18:46:06 +0200
Subject: [PATCH 034/528] Fix verific -vlog-incdir and -vlog-libdir handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 54b682082..8937cdde8 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -65,6 +65,8 @@ int verific_verbose;
 bool verific_import_pending;
 string verific_error_msg;
 
+vector<string> verific_incdirs, verific_libdirs;
+
 void msg_func(msg_type_t msg_type, const char *message_id, linefile_type linefile, const char *msg, va_list args)
 {
 	string message_prefix = stringf("VERIFIC-%s [%s] ",
@@ -1658,6 +1660,8 @@ void verific_import(Design *design, std::string top)
 	veri_file::Reset();
 	vhdl_file::Reset();
 	Libset::Reset();
+	verific_incdirs.clear();
+	verific_libdirs.clear();
 	verific_import_pending = false;
 
 	if (!verific_error_msg.empty())
@@ -1814,13 +1818,13 @@ struct VerificPass : public Pass {
 
 		if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
 			for (argidx++; argidx < GetSize(args); argidx++)
-				veri_file::AddIncludeDir(args[argidx].c_str());
+				verific_incdirs.push_back(args[argidx]);
 			goto check_error;
 		}
 
 		if (GetSize(args) > argidx && args[argidx] == "-vlog-libdir") {
 			for (argidx++; argidx < GetSize(args); argidx++)
-				veri_file::AddYDir(args[argidx].c_str());
+				verific_libdirs.push_back(args[argidx]);
 			goto check_error;
 		}
 
@@ -1886,6 +1890,11 @@ struct VerificPass : public Pass {
 				}
 			}
 
+			for (auto &dir : verific_incdirs)
+				veri_file::AddIncludeDir(dir.c_str());
+			for (auto &dir : verific_libdirs)
+				veri_file::AddYDir(dir.c_str());
+
 			while (argidx < GetSize(args))
 				file_names.Insert(args[argidx++].c_str());
 
@@ -2139,6 +2148,8 @@ struct VerificPass : public Pass {
 			veri_file::Reset();
 			vhdl_file::Reset();
 			Libset::Reset();
+			verific_incdirs.clear();
+			verific_libdirs.clear();
 			verific_import_pending = false;
 			goto check_error;
 		}

From 65234d4b24edd1ec8ec5d41df2d56d76fa41dcc5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 17 Jul 2018 12:43:30 +0200
Subject: [PATCH 035/528] Fix handling of eventually properties in verific
 importer

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verificsva.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 8e985c3a6..85b842186 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1517,9 +1517,11 @@ struct VerificSvaImporter
 
 			Instance *consequent_inst = net_to_ast_driver(consequent_net);
 
-			if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY) {
+			if (consequent_inst == nullptr)
+				return false;
+
+			if (consequent_inst->Type() != PRIM_SVA_S_EVENTUALLY && consequent_inst->Type() != PRIM_SVA_EVENTUALLY)
 				return false;
-			}
 
 			if (mode_cover || mode_trigger)
 				parser_error(consequent_inst);

From 87aef8f0cc9ee63fc8fe5eb26e6ceb73aa83b5c9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 19 Jul 2018 15:31:12 +0200
Subject: [PATCH 036/528] Add async2sync pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/Makefile.inc  |   1 +
 passes/sat/async2sync.cc | 147 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 148 insertions(+)
 create mode 100644 passes/sat/async2sync.cc

diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc
index 4fcce2fad..8ab0280c0 100644
--- a/passes/sat/Makefile.inc
+++ b/passes/sat/Makefile.inc
@@ -7,4 +7,5 @@ OBJS += passes/sat/miter.o
 OBJS += passes/sat/expose.o
 OBJS += passes/sat/assertpmux.o
 OBJS += passes/sat/clk2fflogic.o
+OBJS += passes/sat/async2sync.o
 
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
new file mode 100644
index 000000000..85933acc2
--- /dev/null
+++ b/passes/sat/async2sync.cc
@@ -0,0 +1,147 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Async2syncPass : public Pass {
+	Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { }
+	virtual void help()
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    async2sync [options] [selection]\n");
+		log("\n");
+		log("This command replaces async FF inputs with sync circuits emulating the same\n");
+		log("behavior for when the async signals are actually synchronized to the clock.\n");
+		log("\n");
+		log("This pass assumes negative hold time for the async FF inputs. For example when\n");
+		log("a reset deasserts with the clock edge, then the FF output will still drive the\n");
+		log("reset value in the next cycle regardless of the data-in value at the time of\n");
+		log("the clock edge.\n");
+		log("\n");
+		log("Currently only $adff cells are supported by this pass.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		// bool flag_noinit = false;
+
+		log_header(design, "Executing ASYNC2SYNC pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-noinit") {
+			// 	flag_noinit = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			SigMap sigmap(module);
+			dict<SigBit, State> initbits;
+			pool<SigBit> del_initbits;
+
+			for (auto wire : module->wires())
+				if (wire->attributes.count("\\init") > 0)
+				{
+					Const initval = wire->attributes.at("\\init");
+					SigSpec initsig = sigmap(wire);
+
+					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
+						if (initval[i] == State::S0 || initval[i] == State::S1)
+							initbits[initsig[i]] = initval[i];
+				}
+
+			for (auto cell : vector<Cell*>(module->selected_cells()))
+			{
+				if (cell->type.in("$adff"))
+				{
+					// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
+					bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
+					Const arst_val = cell->parameters["\\ARST_VALUE"];
+
+					SigSpec sig_clk = cell->getPort("\\CLK");
+					SigSpec sig_arst = cell->getPort("\\ARST");
+					SigSpec sig_d = cell->getPort("\\D");
+					SigSpec sig_q = cell->getPort("\\Q");
+
+					log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
+							log_id(module), log_id(cell), log_id(cell->type),
+							log_signal(sig_arst), log_signal(sig_d), log_signal(sig_q));
+
+					Const init_val;
+					for (int i = 0; i < GetSize(sig_q); i++) {
+						SigBit bit = sigmap(sig_q[i]);
+						init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
+						del_initbits.insert(bit);
+					}
+
+					Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
+					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
+					new_q->attributes["\\init"] = init_val;
+
+					if (arst_pol) {
+						module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
+						module->addMux(NEW_ID, new_q, arst_val, sig_arst, sig_q);
+					} else {
+						module->addMux(NEW_ID, arst_val, sig_d, sig_arst, new_d);
+						module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
+					}
+
+					cell->setPort("\\D", new_d);
+					cell->setPort("\\Q", new_q);
+					cell->unsetPort("\\ARST");
+					cell->unsetParam("\\ARST_POLARITY");
+					cell->unsetParam("\\ARST_VALUE");
+					cell->type = "$dff";
+					continue;
+				}
+			}
+
+			for (auto wire : module->wires())
+				if (wire->attributes.count("\\init") > 0)
+				{
+					bool delete_initattr = true;
+					Const initval = wire->attributes.at("\\init");
+					SigSpec initsig = sigmap(wire);
+
+					for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
+						if (del_initbits.count(initsig[i]) > 0)
+							initval[i] = State::Sx;
+						else if (initval[i] != State::Sx)
+							delete_initattr = false;
+
+					if (delete_initattr)
+						wire->attributes.erase("\\init");
+					else
+						wire->attributes.at("\\init") = initval;
+				}
+		}
+	}
+} Async2syncPass;
+
+PRIVATE_NAMESPACE_END

From 1a60126a3468c525ac31de930dfb139b70512a34 Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Thu, 19 Jul 2018 09:40:20 -0700
Subject: [PATCH 037/528] Provide source-location logging.

o Provide log_file_warning() and log_file_error() that prefix the log
  message with <filename>:<lineno>: to be easily picked up by IDEs that
  need to step through errors.
o Simplify some duplicate logging code in kernel/log.cc
o Use the new log functions in genrtlil.
---
 frontends/ast/genrtlil.cc |  5 +--
 kernel/log.cc             | 86 +++++++++++++++++++--------------------
 kernel/log.h              |  5 +++
 3 files changed, 48 insertions(+), 48 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d9f0039af..b8208fa80 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -958,9 +958,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
 				wire->name = str;
 				if (flag_autowire)
-					log_warning("Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_warning(filename, linenum, "Identifier `%s' is implicitly declared.\n", str.c_str());
 				else
-					log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
 			}
 			else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
 				if (id2ast->children[0]->type != AST_CONSTANT)
@@ -1563,4 +1563,3 @@ RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL
 }
 
 YOSYS_NAMESPACE_END
-
diff --git a/kernel/log.cc b/kernel/log.cc
index 6d562b9e6..0ee2170a0 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -203,7 +203,8 @@ void logv_header(RTLIL::Design *design, const char *format, va_list ap)
 		log_files.pop_back();
 }
 
-void logv_warning(const char *format, va_list ap)
+static void logv_warning_with_prefix(const char *prefix,
+                                     const char *format, va_list ap)
 {
 	std::string message = vstringf(format, ap);
 	bool suppressed = false;
@@ -214,7 +215,7 @@ void logv_warning(const char *format, va_list ap)
 
 	if (suppressed)
 	{
-		log("Suppressed warning: %s", message.c_str());
+		log("Suppressed %s%s", prefix, message.c_str());
 	}
 	else
 	{
@@ -224,7 +225,7 @@ void logv_warning(const char *format, va_list ap)
 
 		if (log_warnings.count(message))
 		{
-			log("Warning: %s", message.c_str());
+			log("%s%s", prefix, message.c_str());
 			log_flush();
 		}
 		else
@@ -232,7 +233,7 @@ void logv_warning(const char *format, va_list ap)
 			if (log_errfile != NULL && !log_quiet_warnings)
 				log_files.push_back(log_errfile);
 
-			log("Warning: %s", message.c_str());
+			log("%s%s", prefix, message.c_str());
 			log_flush();
 
 			if (log_errfile != NULL && !log_quiet_warnings)
@@ -245,49 +246,30 @@ void logv_warning(const char *format, va_list ap)
 	}
 }
 
+void logv_warning(const char *format, va_list ap)
+{
+	logv_warning_with_prefix("Warning: ", format, ap);
+}
+
 void logv_warning_noprefix(const char *format, va_list ap)
 {
-	std::string message = vstringf(format, ap);
-	bool suppressed = false;
-
-	for (auto &re : log_nowarn_regexes)
-		if (std::regex_search(message, re))
-			suppressed = true;
-
-	if (suppressed)
-	{
-		log("%s", message.c_str());
-	}
-	else
-	{
-		for (auto &re : log_werror_regexes)
-			if (std::regex_search(message, re))
-				log_error("%s",  message.c_str());
-
-		if (log_warnings.count(message))
-		{
-			log("%s", message.c_str());
-			log_flush();
-		}
-		else
-		{
-			if (log_errfile != NULL && !log_quiet_warnings)
-				log_files.push_back(log_errfile);
-
-			log("%s", message.c_str());
-			log_flush();
-
-			if (log_errfile != NULL && !log_quiet_warnings)
-				log_files.pop_back();
-
-			log_warnings.insert(message);
-		}
-
-		log_warnings_count++;
-	}
+	logv_warning_with_prefix("", format, ap);
 }
 
-void logv_error(const char *format, va_list ap)
+void log_file_warning(const std::string &filename, int lineno,
+                      const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	std::string prefix = stringf("%s:%d: Warning: ",
+				     filename.c_str(), lineno);
+	logv_warning_with_prefix(prefix.c_str(), format, ap);
+	va_end(ap);
+}
+
+YS_ATTRIBUTE(noreturn)
+static void logv_error_with_prefix(const char *prefix,
+                                   const char *format, va_list ap)
 {
 #ifdef EMSCRIPTEN
 	auto backup_log_files = log_files;
@@ -302,7 +284,7 @@ void logv_error(const char *format, va_list ap)
 				f = stderr;
 
 	log_last_error = vstringf(format, ap);
-	log("ERROR: %s", log_last_error.c_str());
+	log("%s%s", prefix, log_last_error.c_str());
 	log_flush();
 
 	if (log_error_atexit)
@@ -318,6 +300,21 @@ void logv_error(const char *format, va_list ap)
 #endif
 }
 
+void logv_error(const char *format, va_list ap)
+{
+	logv_error_with_prefix("ERROR: ", format, ap);
+}
+
+void log_file_error(const string &filename, int lineno,
+                    const char *format, ...)
+{
+	va_list ap;
+	va_start(ap, format);
+	std::string prefix = stringf("%s:%d: ERROR: ",
+				     filename.c_str(), lineno);
+	logv_error_with_prefix(prefix.c_str(), format, ap);
+}
+
 void log(const char *format, ...)
 {
 	va_list ap;
@@ -636,4 +633,3 @@ dict<std::string, std::pair<std::string, int>> get_coverage_data()
 #endif
 
 YOSYS_NAMESPACE_END
-
diff --git a/kernel/log.h b/kernel/log.h
index a2aacfd4d..0b4905c3a 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -73,8 +73,13 @@ YS_NORETURN void logv_error(const char *format, va_list ap) YS_ATTRIBUTE(noretur
 void log(const char *format, ...)  YS_ATTRIBUTE(format(printf, 1, 2));
 void log_header(RTLIL::Design *design, const char *format, ...) YS_ATTRIBUTE(format(printf, 2, 3));
 void log_warning(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
+
+// Log with filename to report a problem in a source file.
+void log_file_warning(const std::string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4));
+
 void log_warning_noprefix(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2));
 YS_NORETURN void log_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
+void log_file_error(const string &filename, int lineno, const char *format, ...) YS_ATTRIBUTE(format(printf, 3, 4), noreturn);
 YS_NORETURN void log_cmd_error(const char *format, ...) YS_ATTRIBUTE(format(printf, 1, 2), noreturn);
 
 void log_spacer();

From b5ea598ef6cec535378c8cbb53170ccd1e5855ca Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 08:11:20 -0700
Subject: [PATCH 038/528] Use log_file_warning(), log_file_error() functions.

Wherever we can report a source-level location.
---
 frontends/ast/genrtlil.cc             |  32 +++----
 frontends/ast/simplify.cc             | 121 +++++++++++++-------------
 frontends/verilog/verilog_frontend.cc |   8 +-
 3 files changed, 79 insertions(+), 82 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index b8208fa80..e611ddcb1 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -238,7 +238,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 		if (found_anyedge_syncs) {
 			if (found_global_syncs)
-				log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum);
+				log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
 			log("Note: Assuming pure combinatorial block at %s:%d in\n", always->filename.c_str(), always->linenum);
 			log("compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending\n");
 			log("use of @* instead of @(...) for better match of synthesis and simulation.\n");
@@ -253,12 +253,12 @@ struct AST_INTERNAL::ProcessGenerator
 					continue;
 				found_clocked_sync = true;
 				if (found_global_syncs || found_anyedge_syncs)
-					log_error("Found non-synthesizable event list at %s:%d!\n", always->filename.c_str(), always->linenum);
+					log_file_error(always->filename, always->linenum, "Found non-synthesizable event list!\n");
 				RTLIL::SyncRule *syncrule = new RTLIL::SyncRule;
 				syncrule->type = child->type == AST_POSEDGE ? RTLIL::STp : RTLIL::STn;
 				syncrule->signal = child->children[0]->genRTLIL();
 				if (GetSize(syncrule->signal) != 1)
-					log_error("Found posedge/negedge event on a signal that is not 1 bit wide at %s:%d!\n", always->filename.c_str(), always->linenum);
+					log_file_error(always->filename, always->linenum, "Found posedge/negedge event on a signal that is not 1 bit wide!\n");
 				addChunkActions(syncrule->actions, subst_lvalue_from, subst_lvalue_to, true);
 				proc->syncs.push_back(syncrule);
 			}
@@ -549,12 +549,12 @@ struct AST_INTERNAL::ProcessGenerator
 			break;
 
 		case AST_WIRE:
-			log_error("Found wire declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
+			log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n");
 			break;
 
 		case AST_PARAMETER:
 		case AST_LOCALPARAM:
-			log_error("Found parameter declaration in block without label at at %s:%d!\n", ast->filename.c_str(), ast->linenum);
+			log_file_error(ast->filename, ast->linenum, "Found parameter declaration in block without label!\n");
 			break;
 
 		case AST_NONE:
@@ -602,7 +602,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		if (id_ast == NULL && current_scope.count(str))
 			id_ast = current_scope.at(str);
 		if (!id_ast)
-			log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", str.c_str());
 		if (id_ast->type == AST_PARAMETER || id_ast->type == AST_LOCALPARAM) {
 			if (id_ast->children.size() > 1 && id_ast->children[1]->range_valid) {
 				this_width = id_ast->children[1]->range_left - id_ast->children[1]->range_right + 1;
@@ -612,7 +612,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 			if (id_ast->children[0]->type == AST_CONSTANT)
 				this_width = id_ast->children[0]->bits.size();
 			else
-				log_error("Failed to detect width for parameter %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Failed to detect width for parameter %s!\n", str.c_str());
 			if (children.size() != 0)
 				range = children[0];
 		} else if (id_ast->type == AST_WIRE || id_ast->type == AST_AUTOWIRE) {
@@ -624,7 +624,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 					// log("---\n");
 					// id_ast->dumpAst(NULL, "decl> ");
 					// dumpAst(NULL, "ref> ");
-					log_error("Failed to detect width of signal access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Failed to detect width of signal access `%s'!\n", str.c_str());
 				}
 			} else {
 				this_width = id_ast->range_left - id_ast->range_right + 1;
@@ -635,10 +635,10 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 			this_width = 32;
 		} else if (id_ast->type == AST_MEMORY) {
 			if (!id_ast->children[0]->range_valid)
-				log_error("Failed to detect width of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
 			this_width = id_ast->children[0]->range_left - id_ast->children[0]->range_right + 1;
 		} else
-			log_error("Failed to detect width for identifier %s at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Failed to detect width for identifier %s!\n", str.c_str());
 		if (range) {
 			if (range->children.size() == 1)
 				this_width = 1;
@@ -665,7 +665,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	case AST_TO_BITS:
 		while (children[0]->simplify(true, false, false, 1, -1, false, false) == true) { }
 		if (children[0]->type != AST_CONSTANT)
-			log_error("Left operand of tobits expression is not constant at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Left operand of tobits expression is not constant!\n");
 		children[1]->detectSignWidthWorker(sub_width_hint, sign_hint);
 		width_hint = max(width_hint, children[0]->bitsAsConst().as_int());
 		break;
@@ -693,7 +693,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	case AST_REPLICATE:
 		while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
 		if (children[0]->type != AST_CONSTANT)
-			log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
 		children[1]->detectSignWidthWorker(sub_width_hint, sub_sign_hint);
 		width_hint = max(width_hint, children[0]->bitsAsConst().as_int() * sub_width_hint);
 		sign_hint = false;
@@ -767,7 +767,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		if (!id2ast->is_signed)
 			sign_hint = false;
 		if (!id2ast->children[0]->range_valid)
-			log_error("Failed to detect width of memory access `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", str.c_str());
 		this_width = id2ast->children[0]->range_left - id2ast->children[0]->range_right + 1;
 		width_hint = max(width_hint, this_width);
 		break;
@@ -1083,7 +1083,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			RTLIL::SigSpec left = children[0]->genRTLIL();
 			RTLIL::SigSpec right = children[1]->genRTLIL();
 			if (!left.is_fully_const())
-				log_error("Left operand of replicate expression is not constant at %s:%d!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Left operand of replicate expression is not constant!\n");
 			int count = left.as_int();
 			RTLIL::SigSpec sig;
 			for (int i = 0; i < count; i++)
@@ -1322,7 +1322,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			int num_words = 1;
 			if (type == AST_MEMINIT) {
 				if (children[2]->type != AST_CONSTANT)
-					log_error("Memory init with non-constant word count at %s:%d!\n", filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Memory init with non-constant word count!\n");
 				num_words = int(children[2]->asInt(false));
 				cell->parameters["\\WORDS"] = RTLIL::Const(num_words);
 			}
@@ -1514,7 +1514,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (attributes.count("\\reg")) {
 					auto &attr = attributes.at("\\reg");
 					if (attr->type != AST_CONSTANT)
-						log_error("Attribute `reg' with non-constant value at %s:%d!\n", filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Attribute `reg' with non-constant value!\n");
 					cell->attributes["\\reg"] =  attr->asAttrConst();
 				}
 
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index a16fdfeeb..81bd3cd7e 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -177,13 +177,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	// note that $display, $finish, and $stop are used for synthesis-time DRC so they're not in this list
 	if ((type == AST_FCALL || type == AST_TCALL) && (str == "$strobe" || str == "$monitor" || str == "$time" ||
 			str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
-		log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum);
+		log_file_warning(filename, linenum, "Ignoring call to system %s %s.\n", type == AST_FCALL ? "function" : "task", str.c_str());
 		delete_children();
 		str = std::string();
 	}
 
 	if ((type == AST_TCALL) && (str == "$display" || str == "$write") && (!current_always || current_always->type != AST_INITIAL)) {
-		log_warning("System task `%s' outside initial block is unsupported at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+		log_file_warning(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str());
 		delete_children();
 		str = std::string();
 	}
@@ -202,7 +202,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		AstNode *node_string = children[0];
 		while (node_string->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 		if (node_string->type != AST_CONSTANT)
-			log_error("Failed to evaluate system task `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant 1st argument.\n", str.c_str());
 		std::string sformat = node_string->bitsAsConst().decode_string();
 
 		// Other arguments are placeholders. Process the string as we go through it
@@ -215,7 +215,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			{
 				// If there's no next character, that's a problem
 				if (i+1 >= sformat.length())
-					log_error("System task `%s' called with `%%' at end of string at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System task `%s' called with `%%' at end of string.\n", str.c_str());
 
 				char cformat = sformat[++i];
 
@@ -245,7 +245,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 						node_arg = children[next_arg++];
 						while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 						if (node_arg->type != AST_CONSTANT)
-							log_error("Failed to evaluate system task `%s' with non-constant argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+							log_file_error(filename, linenum, "Failed to evaluate system task `%s' with non-constant argument.\n", str.c_str());
 						break;
 
 					case 'm':
@@ -253,7 +253,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 						break;
 
 					default:
-						log_error("System task `%s' called with invalid/unsupported format specifier at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "System task `%s' called with invalid/unsupported format specifier.\n", str.c_str());
 						break;
 				}
 
@@ -374,7 +374,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					continue;
 				wires_are_incompatible:
 					if (stage > 1)
-						log_error("Incompatible re-declaration of wire %s at %s:%d.\n", node->str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", node->str.c_str());
 					continue;
 				}
 				this_wire_scope[node->str] = node;
@@ -402,7 +402,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_ALWAYS || type == AST_INITIAL)
 	{
 		if (current_always != nullptr)
-			log_error("Invalid nesting of always blocks and/or initializations at %s:%d.\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Invalid nesting of always blocks and/or initializations.\n");
 
 		current_always = this;
 		current_always_clocked = false;
@@ -451,7 +451,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			while (!children[1]->basic_prep && children[1]->simplify(false, false, false, stage, -1, false, true) == true)
 				did_something = true;
 			if (!children[1]->range_valid)
-				log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n");
 			width_hint = max(width_hint, children[1]->range_left - children[1]->range_right + 1);
 		}
 		break;
@@ -695,7 +695,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_DEFPARAM && !children.empty())
 	{
 		if (children[0]->type != AST_IDENTIFIER)
-			log_error("Module name in defparam at %s:%d contains non-constant expressions!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Module name in defparam contains non-constant expressions!\n");
 
 		string modname, paramname = children[0]->str;
 
@@ -712,7 +712,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		}
 
 		if (pos == std::string::npos)
-			log_error("Can't find object for defparam `%s` at %s:%d!\n", RTLIL::unescape_id(paramname).c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Can't find object for defparam `%s`!\n", RTLIL::unescape_id(paramname).c_str());
 
 		paramname = "\\" + paramname.substr(pos+1);
 
@@ -732,7 +732,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_PREFIX) {
 		if (children[0]->type != AST_CONSTANT) {
 			// dumpAst(NULL, ">   ");
-			log_error("Index in generate block prefix syntax at %s:%d is not constant!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Index in generate block prefix syntax is not constant!\n");
 		}
 		if (children[1]->type == AST_PREFIX)
 			children[1]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param);
@@ -748,9 +748,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	// evaluate TO_BITS nodes
 	if (type == AST_TO_BITS) {
 		if (children[0]->type != AST_CONSTANT)
-			log_error("Left operand of to_bits expression is not constant at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Left operand of to_bits expression is not constant!\n");
 		if (children[1]->type != AST_CONSTANT)
-			log_error("Right operand of to_bits expression is not constant at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Right operand of to_bits expression is not constant!\n");
 		RTLIL::Const new_value = children[1]->bitsAsConst(children[0]->bitsAsConst().as_int(), children[1]->is_signed);
 		newNode = mkconst_bits(new_value.bits, children[1]->is_signed);
 		goto apply_newNode;
@@ -814,7 +814,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		multirange_dimensions.clear();
 		for (auto range : children[1]->children) {
 			if (!range->range_valid)
-				log_error("Non-constant range on memory decl at %s:%d.\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Non-constant range on memory decl.\n");
 			multirange_dimensions.push_back(min(range->range_left, range->range_right));
 			multirange_dimensions.push_back(max(range->range_left, range->range_right) - min(range->range_left, range->range_right) + 1);
 			total_size *= multirange_dimensions.back();
@@ -832,7 +832,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++)
 		{
 			if (GetSize(children[0]->children) < i)
-				log_error("Insufficient number of array indices for %s at %s:%d.\n", log_id(str), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Insufficient number of array indices for %s.\n", log_id(str));
 
 			AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone();
 
@@ -861,7 +861,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_PARAMETER || type == AST_LOCALPARAM) {
 		if (children.size() > 1 && children[1]->type == AST_RANGE) {
 			if (!children[1]->range_valid)
-				log_error("Non-constant width range on parameter decl at %s:%d.\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Non-constant width range on parameter decl.\n");
 			int width = std::abs(children[1]->range_left - children[1]->range_right) + 1;
 			if (children[0]->type == AST_REALVALUE) {
 				RTLIL::Const constvalue = children[0]->realAsConst(width);
@@ -924,7 +924,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_IDENTIFIER && children.size() == 2 && children[0]->type == AST_RANGE && children[1]->type == AST_RANGE && !in_lvalue)
 	{
 		if (id2ast == NULL || id2ast->type != AST_MEMORY || children[0]->children.size() != 1)
-			log_error("Invalid bit-select on memory access at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Invalid bit-select on memory access!\n");
 
 		int mem_width, mem_size, addr_bits;
 		id2ast->meminfo(mem_width, mem_size, addr_bits);
@@ -973,10 +973,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	}
 
 	if (type == AST_WHILE)
-		log_error("While loops are only allowed in constant functions at %s:%d!\n", filename.c_str(), linenum);
+		log_file_error(filename, linenum, "While loops are only allowed in constant functions!\n");
 
 	if (type == AST_REPEAT)
-		log_error("Repeat loops are only allowed in constant functions at %s:%d!\n", filename.c_str(), linenum);
+		log_file_error(filename, linenum, "Repeat loops are only allowed in constant functions!\n");
 
 	// unroll for loops and generate-for blocks
 	if ((type == AST_GENFOR || type == AST_FOR) && children.size() != 0)
@@ -991,31 +991,31 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			body_ast = body_ast->children.at(0);
 
 		if (init_ast->type != AST_ASSIGN_EQ)
-			log_error("Unsupported 1st expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Unsupported 1st expression of generate for-loop!\n");
 		if (next_ast->type != AST_ASSIGN_EQ)
-			log_error("Unsupported 3rd expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Unsupported 3rd expression of generate for-loop!\n");
 
 		if (type == AST_GENFOR) {
 			if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_GENVAR)
-				log_error("Left hand side of 1st expression of generate for-loop at %s:%d is not a gen var!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a gen var!\n");
 			if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_GENVAR)
-				log_error("Left hand side of 3rd expression of generate for-loop at %s:%d is not a gen var!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a gen var!\n");
 		} else {
 			if (init_ast->children[0]->id2ast == NULL || init_ast->children[0]->id2ast->type != AST_WIRE)
-				log_error("Left hand side of 1st expression of generate for-loop at %s:%d is not a register!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Left hand side of 1st expression of generate for-loop is not a register!\n");
 			if (next_ast->children[0]->id2ast == NULL || next_ast->children[0]->id2ast->type != AST_WIRE)
-				log_error("Left hand side of 3rd expression of generate for-loop at %s:%d is not a register!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Left hand side of 3rd expression of generate for-loop is not a register!\n");
 		}
 
 		if (init_ast->children[0]->id2ast != next_ast->children[0]->id2ast)
-			log_error("Incompatible left-hand sides in 1st and 3rd expression of generate for-loop at %s:%d!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Incompatible left-hand sides in 1st and 3rd expression of generate for-loop!\n");
 
 		// eval 1st expression
 		AstNode *varbuf = init_ast->children[1]->clone();
 		while (varbuf->simplify(true, false, false, stage, 32, true, false)) { }
 
 		if (varbuf->type != AST_CONSTANT)
-			log_error("Right hand side of 1st expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Right hand side of 1st expression of generate for-loop is not constant!\n");
 
 		varbuf = new AstNode(AST_LOCALPARAM, varbuf);
 		varbuf->str = init_ast->children[0]->str;
@@ -1037,7 +1037,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 
 			if (buf->type != AST_CONSTANT)
-				log_error("2nd expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "2nd expression of generate for-loop is not constant!\n");
 
 			if (buf->integer == 0) {
 				delete buf;
@@ -1078,7 +1078,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			while (buf->simplify(true, false, false, stage, 32, true, false)) { }
 
 			if (buf->type != AST_CONSTANT)
-				log_error("Right hand side of 3rd expression of generate for-loop at %s:%d is not constant!\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Right hand side of 3rd expression of generate for-loop is not constant!\n");
 
 			delete varbuf->children[0];
 			varbuf->children[0] = buf;
@@ -1144,7 +1144,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		if (buf->type != AST_CONSTANT) {
 			// for (auto f : log_files)
 			// 	dumpAst(f, "verilog-ast> ");
-			log_error("Condition for generate if at %s:%d is not constant!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Condition for generate if is not constant!\n");
 		}
 		if (buf->asBool() != 0) {
 			delete buf;
@@ -1185,7 +1185,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		if (buf->type != AST_CONSTANT) {
 			// for (auto f : log_files)
 			// 	dumpAst(f, "verilog-ast> ");
-			log_error("Condition for generate case at %s:%d is not constant!\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Condition for generate case is not constant!\n");
 		}
 
 		bool ref_signed = buf->is_signed;
@@ -1219,7 +1219,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				if (buf->type != AST_CONSTANT) {
 					// for (auto f : log_files)
 					// 	dumpAst(f, "verilog-ast> ");
-					log_error("Expression in generate case at %s:%d is not constant!\n", filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Expression in generate case is not constant!\n");
 				}
 
 				bool is_selected = RTLIL::const_eq(ref_value, buf->bitsAsConst(), ref_signed && buf->is_signed, ref_signed && buf->is_signed, 1).as_bool();
@@ -1260,7 +1260,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_CELLARRAY)
 	{
 		if (!children.at(0)->range_valid)
-			log_error("Non-constant array range on cell array at %s:%d.\n", filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Non-constant array range on cell array.\n");
 
 		newNode = new AstNode(AST_GENBLOCK);
 		int num = max(children.at(0)->range_left, children.at(0)->range_right) - min(children.at(0)->range_left, children.at(0)->range_right) + 1;
@@ -1271,7 +1271,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			newNode->children.push_back(new_cell);
 			new_cell->str += stringf("[%d]", idx);
 			if (new_cell->type == AST_PRIMITIVE) {
-				log_error("Cell arrays of primitives are currently not supported at %s:%d.\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Cell arrays of primitives are currently not supported.\n");
 			} else {
 				log_assert(new_cell->children.at(0)->type == AST_CELLTYPE);
 				new_cell->children.at(0)->str = stringf("$array:%d:%d:%s", i, num, new_cell->children.at(0)->str.c_str());
@@ -1645,7 +1645,7 @@ skip_dynamic_range_lvalue_expansion:;
 				while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-					log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
 				int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
 
 				assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
@@ -1749,7 +1749,7 @@ skip_dynamic_range_lvalue_expansion:;
 					AstNode *buf = children[1]->clone();
 					while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (buf->type != AST_CONSTANT)
-						log_error("Failed to evaluate system function `%s' with non-constant value at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
 
 					num_steps = buf->asInt(true);
 					delete buf;
@@ -1846,7 +1846,7 @@ skip_dynamic_range_lvalue_expansion:;
 				AstNode *buf = children[0]->clone();
 				while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 				if (buf->type != AST_CONSTANT)
-					log_error("Failed to evaluate system function `%s' with non-constant value at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
 
 				RTLIL::Const arg_value = buf->bitsAsConst();
 				if (arg_value.as_bool())
@@ -1893,7 +1893,7 @@ skip_dynamic_range_lvalue_expansion:;
 					if (id_ast == NULL && current_scope.count(buf->str))
 						id_ast = current_scope.at(buf->str);
 					if (!id_ast)
-						log_error("Failed to resolve identifier %s for width detection at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to resolve identifier %s for width detection!\n", buf->str.c_str());
 					if (id_ast->type == AST_MEMORY) {
 						// We got here only if the argument is a memory
 						// Otherwise $size() and $bits() return the expression width
@@ -1901,15 +1901,15 @@ skip_dynamic_range_lvalue_expansion:;
 						if (str == "\\$bits") {
 							if (mem_range->type == AST_RANGE) {
 								if (!mem_range->range_valid)
-									log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
+									log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str());
 								mem_depth = mem_range->range_left - mem_range->range_right + 1;
 							} else
-								log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
+								log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str());
 						} else {
 							// $size()
 							if (mem_range->type == AST_RANGE) {
 								if (!mem_range->range_valid)
-									log_error("Failed to detect width of memory access `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
+									log_file_error(filename, linenum, "Failed to detect width of memory access `%s'!\n", buf->str.c_str());
 								int dims;
 								if (id_ast->multirange_dimensions.empty())
 									dims = 1;
@@ -1920,9 +1920,9 @@ skip_dynamic_range_lvalue_expansion:;
 								else if (dim <= dims) {
 									width_hint = id_ast->multirange_dimensions[2*dim-1];
 								} else if ((dim > dims+1) || (dim < 0))
-									log_error("Dimension %d out of range in `%s', as it only has dimensions 1..%d at %s:%d!\n", dim, buf->str.c_str(), dims+1, filename.c_str(), linenum);
+									log_file_error(filename, linenum, "Dimension %d out of range in `%s', as it only has dimensions 1..%d!\n", dim, buf->str.c_str(), dims+1);
 							} else
-								log_error("Unknown memory depth AST type in `%s' at %s:%d!\n", buf->str.c_str(), filename.c_str(), linenum);
+								log_file_error(filename, linenum, "Unknown memory depth AST type in `%s'!\n", buf->str.c_str());
 						}
 					}
 				}
@@ -2018,14 +2018,14 @@ skip_dynamic_range_lvalue_expansion:;
 				for (int i = 2; i < GetSize(dpi_decl->children); i++)
 				{
 					if (i-2 >= GetSize(children))
-						log_error("Insufficient number of arguments in DPI function call at %s:%d.\n", filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Insufficient number of arguments in DPI function call.\n");
 
 					argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
 					args.push_back(children.at(i-2)->clone());
 					while (args.back()->simplify(true, false, false, stage, -1, false, true)) { }
 
 					if (args.back()->type != AST_CONSTANT && args.back()->type != AST_REALVALUE)
-						log_error("Failed to evaluate DPI function with non-constant argument at %s:%d.\n", filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to evaluate DPI function with non-constant argument.\n");
 				}
 
 				newNode = dpi_call(rtype, fname, argtypes, args);
@@ -2037,7 +2037,7 @@ skip_dynamic_range_lvalue_expansion:;
 			}
 
 			if (current_scope.count(str) == 0 || current_scope[str]->type != AST_FUNCTION)
-				log_error("Can't resolve function name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Can't resolve function name `%s'.\n", str.c_str());
 		}
 
 		if (type == AST_TCALL)
@@ -2045,9 +2045,9 @@ skip_dynamic_range_lvalue_expansion:;
 			if (str == "$finish" || str == "$stop")
 			{
 				if (!current_always || current_always->type != AST_INITIAL)
-					log_error("System task `%s' outside initial block is unsupported at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System task `%s' outside initial block is unsupported.\n", str.c_str());
 
-				log_error("System task `%s' executed at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "System task `%s' executed.\n", str.c_str());
 			}
 
 			if (str == "\\$readmemh" || str == "\\$readmemb")
@@ -2059,12 +2059,12 @@ skip_dynamic_range_lvalue_expansion:;
 				AstNode *node_filename = children[0]->clone();
 				while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 				if (node_filename->type != AST_CONSTANT)
-					log_error("Failed to evaluate system function `%s' with non-constant 1st argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 1st argument.\n", str.c_str());
 
 				AstNode *node_memory = children[1]->clone();
 				while (node_memory->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 				if (node_memory->type != AST_IDENTIFIER || node_memory->id2ast == nullptr || node_memory->id2ast->type != AST_MEMORY)
-					log_error("Failed to evaluate system function `%s' with non-memory 2nd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-memory 2nd argument.\n", str.c_str());
 
 				int start_addr = -1, finish_addr = -1;
 
@@ -2072,7 +2072,7 @@ skip_dynamic_range_lvalue_expansion:;
 					AstNode *node_addr = children[2]->clone();
 					while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (node_addr->type != AST_CONSTANT)
-						log_error("Failed to evaluate system function `%s' with non-constant 3rd argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 3rd argument.\n", str.c_str());
 					start_addr = int(node_addr->asInt(false));
 				}
 
@@ -2080,7 +2080,7 @@ skip_dynamic_range_lvalue_expansion:;
 					AstNode *node_addr = children[3]->clone();
 					while (node_addr->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (node_addr->type != AST_CONSTANT)
-						log_error("Failed to evaluate system function `%s' with non-constant 4th argument at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant 4th argument.\n", str.c_str());
 					finish_addr = int(node_addr->asInt(false));
 				}
 
@@ -2106,7 +2106,7 @@ skip_dynamic_range_lvalue_expansion:;
 			}
 
 			if (current_scope.count(str) == 0 || current_scope[str]->type != AST_TASK)
-				log_error("Can't resolve task name `%s' at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Can't resolve task name `%s'.\n", str.c_str());
 		}
 
 		AstNode *decl = current_scope[str];
@@ -2134,9 +2134,9 @@ skip_dynamic_range_lvalue_expansion:;
 			}
 
 			if (in_param)
-				log_error("Non-constant function call in constant expression at %s:%d.\n", filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Non-constant function call in constant expression.\n");
 			if (require_const_eval)
-				log_error("Function %s can only be called with constant arguments at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Function %s can only be called with constant arguments.\n", str.c_str());
 		}
 
 		size_t arg_count = 0;
@@ -2253,7 +2253,7 @@ skip_dynamic_range_lvalue_expansion:;
 									goto tcall_incompatible_wires;
 						} else {
 					tcall_incompatible_wires:
-							log_error("Incompatible re-declaration of wire %s at %s:%d.\n", child->str.c_str(), filename.c_str(), linenum);
+							log_file_error(filename, linenum, "Incompatible re-declaration of wire %s.\n", child->str.c_str());
 						}
 					}
 				}
@@ -2641,7 +2641,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
 	yosys_input_files.insert(mem_filename);
 
 	if (f.fail())
-		log_error("Can not open file `%s` for %s at %s:%d.\n", mem_filename.c_str(), str.c_str(), filename.c_str(), linenum);
+		log_file_error(filename, linenum, "Can not open file `%s` for %s.\n", mem_filename.c_str(), str.c_str());
 
 	log_assert(GetSize(memory->children) == 2 && memory->children[1]->type == AST_RANGE && memory->children[1]->range_valid);
 	int range_left =  memory->children[1]->range_left, range_right =  memory->children[1]->range_right;
@@ -2687,7 +2687,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
 				char *endptr;
 				cursor = strtol(nptr, &endptr, 16);
 				if (!*nptr || *endptr)
-					log_error("Can not parse address `%s` for %s at %s:%d.\n", nptr, str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Can not parse address `%s` for %s.\n", nptr, str.c_str());
 				continue;
 			}
 
@@ -2943,7 +2943,7 @@ bool AstNode::mem2reg_check(pool<AstNode*> &mem2reg_set)
 		return false;
 
 	if (children.empty() || children[0]->type != AST_RANGE || GetSize(children[0]->children) != 1)
-		log_error("Invalid array access at %s:%d.\n", filename.c_str(), linenum);
+		log_file_error(filename, linenum, "Invalid array access.\n");
 
 	return true;
 }
@@ -3446,4 +3446,3 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 }
 
 YOSYS_NAMESPACE_END
-
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 505c94619..be925fea2 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -42,7 +42,7 @@ static std::list<std::vector<std::string>> verilog_defaults_stack;
 static void error_on_dpi_function(AST::AstNode *node)
 {
 	if (node->type == AST::AST_DPI_FUNCTION)
-		log_error("Found DPI function %s at %s:%d.\n", node->str.c_str(), node->filename.c_str(), node->linenum);
+		log_file_error(node->filename, node->linenum, "Found DPI function %s.\n", node->str.c_str());
 	for (auto child : node->children)
 		error_on_dpi_function(child);
 }
@@ -519,13 +519,11 @@ void frontend_verilog_yyerror(char const *fmt, ...)
 	va_list ap;
 	char buffer[1024];
 	char *p = buffer;
-	p += snprintf(p, buffer + sizeof(buffer) - p, "Parser error in line %s:%d: ",
-			YOSYS_NAMESPACE_PREFIX AST::current_filename.c_str(), frontend_verilog_yyget_lineno());
 	va_start(ap, fmt);
 	p += vsnprintf(p, buffer + sizeof(buffer) - p, fmt, ap);
 	va_end(ap);
 	p += snprintf(p, buffer + sizeof(buffer) - p, "\n");
-	YOSYS_NAMESPACE_PREFIX log_error("%s", buffer);
+	YOSYS_NAMESPACE_PREFIX log_file_error(YOSYS_NAMESPACE_PREFIX AST::current_filename, frontend_verilog_yyget_lineno(),
+					      "%s", buffer);
 	exit(1);
 }
-

From 68b5d0c3b11588946982939c00fd6febe198e13f Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 09:37:44 -0700
Subject: [PATCH 039/528] Convert more log_error() to log_file_error() where
 possible.

Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
---
 frontends/ast/ast.cc           |  13 ++-
 frontends/ast/genrtlil.cc      | 140 ++++++++++++++++-----------------
 frontends/ast/simplify.cc      | 107 +++++++++++++------------
 frontends/verilog/const2ast.cc |   8 +-
 4 files changed, 131 insertions(+), 137 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 999202b47..54ce6a05d 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -171,8 +171,8 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
 
 	AstNode *attr = attributes.at(id);
 	if (attr->type != AST_CONSTANT)
-		log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-				id.c_str(), attr->filename.c_str(), attr->linenum);
+		log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n",
+			       id.c_str());
 
 	return attr->integer != 0;
 }
@@ -955,8 +955,8 @@ static AstModule* process_module(AstNode *ast, bool defer)
 
 		for (auto &attr : ast->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-						attr.first.c_str(), ast->filename.c_str(), ast->linenum);
+				log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
+					       attr.first.c_str());
 			current_module->attributes[attr.first] = attr.second->asAttrConst();
 		}
 		for (size_t i = 0; i < ast->children.size(); i++) {
@@ -1044,8 +1044,8 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			if (design->has((*it)->str)) {
 				RTLIL::Module *existing_mod = design->module((*it)->str);
 				if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
-					log_error("Re-definition of module `%s' at %s:%d!\n",
-							(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
+					log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n",
+						       (*it)->str.c_str());
 				} else if (nooverwrite) {
 					log("Ignoring re-definition of module `%s' at %s:%d.\n",
 							(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
@@ -1197,4 +1197,3 @@ void AST::use_internal_line_num()
 }
 
 YOSYS_NAMESPACE_END
-
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e611ddcb1..0f7e910f3 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -55,8 +55,8 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 	if (gen_attributes)
 		for (auto &attr : that->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-						attr.first.c_str(), that->filename.c_str(), that->linenum);
+				log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
+					       attr.first.c_str());
 			cell->attributes[attr.first] = attr.second->asAttrConst();
 		}
 
@@ -89,8 +89,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 	if (that != NULL)
 		for (auto &attr : that->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-						attr.first.c_str(), that->filename.c_str(), that->linenum);
+				log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
+					       attr.first.c_str());
 			cell->attributes[attr.first] = attr.second->asAttrConst();
 		}
 
@@ -117,8 +117,8 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
-			log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-					attr.first.c_str(), that->filename.c_str(), that->linenum);
+			log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
+				       attr.first.c_str());
 		cell->attributes[attr.first] = attr.second->asAttrConst();
 	}
 
@@ -152,8 +152,8 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
-			log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-					attr.first.c_str(), that->filename.c_str(), that->linenum);
+			log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
+				       attr.first.c_str());
 		cell->attributes[attr.first] = attr.second->asAttrConst();
 	}
 
@@ -207,8 +207,8 @@ struct AST_INTERNAL::ProcessGenerator
 		proc->name = stringf("$proc$%s:%d$%d", always->filename.c_str(), always->linenum, autoidx++);
 		for (auto &attr : always->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-						attr.first.c_str(), always->filename.c_str(), always->linenum);
+				log_file_error(always->filename, always->linenum, "Attribute `%s' with non-constant value!\n",
+						attr.first.c_str());
 			proc->attributes[attr.first] = attr.second->asAttrConst();
 		}
 		current_module->processes[proc->name] = proc;
@@ -480,8 +480,8 @@ struct AST_INTERNAL::ProcessGenerator
 
 				for (auto &attr : ast->attributes) {
 					if (attr.second->type != AST_CONSTANT)
-						log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-								attr.first.c_str(), ast->filename.c_str(), ast->linenum);
+						log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
+							       attr.first.c_str());
 					sw->attributes[attr.first] = attr.second->asAttrConst();
 				}
 
@@ -648,8 +648,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-					log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
-							str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
+						       str.c_str());
 				this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
 				delete left_at_zero_ast;
 				delete right_at_zero_ast;
@@ -777,8 +777,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 			if (GetSize(children) == 1) {
 				while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
 				if (children[0]->type != AST_CONSTANT)
-					log_error("System function %s called with non-const argument at %s:%d!\n",
-							RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
+						       RTLIL::unescape_id(str).c_str());
 				width_hint = max(width_hint, int(children[0]->asInt(true)));
 			}
 			break;
@@ -799,8 +799,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	default:
 		for (auto f : log_files)
 			current_ast->dumpAst(f, "verilog-ast> ");
-		log_error("Don't know how to detect sign and width for %s node at %s:%d!\n",
-				type2str(type).c_str(), filename.c_str(), linenum);
+		log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n",
+			       type2str(type).c_str());
 	}
 
 	if (*found_real)
@@ -863,11 +863,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// create an RTLIL::Wire for an AST_WIRE node
 	case AST_WIRE: {
 			if (current_module->wires_.count(str) != 0)
-				log_error("Re-definition of signal `%s' at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Re-definition of signal `%s'!\n",
+					       str.c_str());
 			if (!range_valid)
-				log_error("Signal `%s' with non-constant width at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n",
+					       str.c_str());
 
 			log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
 
@@ -881,8 +881,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-							attr.first.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
+						       attr.first.c_str());
 				wire->attributes[attr.first] = attr.second->asAttrConst();
 			}
 		}
@@ -891,16 +891,16 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// create an RTLIL::Memory for an AST_MEMORY node
 	case AST_MEMORY: {
 			if (current_module->memories.count(str) != 0)
-				log_error("Re-definition of memory `%s' at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Re-definition of memory `%s'!\n",
+					       str.c_str());
 
 			log_assert(children.size() >= 2);
 			log_assert(children[0]->type == AST_RANGE);
 			log_assert(children[1]->type == AST_RANGE);
 
 			if (!children[0]->range_valid || !children[1]->range_valid)
-				log_error("Memory `%s' with non-constant width or size at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n",
+					       str.c_str());
 
 			RTLIL::Memory *memory = new RTLIL::Memory;
 			memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -917,8 +917,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-							attr.first.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
+						       attr.first.c_str());
 				memory->attributes[attr.first] = attr.second->asAttrConst();
 			}
 		}
@@ -937,8 +937,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_REALVALUE:
 		{
 			RTLIL::SigSpec sig = realAsConst(width_hint);
-			log_warning("converting real value %e to binary %s at %s:%d.\n",
-					realvalue, log_signal(sig), filename.c_str(), linenum);
+			log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
+					 realvalue, log_signal(sig));
 			return sig;
 		}
 
@@ -964,19 +964,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			}
 			else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
 				if (id2ast->children[0]->type != AST_CONSTANT)
-					log_error("Parameter %s does not evaluate to constant value at %s:%d!\n",
-							str.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n",
+						       str.c_str());
 				chunk = RTLIL::Const(id2ast->children[0]->bits);
 				goto use_const_chunk;
 			}
 			else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
 					id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0)
-				log_error("Identifier `%s' doesn't map to any signal at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n",
+						str.c_str());
 
 			if (id2ast->type == AST_MEMORY)
-				log_error("Identifier `%s' does map to an unexpanded memory at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
+					       str.c_str());
 
 			wire = current_module->wires_[str];
 			chunk.wire = wire;
@@ -994,8 +994,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 					while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 					if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-						log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
-								str.c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
+							       str.c_str());
 					int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
 					AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
 							children[0]->children[1]->clone() : children[0]->children[0]->clone());
@@ -1023,11 +1023,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						chunk.offset = (id2ast->range_left - id2ast->range_right + 1) - (chunk.offset + chunk.width);
 					if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
 						if (chunk.width == 1)
-							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting result bit to undef.\n",
-									str.c_str(), filename.c_str(), linenum);
+							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
+									 str.c_str());
 						else
-							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting all %d result bits to undef.\n",
-									str.c_str(), filename.c_str(), linenum, chunk.width);
+							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n",
+									str.c_str(), chunk.width);
 						chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
 					} else {
 						if (chunk.width + chunk.offset > source_width) {
@@ -1040,11 +1040,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 							chunk.offset += add_undef_bits_lsb;
 						}
 						if (add_undef_bits_lsb)
-							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d LSB bits to undef.\n",
-									str.c_str(), filename.c_str(), linenum, add_undef_bits_lsb);
+							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
+									 str.c_str(), add_undef_bits_lsb);
 						if (add_undef_bits_msb)
-							log_warning("Range select out of bounds on signal `%s' at %s:%d: Setting %d MSB bits to undef.\n",
-									str.c_str(), filename.c_str(), linenum, add_undef_bits_msb);
+							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
+									 str.c_str(), add_undef_bits_msb);
 					}
 				}
 			}
@@ -1379,8 +1379,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-							attr.first.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
+						       attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 
@@ -1401,10 +1401,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						new_left.append(left[i]);
 						new_right.append(right[i]);
 					}
-				log_warning("Ignoring assignment to constant bits at %s:%d:\n"
-						"    old assignment: %s = %s\n    new assignment: %s = %s.\n",
-						filename.c_str(), linenum, log_signal(left), log_signal(right),
-						log_signal(new_left), log_signal(new_right));
+				log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
+						 "    old assignment: %s = %s\n    new assignment: %s = %s.\n",
+						 log_signal(left), log_signal(right),
+						 log_signal(new_left), log_signal(new_right));
 				left = new_left;
 				right = new_right;
 			}
@@ -1418,8 +1418,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			int port_counter = 0, para_counter = 0;
 
 			if (current_module->count_id(str) != 0)
-				log_error("Re-definition of cell `%s' at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Re-definition of cell `%s'!\n", str.c_str());
 
 			RTLIL::Cell *cell = current_module->addCell(str, "");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -1435,16 +1434,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if (child->type == AST_PARASET) {
 					IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
 					if (child->children[0]->type == AST_REALVALUE) {
-						log_warning("Replacing floating point parameter %s.%s = %f with string at %s:%d.\n",
-							log_id(cell), log_id(paraname), child->children[0]->realvalue,
-							filename.c_str(), linenum);
+						log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
+								 log_id(cell), log_id(paraname), child->children[0]->realvalue);
 						auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
 						strnode->cloneInto(child->children[0]);
 						delete strnode;
 					}
 					if (child->children[0]->type != AST_CONSTANT)
-						log_error("Parameter %s.%s with non-constant value at %s:%d!\n",
-								log_id(cell), log_id(paraname), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
+							       log_id(cell), log_id(paraname));
 					cell->parameters[paraname] = child->children[0]->asParaConst();
 					continue;
 				}
@@ -1465,8 +1463,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			}
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_error("Attribute `%s' with non-constant value at %s:%d!\n",
-							attr.first.c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
+						       attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 		}
@@ -1493,19 +1491,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				int width = width_hint;
 
 				if (GetSize(children) > 1)
-					log_error("System function %s got %d arguments, expected 1 or 0 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), GetSize(children), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
+						       RTLIL::unescape_id(str).c_str(), GetSize(children));
 
 				if (GetSize(children) == 1) {
 					if (children[0]->type != AST_CONSTANT)
-						log_error("System function %s called with non-const argument at %s:%d!\n",
-								RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
+							       RTLIL::unescape_id(str).c_str());
 					width = children[0]->asInt(true);
 				}
 
 				if (width <= 0)
-					log_error("Failed to detect width of %s at %s:%d!\n",
-							RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "Failed to detect width of %s!\n",
+						       RTLIL::unescape_id(str).c_str());
 
 				Cell *cell = current_module->addCell(myid, str.substr(1));
 				cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -1532,8 +1530,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		for (auto f : log_files)
 			current_ast->dumpAst(f, "verilog-ast> ");
 		type_name = type2str(type);
-		log_error("Don't know how to generate RTLIL code for %s node at %s:%d!\n",
-				type_name.c_str(), filename.c_str(), linenum);
+		log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n",
+			       type_name.c_str());
 	}
 
 	return RTLIL::SigSpec();
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 81bd3cd7e..be53e8527 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -195,8 +195,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	{
 		int nargs = GetSize(children);
 		if (nargs < 1)
-			log_error("System task `%s' got %d arguments, expected >= 1 at %s:%d.\n",
-					str.c_str(), int(children.size()), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "System task `%s' got %d arguments, expected >= 1.\n",
+				       str.c_str(), int(children.size()));
 
 		// First argument is the format string
 		AstNode *node_string = children[0];
@@ -239,8 +239,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					case 'x':
 					case 'X':
 						if (next_arg >= GetSize(children))
-							log_error("Missing argument for %%%c format specifier in system task `%s' at %s:%d.\n",
-									cformat, str.c_str(), filename.c_str(), linenum);
+							log_file_error(filename, linenum, "Missing argument for %%%c format specifier in system task `%s'.\n",
+								       cformat, str.c_str());
 
 						node_arg = children[next_arg++];
 						while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -717,8 +717,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		paramname = "\\" + paramname.substr(pos+1);
 
 		if (current_scope.at(modname)->type != AST_CELL)
-			log_error("Defparam argument `%s . %s` does not match a cell at %s:%d!\n",
-					RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Defparam argument `%s . %s` does not match a cell!\n",
+				       RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str());
 
 		AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL);
 		paraset->str = paramname;
@@ -865,8 +865,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			int width = std::abs(children[1]->range_left - children[1]->range_right) + 1;
 			if (children[0]->type == AST_REALVALUE) {
 				RTLIL::Const constvalue = children[0]->realAsConst(width);
-				log_warning("converting real value %e to binary %s at %s:%d.\n",
-						children[0]->realvalue, log_signal(constvalue), filename.c_str(), linenum);
+				log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
+						 children[0]->realvalue, log_signal(constvalue));
 				delete children[0];
 				children[0] = mkconst_bits(constvalue.bits, sign_hint);
 				did_something = true;
@@ -1095,8 +1095,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	{
 		for (size_t i = 0; i < children.size(); i++)
 			if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM)
-				log_error("Local declaration in unnamed block at %s:%d is an unsupported SystemVerilog feature!\n",
-						children[i]->filename.c_str(), children[i]->linenum);
+				log_file_error(children[i]->filename, children[i]->linenum, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n");
 	}
 
 	// transform block with name
@@ -1285,8 +1284,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_PRIMITIVE)
 	{
 		if (children.size() < 2)
-			log_error("Insufficient number of arguments for primitive `%s' at %s:%d!\n",
-					str.c_str(), filename.c_str(), linenum);
+			log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n",
+				       str.c_str());
 
 		std::vector<AstNode*> children_list;
 		for (auto child : children) {
@@ -1301,8 +1300,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
 		{
 			if (children_list.size() != 3)
-				log_error("Invalid number of arguments for primitive `%s' at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n",
+					       str.c_str());
 
 			std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
 
@@ -1387,8 +1386,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { }
 			while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { }
 			if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-				log_error("Unsupported expression on dynamic range select on signal `%s' at %s:%d!\n",
-						str.c_str(), filename.c_str(), linenum);
+				log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
+					       str.c_str());
 			result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
 		}
 		did_something = true;
@@ -1737,12 +1736,12 @@ skip_dynamic_range_lvalue_expansion:;
 				int num_steps = 1;
 
 				if (GetSize(children) != 1 && GetSize(children) != 2)
-					log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n",
+						       RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				if (!current_always_clocked)
-					log_error("System function %s is only allowed in clocked blocks at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n",
+						       RTLIL::unescape_id(str).c_str());
 
 				if (GetSize(children) == 2)
 				{
@@ -1805,12 +1804,12 @@ skip_dynamic_range_lvalue_expansion:;
 			if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell")
 			{
 				if (GetSize(children) != 1)
-					log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
+						       RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				if (!current_always_clocked)
-					log_error("System function %s is only allowed in clocked blocks at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n",
+						       RTLIL::unescape_id(str).c_str());
 
 				AstNode *present = children.at(0)->clone();
 				AstNode *past = clone();
@@ -1840,8 +1839,8 @@ skip_dynamic_range_lvalue_expansion:;
 			if (str == "\\$clog2")
 			{
 				if (children.size() != 1)
-					log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
+						       RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				AstNode *buf = children[0]->clone();
 				while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -1865,12 +1864,12 @@ skip_dynamic_range_lvalue_expansion:;
 			if (str == "\\$size" || str == "\\$bits")
 			{
 				if (str == "\\$bits" && children.size() != 1)
-					log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
+						       RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				if (str == "\\$size" && children.size() != 1 && children.size() != 2)
-					log_error("System function %s got %d arguments, expected 1 or 2 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n",
+						       RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				int dim = 1;
 				if (str == "\\$size" && children.size() == 2) {
@@ -1943,19 +1942,19 @@ skip_dynamic_range_lvalue_expansion:;
 
 				if (func_with_two_arguments) {
 					if (children.size() != 2)
-						log_error("System function %s got %d arguments, expected 2 at %s:%d.\n",
-								RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "System function %s got %d arguments, expected 2.\n",
+							       RTLIL::unescape_id(str).c_str(), int(children.size()));
 				} else {
 					if (children.size() != 1)
-						log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",
-								RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
+							       RTLIL::unescape_id(str).c_str(), int(children.size()));
 				}
 
 				if (children.size() >= 1) {
 					while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (!children[0]->isConst())
-						log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n",
-								RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n",
+							       RTLIL::unescape_id(str).c_str());
 					int child_width_hint = width_hint;
 					bool child_sign_hint = sign_hint;
 					children[0]->detectSignWidth(child_width_hint, child_sign_hint);
@@ -1965,8 +1964,8 @@ skip_dynamic_range_lvalue_expansion:;
 				if (children.size() >= 2) {
 					while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (!children[1]->isConst())
-						log_error("Failed to evaluate system function `%s' with non-constant argument at %s:%d.\n",
-								RTLIL::unescape_id(str).c_str(), filename.c_str(), linenum);
+						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n",
+							       RTLIL::unescape_id(str).c_str());
 					int child_width_hint = width_hint;
 					bool child_sign_hint = sign_hint;
 					children[1]->detectSignWidth(child_width_hint, child_sign_hint);
@@ -2053,8 +2052,8 @@ skip_dynamic_range_lvalue_expansion:;
 			if (str == "\\$readmemh" || str == "\\$readmemb")
 			{
 				if (GetSize(children) < 2 || GetSize(children) > 4)
-					log_error("System function %s got %d arguments, expected 2-4 at %s:%d.\n",
-							RTLIL::unescape_id(str).c_str(), int(children.size()), filename.c_str(), linenum);
+					log_file_error(filename, linenum, "System function %s got %d arguments, expected 2-4.\n",
+						       RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				AstNode *node_filename = children[0]->clone();
 				while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -3291,16 +3290,16 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 				continue;
 
 			if (stmt->children.at(1)->type != AST_CONSTANT)
-				log_error("Non-constant expression in constant function at %s:%d (called from %s:%d). X\n",
-						stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d). X\n",
+					       fcall->filename.c_str(), fcall->linenum);
 
 			if (stmt->children.at(0)->type != AST_IDENTIFIER)
-				log_error("Unsupported composite left hand side in constant function at %s:%d (called from %s:%d).\n",
-						stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function (called from %s:%d).\n",
+					       fcall->filename.c_str(), fcall->linenum);
 
 			if (!variables.count(stmt->children.at(0)->str))
-				log_error("Assignment to non-local variable in constant function at %s:%d (called from %s:%d).\n",
-						stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function (called from %s:%d).\n",
+					       fcall->filename.c_str(), fcall->linenum);
 
 			if (stmt->children.at(0)->children.empty()) {
 				variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());
@@ -3339,8 +3338,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			while (cond->simplify(true, false, false, 1, -1, false, true)) { }
 
 			if (cond->type != AST_CONSTANT)
-				log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n",
-						stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n",
+					       fcall->filename.c_str(), fcall->linenum);
 
 			if (cond->asBool()) {
 				block->children.insert(block->children.begin(), stmt->children.at(1)->clone());
@@ -3360,8 +3359,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			while (num->simplify(true, false, false, 1, -1, false, true)) { }
 
 			if (num->type != AST_CONSTANT)
-				log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n",
-						stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n",
+					       fcall->filename.c_str(), fcall->linenum);
 
 			block->children.erase(block->children.begin());
 			for (int i = 0; i < num->bitsAsConst().as_int(); i++)
@@ -3398,8 +3397,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 					while (cond->simplify(true, false, false, 1, -1, false, true)) { }
 
 					if (cond->type != AST_CONSTANT)
-						log_error("Non-constant expression in constant function at %s:%d (called from %s:%d).\n",
-								stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+						log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n",
+							       fcall->filename.c_str(), fcall->linenum);
 
 					found_match = cond->asBool();
 					delete cond;
@@ -3428,8 +3427,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			continue;
 		}
 
-		log_error("Unsupported language construct in constant function at %s:%d (called from %s:%d).\n",
-				stmt->filename.c_str(), stmt->linenum, fcall->filename.c_str(), fcall->linenum);
+		log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function (called from %s:%d).\n",
+			       fcall->filename.c_str(), fcall->linenum);
 		log_abort();
 	}
 
diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc
index 4a58357bf..7848c626d 100644
--- a/frontends/verilog/const2ast.cc
+++ b/frontends/verilog/const2ast.cc
@@ -49,8 +49,7 @@ static int my_decimal_div_by_two(std::vector<uint8_t> &digits)
 	int carry = 0;
 	for (size_t i = 0; i < digits.size(); i++) {
 		if (digits[i] >= 10)
-			log_error("Invalid use of [a-fxz?] in decimal constant at %s:%d.\n",
-				current_filename.c_str(), get_line_num());
+			log_file_error(current_filename, get_line_num(), "Invalid use of [a-fxz?] in decimal constant.\n");
 		digits[i] += carry * 10;
 		carry = digits[i] % 2;
 		digits[i] /= 2;
@@ -105,8 +104,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
 		int bits_per_digit = my_ilog2(base-1);
 		for (auto it = digits.rbegin(), e = digits.rend(); it != e; it++) {
 			if (*it > (base-1) && *it < 0xf0)
-				log_error("Digit larger than %d used in in base-%d constant at %s:%d.\n",
-					base-1, base, current_filename.c_str(), get_line_num());
+				log_file_error(current_filename, get_line_num(), "Digit larger than %d used in in base-%d constant.\n",
+					       base-1, base);
 			for (int i = 0; i < bits_per_digit; i++) {
 				int bitmask = 1 << i;
 				if (*it == 0xf0)
@@ -238,4 +237,3 @@ AstNode *VERILOG_FRONTEND::const2ast(std::string code, char case_type, bool warn
 }
 
 YOSYS_NAMESPACE_END
-

From 3101b9b8c979f0a4239ccd823932a490b60d128c Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 18:52:52 -0700
Subject: [PATCH 040/528] Fix remaining log_file_error(); emit dependent file
 references in new line.

There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
---
 frontends/ast/simplify.cc | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index be53e8527..75dc60c68 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -3201,13 +3201,13 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
 		int offset = variables.at(str).offset, width = variables.at(str).val.bits.size();
 		if (!children.empty()) {
 			if (children.size() != 1 || children.at(0)->type != AST_RANGE)
-				log_error("Memory access in constant function is not supported in %s:%d (called from %s:%d).\n",
-						filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(filename, linenum, "Memory access in constant function is not supported\n%s:%d: ...called from here.\n",
+					       fcall->filename.c_str(), fcall->linenum);
 			children.at(0)->replace_variables(variables, fcall);
 			while (simplify(true, false, false, 1, -1, false, true)) { }
 			if (!children.at(0)->range_valid)
-				log_error("Non-constant range in %s:%d (called from %s:%d).\n",
-						filename.c_str(), linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(filename, linenum, "Non-constant range\n%s:%d: ... called from here.\n",
+					       fcall->filename.c_str(), fcall->linenum);
 			offset = min(children.at(0)->range_left, children.at(0)->range_right);
 			width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
 		}
@@ -3246,8 +3246,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 		{
 			while (child->simplify(true, false, false, 1, -1, false, true)) { }
 			if (!child->range_valid)
-				log_error("Can't determine size of variable %s in %s:%d (called from %s:%d).\n",
-						child->str.c_str(), child->filename.c_str(), child->linenum, fcall->filename.c_str(), fcall->linenum);
+				log_file_error(child->filename, child->linenum, "Can't determine size of variable %s\n%s:%d: ... called from here.\n",
+					       child->str.c_str(), fcall->filename.c_str(), fcall->linenum);
 			variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1);
 			variables[child->str].offset = min(child->range_left, child->range_right);
 			variables[child->str].is_signed = child->is_signed;
@@ -3290,15 +3290,15 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 				continue;
 
 			if (stmt->children.at(1)->type != AST_CONSTANT)
-				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d). X\n",
+				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here. X\n",
 					       fcall->filename.c_str(), fcall->linenum);
 
 			if (stmt->children.at(0)->type != AST_IDENTIFIER)
-				log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function (called from %s:%d).\n",
+				log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function\n%s:%d: ... called from here.\n",
 					       fcall->filename.c_str(), fcall->linenum);
 
 			if (!variables.count(stmt->children.at(0)->str))
-				log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function (called from %s:%d).\n",
+				log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function\n%s:%d: ... called from here.\n",
 					       fcall->filename.c_str(), fcall->linenum);
 
 			if (stmt->children.at(0)->children.empty()) {
@@ -3306,8 +3306,8 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			} else {
 				AstNode *range = stmt->children.at(0)->children.at(0);
 				if (!range->range_valid)
-					log_error("Non-constant range in %s:%d (called from %s:%d).\n",
-							range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum);
+					log_file_error(range->filename, range->linenum, "Non-constant range\n%s:%d: ... called from here.\n",
+						       fcall->filename.c_str(), fcall->linenum);
 				int offset = min(range->range_left, range->range_right);
 				int width = std::abs(range->range_left - range->range_right) + 1;
 				varinfo_t &v = variables[stmt->children.at(0)->str];
@@ -3338,7 +3338,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			while (cond->simplify(true, false, false, 1, -1, false, true)) { }
 
 			if (cond->type != AST_CONSTANT)
-				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n",
+				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
 					       fcall->filename.c_str(), fcall->linenum);
 
 			if (cond->asBool()) {
@@ -3359,7 +3359,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			while (num->simplify(true, false, false, 1, -1, false, true)) { }
 
 			if (num->type != AST_CONSTANT)
-				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n",
+				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
 					       fcall->filename.c_str(), fcall->linenum);
 
 			block->children.erase(block->children.begin());
@@ -3397,7 +3397,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 					while (cond->simplify(true, false, false, 1, -1, false, true)) { }
 
 					if (cond->type != AST_CONSTANT)
-						log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function (called from %s:%d).\n",
+						log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
 							       fcall->filename.c_str(), fcall->linenum);
 
 					found_match = cond->asBool();
@@ -3427,7 +3427,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			continue;
 		}
 
-		log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function (called from %s:%d).\n",
+		log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function\n%s:%d: ... called from here.\n",
 			       fcall->filename.c_str(), fcall->linenum);
 		log_abort();
 	}

From 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc Mon Sep 17 00:00:00 2001
From: Henner Zeller <h.zeller@acm.org>
Date: Fri, 20 Jul 2018 23:41:18 -0700
Subject: [PATCH 041/528] Consistent use of 'override' for virtual methods in
 derived classes.

o Not all derived methods were marked 'override', but it is a great
  feature of C++11 that we should make use of.
o While at it: touched header files got a -*- c++ -*- for emacs to
  provide support for that language.
o use YS_OVERRIDE for all override keywords (though we should probably
  use the plain keyword going forward now that C++11 is established)
---
 CodingReadme                              |  2 +-
 backends/aiger/aiger.cc                   |  4 ++--
 backends/blif/blif.cc                     |  4 ++--
 backends/btor/btor.cc                     |  4 ++--
 backends/edif/edif.cc                     |  4 ++--
 backends/firrtl/firrtl.cc                 |  4 ++--
 backends/ilang/ilang_backend.cc           |  8 ++++----
 backends/intersynth/intersynth.cc         |  4 ++--
 backends/json/json.cc                     |  8 ++++----
 backends/protobuf/protobuf.cc             |  8 ++++----
 backends/simplec/simplec.cc               |  4 ++--
 backends/smt2/smt2.cc                     |  4 ++--
 backends/smv/smv.cc                       |  4 ++--
 backends/spice/spice.cc                   |  4 ++--
 backends/table/table.cc                   |  4 ++--
 backends/verilog/verilog_backend.cc       |  4 ++--
 examples/cxx-api/evaldemo.cc              |  2 +-
 frontends/ast/ast.h                       |  8 ++++----
 frontends/blif/blifparse.cc               |  4 ++--
 frontends/ilang/ilang_frontend.cc         |  4 ++--
 frontends/json/jsonparse.cc               |  4 ++--
 frontends/liberty/liberty.cc              |  4 ++--
 frontends/verific/verific.cc              | 10 +++++-----
 frontends/verilog/verilog_frontend.cc     | 12 ++++++------
 kernel/celledges.h                        |  6 +++---
 kernel/modtools.h                         | 10 +++++-----
 kernel/register.cc                        | 11 +++++------
 kernel/register.h                         | 14 +++++++-------
 kernel/rtlil.h                            |  2 +-
 kernel/satgen.h                           |  2 +-
 kernel/yosys.cc                           | 16 ++++++++--------
 kernel/yosys.h                            |  2 +-
 manual/CHAPTER_Prog/stubnets.cc           |  2 +-
 manual/PRESENTATION_Prog/my_cmd.cc        |  6 +++---
 passes/cmds/add.cc                        |  4 ++--
 passes/cmds/blackbox.cc                   |  4 ++--
 passes/cmds/check.cc                      |  4 ++--
 passes/cmds/chformal.cc                   |  4 ++--
 passes/cmds/chtype.cc                     |  4 ++--
 passes/cmds/connect.cc                    |  4 ++--
 passes/cmds/connwrappers.cc               |  4 ++--
 passes/cmds/copy.cc                       |  4 ++--
 passes/cmds/cover.cc                      |  4 ++--
 passes/cmds/delete.cc                     |  4 ++--
 passes/cmds/design.cc                     |  6 +++---
 passes/cmds/edgetypes.cc                  |  4 ++--
 passes/cmds/logcmd.cc                     |  4 ++--
 passes/cmds/ltp.cc                        |  4 ++--
 passes/cmds/plugin.cc                     |  4 ++--
 passes/cmds/qwp.cc                        |  4 ++--
 passes/cmds/rename.cc                     |  4 ++--
 passes/cmds/scatter.cc                    |  4 ++--
 passes/cmds/scc.cc                        |  4 ++--
 passes/cmds/select.cc                     | 14 +++++++-------
 passes/cmds/setattr.cc                    | 12 ++++++------
 passes/cmds/setundef.cc                   |  4 ++--
 passes/cmds/show.cc                       |  4 ++--
 passes/cmds/splice.cc                     |  4 ++--
 passes/cmds/splitnets.cc                  |  4 ++--
 passes/cmds/stat.cc                       |  4 ++--
 passes/cmds/tee.cc                        |  4 ++--
 passes/cmds/torder.cc                     |  4 ++--
 passes/cmds/trace.cc                      | 17 ++++++++---------
 passes/cmds/write_file.cc                 |  4 ++--
 passes/equiv/equiv_add.cc                 |  4 ++--
 passes/equiv/equiv_induct.cc              |  4 ++--
 passes/equiv/equiv_make.cc                |  4 ++--
 passes/equiv/equiv_mark.cc                |  4 ++--
 passes/equiv/equiv_miter.cc               |  4 ++--
 passes/equiv/equiv_purge.cc               |  4 ++--
 passes/equiv/equiv_remove.cc              |  4 ++--
 passes/equiv/equiv_simple.cc              |  4 ++--
 passes/equiv/equiv_status.cc              |  4 ++--
 passes/equiv/equiv_struct.cc              |  4 ++--
 passes/fsm/fsm.cc                         |  4 ++--
 passes/fsm/fsm_detect.cc                  |  4 ++--
 passes/fsm/fsm_expand.cc                  |  4 ++--
 passes/fsm/fsm_export.cc                  |  4 ++--
 passes/fsm/fsm_extract.cc                 |  4 ++--
 passes/fsm/fsm_info.cc                    |  4 ++--
 passes/fsm/fsm_map.cc                     |  4 ++--
 passes/fsm/fsm_opt.cc                     |  4 ++--
 passes/fsm/fsm_recode.cc                  |  4 ++--
 passes/hierarchy/hierarchy.cc             |  4 ++--
 passes/hierarchy/submod.cc                |  4 ++--
 passes/hierarchy/uniquify.cc              |  4 ++--
 passes/memory/memory.cc                   |  4 ++--
 passes/memory/memory_bram.cc              |  4 ++--
 passes/memory/memory_collect.cc           |  4 ++--
 passes/memory/memory_dff.cc               |  4 ++--
 passes/memory/memory_map.cc               |  4 ++--
 passes/memory/memory_memx.cc              |  4 ++--
 passes/memory/memory_nordff.cc            |  4 ++--
 passes/memory/memory_share.cc             |  4 ++--
 passes/memory/memory_unpack.cc            |  4 ++--
 passes/opt/opt.cc                         |  4 ++--
 passes/opt/opt_clean.cc                   |  8 ++++----
 passes/opt/opt_demorgan.cc                |  4 ++--
 passes/opt/opt_expr.cc                    |  4 ++--
 passes/opt/opt_merge.cc                   |  4 ++--
 passes/opt/opt_muxtree.cc                 |  4 ++--
 passes/opt/opt_reduce.cc                  |  4 ++--
 passes/opt/opt_rmdff.cc                   |  4 ++--
 passes/opt/rmports.cc                     |  4 ++--
 passes/opt/share.cc                       |  4 ++--
 passes/opt/wreduce.cc                     |  4 ++--
 passes/proc/proc.cc                       |  4 ++--
 passes/proc/proc_arst.cc                  |  4 ++--
 passes/proc/proc_clean.cc                 |  4 ++--
 passes/proc/proc_dff.cc                   |  4 ++--
 passes/proc/proc_dlatch.cc                |  4 ++--
 passes/proc/proc_init.cc                  |  4 ++--
 passes/proc/proc_mux.cc                   |  4 ++--
 passes/proc/proc_rmdead.cc                |  4 ++--
 passes/sat/assertpmux.cc                  |  4 ++--
 passes/sat/async2sync.cc                  |  4 ++--
 passes/sat/clk2fflogic.cc                 |  4 ++--
 passes/sat/eval.cc                        |  4 ++--
 passes/sat/expose.cc                      |  4 ++--
 passes/sat/freduce.cc                     |  4 ++--
 passes/sat/miter.cc                       |  4 ++--
 passes/sat/sat.cc                         |  4 ++--
 passes/sat/sim.cc                         |  4 ++--
 passes/techmap/abc.cc                     |  4 ++--
 passes/techmap/aigmap.cc                  |  4 ++--
 passes/techmap/alumacc.cc                 |  4 ++--
 passes/techmap/attrmap.cc                 | 12 ++++++------
 passes/techmap/attrmvcp.cc                |  4 ++--
 passes/techmap/deminout.cc                |  4 ++--
 passes/techmap/dff2dffe.cc                |  4 ++--
 passes/techmap/dff2dffs.cc                |  4 ++--
 passes/techmap/dffinit.cc                 |  4 ++--
 passes/techmap/dfflibmap.cc               |  4 ++--
 passes/techmap/dffsr2dff.cc               |  4 ++--
 passes/techmap/extract.cc                 |  4 ++--
 passes/techmap/extract_counter.cc         |  4 ++--
 passes/techmap/extract_fa.cc              |  4 ++--
 passes/techmap/extract_reduce.cc          |  4 ++--
 passes/techmap/hilomap.cc                 |  4 ++--
 passes/techmap/insbuf.cc                  |  4 ++--
 passes/techmap/iopadmap.cc                |  4 ++--
 passes/techmap/lut2mux.cc                 |  4 ++--
 passes/techmap/maccmap.cc                 |  4 ++--
 passes/techmap/muxcover.cc                |  4 ++--
 passes/techmap/nlutmap.cc                 |  4 ++--
 passes/techmap/pmuxtree.cc                |  4 ++--
 passes/techmap/shregmap.cc                |  4 ++--
 passes/techmap/simplemap.cc               |  4 ++--
 passes/techmap/techmap.cc                 |  8 ++++----
 passes/techmap/tribuf.cc                  |  4 ++--
 passes/techmap/zinit.cc                   |  4 ++--
 passes/tests/test_abcloop.cc              |  4 ++--
 passes/tests/test_autotb.cc               |  4 ++--
 passes/tests/test_cell.cc                 |  4 ++--
 techlibs/achronix/synth_achronix.cc       |  8 ++++----
 techlibs/common/prep.cc                   |  8 ++++----
 techlibs/common/synth.cc                  |  8 ++++----
 techlibs/coolrunner2/coolrunner2_sop.cc   |  4 ++--
 techlibs/coolrunner2/synth_coolrunner2.cc |  8 ++++----
 techlibs/easic/synth_easic.cc             |  8 ++++----
 techlibs/ecp5/synth_ecp5.cc               |  8 ++++----
 techlibs/gowin/synth_gowin.cc             |  8 ++++----
 techlibs/greenpak4/greenpak4_dffinv.cc    |  4 ++--
 techlibs/greenpak4/synth_greenpak4.cc     |  8 ++++----
 techlibs/ice40/ice40_ffinit.cc            |  4 ++--
 techlibs/ice40/ice40_ffssr.cc             |  4 ++--
 techlibs/ice40/ice40_opt.cc               |  4 ++--
 techlibs/ice40/synth_ice40.cc             |  8 ++++----
 techlibs/intel/synth_intel.cc             | 12 ++++++------
 techlibs/xilinx/synth_xilinx.cc           |  4 ++--
 170 files changed, 414 insertions(+), 416 deletions(-)

diff --git a/CodingReadme b/CodingReadme
index 5800e30c3..4ab132a63 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -21,7 +21,7 @@ Here is a the C++ code for a "hello_world" Yosys command (hello.cc):
 
 	struct HelloWorldPass : public Pass {
 		HelloWorldPass() : Pass("hello_world") { }
-		virtual void execute(vector<string>, Design*) {
+		void execute(vector<string>, Design*) override {
 			log("Hello World!\n");
 		}
 	} HelloWorldPass;
diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index 526e50a49..c323691a3 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -657,7 +657,7 @@ struct AigerWriter
 
 struct AigerBackend : public Backend {
 	AigerBackend() : Backend("aiger", "write design to AIGER file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -690,7 +690,7 @@ struct AigerBackend : public Backend {
 		log("        like -map, but more verbose\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool ascii_mode = false;
 		bool zinit_mode = false;
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index e4509e0d0..0db5ff27c 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -464,7 +464,7 @@ struct BlifDumper
 
 struct BlifBackend : public Backend {
 	BlifBackend() : Backend("blif", "write design to BLIF file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -534,7 +534,7 @@ struct BlifBackend : public Backend {
 		log("        do not write definitions for the $true, $false and $undef wires.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string top_module_name;
 		std::string buf_type, buf_in, buf_out;
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 61a2f8ba3..58d2a8625 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -1076,7 +1076,7 @@ struct BtorWorker
 
 struct BtorBackend : public Backend {
 	BtorBackend() : Backend("btor", "write design to BTOR file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1091,7 +1091,7 @@ struct BtorBackend : public Backend {
 		log("    Output only a single bad property for all asserts\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool verbose = false, single_bad = false;
 
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index a6534b911..5f9ec54fd 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -90,7 +90,7 @@ struct EdifNames
 
 struct EdifBackend : public Backend {
 	EdifBackend() : Backend("edif", "write design to EDIF netlist file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -116,7 +116,7 @@ struct EdifBackend : public Backend {
 		log("is targeted.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing EDIF backend.\n");
 		std::string top_module_name;
diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 06cbc9b2b..4f56f498c 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -527,7 +527,7 @@ struct FirrtlWorker
 
 struct FirrtlBackend : public Backend {
 	FirrtlBackend() : Backend("firrtl", "write design to a FIRRTL file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -536,7 +536,7 @@ struct FirrtlBackend : public Backend {
 		log("Write a FIRRTL netlist of the current design.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 1f7f12361..4c58ea087 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -382,7 +382,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct IlangBackend : public Backend {
 	IlangBackend() : Backend("ilang", "write design to ilang file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -395,7 +395,7 @@ struct IlangBackend : public Backend {
 		log("        only write selected parts of the design.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool selected = false;
 
@@ -422,7 +422,7 @@ struct IlangBackend : public Backend {
 
 struct DumpPass : public Pass {
 	DumpPass() : Pass("dump", "print parts of the design in ilang format") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -445,7 +445,7 @@ struct DumpPass : public Pass {
 		log("        like -outfile but append instead of overwrite\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string filename;
 		bool flag_m = false, flag_n = false, append = false;
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 34cb52fb4..2eb08dbe9 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -46,7 +46,7 @@ static std::string netname(std::set<std::string> &conntypes_code, std::set<std::
 
 struct IntersynthBackend : public Backend {
 	IntersynthBackend() : Backend("intersynth", "write design to InterSynth netlist file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -71,7 +71,7 @@ struct IntersynthBackend : public Backend {
 		log("http://www.clifford.at/intersynth/\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing INTERSYNTH backend.\n");
 		log_push();
diff --git a/backends/json/json.cc b/backends/json/json.cc
index d3b7077a2..5a87859a0 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -250,7 +250,7 @@ struct JsonWriter
 
 struct JsonBackend : public Backend {
 	JsonBackend() : Backend("json", "write design to a JSON file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -458,7 +458,7 @@ struct JsonBackend : public Backend {
 		log("format. A program processing this format must ignore all unknown fields.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool aig_mode = false;
 
@@ -482,7 +482,7 @@ struct JsonBackend : public Backend {
 
 struct JsonPass : public Pass {
 	JsonPass() : Pass("json", "write design in JSON format") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -499,7 +499,7 @@ struct JsonPass : public Pass {
 		log("See 'help write_json' for a description of the JSON format used.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string filename;
 		bool aig_mode = false;
diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc
index 9a6fedee7..f56147cef 100644
--- a/backends/protobuf/protobuf.cc
+++ b/backends/protobuf/protobuf.cc
@@ -231,7 +231,7 @@ struct ProtobufDesignSerializer
 
 struct ProtobufBackend : public Backend {
 	ProtobufBackend(): Backend("protobuf", "write design to a Protocol Buffer file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -249,7 +249,7 @@ struct ProtobufBackend : public Backend {
 		log("Yosys source code distribution.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool aig_mode = false;
 		bool text_mode = false;
@@ -286,7 +286,7 @@ struct ProtobufBackend : public Backend {
 
 struct ProtobufPass : public Pass {
 	ProtobufPass() : Pass("protobuf", "write design in Protobuf format") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -307,7 +307,7 @@ struct ProtobufPass : public Pass {
 		log("Yosys source code distribution.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string filename;
 		bool aig_mode = false;
diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index c9656caff..349bc5a6d 100644
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -742,7 +742,7 @@ struct SimplecWorker
 
 struct SimplecBackend : public Backend {
 	SimplecBackend() : Backend("simplec", "convert design to simple C code") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -761,7 +761,7 @@ struct SimplecBackend : public Backend {
 		log("THIS COMMAND IS UNDER CONSTRUCTION\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		reserved_cids.clear();
 		id2cid.clear();
diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index ca1ceacc7..e2777ae04 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -1251,7 +1251,7 @@ struct Smt2Worker
 
 struct Smt2Backend : public Backend {
 	Smt2Backend() : Backend("smt2", "write design to SMT-LIBv2 file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1407,7 +1407,7 @@ struct Smt2Backend : public Backend {
 		log("from non-zero to zero in the test design.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::ifstream template_f;
 		bool bvmode = true, memmode = true, wiresmode = false, verbose = false, statebv = false, statedt = false;
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index 768969e6b..b8383412b 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -675,7 +675,7 @@ struct SmvWorker
 
 struct SmvBackend : public Backend {
 	SmvBackend() : Backend("smv", "write design to SMV file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -693,7 +693,7 @@ struct SmvBackend : public Backend {
 		log("THIS COMMAND IS UNDER CONSTRUCTION\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::ifstream template_f;
 		bool verbose = false;
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 4101cbf98..b6a3f1e77 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -132,7 +132,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
 
 struct SpiceBackend : public Backend {
 	SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -161,7 +161,7 @@ struct SpiceBackend : public Backend {
 		log("        set the specified module as design top module\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string top_module_name;
 		RTLIL::Module *top_module = NULL;
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 27b7edfff..979273dd3 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -29,7 +29,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct TableBackend : public Backend {
 	TableBackend() : Backend("table", "write design as connectivity table") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -48,7 +48,7 @@ struct TableBackend : public Backend {
 		log("module inputs and outputs are output using cell type and port '-' and with\n");
 		log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing TABLE backend.\n");
 
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index b50dc12af..44e4e5f97 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1482,7 +1482,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 
 struct VerilogBackend : public Backend {
 	VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1550,7 +1550,7 @@ struct VerilogBackend : public Backend {
 		log("this command is called on a design with RTLIL processes.\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing Verilog backend.\n");
 
diff --git a/examples/cxx-api/evaldemo.cc b/examples/cxx-api/evaldemo.cc
index e5cc8d8e7..34373487d 100644
--- a/examples/cxx-api/evaldemo.cc
+++ b/examples/cxx-api/evaldemo.cc
@@ -22,7 +22,7 @@ struct EvalDemoPass : public Pass
 {
 	EvalDemoPass() : Pass("evaldemo") { }
 
-	virtual void execute(vector<string>, Design *design)
+	void execute(vector<string>, Design *design) YS_OVERRIDE
 	{
 		Module *module = design->top_module();
 
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 756629aca..ed784e831 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
@@ -282,9 +282,9 @@ namespace AST
 	struct AstModule : RTLIL::Module {
 		AstNode *ast;
 		bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
-		virtual ~AstModule();
-		virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail);
-		virtual RTLIL::Module *clone() const;
+		~AstModule() YS_OVERRIDE;
+		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
+		RTLIL::Module *clone() const YS_OVERRIDE;
 	};
 
 	// this must be set by the language frontend before parsing the sources
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index e6bb99954..85ac4ff21 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -550,7 +550,7 @@ error:
 
 struct BlifFrontend : public Frontend {
 	BlifFrontend() : Frontend("blif", "read BLIF file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -566,7 +566,7 @@ struct BlifFrontend : public Frontend {
 		log("        multi-bit port 'name'.\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool sop_mode = false;
 		bool wideports = false;
diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc
index ed6789987..d8783ac1d 100644
--- a/frontends/ilang/ilang_frontend.cc
+++ b/frontends/ilang/ilang_frontend.cc
@@ -35,7 +35,7 @@ YOSYS_NAMESPACE_BEGIN
 
 struct IlangFrontend : public Frontend {
 	IlangFrontend() : Frontend("ilang", "read modules from ilang file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -45,7 +45,7 @@ struct IlangFrontend : public Frontend {
 		log("representation of a design in yosys's internal format.)\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ILANG frontend.\n");
 		extra_args(f, filename, args, 1);
diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index 629578c61..82361ea9b 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -494,7 +494,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
 
 struct JsonFrontend : public Frontend {
 	JsonFrontend() : Frontend("json", "read JSON file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -504,7 +504,7 @@ struct JsonFrontend : public Frontend {
 		log("for a description of the file format.\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing JSON frontend.\n");
 
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index b9e53a4be..0a5bd84de 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -452,7 +452,7 @@ void parse_type_map(std::map<std::string, std::tuple<int, int, bool>> &type_map,
 
 struct LibertyFrontend : public Frontend {
 	LibertyFrontend() : Frontend("liberty", "read cells from liberty file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -485,7 +485,7 @@ struct LibertyFrontend : public Frontend {
 		log("        set the specified attribute (to the value 1) on all loaded modules\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_lib = false;
 		bool flag_nooverwrite = false;
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8937cdde8..09bb253f5 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1685,7 +1685,7 @@ bool check_noverific_env()
 
 struct VerificPass : public Pass {
 	VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1784,7 +1784,7 @@ struct VerificPass : public Pass {
 		log("\n");
 	}
 #ifdef YOSYS_ENABLE_VERIFIC
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		if (check_noverific_env())
 			log_cmd_error("This version of Yosys is built without Verific support.\n");
@@ -2162,7 +2162,7 @@ struct VerificPass : public Pass {
 
 	}
 #else /* YOSYS_ENABLE_VERIFIC */
-	virtual void execute(std::vector<std::string>, RTLIL::Design *) {
+	void execute(std::vector<std::string>, RTLIL::Design *) YS_OVERRIDE {
 		log_cmd_error("This version of Yosys is built without Verific support.\n");
 	}
 #endif
@@ -2170,7 +2170,7 @@ struct VerificPass : public Pass {
 
 struct ReadPass : public Pass {
 	ReadPass() : Pass("read", "load HDL designs") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -2203,7 +2203,7 @@ struct ReadPass : public Pass {
 		log("Add directory to global Verilog/SystemVerilog include directories.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		if (args.size() < 2)
 			log_cmd_error("Missing mode parameter.\n");
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index be925fea2..911e36112 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -49,7 +49,7 @@ static void error_on_dpi_function(AST::AstNode *node)
 
 struct VerilogFrontend : public Frontend {
 	VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -180,7 +180,7 @@ struct VerilogFrontend : public Frontend {
 		log("supported by the Yosys Verilog front-end.\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
@@ -395,7 +395,7 @@ struct VerilogFrontend : public Frontend {
 
 struct VerilogDefaults : public Pass {
 	VerilogDefaults() : Pass("verilog_defaults", "set default options for read_verilog") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -416,7 +416,7 @@ struct VerilogDefaults : public Pass {
 		log("not imply -clear.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		if (args.size() < 2)
 			cmd_error(args, 1, "Missing argument.");
@@ -453,7 +453,7 @@ struct VerilogDefaults : public Pass {
 
 struct VerilogDefines : public Pass {
 	VerilogDefines() : Pass("verilog_defines", "define and undefine verilog defines") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -469,7 +469,7 @@ struct VerilogDefines : public Pass {
 		log("        undefine the preprocessor symbol 'name'\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/kernel/celledges.h b/kernel/celledges.h
index 6aab9ed43..2cc297cb2 100644
--- a/kernel/celledges.h
+++ b/kernel/celledges.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
@@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
 	dict<SigBit, pool<SigBit>> db;
 	FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
 
-	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
+	void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
 		SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
 		SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
 		db[from_sigbit].insert(to_sigbit);
@@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
 	dict<SigBit, pool<SigBit>> db;
 	RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
 
-	virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
+	void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE {
 		SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
 		SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
 		db[to_sigbit].insert(from_sigbit);
diff --git a/kernel/modtools.h b/kernel/modtools.h
index ffcb48d44..409562eb9 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
@@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor
 #endif
 	}
 
-	virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
+	void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
 	{
 		log_assert(module == cell->module);
 
@@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor
 		port_add(cell, port, sig);
 	}
 
-	virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
+	void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE
 	{
 		log_assert(module == mod);
 
@@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor
 		}
 	}
 
-	virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
+	void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE
 	{
 		log_assert(module == mod);
 		auto_reload_module = true;
 	}
 
-	virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
+	void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE
 	{
 		log_assert(module == mod);
 		auto_reload_module = true;
diff --git a/kernel/register.cc b/kernel/register.cc
index e30414f44..402a5b3ea 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -615,7 +615,7 @@ static struct CellHelpMessages {
 
 struct HelpPass : public Pass {
 	HelpPass() : Pass("help", "display help messages") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    help  ................  list all commands\n");
@@ -684,7 +684,7 @@ struct HelpPass : public Pass {
 
 		fclose(f);
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		if (args.size() == 1) {
 			log("\n");
@@ -768,7 +768,7 @@ struct HelpPass : public Pass {
 
 struct EchoPass : public Pass {
 	EchoPass() : Pass("echo", "turning echoing back of commands on and off") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    echo on\n");
@@ -781,7 +781,7 @@ struct EchoPass : public Pass {
 		log("Do not print all commands to log before executing them. (default)\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		if (args.size() > 2)
 			cmd_error(args, 2, "Unexpected argument.");
@@ -806,10 +806,9 @@ struct MinisatSatSolver : public SatSolver {
 	MinisatSatSolver() : SatSolver("minisat") {
 		yosys_satsolver = this;
 	}
-	virtual ezSAT *create() YS_OVERRIDE {
+	ezSAT *create() YS_OVERRIDE {
 		return new ezMiniSAT();
 	}
 } MinisatSatSolver;
 
 YOSYS_NAMESPACE_END
-
diff --git a/kernel/register.h b/kernel/register.h
index 8024c56a0..c74029823 100644
--- a/kernel/register.h
+++ b/kernel/register.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
@@ -88,9 +88,9 @@ struct Frontend : Pass
 
 	std::string frontend_name;
 	Frontend(std::string name, std::string short_help = "** document me **");
-	virtual void run_register() YS_OVERRIDE;
-	virtual ~Frontend();
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
+	void run_register() YS_OVERRIDE;
+	~Frontend() YS_OVERRIDE;
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
 	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0;
 
 	static std::vector<std::string> next_args;
@@ -104,9 +104,9 @@ struct Backend : Pass
 {
 	std::string backend_name;
 	Backend(std::string name, std::string short_help = "** document me **");
-	virtual void run_register() YS_OVERRIDE;
-	virtual ~Backend();
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
+	void run_register() YS_OVERRIDE;
+	~Backend() YS_OVERRIDE;
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL;
 	virtual void execute(std::ostream *&f, std::string filename,  std::vector<std::string> args, RTLIL::Design *design) = 0;
 
 	void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 54d0b8c22..027faf416 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 8d760fff7..210cca3f3 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 750a154e6..2a8ab2005 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -636,7 +636,7 @@ extern Tcl_Interp *yosys_get_tcl_interp()
 
 struct TclPass : public Pass {
 	TclPass() : Pass("tcl", "execute a TCL script file") { }
-	virtual void help() {
+	void help() YS_OVERRIDE {
 		log("\n");
 		log("    tcl <filename>\n");
 		log("\n");
@@ -649,7 +649,7 @@ struct TclPass : public Pass {
 		log("in order to avoid a name collision with the built in commands.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		if (args.size() < 2)
 			log_cmd_error("Missing script file.\n");
 		if (args.size() > 2)
@@ -1111,7 +1111,7 @@ void shell(RTLIL::Design *design)
 
 struct ShellPass : public Pass {
 	ShellPass() : Pass("shell", "enter interactive command mode") { }
-	virtual void help() {
+	void help() YS_OVERRIDE {
 		log("\n");
 		log("    shell\n");
 		log("\n");
@@ -1143,7 +1143,7 @@ struct ShellPass : public Pass {
 		log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		extra_args(args, 1, design, false);
 		shell(design);
 	}
@@ -1152,7 +1152,7 @@ struct ShellPass : public Pass {
 #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE)
 struct HistoryPass : public Pass {
 	HistoryPass() : Pass("history", "show last interactive commands") { }
-	virtual void help() {
+	void help() YS_OVERRIDE {
 		log("\n");
 		log("    history\n");
 		log("\n");
@@ -1161,7 +1161,7 @@ struct HistoryPass : public Pass {
 		log("from executed scripts.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		extra_args(args, 1, design, false);
 #ifdef YOSYS_ENABLE_READLINE
 		for(HIST_ENTRY **list = history_list(); *list != NULL; list++)
@@ -1176,7 +1176,7 @@ struct HistoryPass : public Pass {
 
 struct ScriptCmdPass : public Pass {
 	ScriptCmdPass() : Pass("script", "execute commands from script file") { }
-	virtual void help() {
+	void help() YS_OVERRIDE {
 		log("\n");
 		log("    script <filename> [<from_label>:<to_label>]\n");
 		log("\n");
@@ -1191,7 +1191,7 @@ struct ScriptCmdPass : public Pass {
 		log("marked with that label (until the next label) is executed.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		if (args.size() < 2)
 			log_cmd_error("Missing script file.\n");
 		else if (args.size() == 2)
diff --git a/kernel/yosys.h b/kernel/yosys.h
index 14cbcd610..c9f973318 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -1,4 +1,4 @@
-/*
+/* -*- c++ -*-
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
diff --git a/manual/CHAPTER_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc
index eb77bd404..8123e63db 100644
--- a/manual/CHAPTER_Prog/stubnets.cc
+++ b/manual/CHAPTER_Prog/stubnets.cc
@@ -98,7 +98,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
 // each pass contains a singleton object that is derived from Pass
 struct StubnetsPass : public Pass {
 	StubnetsPass() : Pass("stubnets") { }
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		// variables to mirror information from passed options
 		bool report_bits = 0;
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc
index d99bfe1e8..5d9a7e13b 100644
--- a/manual/PRESENTATION_Prog/my_cmd.cc
+++ b/manual/PRESENTATION_Prog/my_cmd.cc
@@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct MyPass : public Pass {
     MyPass() : Pass("my_cmd", "just a simple test") { }
-    virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+    void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
     {
         log("Arguments to my_cmd:\n");
         for (auto &arg : args)
@@ -22,7 +22,7 @@ struct MyPass : public Pass {
 
 struct Test1Pass : public Pass {
     Test1Pass() : Pass("test1", "creating the absval module") { }
-    virtual void execute(std::vector<std::string>, RTLIL::Design *design)
+    void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
     {
         if (design->has("\\absval") != 0)
             log_error("A module with the name absval already exists!\n");
@@ -49,7 +49,7 @@ struct Test1Pass : public Pass {
 
 struct Test2Pass : public Pass {
     Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
-    virtual void execute(std::vector<std::string>, RTLIL::Design *design)
+    void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
     {
         if (design->selection_stack.back().empty())
             log_cmd_error("This command can't operator on an empty selection!\n");
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index e698926f9..cfccca966 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -83,7 +83,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 
 struct AddPass : public Pass {
 	AddPass() : Pass("add", "add objects to the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -106,7 +106,7 @@ struct AddPass : public Pass {
 		log("selected modules.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string command;
 		std::string arg_name;
diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 497b35f5c..6094f8f16 100644
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct BlackboxPass : public Pass {
 	BlackboxPass() : Pass("blackbox", "change type of cells in the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -34,7 +34,7 @@ struct BlackboxPass : public Pass {
 		log("module attribute).\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index bb8fe6856..64697c134 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct CheckPass : public Pass {
 	CheckPass() : Pass("check", "check for obvious problems in the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -51,7 +51,7 @@ struct CheckPass : public Pass {
 		log("problems are found in the current design.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		int counter = 0;
 		bool noinit = false;
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc
index a8c1fef85..522758eae 100644
--- a/passes/cmds/chformal.cc
+++ b/passes/cmds/chformal.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ChformalPass : public Pass {
 	ChformalPass() : Pass("chformal", "change formal constraints of the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -62,7 +62,7 @@ struct ChformalPass : public Pass {
 		log("        change the roles of cells as indicated. this options can be combined\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool assert2assume = false;
 		bool assume2assert = false;
diff --git a/passes/cmds/chtype.cc b/passes/cmds/chtype.cc
index 90d51667c..979aeadd4 100644
--- a/passes/cmds/chtype.cc
+++ b/passes/cmds/chtype.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ChtypePass : public Pass {
 	ChtypePass() : Pass("chtype", "change type of cells in the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -40,7 +40,7 @@ struct ChtypePass : public Pass {
 		log("\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		IdString set_type;
 		dict<IdString, IdString> map_types;
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index 52611cf44..d480b79ac 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -43,7 +43,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
 
 struct ConnectPass : public Pass {
 	ConnectPass() : Pass("connect", "create or remove connections") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -75,7 +75,7 @@ struct ConnectPass : public Pass {
 		log("This command does not operate on module with processes.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		RTLIL::Module *module = NULL;
 		for (auto &it : design->modules_) {
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 1ea48b7eb..5a15cbbaf 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -150,7 +150,7 @@ struct ConnwrappersWorker
 
 struct ConnwrappersPass : public Pass {
 	ConnwrappersPass() : Pass("connwrappers", "match width of input-output port pairs") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -172,7 +172,7 @@ struct ConnwrappersPass : public Pass {
 		log("The options -signed, -unsigned, and -port can be specified multiple times.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		ConnwrappersWorker worker;
 
diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc
index fb863512b..acd2dba52 100644
--- a/passes/cmds/copy.cc
+++ b/passes/cmds/copy.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct CopyPass : public Pass {
 	CopyPass() : Pass("copy", "copy modules in the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -36,7 +36,7 @@ struct CopyPass : public Pass {
 		log("by this command.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		if (args.size() != 3)
 			log_cmd_error("Invalid number of arguments!\n");
diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc
index ef4f3f7d0..0ec747671 100644
--- a/passes/cmds/cover.cc
+++ b/passes/cmds/cover.cc
@@ -35,7 +35,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct CoverPass : public Pass {
 	CoverPass() : Pass("cover", "print code coverage counters") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -83,7 +83,7 @@ struct CoverPass : public Pass {
 		log("Coverage counters are only available in Yosys for Linux.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::vector<FILE*> out_files;
 		std::vector<std::string> patterns;
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 6d51d30e7..f8d91ea48 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct DeletePass : public Pass {
 	DeletePass() : Pass("delete", "delete objects in the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -40,7 +40,7 @@ struct DeletePass : public Pass {
 		log("selected wires, thus 'deleting' module ports.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_input = false;
 		bool flag_output = false;
diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 490c8dde5..172addcc1 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -27,7 +27,7 @@ std::vector<RTLIL::Design*> pushed_designs;
 
 struct DesignPass : public Pass {
 	DesignPass() : Pass("design", "save, restore and reset current design") { }
-	virtual ~DesignPass() {
+	~DesignPass() YS_OVERRIDE {
 		for (auto &it : saved_designs)
 			delete it.second;
 		saved_designs.clear();
@@ -35,7 +35,7 @@ struct DesignPass : public Pass {
 			delete it;
 		pushed_designs.clear();
 	}
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -94,7 +94,7 @@ struct DesignPass : public Pass {
 		log("between calls to 'read_verilog'. This command resets this memory.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool got_mode = false;
 		bool reset_mode = false;
diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc
index 7b75a009f..58ed6457d 100644
--- a/passes/cmds/edgetypes.cc
+++ b/passes/cmds/edgetypes.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct EdgetypePass : public Pass {
 	EdgetypePass() : Pass("edgetypes", "list all types of edges in selection") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -35,7 +35,7 @@ struct EdgetypePass : public Pass {
 		log("is a 4-tuple of source and sink cell type and port name.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/cmds/logcmd.cc b/passes/cmds/logcmd.cc
index 85386f3d2..522e1089d 100644
--- a/passes/cmds/logcmd.cc
+++ b/passes/cmds/logcmd.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct LogPass : public Pass {
 	LogPass() : Pass("log", "print text and log files") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -52,7 +52,7 @@ struct LogPass : public Pass {
 		log("        do not append a newline\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		size_t argidx;
 		bool to_stdout = false;
diff --git a/passes/cmds/ltp.cc b/passes/cmds/ltp.cc
index 42dc794ec..05701710b 100644
--- a/passes/cmds/ltp.cc
+++ b/passes/cmds/ltp.cc
@@ -141,7 +141,7 @@ struct LtpWorker
 
 struct LtpPass : public Pass {
 	LtpPass() : Pass("ltp", "print longest topological path") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -154,7 +154,7 @@ struct LtpPass : public Pass {
 		log("        automatically exclude FF cell types\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool noff = false;
 
diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc
index 828c671de..aa6d5b6cc 100644
--- a/passes/cmds/plugin.cc
+++ b/passes/cmds/plugin.cc
@@ -58,7 +58,7 @@ void load_plugin(std::string, std::vector<std::string>)
 
 struct PluginPass : public Pass {
 	PluginPass() : Pass("plugin", "load and list loaded plugins") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -76,7 +76,7 @@ struct PluginPass : public Pass {
 		log("        List loaded plugins\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string plugin_filename;
 		std::vector<std::string> plugin_aliases;
diff --git a/passes/cmds/qwp.cc b/passes/cmds/qwp.cc
index f2dfa760e..1c64a7b77 100644
--- a/passes/cmds/qwp.cc
+++ b/passes/cmds/qwp.cc
@@ -778,7 +778,7 @@ struct QwpWorker
 
 struct QwpPass : public Pass {
 	QwpPass() : Pass("qwp", "quadratic wirelength placer") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -808,7 +808,7 @@ struct QwpPass : public Pass {
 		log("dense matrix operations. It is only a toy-placer for small circuits.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		QwpConfig config;
 		xorshift32_state = 123456789;
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 6a002869b..dce576fdf 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -54,7 +54,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 
 struct RenamePass : public Pass {
 	RenamePass() : Pass("rename", "rename object in the design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -81,7 +81,7 @@ struct RenamePass : public Pass {
 		log("Rename top module.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string pattern_prefix = "_", pattern_suffix = "_";
 		bool flag_enumerate = false;
diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc
index f083e1f67..7123ba9fb 100644
--- a/passes/cmds/scatter.cc
+++ b/passes/cmds/scatter.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ScatterPass : public Pass {
 	ScatterPass() : Pass("scatter", "add additional intermediate nets") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -41,7 +41,7 @@ struct ScatterPass : public Pass {
 		log("Use the opt_clean command to get rid of the additional nets.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		CellTypes ct(design);
 		extra_args(args, 1, design);
diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc
index 76363e051..99f4fbae8 100644
--- a/passes/cmds/scc.cc
+++ b/passes/cmds/scc.cc
@@ -218,7 +218,7 @@ struct SccWorker
 
 struct SccPass : public Pass {
 	SccPass() : Pass("scc", "detect strongly connected components (logic loops)") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -255,7 +255,7 @@ struct SccPass : public Pass {
 		log("        that are part of a found logic loop\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::map<std::string, std::string> setAttr;
 		bool allCellTypes = false;
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index a0720797f..d97aa2b37 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -950,7 +950,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct SelectPass : public Pass {
 	SelectPass() : Pass("select", "modify and view the list of selected objects") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -964,7 +964,7 @@ struct SelectPass : public Pass {
 		log("list of selected objects.\n");
 		log("\n");
 		log("Note that many commands support an optional [selection] argument that can be\n");
-		log("used to override the global selection for the command. The syntax of this\n");
+		log("used to YS_OVERRIDE the global selection for the command. The syntax of this\n");
 		log("optional argument is identical to the syntax of the <selection> argument\n");
 		log("described here.\n");
 		log("\n");
@@ -1167,7 +1167,7 @@ struct SelectPass : public Pass {
 		log("    select */t:SWITCH %%x:+[GATE] */t:SWITCH %%d\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool add_mode = false;
 		bool del_mode = false;
@@ -1470,7 +1470,7 @@ struct SelectPass : public Pass {
 
 struct CdPass : public Pass {
 	CdPass() : Pass("cd", "a shortcut for 'select -module <name>'") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1496,7 +1496,7 @@ struct CdPass : public Pass {
 		log("This is just a shortcut for 'select -clear'.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		if (args.size() != 1 && args.size() != 2)
 			log_cmd_error("Invalid number of arguments.\n");
@@ -1578,7 +1578,7 @@ static void log_matches(const char *title, Module *module, T list)
 
 struct LsPass : public Pass {
 	LsPass() : Pass("ls", "list modules or objects in modules") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1589,7 +1589,7 @@ struct LsPass : public Pass {
 		log("When an active module is selected, this prints a list of objects in the module.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx = 1;
 		extra_args(args, argidx, design);
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 689e3148b..d38a6b3da 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -56,7 +56,7 @@ static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, const std::v
 
 struct SetattrPass : public Pass {
 	SetattrPass() : Pass("setattr", "set/unset attributes on objects") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -69,7 +69,7 @@ struct SetattrPass : public Pass {
 		log("instead of objects within modules.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::vector<setunset_t> setunset_list;
 		bool flag_mod = false;
@@ -130,7 +130,7 @@ struct SetattrPass : public Pass {
 
 struct SetparamPass : public Pass {
 	SetparamPass() : Pass("setparam", "set/unset parameters on objects") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -142,7 +142,7 @@ struct SetparamPass : public Pass {
 		log("The -type option can be used to change the cell type of the selected cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		vector<setunset_t> setunset_list;
 		string new_cell_type;
@@ -188,7 +188,7 @@ struct SetparamPass : public Pass {
 
 struct ChparamPass : public Pass {
 	ChparamPass() : Pass("chparam", "re-evaluate modules with new parameters") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -203,7 +203,7 @@ struct ChparamPass : public Pass {
 		log("List the available parameters of the selected modules.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::vector<setunset_t> setunset_list;
 		dict<RTLIL::IdString, RTLIL::Const> new_parameters;
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 3a3ebedf1..0c51c3f06 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -79,7 +79,7 @@ struct SetundefWorker
 
 struct SetundefPass : public Pass {
 	SetundefPass() : Pass("setundef", "replace undef values with defined constants") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -113,7 +113,7 @@ struct SetundefPass : public Pass {
 		log("        also create/update init values for flip-flops\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool got_value = false;
 		bool undriven_mode = false;
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 56e1122bf..ec04418fa 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -573,7 +573,7 @@ struct ShowWorker
 
 struct ShowPass : public Pass {
 	ShowPass() : Pass("show", "generate schematics using graphviz") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -655,7 +655,7 @@ struct ShowPass : public Pass {
 		log("the 'show' command is executed.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Generating Graphviz representation of design.\n");
 		log_push();
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 7418ec4d2..bafafca4e 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -247,7 +247,7 @@ struct SpliceWorker
 
 struct SplicePass : public Pass {
 	SplicePass() : Pass("splice", "create explicit splicing cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -288,7 +288,7 @@ struct SplicePass : public Pass {
 		log("by selected wires are rewired.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool sel_by_cell = false;
 		bool sel_by_wire = false;
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 5e37fc597..f5a1f17b3 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -87,7 +87,7 @@ struct SplitnetsWorker
 
 struct SplitnetsPass : public Pass {
 	SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -109,7 +109,7 @@ struct SplitnetsPass : public Pass {
 		log("        and split nets so that no driver drives only part of a net.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_ports = false;
 		bool flag_driver = false;
diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc
index f1d958a1a..54f4ea817 100644
--- a/passes/cmds/stat.cc
+++ b/passes/cmds/stat.cc
@@ -209,7 +209,7 @@ void read_liberty_cellarea(dict<IdString, double> &cell_area, string liberty_fil
 
 struct StatPass : public Pass {
 	StatPass() : Pass("stat", "print some statistics") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -231,7 +231,7 @@ struct StatPass : public Pass {
 		log("        e.g. $add_8 for an 8 bit wide $add cell.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Printing statistics.\n");
 
diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc
index b68c089e9..ff80f3859 100644
--- a/passes/cmds/tee.cc
+++ b/passes/cmds/tee.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct TeePass : public Pass {
 	TeePass() : Pass("tee", "redirect command output to file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -49,7 +49,7 @@ struct TeePass : public Pass {
 		log("        Add/subract INT from the -v setting for this command.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::vector<FILE*> backup_log_files, files_to_close;
 		int backup_log_verbose_level = log_verbose_level;
diff --git a/passes/cmds/torder.cc b/passes/cmds/torder.cc
index 56223610d..3c0eac8de 100644
--- a/passes/cmds/torder.cc
+++ b/passes/cmds/torder.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct TorderPass : public Pass {
 	TorderPass() : Pass("torder", "print cells in topological order") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -43,7 +43,7 @@ struct TorderPass : public Pass {
 		log("        are not used in topological sorting. this option deactivates that.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool noautostop = false;
 		dict<IdString, pool<IdString>> stop_db;
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index 1a5f873ff..f5305cde9 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -25,34 +25,34 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct TraceMonitor : public RTLIL::Monitor
 {
-	virtual void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
+	void notify_module_add(RTLIL::Module *module) YS_OVERRIDE
 	{
 		log("#TRACE# Module add: %s\n", log_id(module));
 	}
 
-	virtual void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
+	void notify_module_del(RTLIL::Module *module) YS_OVERRIDE
 	{
 		log("#TRACE# Module delete: %s\n", log_id(module));
 	}
 
-	virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
+	void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE
 	{
 		log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
 	}
 
-	virtual void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
+	void notify_connect(RTLIL::Module *module, const RTLIL::SigSig &sigsig) YS_OVERRIDE
 	{
 		log("#TRACE# Connection in module %s: %s = %s\n", log_id(module), log_signal(sigsig.first), log_signal(sigsig.second));
 	}
 
-	virtual void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
+	void notify_connect(RTLIL::Module *module, const std::vector<RTLIL::SigSig> &sigsig_vec) YS_OVERRIDE
 	{
 		log("#TRACE# New connections in module %s:\n", log_id(module));
 		for (auto &sigsig : sigsig_vec)
 			log("##    %s = %s\n", log_signal(sigsig.first), log_signal(sigsig.second));
 	}
 
-	virtual void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
+	void notify_blackout(RTLIL::Module *module) YS_OVERRIDE
 	{
 		log("#TRACE# Blackout in module %s:\n", log_id(module));
 	}
@@ -60,7 +60,7 @@ struct TraceMonitor : public RTLIL::Monitor
 
 struct TracePass : public Pass {
 	TracePass() : Pass("trace", "redirect command output to file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -70,7 +70,7 @@ struct TracePass : public Pass {
 		log("the design in real time.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -95,4 +95,3 @@ struct TracePass : public Pass {
 } TracePass;
 
 PRIVATE_NAMESPACE_END
-
diff --git a/passes/cmds/write_file.cc b/passes/cmds/write_file.cc
index 70892a945..9613b462b 100644
--- a/passes/cmds/write_file.cc
+++ b/passes/cmds/write_file.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct WriteFileFrontend : public Frontend {
 	WriteFileFrontend() : Frontend("=write_file", "write a text to a file") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -44,7 +44,7 @@ struct WriteFileFrontend : public Frontend {
 		log("    EOT\n");
 		log("\n");
 	}
-	virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		bool append_mode = false;
 		std::string output_filename;
diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc
index 0494a724f..71599f46e 100644
--- a/passes/equiv/equiv_add.cc
+++ b/passes/equiv/equiv_add.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct EquivAddPass : public Pass {
 	EquivAddPass() : Pass("equiv_add", "add a $equiv cell") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -39,7 +39,7 @@ struct EquivAddPass : public Pass {
 		log("This command adds $equiv cells for the ports of the specified cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		bool try_mode = false;
 
diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index c958c3de4..bcc68d6d2 100644
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -162,7 +162,7 @@ struct EquivInductWorker
 
 struct EquivInductPass : public Pass {
 	EquivInductPass() : Pass("equiv_induct", "proving $equiv cells using temporal induction") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -192,7 +192,7 @@ struct EquivInductPass : public Pass {
 		log("after reset.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		int success_counter = 0;
 		bool model_undef = false;
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index b20463777..b1f88d55e 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -390,7 +390,7 @@ struct EquivMakeWorker
 
 struct EquivMakePass : public Pass {
 	EquivMakePass() : Pass("equiv_make", "prepare a circuit for equivalence checking") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -415,7 +415,7 @@ struct EquivMakePass : public Pass {
 		log("checking problem. Use 'miter -equiv' if you want to create a miter circuit.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		EquivMakeWorker worker;
 		worker.ct.setup(design);
diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
index 22c501763..135eaf145 100644
--- a/passes/equiv/equiv_mark.cc
+++ b/passes/equiv/equiv_mark.cc
@@ -204,7 +204,7 @@ struct EquivMarkWorker
 
 struct EquivMarkPass : public Pass {
 	EquivMarkPass() : Pass("equiv_mark", "mark equivalence checking regions") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -216,7 +216,7 @@ struct EquivMarkPass : public Pass {
 		log("wires and cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing EQUIV_MARK pass.\n");
 
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc
index eb2e5a171..e06f9515b 100644
--- a/passes/equiv/equiv_miter.cc
+++ b/passes/equiv/equiv_miter.cc
@@ -261,7 +261,7 @@ struct EquivMiterWorker
 
 struct EquivMiterPass : public Pass {
 	EquivMiterPass() : Pass("equiv_miter", "extract miter from equiv circuit") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -282,7 +282,7 @@ struct EquivMiterPass : public Pass {
 		log("        Create compare logic that handles undefs correctly\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		EquivMiterWorker worker;
 		worker.ct.setup(design);
diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
index f8d3cd0af..18b3e7d36 100644
--- a/passes/equiv/equiv_purge.cc
+++ b/passes/equiv/equiv_purge.cc
@@ -176,7 +176,7 @@ struct EquivPurgeWorker
 
 struct EquivPurgePass : public Pass {
 	EquivPurgePass() : Pass("equiv_purge", "purge equivalence checking module") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -187,7 +187,7 @@ struct EquivPurgePass : public Pass {
 		log("ports as needed.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing EQUIV_PURGE pass.\n");
 
diff --git a/passes/equiv/equiv_remove.cc b/passes/equiv/equiv_remove.cc
index 770497a51..c5c28c7d9 100644
--- a/passes/equiv/equiv_remove.cc
+++ b/passes/equiv/equiv_remove.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct EquivRemovePass : public Pass {
 	EquivRemovePass() : Pass("equiv_remove", "remove $equiv cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -40,7 +40,7 @@ struct EquivRemovePass : public Pass {
 		log("        keep gate circuit\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		bool mode_gold = false;
 		bool mode_gate = false;
diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index e69e17ac6..c2fab26f2 100644
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -273,7 +273,7 @@ struct EquivSimpleWorker
 
 struct EquivSimplePass : public Pass {
 	EquivSimplePass() : Pass("equiv_simple", "try proving simple $equiv instances") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -298,7 +298,7 @@ struct EquivSimplePass : public Pass {
 		log("        the max. number of time steps to be considered (default = 1)\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		bool verbose = false, short_cones = false, model_undef = false, nogroup = false;
 		int success_counter = 0;
diff --git a/passes/equiv/equiv_status.cc b/passes/equiv/equiv_status.cc
index 7b9230b35..b4a93ccf5 100644
--- a/passes/equiv/equiv_status.cc
+++ b/passes/equiv/equiv_status.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct EquivStatusPass : public Pass {
 	EquivStatusPass() : Pass("equiv_status", "print status of equivalent checking module") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -36,7 +36,7 @@ struct EquivStatusPass : public Pass {
 		log("        produce an error if any unproven $equiv cell is found\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		bool assert_mode = false;
 		int unproven_count = 0;
diff --git a/passes/equiv/equiv_struct.cc b/passes/equiv/equiv_struct.cc
index c4ced6a71..a7973fd04 100644
--- a/passes/equiv/equiv_struct.cc
+++ b/passes/equiv/equiv_struct.cc
@@ -283,7 +283,7 @@ struct EquivStructWorker
 
 struct EquivStructPass : public Pass {
 	EquivStructPass() : Pass("equiv_struct", "structural equivalence checking") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -314,7 +314,7 @@ struct EquivStructPass : public Pass {
 		log("        maximum number of iterations to run before aborting\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		pool<IdString> fwonly_cells({ "$equiv" });
 		bool mode_icells = false;
diff --git a/passes/fsm/fsm.cc b/passes/fsm/fsm.cc
index 997558b85..c5cb338ab 100644
--- a/passes/fsm/fsm.cc
+++ b/passes/fsm/fsm.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct FsmPass : public Pass {
 	FsmPass() : Pass("fsm", "extract and optimize finite state machines") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -68,7 +68,7 @@ struct FsmPass : public Pass {
 		log("        passed through to fsm_recode pass\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_nomap = false;
 		bool flag_norecode = false;
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 9fb5446e7..fc504e98c 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -245,7 +245,7 @@ static void detect_fsm(RTLIL::Wire *wire)
 
 struct FsmDetectPass : public Pass {
 	FsmDetectPass() : Pass("fsm_detect", "finding FSMs in design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -261,7 +261,7 @@ struct FsmDetectPass : public Pass {
 		log("'fsm_encoding' attribute to \"none\".\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FSM_DETECT pass (finding FSMs in design).\n");
 		extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc
index 2c344a1c1..c34d0c15c 100644
--- a/passes/fsm/fsm_expand.cc
+++ b/passes/fsm/fsm_expand.cc
@@ -265,7 +265,7 @@ struct FsmExpand
 
 struct FsmExpandPass : public Pass {
 	FsmExpandPass() : Pass("fsm_expand", "expand FSM cells by merging logic into it") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -279,7 +279,7 @@ struct FsmExpandPass : public Pass {
 		log("word-wide cells. Call with -full to consider all cells for merging.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool full_mode = false;
 
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index 1cbfcfae8..8eb1872f0 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -120,7 +120,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
  */
 struct FsmExportPass : public Pass {
 	FsmExportPass() : Pass("fsm_export", "exporting FSMs to KISS2 files") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -143,7 +143,7 @@ struct FsmExportPass : public Pass {
 		log("        use binary state encoding as state names instead of s0, s1, ...\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
 		std::string arg;
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 8a4ee3f26..67551f673 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -401,7 +401,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 
 struct FsmExtractPass : public Pass {
 	FsmExtractPass() : Pass("fsm_extract", "extracting FSMs in design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -417,7 +417,7 @@ struct FsmExtractPass : public Pass {
 		log("'opt_clean' pass to eliminate this signal.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FSM_EXTRACT pass (extracting FSM from design).\n");
 		extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc
index 2cc1a7d53..0548259ee 100644
--- a/passes/fsm/fsm_info.cc
+++ b/passes/fsm/fsm_info.cc
@@ -30,7 +30,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct FsmInfoPass : public Pass {
 	FsmInfoPass() : Pass("fsm_info", "print information on finite state machines") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -41,7 +41,7 @@ struct FsmInfoPass : public Pass {
 		log("pass so that this information is included in the synthesis log file.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
 		extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc
index 3edaf84d2..90c958912 100644
--- a/passes/fsm/fsm_map.cc
+++ b/passes/fsm/fsm_map.cc
@@ -322,7 +322,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
 struct FsmMapPass : public Pass {
 	FsmMapPass() : Pass("fsm_map", "mapping FSMs to basic logic") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -331,7 +331,7 @@ struct FsmMapPass : public Pass {
 		log("This pass translates FSM cells to flip-flops and logic.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
 		extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 5b1da44fc..3a6ac2746 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -323,7 +323,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct FsmOptPass : public Pass {
 	FsmOptPass() : Pass("fsm_opt", "optimize finite state machines") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -334,7 +334,7 @@ struct FsmOptPass : public Pass {
 		log("combination with the 'opt_clean' pass (see also 'help fsm').\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
 		extra_args(args, 1, design);
diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc
index e1bde728f..fa1ff48cc 100644
--- a/passes/fsm/fsm_recode.cc
+++ b/passes/fsm/fsm_recode.cc
@@ -126,7 +126,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
 
 struct FsmRecodePass : public Pass {
 	FsmRecodePass() : Pass("fsm_recode", "recoding finite state machines") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -151,7 +151,7 @@ struct FsmRecodePass : public Pass {
 		log("            .map <old_bitpattern> <new_bitpattern>\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		FILE *fm_set_fsm_file = NULL;
 		FILE *encfile = NULL;
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index e61851481..5df69848e 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -343,7 +343,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 
 struct HierarchyPass : public Pass {
 	HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -414,7 +414,7 @@ struct HierarchyPass : public Pass {
 		log("in the current design.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
 
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index e9ee4eef9..ec242aa1f 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -269,7 +269,7 @@ struct SubmodWorker
 
 struct SubmodPass : public Pass {
 	SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -297,7 +297,7 @@ struct SubmodPass : public Pass {
 		log("with -copy to not modify the source module.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
 		log_push();
diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index 1da0870f6..c88ecd82e 100644
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct UniquifyPass : public Pass {
 	UniquifyPass() : Pass("uniquify", "create unique copies of modules") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -41,7 +41,7 @@ struct UniquifyPass : public Pass {
 		log("attribute set (the 'top' module is unique implicitly).\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");
 
diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index 947d598be..712bc2537 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct MemoryPass : public Pass {
 	MemoryPass() : Pass("memory", "translate memories to basic cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -48,7 +48,7 @@ struct MemoryPass : public Pass {
 		log("or multiport memory blocks if called with the -nomap option.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_nomap = false;
 		bool flag_nordff = false;
diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index a7f9cf382..e8552bbcf 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -1120,7 +1120,7 @@ void handle_cell(Cell *cell, const rules_t &rules)
 
 struct MemoryBramPass : public Pass {
 	MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1210,7 +1210,7 @@ struct MemoryBramPass : public Pass {
 		log("the data bits to accommodate the enable pattern of port A.\n");
 		log("\n");
 	}
-	virtual void execute(vector<string> args, Design *design)
+	void execute(vector<string> args, Design *design) YS_OVERRIDE
 	{
 		rules_t rules;
 
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index ab66e3fb8..70d98713c 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -246,7 +246,7 @@ static void handle_module(Design *design, Module *module)
 
 struct MemoryCollectPass : public Pass {
 	MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -256,7 +256,7 @@ struct MemoryCollectPass : public Pass {
 		log("memory cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		log_header(design, "Executing MEMORY_COLLECT pass (generating $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto &mod_it : design->modules_)
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 6e036397d..32df19174 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -283,7 +283,7 @@ struct MemoryDffWorker
 
 struct MemoryDffPass : public Pass {
 	MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -297,7 +297,7 @@ struct MemoryDffPass : public Pass {
 		log("        do not merge registers on read ports\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_wr_only = false;
 
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index bffeec857..a0b808e56 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -352,7 +352,7 @@ struct MemoryMapWorker
 
 struct MemoryMapPass : public Pass {
 	MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -362,7 +362,7 @@ struct MemoryMapPass : public Pass {
 		log("pass to word-wide DFFs and address decoders.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		log_header(design, "Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
 		extra_args(args, 1, design);
 		for (auto mod : design->selected_modules())
diff --git a/passes/memory/memory_memx.cc b/passes/memory/memory_memx.cc
index 2b02e2490..958370164 100644
--- a/passes/memory/memory_memx.cc
+++ b/passes/memory/memory_memx.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct MemoryMemxPass : public Pass {
 	MemoryMemxPass() : Pass("memory_memx", "emulate vlog sim behavior for mem ports") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -38,7 +38,7 @@ struct MemoryMemxPass : public Pass {
 		log("behavior for out-of-bounds memory reads and writes.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		log_header(design, "Executing MEMORY_MEMX pass (converting $mem cells to logic and flip-flops).\n");
 		extra_args(args, 1, design);
 
diff --git a/passes/memory/memory_nordff.cc b/passes/memory/memory_nordff.cc
index 87ab7c623..ba0361c0f 100644
--- a/passes/memory/memory_nordff.cc
+++ b/passes/memory/memory_nordff.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct MemoryNordffPass : public Pass {
 	MemoryNordffPass() : Pass("memory_nordff", "extract read port FFs from memories") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -35,7 +35,7 @@ struct MemoryNordffPass : public Pass {
 		log("similar to what one would get from calling memory_dff with -nordff.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing MEMORY_NORDFF pass (extracting $dff cells from $mem).\n");
 
diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index ca09ac52c..172afe0cb 100644
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -726,7 +726,7 @@ struct MemoryShareWorker
 
 struct MemorySharePass : public Pass {
 	MemorySharePass() : Pass("memory_share", "consolidate memory ports") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -752,7 +752,7 @@ struct MemorySharePass : public Pass {
 		log("optimizations) such as \"share\" and \"opt_merge\".\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		log_header(design, "Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).\n");
 		extra_args(args, 1, design);
 		for (auto module : design->selected_modules())
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index a0fc31b5e..49ec66792 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -127,7 +127,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module)
 
 struct MemoryUnpackPass : public Pass {
 	MemoryUnpackPass() : Pass("memory_unpack", "unpack multi-port memory cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -137,7 +137,7 @@ struct MemoryUnpackPass : public Pass {
 		log("$memwr cells. It is the counterpart to the memory_collect pass.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
 		log_header(design, "Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n");
 		extra_args(args, 1, design);
 		for (auto &mod_it : design->modules_)
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index 021c1a03f..a4aca2fee 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct OptPass : public Pass {
 	OptPass() : Pass("opt", "perform simple optimizations") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -63,7 +63,7 @@ struct OptPass : public Pass {
 		log("\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string opt_clean_args;
 		std::string opt_expr_args;
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 25d462ada..c3b13acaf 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -442,7 +442,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
 
 struct OptCleanPass : public Pass {
 	OptCleanPass() : Pass("opt_clean", "remove unused cells and wires") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -459,7 +459,7 @@ struct OptCleanPass : public Pass {
 		log("        also remove internal nets if they have a public name\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool purge_mode = false;
 
@@ -505,7 +505,7 @@ struct OptCleanPass : public Pass {
 
 struct CleanPass : public Pass {
 	CleanPass() : Pass("clean", "remove unused cells and wires") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -520,7 +520,7 @@ struct CleanPass : public Pass {
 		log("in -purge mode between the commands.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool purge_mode = false;
 
diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
index f2af1cb93..1699a6454 100644
--- a/passes/opt/opt_demorgan.cc
+++ b/passes/opt/opt_demorgan.cc
@@ -169,7 +169,7 @@ void demorgan_worker(
 
 struct OptDemorganPass : public Pass {
 	OptDemorganPass() : Pass("opt_demorgan", "Optimize reductions with DeMorgan equivalents") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -179,7 +179,7 @@ struct OptDemorganPass : public Pass {
 		log("overall gate count of the circuit\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
 
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index a54a5c6b8..0ba233c62 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1470,7 +1470,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 struct OptExprPass : public Pass {
 	OptExprPass() : Pass("opt_expr", "perform const folding and simple expression rewriting") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1504,7 +1504,7 @@ struct OptExprPass : public Pass {
 		log("        replaced by 'a'. the -keepdc option disables all such optimizations.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool mux_undef = false;
 		bool mux_bool = false;
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 2aeb514e4..eedf88904 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -341,7 +341,7 @@ struct OptMergeWorker
 
 struct OptMergePass : public Pass {
 	OptMergePass() : Pass("opt_merge", "consolidate identical cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -357,7 +357,7 @@ struct OptMergePass : public Pass {
 		log("        Operate on all cell types, not just built-in types.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing OPT_MERGE pass (detect identical cells).\n");
 
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index f5ddc2af9..87c7ce9b2 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -449,7 +449,7 @@ struct OptMuxtreeWorker
 
 struct OptMuxtreePass : public Pass {
 	OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -462,7 +462,7 @@ struct OptMuxtreePass : public Pass {
 		log("This pass only operates on completely selected modules without processes.\n");
 		log("\n");
 	}
-	virtual void execute(vector<std::string> args, RTLIL::Design *design)
+	void execute(vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
 		extra_args(args, 1, design);
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index eb9d02ad5..d99f1ca6a 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -329,7 +329,7 @@ struct OptReduceWorker
 
 struct OptReducePass : public Pass {
 	OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -350,7 +350,7 @@ struct OptReducePass : public Pass {
 		log("      alias for -fine\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool do_fine = false;
 
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index b5edb357b..5880254c1 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -399,7 +399,7 @@ delete_dff:
 
 struct OptRmdffPass : public Pass {
 	OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -409,7 +409,7 @@ struct OptRmdffPass : public Pass {
 		log("a constant driver.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		int total_count = 0, total_initdrv = 0;
 		log_header(design, "Executing OPT_RMDFF pass (remove dff with constant values).\n");
diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
index 756be7473..fc1596ebf 100644
--- a/passes/opt/rmports.cc
+++ b/passes/opt/rmports.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct RmportsPassPass : public Pass {
 	RmportsPassPass() : Pass("rmports", "remove module ports with no connections") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -39,7 +39,7 @@ struct RmportsPassPass : public Pass {
 		log("\n");
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
 
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 22914eaa7..b80280829 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -1421,7 +1421,7 @@ struct ShareWorker
 
 struct SharePass : public Pass {
 	SharePass() : Pass("share", "perform sat-based resource sharing") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1453,7 +1453,7 @@ struct SharePass : public Pass {
 		log("    Only perform the first N merges, then stop. This is useful for debugging.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		ShareWorkerConfig config;
 
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 07503fbb3..0164f58d6 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -353,7 +353,7 @@ struct WreduceWorker
 
 struct WreducePass : public Pass {
 	WreducePass() : Pass("wreduce", "reduce the word size of operations if possible") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -373,7 +373,7 @@ struct WreducePass : public Pass {
 		log("        flows that use the 'memory_memx' pass.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, Design *design)
+	void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
 	{
 		WreduceConfig config;
 		bool opt_memx = false;
diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc
index d5366f266..ef7cb0f71 100644
--- a/passes/proc/proc.cc
+++ b/passes/proc/proc.cc
@@ -27,7 +27,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ProcPass : public Pass {
 	ProcPass() : Pass("proc", "translate processes to netlists") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -57,7 +57,7 @@ struct ProcPass : public Pass {
 		log("        executed in -ifx mode.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string global_arst;
 		bool ifxmode = false;
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index 216b00ddd..b69eba3f9 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -203,7 +203,7 @@ restart_proc_arst:
 
 struct ProcArstPass : public Pass {
 	ProcArstPass() : Pass("proc_arst", "detect asynchronous resets") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -221,7 +221,7 @@ struct ProcArstPass : public Pass {
 		log("        in the 'init' attribute on the net.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string global_arst;
 		bool global_arst_neg = false;
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 7dbabc211..b9e43d1db 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -143,7 +143,7 @@ void proc_clean(RTLIL::Module *mod, RTLIL::Process *proc, int &total_count)
 
 struct ProcCleanPass : public Pass {
 	ProcCleanPass() : Pass("proc_clean", "remove empty parts of processes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -153,7 +153,7 @@ struct ProcCleanPass : public Pass {
 		log("if it contains only empty structures.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		int total_count = 0;
 		log_header(design, "Executing PROC_CLEAN pass (remove empty switches from decision trees).\n");
diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc
index f732baa17..519d35cd6 100644
--- a/passes/proc/proc_dff.cc
+++ b/passes/proc/proc_dff.cc
@@ -370,7 +370,7 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
 
 struct ProcDffPass : public Pass {
 	ProcDffPass() : Pass("proc_dff", "extract flip-flops from processes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -380,7 +380,7 @@ struct ProcDffPass : public Pass {
 		log("d-type flip-flop cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing PROC_DFF pass (convert process syncs to FFs).\n");
 
diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc
index 15200ec12..d9d5dfbed 100644
--- a/passes/proc/proc_dlatch.cc
+++ b/passes/proc/proc_dlatch.cc
@@ -422,7 +422,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
 
 struct ProcDlatchPass : public Pass {
 	ProcDlatchPass() : Pass("proc_dlatch", "extract latches from processes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -432,7 +432,7 @@ struct ProcDlatchPass : public Pass {
 		log("d-type latches.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
 
diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc
index 0c8fb83dc..e2dc07e53 100644
--- a/passes/proc/proc_init.cc
+++ b/passes/proc/proc_init.cc
@@ -102,7 +102,7 @@ void proc_init(RTLIL::Module *mod, RTLIL::Process *proc)
 
 struct ProcInitPass : public Pass {
 	ProcInitPass() : Pass("proc_init", "convert initial block to init attributes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -113,7 +113,7 @@ struct ProcInitPass : public Pass {
 		log("respective wire.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing PROC_INIT pass (extract init attributes).\n");
 
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 57e131ca5..1329c1fef 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -382,7 +382,7 @@ void proc_mux(RTLIL::Module *mod, RTLIL::Process *proc, bool ifxmode)
 
 struct ProcMuxPass : public Pass {
 	ProcMuxPass() : Pass("proc_mux", "convert decision trees to multiplexers") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -396,7 +396,7 @@ struct ProcMuxPass : public Pass {
 		log("        'case' expressions and 'if' conditions.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool ifxmode = false;
 		log_header(design, "Executing PROC_MUX pass (convert decision trees to multiplexers).\n");
diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc
index 5672fb475..7c334e661 100644
--- a/passes/proc/proc_rmdead.cc
+++ b/passes/proc/proc_rmdead.cc
@@ -65,7 +65,7 @@ void proc_rmdead(RTLIL::SwitchRule *sw, int &counter)
 
 struct ProcRmdeadPass : public Pass {
 	ProcRmdeadPass() : Pass("proc_rmdead", "eliminate dead trees in decision trees") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -74,7 +74,7 @@ struct ProcRmdeadPass : public Pass {
 		log("This pass identifies unreachable branches in decision trees and removes them.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing PROC_RMDEAD pass (remove dead branches from decision trees).\n");
 
diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc
index 63a907671..509cb0ba9 100644
--- a/passes/sat/assertpmux.cc
+++ b/passes/sat/assertpmux.cc
@@ -181,7 +181,7 @@ struct AssertpmuxWorker
 
 struct AssertpmuxPass : public Pass {
 	AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -199,7 +199,7 @@ struct AssertpmuxPass : public Pass {
 		log("        additional constrained and check the $pmux condition always.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_noinit = false;
 		bool flag_always = false;
diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index 85933acc2..c92db7118 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Async2syncPass : public Pass {
 	Async2syncPass() : Pass("async2sync", "convert async FF inputs to sync circuits") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -42,7 +42,7 @@ struct Async2syncPass : public Pass {
 		log("Currently only $adff cells are supported by this pass.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		// bool flag_noinit = false;
 
diff --git a/passes/sat/clk2fflogic.cc b/passes/sat/clk2fflogic.cc
index 736c6f571..49ec795d3 100644
--- a/passes/sat/clk2fflogic.cc
+++ b/passes/sat/clk2fflogic.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Clk2fflogicPass : public Pass {
 	Clk2fflogicPass() : Pass("clk2fflogic", "convert clocked FFs to generic $ff cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -36,7 +36,7 @@ struct Clk2fflogicPass : public Pass {
 		log("multiple clocks.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		// bool flag_noinit = false;
 
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 09f69cc5c..008cd2dfa 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -360,7 +360,7 @@ struct VlogHammerReporter
 
 struct EvalPass : public Pass {
 	EvalPass() : Pass("eval", "evaluate the circuit given an input") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -383,7 +383,7 @@ struct EvalPass : public Pass {
 		log("        then all output ports of the current module are used.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::vector<std::pair<std::string, std::string>> sets;
 		std::vector<std::string> shows, tables;
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index fa8f0c6be..809345486 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -220,7 +220,7 @@ RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width
 
 struct ExposePass : public Pass {
 	ExposePass() : Pass("expose", "convert internal signals to module ports") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -257,7 +257,7 @@ struct ExposePass : public Pass {
 		log("        designator for the exposed signal.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool flag_shared = false;
 		bool flag_evert = false;
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index a3028bfce..f29631639 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -760,7 +760,7 @@ struct FreduceWorker
 
 struct FreducePass : public Pass {
 	FreducePass() : Pass("freduce", "perform functional reduction") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -791,7 +791,7 @@ struct FreducePass : public Pass {
 		log("circuit that is analyzed.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		reduce_counter = 0;
 		reduce_stop_at = 0;
diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index 9e150b60c..d37f1b126 100644
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -358,7 +358,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
 
 struct MiterPass : public Pass {
 	MiterPass() : Pass("miter", "automatically create a miter circuit") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -402,7 +402,7 @@ struct MiterPass : public Pass {
 		log("        call 'flatten; opt_expr -keepdc -undriven;;' on the miter circuit.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		if (args.size() > 1 && args[1] == "-equiv") {
 			create_miter_equiv(this, args, design);
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 6c0834deb..695a03e15 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -890,7 +890,7 @@ void print_qed()
 
 struct SatPass : public Pass {
 	SatPass() : Pass("sat", "solve a SAT problem in the circuit") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1057,7 +1057,7 @@ struct SatPass : public Pass {
 		log("        Like -falsify but do not return an error for timeouts.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::vector<std::pair<std::string, std::string>> sets, sets_init, prove, prove_x;
 		std::map<int, std::vector<std::pair<std::string, std::string>>> sets_at;
diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index b49c12529..fadffcdbc 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -745,7 +745,7 @@ struct SimWorker : SimShared
 
 struct SimPass : public Pass {
 	SimPass() : Pass("sim", "simulate the circuit") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -787,7 +787,7 @@ struct SimPass : public Pass {
 		log("        enable debug output\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		SimWorker worker;
 		int numcycles = 20;
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 18868c6d7..d2d15a4a9 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1248,7 +1248,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 struct AbcPass : public Pass {
 	AbcPass() : Pass("abc", "use ABC for technology mapping") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1420,7 +1420,7 @@ struct AbcPass : public Pass {
 		log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
 		log_push();
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index b9ac7aded..35df2ff79 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct AigmapPass : public Pass {
 	AigmapPass() : Pass("aigmap", "map logic to and-inverter-graph circuit") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    aigmap [options] [selection]\n");
@@ -37,7 +37,7 @@ struct AigmapPass : public Pass {
 		log("        Enable creation of $_NAND_ cells\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool nand_mode = false;
 
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 95be7ab3b..dc7d416b0 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -539,7 +539,7 @@ struct AlumaccWorker
 
 struct AlumaccPass : public Pass {
 	AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -549,7 +549,7 @@ struct AlumaccPass : public Pass {
 		log("and $macc cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
 
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
index dec81d216..0b5576b06 100644
--- a/passes/techmap/attrmap.cc
+++ b/passes/techmap/attrmap.cc
@@ -81,7 +81,7 @@ struct AttrmapAction {
 
 struct AttrmapTocase : AttrmapAction {
 	string name;
-	virtual bool apply(IdString &id, Const&) {
+	bool apply(IdString &id, Const&) YS_OVERRIDE {
 		if (match_name(name, id, true))
 			id = RTLIL::escape_id(name);
 		return true;
@@ -90,7 +90,7 @@ struct AttrmapTocase : AttrmapAction {
 
 struct AttrmapRename : AttrmapAction {
 	string old_name, new_name;
-	virtual bool apply(IdString &id, Const&) {
+	bool apply(IdString &id, Const&) YS_OVERRIDE {
 		if (match_name(old_name, id))
 			id = RTLIL::escape_id(new_name);
 		return true;
@@ -101,7 +101,7 @@ struct AttrmapMap : AttrmapAction {
 	bool imap;
 	string old_name, new_name;
 	string old_value, new_value;
-	virtual bool apply(IdString &id, Const &val) {
+	bool apply(IdString &id, Const &val) YS_OVERRIDE {
 		if (match_name(old_name, id) && match_value(old_value, val, true)) {
 			id = RTLIL::escape_id(new_name);
 			val = make_value(new_value);
@@ -112,7 +112,7 @@ struct AttrmapMap : AttrmapAction {
 
 struct AttrmapRemove : AttrmapAction {
 	string name, value;
-	virtual bool apply(IdString &id, Const &val) {
+	bool apply(IdString &id, Const &val) YS_OVERRIDE {
 		return !(match_name(name, id) && match_value(value, val));
 	}
 };
@@ -144,7 +144,7 @@ void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actio
 
 struct AttrmapPass : public Pass {
 	AttrmapPass() : Pass("attrmap", "renaming attributes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -179,7 +179,7 @@ struct AttrmapPass : public Pass {
 		log("            -imap keep=\"false\" keep=0 -remove keep=0\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n");
 
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
index 1537def00..e59aa6518 100644
--- a/passes/techmap/attrmvcp.cc
+++ b/passes/techmap/attrmvcp.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct AttrmvcpPass : public Pass {
 	AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    attrmvcp [options] [selection]\n");
@@ -53,7 +53,7 @@ struct AttrmvcpPass : public Pass {
 		log("        multiple times.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
 
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 0b8fd5246..9f0c7bf67 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct DeminoutPass : public Pass {
 	DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    deminout [options] [selection]\n");
@@ -33,7 +33,7 @@ struct DeminoutPass : public Pass {
 		log("\"Demote\" inout ports to input or output ports, if possible.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n");
 
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 4d515f174..3291f5a4a 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -253,7 +253,7 @@ struct Dff2dffeWorker
 
 struct Dff2dffePass : public Pass {
 	Dff2dffePass() : Pass("dff2dffe", "transform $dff cells to $dffe cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -284,7 +284,7 @@ struct Dff2dffePass : public Pass {
 		log("        $_DFFE_[NP]_.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
 
diff --git a/passes/techmap/dff2dffs.cc b/passes/techmap/dff2dffs.cc
index 0bfbdc965..39a4f6ade 100644
--- a/passes/techmap/dff2dffs.cc
+++ b/passes/techmap/dff2dffs.cc
@@ -26,7 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Dff2dffsPass : public Pass {
 	Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    dff2dffs [options] [selection]\n");
@@ -35,7 +35,7 @@ struct Dff2dffsPass : public Pass {
 		log("dff2dffe for SR over CE priority.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");
 
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 6a8a86383..a8eecc970 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct DffinitPass : public Pass {
 	DffinitPass() : Pass("dffinit", "set INIT param on FF cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -44,7 +44,7 @@ struct DffinitPass : public Pass {
 		log("        mode.)\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
 
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 5ccb770c4..416ed2bd5 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -537,7 +537,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module, bool prepare
 
 struct DfflibmapPass : public Pass {
 	DfflibmapPass() : Pass("dfflibmap", "technology mapping of flip-flops") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    dfflibmap [-prepare] -liberty <file> [selection]\n");
@@ -553,7 +553,7 @@ struct DfflibmapPass : public Pass {
 		log("liberty file.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
 
diff --git a/passes/techmap/dffsr2dff.cc b/passes/techmap/dffsr2dff.cc
index 0d4d53627..086a1d2fa 100644
--- a/passes/techmap/dffsr2dff.cc
+++ b/passes/techmap/dffsr2dff.cc
@@ -176,7 +176,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
 
 struct Dffsr2dffPass : public Pass {
 	Dffsr2dffPass() : Pass("dffsr2dff", "convert DFFSR cells to simpler FF cell types") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -186,7 +186,7 @@ struct Dffsr2dffPass : public Pass {
 		log("$_DFF_???_) to simpler FF cell types when any of the set/reset inputs is unused.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
 
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 71e29c60b..fff90f13c 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -352,7 +352,7 @@ bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
 
 struct ExtractPass : public Pass {
 	ExtractPass() : Pass("extract", "find subcircuits and replace them with cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -440,7 +440,7 @@ struct ExtractPass : public Pass {
 		log("See 'help techmap' for a pass that does the opposite thing.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
 		log_push();
diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc
index af0eb852a..a8d0bc834 100644
--- a/passes/techmap/extract_counter.cc
+++ b/passes/techmap/extract_counter.cc
@@ -559,7 +559,7 @@ void counter_worker(
 
 struct ExtractCounterPass : public Pass {
 	ExtractCounterPass() : Pass("extract_counter", "Extract GreenPak4 counter cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -578,7 +578,7 @@ struct ExtractCounterPass : public Pass {
 		log("\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n");
 
diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc
index a68cc5e2e..9e6dc0d24 100644
--- a/passes/techmap/extract_fa.cc
+++ b/passes/techmap/extract_fa.cc
@@ -531,7 +531,7 @@ struct ExtractFaWorker
 
 struct ExtractFaPass : public Pass {
 	ExtractFaPass() : Pass("extract_fa", "find and extract full/half adders") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -553,7 +553,7 @@ struct ExtractFaPass : public Pass {
 		log("        Verbose output\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		ExtractFaConfig config;
 
diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index cc21c8665..519cad55c 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -33,7 +33,7 @@ struct ExtractReducePass : public Pass
 
 	ExtractReducePass() : Pass("extract_reduce", "converts gate chains into $reduce_* cells") { }
 
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -62,7 +62,7 @@ struct ExtractReducePass : public Pass
 				(cell->type == "$_XOR_" && gt == GateType::Xor);
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing EXTRACT_REDUCE pass.\n");
 		log_push();
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index 82cecac26..9ec651aef 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -55,7 +55,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
 
 struct HilomapPass : public Pass {
 	HilomapPass() : Pass("hilomap", "technology mapping of constant hi- and/or lo-drivers") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    hilomap [options] [selection]\n");
@@ -74,7 +74,7 @@ struct HilomapPass : public Pass {
 		log("        each constant bit.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
 
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
index aa81468dc..2173049b4 100644
--- a/passes/techmap/insbuf.cc
+++ b/passes/techmap/insbuf.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct InsbufPass : public Pass {
 	InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    insbuf [options] [selection]\n");
@@ -37,7 +37,7 @@ struct InsbufPass : public Pass {
 		log("        call to \"clean\" will remove all $_BUF_ in the design.)\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
 
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 690ba87ed..efcc082d5 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -34,7 +34,7 @@ void split_portname_pair(std::string &port1, std::string &port2)
 
 struct IopadmapPass : public Pass {
 	IopadmapPass() : Pass("iopadmap", "technology mapping of i/o pads (or buffers)") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    iopadmap [options] [selection]\n");
@@ -78,7 +78,7 @@ struct IopadmapPass : public Pass {
 		log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
 
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index 2bb0bd8b4..d32bbff14 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -56,7 +56,7 @@ int lut2mux(Cell *cell)
 
 struct Lut2muxPass : public Pass {
 	Lut2muxPass() : Pass("lut2mux", "convert $lut to $_MUX_") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -65,7 +65,7 @@ struct Lut2muxPass : public Pass {
 		log("This pass converts $lut cells to $_MUX_ gates.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
 
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index 32569d076..3e8e59e6b 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -365,7 +365,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct MaccmapPass : public Pass {
 	MaccmapPass() : Pass("maccmap", "mapping macc cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -375,7 +375,7 @@ struct MaccmapPass : public Pass {
 		log("is used then the $macc cell is mapped to $add, $sub, etc. cells instead.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool unmap_mode = false;
 
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 1dc649587..12da9ed0c 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -561,7 +561,7 @@ struct MuxcoverWorker
 
 struct MuxcoverPass : public Pass {
 	MuxcoverPass() : Pass("muxcover", "cover trees of MUX cells with wider MUXes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -579,7 +579,7 @@ struct MuxcoverPass : public Pass {
 		log("        less efficient than the original circuit.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n");
 
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc
index f1a41cc3e..cc765d89c 100644
--- a/passes/techmap/nlutmap.cc
+++ b/passes/techmap/nlutmap.cc
@@ -129,7 +129,7 @@ struct NlutmapWorker
 
 struct NlutmapPass : public Pass {
 	NlutmapPass() : Pass("nlutmap", "map to LUTs of different sizes") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -149,7 +149,7 @@ struct NlutmapPass : public Pass {
 		log("to generic logic gates ($_AND_, etc.).\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		NlutmapConfig config;
 
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc
index c626dbcc5..b7a22dc3b 100644
--- a/passes/techmap/pmuxtree.cc
+++ b/passes/techmap/pmuxtree.cc
@@ -67,7 +67,7 @@ static SigSpec recursive_mux_generator(Module *module, const SigSpec &sig_data,
 
 struct PmuxtreePass : public Pass {
 	PmuxtreePass() : Pass("pmuxtree", "transform $pmux cells to trees of $mux cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -76,7 +76,7 @@ struct PmuxtreePass : public Pass {
 		log("This pass transforms $pmux cells to a trees of $mux cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing PMUXTREE pass.\n");
 
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 6936b499e..f20863ba0 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -391,7 +391,7 @@ struct ShregmapWorker
 
 struct ShregmapPass : public Pass {
 	ShregmapPass() : Pass("shregmap", "map shift registers") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -449,7 +449,7 @@ struct ShregmapPass : public Pass {
 		log("        map to greenpak4 shift registers.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		ShregmapOptions opts;
 		string clkpol, enpol;
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index c6b932bdc..660b60601 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -575,7 +575,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct SimplemapPass : public Pass {
 	SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -590,7 +590,7 @@ struct SimplemapPass : public Pass {
 		log("  $sr, $ff, $dff, $dffsr, $adff, $dlatch\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 		extra_args(args, 1, design);
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1908ae8b5..d0e5e2236 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -891,7 +891,7 @@ struct TechmapWorker
 
 struct TechmapPass : public Pass {
 	TechmapPass() : Pass("techmap", "generic technology mapper") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1022,7 +1022,7 @@ struct TechmapPass : public Pass {
 		log("essentially techmap but using the design itself as map library).\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
 		log_push();
@@ -1141,7 +1141,7 @@ struct TechmapPass : public Pass {
 
 struct FlattenPass : public Pass {
 	FlattenPass() : Pass("flatten", "flatten design") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -1155,7 +1155,7 @@ struct FlattenPass : public Pass {
 		log("flattened by this command.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing FLATTEN pass (flatten design).\n");
 		log_push();
diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc
index 03629082c..587cb9038 100644
--- a/passes/techmap/tribuf.cc
+++ b/passes/techmap/tribuf.cc
@@ -139,7 +139,7 @@ struct TribufWorker {
 
 struct TribufPass : public Pass {
 	TribufPass() : Pass("tribuf", "infer tri-state buffers") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -156,7 +156,7 @@ struct TribufPass : public Pass {
 		log("        to non-tristate logic. this option implies -merge.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		TribufConfig config;
 
diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index a577e1235..b46147fb9 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ZinitPass : public Pass {
 	ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -37,7 +37,7 @@ struct ZinitPass : public Pass {
 		log("        also add zero initialization to uninitialized FFs\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		bool all_mode = false;
 
diff --git a/passes/tests/test_abcloop.cc b/passes/tests/test_abcloop.cc
index 09cb41954..5d5466afe 100644
--- a/passes/tests/test_abcloop.cc
+++ b/passes/tests/test_abcloop.cc
@@ -244,7 +244,7 @@ static void test_abcloop()
 
 struct TestAbcloopPass : public Pass {
 	TestAbcloopPass() : Pass("test_abcloop", "automatically test handling of loops in abc command") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -259,7 +259,7 @@ struct TestAbcloopPass : public Pass {
 		log("        use this value as rng seed value (default = unix time).\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		int num_iter = 100;
 		xorshift32_state = 0;
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index cb31056f4..bfb1d6642 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -324,7 +324,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter, int s
 
 struct TestAutotbBackend : public Backend {
 	TestAutotbBackend() : Backend("=test_autotb", "generate simple test benches") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -349,7 +349,7 @@ struct TestAutotbBackend : public Backend {
 		log("        number of iterations the test bench should run (default = 1000)\n");
 		log("\n");
 	}
-	virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		int num_iter = 1000;
 		int seed = 0;
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index 47b6bdf23..e360b5edb 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -652,7 +652,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, bool nosat, std::
 
 struct TestCellPass : public Pass {
 	TestCellPass() : Pass("test_cell", "automatically test the implementation of a cell type") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -712,7 +712,7 @@ struct TestCellPass : public Pass {
 		log("        create a Verilog test bench to test simlib and write_verilog\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design*)
+	void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE
 	{
 		int num_iter = 100;
 		std::string techmap_cmd = "techmap -assert";
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 7f4503070..92b10781d 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 struct SynthAchronixPass : public ScriptPass {
   SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Acrhonix Speedster22i FPGAs.") { }
 
-  virtual void help() YS_OVERRIDE
+  void help() YS_OVERRIDE
   {
     //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
     log("\n");
@@ -63,7 +63,7 @@ struct SynthAchronixPass : public ScriptPass {
   string top_opt, family_opt, vout_file;
   bool retime, flatten;
 
-  virtual void clear_flags() YS_OVERRIDE
+  void clear_flags() YS_OVERRIDE
   {
     top_opt = "-auto-top";
     vout_file = "";
@@ -71,7 +71,7 @@ struct SynthAchronixPass : public ScriptPass {
     flatten = true;
   }
 
-  virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+  void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
   {
     string run_from, run_to;
     clear_flags();
@@ -118,7 +118,7 @@ struct SynthAchronixPass : public ScriptPass {
     log_pop();
   }
 
-  virtual void script() YS_OVERRIDE
+  void script() YS_OVERRIDE
   {
     if (check_label("begin"))
       {
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index cc977f97e..897f37dbb 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -29,7 +29,7 @@ struct PrepPass : public ScriptPass
 {
 	PrepPass() : ScriptPass("prep", "generic synthesis script") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -81,7 +81,7 @@ struct PrepPass : public ScriptPass
 	string top_module, fsm_opts;
 	bool autotop, flatten, ifxmode, memxmode, nomemmode, nokeepdc, nordff;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_module.clear();
 
@@ -94,7 +94,7 @@ struct PrepPass : public ScriptPass
 		nordff = true;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 
@@ -163,7 +163,7 @@ struct PrepPass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 
 		if (check_label("begin"))
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 4ca34839e..efb214759 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -29,7 +29,7 @@ struct SynthPass : public ScriptPass
 {
 	SynthPass() : ScriptPass("synth", "generic synthesis script") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -81,7 +81,7 @@ struct SynthPass : public ScriptPass
 	string top_module, fsm_opts, memory_opts;
 	bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_module.clear();
 		fsm_opts.clear();
@@ -95,7 +95,7 @@ struct SynthPass : public ScriptPass
 		noshare = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -165,7 +165,7 @@ struct SynthPass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 431e0a127..48da0d8ad 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Coolrunner2SopPass : public Pass {
 	Coolrunner2SopPass() : Pass("coolrunner2_sop", "break $sop cells into ANDTERM/ORTERM cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    coolrunner2_sop [options] [selection]\n");
@@ -33,7 +33,7 @@ struct Coolrunner2SopPass : public Pass {
 		log("Break $sop cells into ANDTERM/ORTERM cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing COOLRUNNER2_SOP pass (break $sop cells into ANDTERM/ORTERM cells).\n");
 		extra_args(args, 1, design);
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 2e94c3449..a5dac3566 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -29,7 +29,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 {
 	SynthCoolrunner2Pass() : ScriptPass("synth_coolrunner2", "synthesis for Xilinx Coolrunner-II CPLDs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -66,7 +66,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 	string top_opt, json_file;
 	bool flatten, retime;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		json_file = "";
@@ -74,7 +74,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		retime = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -121,7 +121,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index e17138f3a..b5ed93be4 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -29,7 +29,7 @@ struct SynthEasicPass : public ScriptPass
 {
 	SynthEasicPass() : ScriptPass("synth_easic", "synthesis for eASIC platform") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -67,7 +67,7 @@ struct SynthEasicPass : public ScriptPass
 	string top_opt, vlog_file, etools_path;
 	bool flatten, retime;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		vlog_file = "";
@@ -76,7 +76,7 @@ struct SynthEasicPass : public ScriptPass
 		retime = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -127,7 +127,7 @@ struct SynthEasicPass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		string phys_clk_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_phys_clk_0v893ff125c.lib", etools_path.c_str());
 		string logic_lut_lib = stringf("%s/data_ruby28/design_libs/logical/timing/gp/n3x_logic_lut_0v893ff125c.lib", etools_path.c_str());
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 76051d1a2..a13dd8d41 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -30,7 +30,7 @@ struct SynthEcp5Pass : public ScriptPass
 {
 	SynthEcp5Pass() : ScriptPass("synth_ecp5", "synthesis for ECP5 FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -95,7 +95,7 @@ struct SynthEcp5Pass : public ScriptPass
 	string top_opt, blif_file, edif_file, json_file;
 	bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		blif_file = "";
@@ -112,7 +112,7 @@ struct SynthEcp5Pass : public ScriptPass
 		vpr = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -199,7 +199,7 @@ struct SynthEcp5Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 44dec265d..793f345be 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -29,7 +29,7 @@ struct SynthGowinPass : public ScriptPass
 {
 	SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -61,14 +61,14 @@ struct SynthGowinPass : public ScriptPass
 	string top_opt, vout_file;
 	bool retime;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		vout_file = "";
 		retime = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -111,7 +111,7 @@ struct SynthGowinPass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
diff --git a/techlibs/greenpak4/greenpak4_dffinv.cc b/techlibs/greenpak4/greenpak4_dffinv.cc
index 7d9d7d5b0..d57e978a0 100644
--- a/techlibs/greenpak4/greenpak4_dffinv.cc
+++ b/techlibs/greenpak4/greenpak4_dffinv.cc
@@ -91,7 +91,7 @@ void invert_gp_dff(Cell *cell, bool invert_input)
 
 struct Greenpak4DffInvPass : public Pass {
 	Greenpak4DffInvPass() : Pass("greenpak4_dffinv", "merge greenpak4 inverters and DFF/latches") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    greenpak4_dffinv [options] [selection]\n");
@@ -99,7 +99,7 @@ struct Greenpak4DffInvPass : public Pass {
 		log("Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing GREENPAK4_DFFINV pass (merge input/output inverters into FF/latch cells).\n");
 
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 5e0e9e5d5..b91d5273a 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 {
 	SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 	string top_opt, part, json_file;
 	bool flatten, retime;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		part = "SLG46621V";
@@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		retime = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
diff --git a/techlibs/ice40/ice40_ffinit.cc b/techlibs/ice40/ice40_ffinit.cc
index c914b20e8..3089d8932 100644
--- a/techlibs/ice40/ice40_ffinit.cc
+++ b/techlibs/ice40/ice40_ffinit.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Ice40FfinitPass : public Pass {
 	Ice40FfinitPass() : Pass("ice40_ffinit", "iCE40: handle FF init values") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -35,7 +35,7 @@ struct Ice40FfinitPass : public Pass {
 		log("nonzero init values.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ICE40_FFINIT pass (implement FF init values).\n");
 
diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 9afbc0fce..668df09dd 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -25,7 +25,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct Ice40FfssrPass : public Pass {
 	Ice40FfssrPass() : Pass("ice40_ffssr", "iCE40: merge synchronous set/reset into FF cells") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		log("\n");
 		log("    ice40_ffssr [options] [selection]\n");
@@ -33,7 +33,7 @@ struct Ice40FfssrPass : public Pass {
 		log("Merge synchronous set/reset $_MUX_ cells into iCE40 FFs.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).\n");
 
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 7af60f297..162740059 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -136,7 +136,7 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
 
 struct Ice40OptPass : public Pass {
 	Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { }
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -156,7 +156,7 @@ struct Ice40OptPass : public Pass {
 		log("mapped SB_LUT4 cells back to logic.\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string opt_expr_args = "-mux_undef -undriven";
 		bool unlut_mode = false;
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index abd890a56..b0687e5e3 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -29,7 +29,7 @@ struct SynthIce40Pass : public ScriptPass
 {
 	SynthIce40Pass() : ScriptPass("synth_ice40", "synthesis for iCE40 FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -88,7 +88,7 @@ struct SynthIce40Pass : public ScriptPass
 	string top_opt, blif_file, edif_file, json_file;
 	bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		blif_file = "";
@@ -103,7 +103,7 @@ struct SynthIce40Pass : public ScriptPass
 		vpr = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -182,7 +182,7 @@ struct SynthIce40Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index c51949bd4..d74f295ec 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -28,7 +28,7 @@ PRIVATE_NAMESPACE_BEGIN
 struct SynthIntelPass : public ScriptPass {
   SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { }
 
-  virtual void help() YS_OVERRIDE
+  void help() YS_OVERRIDE
   {
     //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
     log("\n");
@@ -79,7 +79,7 @@ struct SynthIntelPass : public ScriptPass {
   string top_opt, family_opt, vout_file, blif_file;
   bool retime, flatten, nobram, noiopads;
 
-  virtual void clear_flags() YS_OVERRIDE
+  void clear_flags() YS_OVERRIDE
   {
     top_opt = "-auto-top";
     family_opt = "max10";
@@ -91,7 +91,7 @@ struct SynthIntelPass : public ScriptPass {
     noiopads = false;
   }
 
-  virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+  void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
   {
     string run_from, run_to;
     clear_flags();
@@ -156,7 +156,7 @@ struct SynthIntelPass : public ScriptPass {
     log_pop();
   }
 
-  virtual void script() YS_OVERRIDE
+  void script() YS_OVERRIDE
   {
     if (check_label("begin"))
       {
@@ -255,7 +255,7 @@ struct SynthIntelPass : public ScriptPass {
           run(stringf("write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ %s",
                       help_mode ? "<file-name>" : vout_file.c_str()));
       }
-    
+
     if (check_label("vpr"))
       {
         if (!blif_file.empty() || help_mode)
@@ -264,7 +264,7 @@ struct SynthIntelPass : public ScriptPass {
             run(stringf("write_blif %s", help_mode ? "<file-name>" : blif_file.c_str()));
           }
       }
-  }       
+  }
 } SynthIntelPass;
 
 PRIVATE_NAMESPACE_END
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 1bc61daef..590fe61d2 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -38,7 +38,7 @@ struct SynthXilinxPass : public Pass
 {
 	SynthXilinxPass() : Pass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
 
-	virtual void help()
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -128,7 +128,7 @@ struct SynthXilinxPass : public Pass
 		log("        write_blif <file-name>\n");
 		log("\n");
 	}
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string top_opt = "-auto-top";
 		std::string edif_file;

From ab700ef215d7e6fd70c7b24de17f46b80de09c9f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Jul 2018 14:28:45 +0200
Subject: [PATCH 042/528] Add missing -lz to MXE build

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 11803ec0a..2090a083a 100644
--- a/Makefile
+++ b/Makefile
@@ -276,7 +276,7 @@ endif
 
 ifeq ($(CONFIG),mxe)
 CXXFLAGS += -DYOSYS_ENABLE_TCL
-LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32
+LDLIBS += -ltcl86 -lwsock32 -lws2_32 -lnetapi32 -lz
 else
 CXXFLAGS += $(shell PKG_CONFIG_PATH=$(PKG_CONFIG_PATH) $(PKG_CONFIG) --silence-errors --cflags tcl || echo -I$(TCL_INCLUDE)) -DYOSYS_ENABLE_TCL
 ifeq ($(OS), FreeBSD)

From b50fe1e3e9d2f60ebd3053d42e7f9c2f6f5a79be Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Jul 2018 14:35:32 +0200
Subject: [PATCH 043/528] Upodate ABC to git rev ae6716b

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 2090a083a..be266b628 100644
--- a/Makefile
+++ b/Makefile
@@ -107,7 +107,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 6df1396
+ABCREV = ae6716b
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1

From 0eaab6cd1d3fca807861a9090e684ddde16b0ba2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Jul 2018 15:21:59 +0200
Subject: [PATCH 044/528] Add missing <deque> include (MSVC build fix)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/techmap/extract_reduce.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/techmap/extract_reduce.cc b/passes/techmap/extract_reduce.cc
index cc21c8665..0ce596fda 100644
--- a/passes/techmap/extract_reduce.cc
+++ b/passes/techmap/extract_reduce.cc
@@ -19,6 +19,7 @@
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
+#include <deque>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN

From e275692e84c935d0cdf42c2a4adf7ac949a88132 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 22 Jul 2018 18:44:05 +0200
Subject: [PATCH 045/528] Verific: Produce errors for instantiating unknown
 module

Because if the unknown module is connected to any constants, Verific will
actually break all constants in the same module, even if they have nothing
to do structurally with that instance of an unknown module.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8937cdde8..b8dd72b98 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1800,6 +1800,9 @@ struct VerificPass : public Pass {
 		RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
 		RuntimeFlags::SetVar("db_infer_wide_operators", 1);
 
+		// WARNING: instantiating unknown module 'XYZ' (VERI-1063)
+		Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
+
 		verific_verbose = 0;
 
 		const char *release_str = Message::ReleaseString();

From beedaa58561eb7cabf24e0d267beb77d5c78ef1d Mon Sep 17 00:00:00 2001
From: japm48 <japm48@users.noreply.github.com>
Date: Sun, 22 Jul 2018 22:29:31 +0200
Subject: [PATCH 046/528] fix basys3 example

Added `CONFIG_VOLTAGE` and `CFGBVS` to constraints file
to avoid warning `DRC 23-20`.

Added `open_hw` needed for programming.
---
 examples/basys3/example.xdc  | 3 +++
 examples/basys3/run_prog.tcl | 1 +
 2 files changed, 4 insertions(+)

diff --git a/examples/basys3/example.xdc b/examples/basys3/example.xdc
index c1fd0e925..8cdaa1996 100644
--- a/examples/basys3/example.xdc
+++ b/examples/basys3/example.xdc
@@ -19,3 +19,6 @@ set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN L1  } [get_ports {LD[15]}]
 
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports CLK]
 
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
diff --git a/examples/basys3/run_prog.tcl b/examples/basys3/run_prog.tcl
index d711af840..b078ad511 100644
--- a/examples/basys3/run_prog.tcl
+++ b/examples/basys3/run_prog.tcl
@@ -1,3 +1,4 @@
+open_hw
 connect_hw_server
 open_hw_target [lindex [get_hw_targets] 0]
 set_property PROGRAM.FILE example.bit [lindex [get_hw_devices] 0]

From f42d6a9c93f8bd456bf5e857dc67f19e3b10ab25 Mon Sep 17 00:00:00 2001
From: litghost <537074+litghost@users.noreply.github.com>
Date: Thu, 2 Aug 2018 14:33:39 -0700
Subject: [PATCH 047/528] Add BLIF parsing support for .conn and .cname

---
 frontends/blif/blifparse.cc | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index e6bb99954..e2be61da8 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -83,6 +83,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 	RTLIL::Module *module = nullptr;
 	RTLIL::Const *lutptr = NULL;
 	RTLIL::Cell *sopcell = NULL;
+	RTLIL::Cell *lastcell = nullptr;
 	RTLIL::State lut_default_state = RTLIL::State::Sx;
 	int blif_maxnum = 0, sopmode = -1;
 
@@ -159,6 +160,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 				if (module != nullptr)
 					goto error;
 				module = new RTLIL::Module;
+				lastcell = nullptr;
 				module->name = RTLIL::escape_id(strtok(NULL, " \t\r\n"));
 				obj_attributes = &module->attributes;
 				obj_parameters = nullptr;
@@ -232,6 +234,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 				}
 
 				module = nullptr;
+				lastcell = nullptr;
 				obj_attributes = nullptr;
 				obj_parameters = nullptr;
 				continue;
@@ -264,6 +267,22 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 				continue;
 			}
 
+			if (!strcmp(cmd, ".cname"))
+			{
+				char *p = strtok(NULL, " \t\r\n");
+				if (p == NULL)
+					goto error;
+
+				if(lastcell == nullptr || module == nullptr)
+				{
+					log_error("No primative object to attach .cname %s.\n", p);
+					goto error;
+				}
+
+				module->rename(lastcell, p);
+				continue;
+			}
+
 			if (!strcmp(cmd, ".attr") || !strcmp(cmd, ".param")) {
 				char *n = strtok(NULL, " \t\r\n");
 				char *v = strtok(NULL, "\r\n");
@@ -281,12 +300,16 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 						const_v.bits[i] = v[n-i-1] != '0' ? State::S1 : State::S0;
 				}
 				if (!strcmp(cmd, ".attr")) {
-					if (obj_attributes == nullptr)
+					if (obj_attributes == nullptr) {
+						log_error("No object to attach .attr too.\n");
 						goto error;
+					}
 					(*obj_attributes)[id_n] = const_v;
 				} else {
-					if (obj_parameters == nullptr)
+					if (obj_parameters == nullptr) {
+						log_error("No object to attach .param too.\n");
 						goto error;
+					}
 					(*obj_parameters)[id_n] = const_v;
 				}
 				continue;
@@ -331,6 +354,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 					}
 				}
 
+				lastcell = cell;
 				obj_attributes = &cell->attributes;
 				obj_parameters = &cell->parameters;
 				continue;
@@ -383,6 +407,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 					cell->setPort(it.first, sig);
 				}
 
+				lastcell = cell;
 				obj_attributes = &cell->attributes;
 				obj_parameters = &cell->parameters;
 				continue;
@@ -391,7 +416,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 			obj_attributes = nullptr;
 			obj_parameters = nullptr;
 
-			if (!strcmp(cmd, ".barbuf"))
+			if (!strcmp(cmd, ".barbuf") || !strcmp(cmd, ".conn"))
 			{
 				char *p = strtok(NULL, " \t\r\n");
 				if (p == NULL)
@@ -459,6 +484,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 					sopcell->setPort("\\A", input_sig);
 					sopcell->setPort("\\Y", output_sig);
 					sopmode = -1;
+					lastcell = sopcell;
 				}
 				else
 				{
@@ -469,6 +495,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 					cell->setPort("\\Y", output_sig);
 					lutptr = &cell->parameters.at("\\LUT");
 					lut_default_state = RTLIL::State::Sx;
+					lastcell = cell;
 				}
 				continue;
 			}

From 475c2af8120199f0acaa02e6e0993b27a553b22f Mon Sep 17 00:00:00 2001
From: litghost <537074+litghost@users.noreply.github.com>
Date: Fri, 3 Aug 2018 08:02:49 -0700
Subject: [PATCH 048/528] Use log_warning which does not immediately terminate.

---
 frontends/blif/blifparse.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index e2be61da8..1d4cf39a8 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -275,7 +275,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 				if(lastcell == nullptr || module == nullptr)
 				{
-					log_error("No primative object to attach .cname %s.\n", p);
+					log_warning("No primative object to attach .cname %s.\n", p);
 					goto error;
 				}
 
@@ -301,13 +301,13 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 				}
 				if (!strcmp(cmd, ".attr")) {
 					if (obj_attributes == nullptr) {
-						log_error("No object to attach .attr too.\n");
+						log_warning("No object to attach .attr too.\n");
 						goto error;
 					}
 					(*obj_attributes)[id_n] = const_v;
 				} else {
 					if (obj_parameters == nullptr) {
-						log_error("No object to attach .param too.\n");
+						log_warning("No object to attach .param too.\n");
 						goto error;
 					}
 					(*obj_parameters)[id_n] = const_v;

From da53206cd4b1e32d8bf29bb33cdfec81d614525e Mon Sep 17 00:00:00 2001
From: Konrad Beckmann <konrad.beckmann@gmail.com>
Date: Mon, 6 Aug 2018 13:30:33 +0900
Subject: [PATCH 049/528] readme: Fix formatting of a keyword

Single quotes were used instead of backticks leading to
incorrect formatting.
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index c02691d94..424d9bbf2 100644
--- a/README.md
+++ b/README.md
@@ -389,7 +389,7 @@ Verilog Attributes and non-standard features
 Non-standard or SystemVerilog features for formal verification
 ==============================================================
 
-- Support for ``assert``, ``assume``, ``restrict``, and ``cover'' is enabled
+- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled
   when ``read_verilog`` is called with ``-formal``.
 
 - The system task ``$initstate`` evaluates to 1 in the initial state and

From 7db05b2cc1befba7e9d7afbb270dd503e8ec5857 Mon Sep 17 00:00:00 2001
From: jpathy <15735913+jpathy@users.noreply.github.com>
Date: Mon, 6 Aug 2018 06:51:07 +0000
Subject: [PATCH 050/528] Use `realpath`

Use `os.path.realpath` instead to make sure symlinks are followed. This is also required to work for nix package manager.
---
 backends/smt2/Makefile.inc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/smt2/Makefile.inc b/backends/smt2/Makefile.inc
index eacda2734..dce82f01a 100644
--- a/backends/smt2/Makefile.inc
+++ b/backends/smt2/Makefile.inc
@@ -6,7 +6,7 @@ ifneq ($(CONFIG),emcc)
 TARGETS += yosys-smtbmc
 
 yosys-smtbmc: backends/smt2/smtbmc.py
-	$(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(__file__) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new
+	$(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new
 	$(Q) chmod +x $@.new
 	$(Q) mv $@.new $@
 

From 219f1e9fc9bda90422d1ec81db581a0f469ef192 Mon Sep 17 00:00:00 2001
From: litghost <537074+litghost@users.noreply.github.com>
Date: Wed, 8 Aug 2018 10:22:55 -0700
Subject: [PATCH 051/528] Report error reason on same line as syntax error.

Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
---
 frontends/blif/blifparse.cc | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 1d4cf39a8..b81808b1e 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -85,6 +85,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 	RTLIL::Cell *sopcell = NULL;
 	RTLIL::Cell *lastcell = nullptr;
 	RTLIL::State lut_default_state = RTLIL::State::Sx;
+	char err_reason[80];
 	int blif_maxnum = 0, sopmode = -1;
 
 	auto blif_wire = [&](const std::string &wire_name) -> Wire*
@@ -275,8 +276,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 				if(lastcell == nullptr || module == nullptr)
 				{
-					log_warning("No primative object to attach .cname %s.\n", p);
-					goto error;
+					snprintf(err_reason, sizeof(err_reason), "No primative object to attach .cname %s.", p);
+					goto error_with_reason;
 				}
 
 				module->rename(lastcell, p);
@@ -301,14 +302,14 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 				}
 				if (!strcmp(cmd, ".attr")) {
 					if (obj_attributes == nullptr) {
-						log_warning("No object to attach .attr too.\n");
-						goto error;
+						snprintf(err_reason, sizeof(err_reason), "No object to attach .attr too.");
+						goto error_with_reason;
 					}
 					(*obj_attributes)[id_n] = const_v;
 				} else {
 					if (obj_parameters == nullptr) {
-						log_warning("No object to attach .param too.\n");
-						goto error;
+						snprintf(err_reason, sizeof(err_reason), "No object to attach .param too.");
+						goto error_with_reason;
 					}
 					(*obj_parameters)[id_n] = const_v;
 				}
@@ -573,6 +574,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 error:
 	log_error("Syntax error in line %d!\n", line_count);
+error_with_reason:
+	log_error("Syntax error in line %d: %s\n", line_count, err_reason);
 }
 
 struct BlifFrontend : public Frontend {

From 93efbd5d158e374a0abe2afb06484ccc14aa2c88 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 8 Aug 2018 19:41:47 +0200
Subject: [PATCH 052/528] Fixed use of char array for string in blifparse error
 handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/blif/blifparse.cc | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index b81808b1e..26cd14033 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -85,7 +85,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 	RTLIL::Cell *sopcell = NULL;
 	RTLIL::Cell *lastcell = nullptr;
 	RTLIL::State lut_default_state = RTLIL::State::Sx;
-	char err_reason[80];
+	std::string err_reason;
 	int blif_maxnum = 0, sopmode = -1;
 
 	auto blif_wire = [&](const std::string &wire_name) -> Wire*
@@ -276,7 +276,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 				if(lastcell == nullptr || module == nullptr)
 				{
-					snprintf(err_reason, sizeof(err_reason), "No primative object to attach .cname %s.", p);
+					err_reason = stringf("No primative object to attach .cname %s.", p);
 					goto error_with_reason;
 				}
 
@@ -302,13 +302,13 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 				}
 				if (!strcmp(cmd, ".attr")) {
 					if (obj_attributes == nullptr) {
-						snprintf(err_reason, sizeof(err_reason), "No object to attach .attr too.");
+						err_reason = stringf("No object to attach .attr too.");
 						goto error_with_reason;
 					}
 					(*obj_attributes)[id_n] = const_v;
 				} else {
 					if (obj_parameters == nullptr) {
-						snprintf(err_reason, sizeof(err_reason), "No object to attach .param too.");
+						err_reason = stringf("No object to attach .param too.");
 						goto error_with_reason;
 					}
 					(*obj_parameters)[id_n] = const_v;
@@ -575,7 +575,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 error:
 	log_error("Syntax error in line %d!\n", line_count);
 error_with_reason:
-	log_error("Syntax error in line %d: %s\n", line_count, err_reason);
+	log_error("Syntax error in line %d: %s\n", line_count, err_reason.c_str());
 }
 
 struct BlifFrontend : public Frontend {

From 80d7e007ff4cbe0a9669224751c68e5325fbed0a Mon Sep 17 00:00:00 2001
From: litghost <537074+litghost@users.noreply.github.com>
Date: Mon, 13 Aug 2018 14:02:53 -0700
Subject: [PATCH 053/528] Map .eblif extension as blif.

Signed-off-by: litghost <537074+litghost@users.noreply.github.com>
---
 kernel/yosys.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 750a154e6..dca277532 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -825,6 +825,8 @@ void run_frontend(std::string filename, std::string command, std::string *backen
 			command = "vhdl";
 		else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif")
 			command = "blif";
+		else if (filename.size() > 5 && filename.substr(filename.size()-6) == ".eblif")
+			command = "blif";
 		else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".json")
 			command = "json";
 		else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".il")

From 1dd156f5167d9949eccb7abcbc65d9bc74f49ee8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 14 Aug 2018 23:31:25 +0200
Subject: [PATCH 054/528] Fix use of signed integers in JSON back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/json/json.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/backends/json/json.cc b/backends/json/json.cc
index d3b7077a2..1a3ca64a3 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -93,8 +93,10 @@ struct JsonWriter
 				f << get_string(param.second.decode_string());
 			else if (GetSize(param.second.bits) > 32)
 				f << get_string(param.second.as_string());
-			else
+			else if ((param.second.flags & RTLIL::ConstFlags::CONST_FLAG_SIGNED) != 0)
 				f << stringf("%d", param.second.as_int());
+			else
+				f << stringf("%u", param.second.as_int());
 			first = false;
 		}
 	}

From a5136c768b87c3e7ad675888ec51dbe3fc030fc2 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 15 Aug 2018 19:08:45 +0200
Subject: [PATCH 055/528] Changes for MXE configuration in order to compile

---
 Makefile | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index c90ff6da9..eed4e8f23 100644
--- a/Makefile
+++ b/Makefile
@@ -200,14 +200,14 @@ yosys.html: misc/yosys.html
 
 else ifeq ($(CONFIG),mxe)
 PKG_CONFIG = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-pkg-config
-CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc
-LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc
+CXX = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
+LD = /usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-g++
 CXXFLAGS += -std=c++11 -Os -D_POSIX_SOURCE -DYOSYS_MXE_HACKS -Wno-attributes
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := $(filter-out -lrt,$(LDLIBS))
-ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H -DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
-ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1
+ABCMKARGS += ARCHFLAGS="-DWIN32_NO_DLL -DHAVE_STRUCT_TIMESPEC -fpermissive -w"
+ABCMKARGS += LIBS="lib/x86/pthreadVC2.lib -s" ABC_USE_NO_READLINE=1 CC="/usr/local/src/mxe/usr/bin/i686-w64-mingw32.static-gcc"
 EXE = .exe
 
 else ifeq ($(CONFIG),msys2)

From 28cfc75a902574c3ad96876d2f5e01af6c583bac Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Wed, 15 Aug 2018 19:56:30 +0300
Subject: [PATCH 056/528] A few minor enhancements to specify block parsing.
 Just remember specify blocks are parsed but ignored.

---
 frontends/verilog/verilog_parser.y | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 78cac5543..61da12b76 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -688,8 +688,8 @@ path_declaration :
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';'
-	// | full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value ';' |
+	full_path_description '=' path_delay_value ';'
 	;
 
 path_delay_value :
@@ -723,6 +723,17 @@ list_of_path_delay_expressions :
 parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
+full_path_description :
+	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+
+list_of_path_inputs :
+	specify_input_terminal_descriptor |
+	list_of_path_inputs ',' specify_input_terminal_descriptor ;
+	
+list_of_path_outputs :
+	specify_output_terminal_descriptor |
+	list_of_path_outputs ',' specify_output_terminal_descriptor ;
+	
 opt_polarity_operator :
 	'+'
 	| '-'

From 9f91c62348c533d0d0d167a393bab284b2c6de8d Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 15 Aug 2018 17:15:44 -0400
Subject: [PATCH 057/528] Fix run_command() when using -format and -viewer in
 show pass.

---
 passes/cmds/show.cc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index ec04418fa..fa88cd668 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -817,14 +817,30 @@ struct ShowPass : public Pass {
 			log_cmd_error("Nothing there to show.\n");
 
 		if (format != "dot" && !format.empty()) {
-			std::string cmd = stringf("dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'", format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
+			#ifdef _WIN32
+				// system()/cmd.exe does not understand single quotes on Windows.
+				#define DOT_CMD "dot -T%s \"%s\" > \"%s.new\" && move \"%s.new\" \"%s\""
+			#else
+				#define DOT_CMD "dot -T%s '%s' > '%s.new' && mv '%s.new' '%s'"
+			#endif
+			std::string cmd = stringf(DOT_CMD, format.c_str(), dot_file.c_str(), out_file.c_str(), out_file.c_str(), out_file.c_str());
+			#undef DOT_CMD
 			log("Exec: %s\n", cmd.c_str());
 			if (run_command(cmd) != 0)
 				log_cmd_error("Shell command failed!\n");
 		}
 
 		if (!viewer_exe.empty()) {
-			std::string cmd = stringf("%s '%s' &", viewer_exe.c_str(), out_file.c_str());
+			#ifdef _WIN32
+				// system()/cmd.exe does not understand single quotes nor
+				// background tasks on Windows. So we have to pause yosys
+				// until the viewer exits.
+				#define VIEW_CMD "%s \"%s\""
+			#else
+				#define VIEW_CMD "%s '%s' &"
+			#endif
+			std::string cmd = stringf(VIEW_CMD, viewer_exe.c_str(), out_file.c_str());
+			#undef VIEW_CMD
 			log("Exec: %s\n", cmd.c_str());
 			if (run_command(cmd) != 0)
 				log_cmd_error("Shell command failed!\n");

From 7ce7ea2eb4903058ac4560d7b192cb5ed02aed89 Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Wed, 15 Aug 2018 17:16:07 -0400
Subject: [PATCH 058/528] Update show pass documentation with Windows caveats.

---
 passes/cmds/show.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index fa88cd668..a48873244 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -584,6 +584,7 @@ struct ShowPass : public Pass {
 		log("\n");
 		log("    -viewer <viewer>\n");
 		log("        Run the specified command with the graphics file as parameter.\n");
+		log("        On Windows, this pauses yosys until the viewer exits.\n");
 		log("\n");
 		log("    -format <format>\n");
 		log("        Generate a graphics file in the specified format. Use 'dot' to just\n");
@@ -645,7 +646,7 @@ struct ShowPass : public Pass {
 		log("        do not add the module name as graph title to the dot file\n");
 		log("\n");
 		log("When no <format> is specified, 'dot' is used. When no <format> and <viewer> is\n");
-		log("specified, 'xdot' is used to display the schematic.\n");
+		log("specified, 'xdot' is used to display the schematic (POSIX systems only).\n");
 		log("\n");
 		log("The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',\n");
 		log("unless another prefix is specified using -prefix <prefix>.\n");

From 0899a53bee39e209551a3122c7c820b7ed2b48c3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Aug 2018 11:31:19 +0200
Subject: [PATCH 059/528] Verific workaround for VIPER ticket 13851

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index e993eb740..2895d40c2 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1800,6 +1800,9 @@ struct VerificPass : public Pass {
 		RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
 		RuntimeFlags::SetVar("db_infer_wide_operators", 1);
 
+		// Workaround for VIPER #13851
+		RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
+
 		// WARNING: instantiating unknown module 'XYZ' (VERI-1063)
 		Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
 

From e343f3e6d475984c21611474bffe7dcd8f599497 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 16 Aug 2018 11:49:17 +0200
Subject: [PATCH 060/528] Add "verific -set-<severity> <msg_id>.."

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 62 +++++++++++++++++++++++++++++-------
 1 file changed, 50 insertions(+), 12 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 2895d40c2..b8c0375ce 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1732,6 +1732,15 @@ struct VerificPass : public Pass {
 		log("Remove Verilog defines previously set with -vlog-define.\n");
 		log("\n");
 		log("\n");
+		log("    verific -set-error <msg_id>..\n");
+		log("    verific -set-warning <msg_id>..\n");
+		log("    verific -set-info <msg_id>..\n");
+		log("    verific -set-ignore <msg_id>..\n");
+		log("\n");
+		log("Set message severity. <msg_id> is the string in square brackets when a message\n");
+		log("is printed, such as VERI-1209.\n");
+		log("\n");
+		log("\n");
 		log("    verific -import [options] <top-module>..\n");
 		log("\n");
 		log("Elaborate the design for the specified top modules, import to Yosys and\n");
@@ -1786,25 +1795,32 @@ struct VerificPass : public Pass {
 #ifdef YOSYS_ENABLE_VERIFIC
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
+		static bool set_verific_global_flags = true;
+
 		if (check_noverific_env())
 			log_cmd_error("This version of Yosys is built without Verific support.\n");
 
 		log_header(design, "Executing VERIFIC (loading SystemVerilog and VHDL designs using Verific).\n");
 
-		Message::SetConsoleOutput(0);
-		Message::RegisterCallBackMsg(msg_func);
-		RuntimeFlags::SetVar("db_preserve_user_nets", 1);
-		RuntimeFlags::SetVar("db_allow_external_nets", 1);
-		RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
-		RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
-		RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
-		RuntimeFlags::SetVar("db_infer_wide_operators", 1);
+		if (set_verific_global_flags)
+		{
+			Message::SetConsoleOutput(0);
+			Message::RegisterCallBackMsg(msg_func);
+			RuntimeFlags::SetVar("db_preserve_user_nets", 1);
+			RuntimeFlags::SetVar("db_allow_external_nets", 1);
+			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
+			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
+			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
+			RuntimeFlags::SetVar("db_infer_wide_operators", 1);
 
-		// Workaround for VIPER #13851
-		RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
+			// Workaround for VIPER #13851
+			RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);
 
-		// WARNING: instantiating unknown module 'XYZ' (VERI-1063)
-		Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
+			// WARNING: instantiating unknown module 'XYZ' (VERI-1063)
+			Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
+
+			set_verific_global_flags = false;
+		}
 
 		verific_verbose = 0;
 
@@ -1822,6 +1838,28 @@ struct VerificPass : public Pass {
 
 		int argidx = 1;
 
+		if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
+				args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
+		{
+			msg_type_t new_type;
+
+			if (args[argidx] == "-set-error")
+				new_type = VERIFIC_ERROR;
+			else if (args[argidx] == "-set-warning")
+				new_type = VERIFIC_WARNING;
+			else if (args[argidx] == "-set-info")
+				new_type = VERIFIC_INFO;
+			else if (args[argidx] == "-set-ignore")
+				new_type = VERIFIC_IGNORE;
+			else
+				log_abort();
+
+			for (argidx++; argidx < GetSize(args); argidx++)
+				Message::SetMessageType(args[argidx].c_str(), new_type);
+
+			goto check_error;
+		}
+
 		if (GetSize(args) > argidx && args[argidx] == "-vlog-incdir") {
 			for (argidx++; argidx < GetSize(args); argidx++)
 				verific_incdirs.push_back(args[argidx]);

From 83b41260f6c8dd3ba617cc03b06435521038e7db Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Sat, 18 Aug 2018 09:08:07 +0530
Subject: [PATCH 061/528] Revision to expose option in setundef pass

Corrects indentation

Simplifications and corrections
---
 passes/cmds/setundef.cc | 247 ++++++++++++++++++----------------------
 1 file changed, 108 insertions(+), 139 deletions(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index eac1f6236..62d940ce6 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -33,67 +33,32 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static RTLIL::Wire * add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output, bool flag_global)
+static RTLIL::Wire * add_wire(RTLIL::Module *module, std::string name, int width, bool flag_input, bool flag_output)
 {
-  RTLIL::Wire *wire = NULL;
-  name = RTLIL::escape_id(name);
+	RTLIL::Wire *wire = NULL;
+	name = RTLIL::escape_id(name);
 
-  if (module->count_id(name) != 0)
-  {
-    if (module->wires_.count(name) > 0)
-      wire = module->wires_.at(name);
+	if (module->count_id(name) != 0)
+	{
+		log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
+		name += "$";
+		return add_wire(module, name, width, flag_input, flag_output);
+	}
+	else
+	{
+		wire = module->addWire(name, width);
+		wire->port_input = flag_input;
+		wire->port_output = flag_output;
 
-    if (wire != NULL && wire->width != width)
-      wire = NULL;
+		if (flag_input || flag_output) {
+			wire->port_id = module->wires_.size();
+			module->fixup_ports();
+		}
 
-    if (wire != NULL && wire->port_input != flag_input)
-      wire = NULL;
+		log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
+	}
 
-    if (wire != NULL && wire->port_output != flag_output)
-      wire = NULL;
-
-    if (wire == NULL) {
-      return wire;
-      log_cmd_error("Found incompatible object %s with same name in module %s!\n", name.c_str(), module->name.c_str());
-    }
-
-    log("Module %s already has such an object %s.\n", module->name.c_str(), name.c_str());
-  }
-  else
-  {
-    wire = module->addWire(name, width);
-    wire->port_input = flag_input;
-    wire->port_output = flag_output;
-
-    if (flag_input || flag_output) {
-      wire->port_id = module->wires_.size();
-      module->fixup_ports();
-    }
-
-    log("Added wire %s to module %s.\n", name.c_str(), module->name.c_str());
-  }
-
-  if (!flag_global)
-    return wire;
-
-  for (auto &it : module->cells_)
-  {
-    if (design->modules_.count(it.second->type) == 0)
-      continue;
-
-    RTLIL::Module *mod = design->modules_.at(it.second->type);
-    if (!design->selected_whole_module(mod->name))
-      continue;
-    if (mod->get_bool_attribute("\\blackbox"))
-      continue;
-    if (it.second->hasPort(name))
-      continue;
-
-    it.second->setPort(name, wire);
-    log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
-  }
-
-  return wire;
+	return wire;
 }
 
 struct SetundefWorker
@@ -262,100 +227,104 @@ struct SetundefPass : public Pass {
 				if (!module->processes.empty())
 					log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n");
 
-        if (expose_mode) {
-          SigMap sigmap(module);
-          dict<SigBit, bool> wire_drivers;
-          pool<SigBit> used_wires;
-          SigPool undriven_signals;
+				if (expose_mode)
+				{
+					SigMap sigmap(module);
+					dict<SigBit, bool> wire_drivers;
+					pool<SigBit> used_wires;
+					SigPool undriven_signals;
 
-          for (auto cell : module->cells())
-          for (auto &conn : cell->connections()) {
-            SigSpec sig = sigmap(conn.second);
-            if (cell->input(conn.first))
-              for (auto bit : sig)
-                if (bit.wire) {
-                  used_wires.insert(bit);
-                }
-            if (cell->output(conn.first))
-              for (int i = 0; i < GetSize(sig); i++) {
-                if (sig[i].wire)
-                  wire_drivers[sig[i]] = true;
-              }
-          }
+					for (auto cell : module->cells())
+						for (auto &conn : cell->connections()) {
+							SigSpec sig = sigmap(conn.second);
+							if (cell->input(conn.first))
+								for (auto bit : sig)
+									if (bit.wire)
+										used_wires.insert(bit);
+							if (cell->output(conn.first))
+								for (int i = 0; i < GetSize(sig); i++)
+									if (sig[i].wire)
+										wire_drivers[sig[i]] = true;
+						}
 
-          for (auto wire : module->wires()) {
-            if (wire->port_input) {
-              SigSpec sig = sigmap(wire);
-              for (int i = 0; i < GetSize(sig); i++)
-                wire_drivers[sig[i]] = true;
-            }
-            if (wire->port_output)
-              for (auto bit : sigmap(wire))
-                if (bit.wire) used_wires.insert(bit);
-          }
+					for (auto wire : module->wires()) {
+						if (wire->port_input) {
+							SigSpec sig = sigmap(wire);
+							for (int i = 0; i < GetSize(sig); i++)
+								wire_drivers[sig[i]] = true;
+						}
+						if (wire->port_output) {
+							SigSpec sig = sigmap(wire);
+							for (auto bit : sig)
+								if (bit.wire)
+									used_wires.insert(bit);
+						}
+					}
 
-          pool<RTLIL::Wire*> undriven_wires;
-          for (auto bit : used_wires) {
-            if (!wire_drivers.count(bit)) {
-              undriven_wires.insert(bit.wire);
-            }
-          }
+					pool<RTLIL::Wire*> undriven_wires;
+					for (auto bit : used_wires)
+						if (!wire_drivers.count(bit))
+							undriven_wires.insert(bit.wire);
 
-          for (auto &it : undriven_wires)
-            undriven_signals.add(sigmap(it));
+					for (auto &it : undriven_wires)
+						undriven_signals.add(sigmap(it));
 
-          for (auto &it : undriven_wires)
-            if (it->port_input)
-              undriven_signals.del(sigmap(it));
+					for (auto &it : undriven_wires)
+						if (it->port_input)
+							undriven_signals.del(sigmap(it));
 
-          CellTypes ct(design);
-          for (auto &it : module->cells_)
-          for (auto &conn : it.second->connections())
-            if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
-              undriven_signals.del(sigmap(conn.second));
+					CellTypes ct(design);
+					for (auto &it : module->cells_)
+					for (auto &conn : it.second->connections())
+						if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+							undriven_signals.del(sigmap(conn.second));
 
-          RTLIL::SigSpec sig = undriven_signals.export_all();
-          for (auto &c : sig.chunks()) {
-            RTLIL::Wire * wire;
-            if (c.wire->width == c.width) {
-              wire = c.wire;
-              wire->port_input = true;
-            }
-            else {
-              string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
-              wire = add_wire(design, module, name, c.width, true, false, false);
-              module->connect(RTLIL::SigSig(c, wire));
-            }
-            log("Exposing undriven wire %s as input.\n", wire->name.c_str());
-          }
-          module->fixup_ports();
-          continue;
-        }
-        else {
-          SigMap sigmap(module);
-          SigPool undriven_signals;
+					RTLIL::SigSpec sig = undriven_signals.export_all();
+					for (auto &c : sig.chunks()) {
+						RTLIL::Wire * wire;
+						if (c.wire->width == c.width) {
+							wire = c.wire;
+							wire->port_input = true;
+						} else {
+							string name = c.wire->name.str() + "$[" + std::to_string(c.width + c.offset) + ":" + std::to_string(c.offset) + "]";
+							wire = add_wire(module, name, c.width, true, false);
+							module->connect(RTLIL::SigSig(c, wire));
+						}
+						log("Exposing undriven wire %s as input.\n", wire->name.c_str());
+					}
+					module->fixup_ports();
+				}
+				else
+				{
+					SigMap sigmap(module);
+					SigPool undriven_signals;
 
-          for (auto &it : module->wires_)
-            undriven_signals.add(sigmap(it.second));
+					for (auto &it : module->wires_)
+						undriven_signals.add(sigmap(it.second));
 
-          for (auto &it : module->wires_)
-            if (it.second->port_input)
-              undriven_signals.del(sigmap(it.second));
+					for (auto &it : module->wires_)
+						if (it.second->port_input)
+							undriven_signals.del(sigmap(it.second));
 
-          CellTypes ct(design);
-          for (auto &it : module->cells_)
-          for (auto &conn : it.second->connections())
-            if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
-              undriven_signals.del(sigmap(conn.second));
+					CellTypes ct(design);
+					for (auto &it : module->cells_)
+					for (auto &conn : it.second->connections())
+						if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first))
+							undriven_signals.del(sigmap(conn.second));
 
-          RTLIL::SigSpec sig = undriven_signals.export_all();
-          for (auto &c : sig.chunks()) {
-            RTLIL::SigSpec bits;
-            for (int i = 0; i < c.width; i++)
-              bits.append(worker.next_bit());
-            module->connect(RTLIL::SigSig(c, bits));
-          }
-        }
+					RTLIL::SigSpec sig = undriven_signals.export_all();
+					for (auto &c : sig.chunks()) {
+						RTLIL::SigSpec bits;
+						if (worker.next_bit_mode == MODE_ANYSEQ)
+							bits = module->Anyseq(NEW_ID, c.width);
+						else if (worker.next_bit_mode == MODE_ANYCONST)
+							bits = module->Anyconst(NEW_ID, c.width);
+						else
+							for (int i = 0; i < c.width; i++)
+								bits.append(worker.next_bit());
+						module->connect(RTLIL::SigSig(c, bits));
+					}
+				}
 			}
 
 			if (init_mode)

From 3e20788c24d2b0472fa9e3ecee31b636c5866d8d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 14:00:55 +0200
Subject: [PATCH 062/528] Added gcc-static for easier cross compilation

---
 Makefile | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index eed4e8f23..c2a3293ae 100644
--- a/Makefile
+++ b/Makefile
@@ -156,6 +156,14 @@ LD = gcc
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
+else ifeq ($(CONFIG),gcc-static)
+LD = $(CXX)
+LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
+LDLIBS := -static $(filter-out -lrt,$(LDLIBS))
+CXXFLAGS += -std=c++11 -Os
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \
+                       ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1
+
 else ifeq ($(CONFIG),gcc-4.8)
 CXX = gcc-4.8
 LD = gcc-4.8
@@ -671,6 +679,12 @@ config-clang: clean
 config-gcc: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 
+config-gcc-static: clean
+	echo 'CONFIG := gcc-static' > Makefile.conf
+	echo 'ENABLE_PLUGINS := 0' >> Makefile.conf
+	echo 'ENABLE_READLINE := 0' >> Makefile.conf
+	echo 'ENABLE_TCL := 0' >> Makefile.conf
+
 config-gcc-4.8: clean
 	echo 'CONFIG := gcc-4.8' > Makefile.conf
 
@@ -712,5 +726,5 @@ echo-git-rev:
 -include techlibs/*/*.d
 
 .PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator
-.PHONY: config-clean config-clang config-gcc config-gcc-4.8 config-gprof config-sudo
+.PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo
 

From 539053ab68d7a124f0c710e3fbd87aba8ee8b0aa Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 14:14:17 +0200
Subject: [PATCH 063/528] Added option to disable -fPIC on unsupported
 platforms

---
 Makefile | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Makefile b/Makefile
index c2a3293ae..c2a076229 100644
--- a/Makefile
+++ b/Makefile
@@ -160,6 +160,9 @@ else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
 LDLIBS := -static $(filter-out -lrt,$(LDLIBS))
+ifeq ($(NO_FPIC),1)
+CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
+endif
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1

From 45740236b6b0aa8d445fb3fea8d8c1ec497be3cf Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 15:11:58 +0200
Subject: [PATCH 064/528] Enable propagating ARCHFLAGS

---
 Makefile | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index c2a076229..024b216f0 100644
--- a/Makefile
+++ b/Makefile
@@ -164,8 +164,8 @@ ifeq ($(NO_FPIC),1)
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 endif
 CXXFLAGS += -std=c++11 -Os
-ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" LIBS="-static -lm -ldl -pthread" OPTFLAGS="-O" \
-                       ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable" ABC_USE_NO_READLINE=1
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-static -lm -lpthread" OPTFLAGS="-O" \
+                       ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
 
 else ifeq ($(CONFIG),gcc-4.8)
 CXX = gcc-4.8

From 443865ab870248aed91700686160d36ed616503d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 18:21:28 +0200
Subject: [PATCH 065/528] respect DISABLE_ABC_THREADS if used

---
 Makefile | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index 024b216f0..c3e3a4b47 100644
--- a/Makefile
+++ b/Makefile
@@ -159,13 +159,16 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := -static $(filter-out -lrt,$(LDLIBS))
+LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) 
 ifeq ($(NO_FPIC),1)
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 endif
 CXXFLAGS += -std=c++11 -Os
-ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-static -lm -lpthread" OPTFLAGS="-O" \
+ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1
+ifeq ($(DISABLE_ABC_THREADS),1)
+ABCMKARGS += "ABC_USE_NO_PTHREADS=1"
+endif
 
 else ifeq ($(CONFIG),gcc-4.8)
 CXX = gcc-4.8

From 75d185294362ae9ed2fbb08e5348cbdf113c3e8f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 18 Aug 2018 19:17:02 +0200
Subject: [PATCH 066/528] no -fPIC for any static build

---
 Makefile | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index c3e3a4b47..c1e5c789d 100644
--- a/Makefile
+++ b/Makefile
@@ -159,10 +159,8 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
-LDLIBS := -static $(filter-out -lrt,$(LDLIBS)) 
-ifeq ($(NO_FPIC),1)
+LDLIBS := $(filter-out -lrt,$(LDLIBS)) 
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
-endif
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
                        ARCHFLAGS="-DABC_USE_STDINT_H -DABC_NO_DYNAMIC_LINKING=1 -Wno-unused-but-set-variable $(ARCHFLAGS)" ABC_USE_NO_READLINE=1

From 95241c8f4d32c5bd644bef71509965a82582264c Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Mon, 20 Aug 2018 00:08:08 +0300
Subject: [PATCH 067/528] Yosys can now parse
 https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v
 , (specify block ignored). Must use 'read_verilog -defer' due to a parameter
 not assigned a default value.

---
 frontends/verilog/verilog_parser.y | 32 ++++++++++++++++++++----------
 1 file changed, 22 insertions(+), 10 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 61da12b76..58a6824d1 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -654,7 +654,7 @@ specify_item:
 	// | pulsestyle_declaration
 	// | showcancelled_declaration
 	| path_declaration
-	// | system_timing_declaration
+	| system_timing_declaration
 	;
 
 specparam_declaration:
@@ -693,8 +693,8 @@ simple_path_declaration :
 	;
 
 path_delay_value :
-	//list_of_path_delay_expressions
-	'(' list_of_path_delay_expressions ')'
+	list_of_path_delay_expressions |
+	%prec '(' list_of_path_delay_expressions ')'
 	;
 
 list_of_path_delay_expressions :
@@ -724,12 +724,17 @@ parallel_path_description :
 	'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
 
 full_path_description :
-	'(' list_of_path_inputs opt_polarity_operator '*' '>' list_of_path_outputs ')' ;
+	'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
 
+// This was broken into 2 rules to solve shift/reduce conflicts
 list_of_path_inputs :
-	specify_input_terminal_descriptor |
-	list_of_path_inputs ',' specify_input_terminal_descriptor ;
-	
+	specify_input_terminal_descriptor                  opt_polarity_operator  |
+	specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
+
+more_path_inputs :
+    ',' specify_input_terminal_descriptor |
+    more_path_inputs ',' specify_input_terminal_descriptor ;
+
 list_of_path_outputs :
 	specify_output_terminal_descriptor |
 	list_of_path_outputs ',' specify_output_terminal_descriptor ;
@@ -747,11 +752,18 @@ specify_input_terminal_descriptor :
 specify_output_terminal_descriptor :
 	TOK_ID ;
 
-/*
 system_timing_declaration :
-	;
-*/
+	TOK_ID '(' system_timing_args ')' ';' ;
 
+system_timing_arg :
+	TOK_POSEDGE TOK_ID |
+	TOK_NEGEDGE TOK_ID |
+	expr ;
+
+system_timing_args :
+	system_timing_arg |
+	system_timing_args ',' system_timing_arg ;
+ 
 /*
 t_path_delay_expression :
 	path_delay_expression;

From fbfc677df3e54798faba3ab2f27c270759b96507 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Mon, 20 Aug 2018 17:27:45 +0300
Subject: [PATCH 068/528] Fixed all known specify/endspecify issues, without
 breaking 'make test'. Some the of parser fixes may look strange but they were
 needed to avoid shift/reduce conflicts, due to the explicit parentheses in
 path_delay_value, and the mintypmax values without parentheses

---
 frontends/verilog/verilog_parser.y | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 58a6824d1..2389d7d31 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -682,22 +682,23 @@ showcancelled_declaration :
 */
 
 path_declaration :
-	simple_path_declaration
+	simple_path_declaration ';'
 	// | edge_sensitive_path_declaration
 	// | state_dependent_path_declaration
 	;
 
 simple_path_declaration :
-	parallel_path_description '=' path_delay_value ';' |
-	full_path_description '=' path_delay_value ';'
+	parallel_path_description '=' path_delay_value |
+	full_path_description '=' path_delay_value
 	;
 
 path_delay_value :
-	list_of_path_delay_expressions |
-	%prec '(' list_of_path_delay_expressions ')'
+	'(' path_delay_expression list_of_path_delay_extra_expressions ')'
+	|     path_delay_expression
+	|     path_delay_expression list_of_path_delay_extra_expressions
 	;
 
-list_of_path_delay_expressions :
+list_of_path_delay_extra_expressions :
 /*
 	t_path_delay_expression
 	| trise_path_delay_expression ',' tfall_path_delay_expression
@@ -709,12 +710,11 @@ list_of_path_delay_expressions :
 	  t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
 	  tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
 */
-	path_delay_expression
-	| path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	',' path_delay_expression
+	|  ',' path_delay_expression ',' path_delay_expression
+	|  ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
-	| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
+	|  ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
 	  path_delay_expression ',' path_delay_expression ',' path_delay_expression
@@ -815,7 +815,7 @@ tzx_path_delay_expression :
 */
 
 path_delay_expression :
-	constant_mintypmax_expression;
+	constant_expression;
 
 constant_mintypmax_expression :
 	constant_expression

From 4b02ee91627c49bd4ea0e89d6c8531283501a24b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 22 Aug 2018 13:30:22 +0200
Subject: [PATCH 069/528] Add Verific -work parameter

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 26 ++++++++++++++++++--------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index b8c0375ce..cb31634dd 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1837,6 +1837,7 @@ struct VerificPass : public Pass {
 		log("Built with Verific %s, released at %s.\n", release_str, release_tmstr);
 
 		int argidx = 1;
+		std::string work = "work";
 
 		if (GetSize(args) > argidx && (args[argidx] == "-set-error" || args[argidx] == "-set-warning" ||
 				args[argidx] == "-set-info" || args[argidx] == "-set-ignore"))
@@ -1895,6 +1896,15 @@ struct VerificPass : public Pass {
 			goto check_error;
 		}
 
+		for (; argidx < GetSize(args); argidx++)
+		{
+			if (args[argidx] == "-work" && argidx+1 < GetSize(args)) {
+				work = args[++argidx];
+				continue;
+			}
+			break;
+		}
+
 		if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
 				args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
 		{
@@ -1942,7 +1952,7 @@ struct VerificPass : public Pass {
 			while (argidx < GetSize(args))
 				file_names.Insert(args[argidx++].c_str());
 
-			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, "work", veri_file::MFCU))
+			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU))
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 
 			verific_import_pending = true;
@@ -1952,7 +1962,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_87))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_87))
 					log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -1961,7 +1971,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_93))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_93))
 					log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -1970,7 +1980,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2K))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2K))
 					log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -1979,7 +1989,7 @@ struct VerificPass : public Pass {
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
 			for (argidx++; argidx < GetSize(args); argidx++)
-				if (!vhdl_file::Analyze(args[argidx].c_str(), "work", vhdl_file::VHDL_2008))
+				if (!vhdl_file::Analyze(args[argidx].c_str(), work.c_str(), vhdl_file::VHDL_2008))
 					log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", args[argidx].c_str());
 			verific_import_pending = true;
 			goto check_error;
@@ -2089,8 +2099,8 @@ struct VerificPass : public Pass {
 #else
 				log("Running hier_tree::ElaborateAll().\n");
 
-				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
-				VeriLibrary *veri_lib = veri_file::GetLibrary("work", 1);
+				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
+				VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
 
 				Array veri_libs, vhdl_libs;
 				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
@@ -2137,7 +2147,7 @@ struct VerificPass : public Pass {
 						continue;
 					}
 
-					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary("work", 1);
+					VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
 					VhdlDesignUnit *vhdl_unit = vhdl_lib->GetPrimUnit(name);
 					if (vhdl_unit) {
 						log("Adding VHDL unit '%s' to elaboration queue.\n", name);

From 408077769ff022f78f10ec1ffb60926361f8dc9f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 22 Aug 2018 17:22:24 +0200
Subject: [PATCH 070/528] Add "verific -work" help message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index cb31634dd..1dd6d7e24 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1706,11 +1706,18 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("Like -sv, but define FORMAL instead of SYNTHESIS.\n");
 		log("\n");
+		log("\n");
 		log("    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..\n");
 		log("\n");
 		log("Load the specified VHDL files into Verific.\n");
 		log("\n");
 		log("\n");
+		log("    verific -work <libname> {-sv|-vhdl|...} <hdl-file>\n");
+		log("\n");
+		log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
+		log("(default library when -work is not present: \"work\")\n");
+		log("\n");
+		log("\n");
 		log("    verific -vlog-incdir <directory>..\n");
 		log("\n");
 		log("Add Verilog include directories.\n");

From 042b3074f8096212b3f2114d353b2ec75818810b Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 23 Aug 2018 15:19:46 +0300
Subject: [PATCH 071/528] Added -no_dump_ptr flag for AST dump options in
 'read_verilog' This option disables the memory pointer display. This is
 useful when diff'ing different dumps because otherwise the node pointers
 makes every diff line different when the AST content is the same.

---
 frontends/ast/ast.cc                  | 15 +++++++++------
 frontends/ast/ast.h                   |  4 ++--
 frontends/verilog/verilog_frontend.cc | 10 +++++++++-
 3 files changed, 20 insertions(+), 9 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 7c72a50d9..e79be953a 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -44,7 +44,7 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
@@ -267,10 +267,12 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
 	std::string type_name = type2str(type);
 	fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
 
-	if (id2ast)
-		fprintf(f, " [%p -> %p]", this, id2ast);
-	else
-		fprintf(f, " [%p]", this);
+	if (!flag_no_dump_ptr) {
+		if (id2ast)
+			fprintf(f, " [%p -> %p]", this, id2ast);
+		else
+			fprintf(f, " [%p]", this);
+	}
 
 	if (!str.empty())
 		fprintf(f, " str='%s'", str.c_str());
@@ -1008,12 +1010,13 @@ static AstModule* process_module(AstNode *ast, bool defer)
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil,
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
 		bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
 {
 	current_ast = ast;
 	flag_dump_ast1 = dump_ast1;
 	flag_dump_ast2 = dump_ast2;
+	flag_no_dump_ptr = no_dump_ptr;
 	flag_dump_vlog = dump_vlog;
 	flag_dump_rtlil = dump_rtlil;
 	flag_nolatches = nolatches;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index d94199643..7e97bdb3b 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -274,7 +274,7 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
 			bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
@@ -305,7 +305,7 @@ namespace AST
 namespace AST_INTERNAL
 {
 	// internal state variables
-	extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	extern AST::AstNode *current_ast, *current_ast_mod;
 	extern std::map<std::string, AST::AstNode*> current_scope;
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 911e36112..8dcc7c5aa 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend {
 		log("    -dump_ast2\n");
 		log("        dump abstract syntax tree (after simplification)\n");
 		log("\n");
+		log("    -no_dump_ptr\n");
+		log("        do not include hex memory addresses in dump (easier to diff dumps)\n");
+		log("\n");
 		log("    -dump_vlog\n");
 		log("        dump ast as Verilog code (after simplification)\n");
 		log("\n");
@@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend {
 	{
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
+		bool flag_no_dump_ptr = false;
 		bool flag_dump_vlog = false;
 		bool flag_dump_rtlil = false;
 		bool flag_nolatches = false;
@@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend {
 				flag_dump_ast2 = true;
 				continue;
 			}
+			if (arg == "-no_dump_ptr") {
+				flag_no_dump_ptr = true;
+				continue;
+			}
 			if (arg == "-dump_vlog") {
 				flag_dump_vlog = true;
 				continue;
@@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;

From 93d19dc2fb35335607e67cab8ecf5ebe28268a1f Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Thu, 23 Aug 2018 14:35:11 -0700
Subject: [PATCH 072/528] Add support for module instances. Don't pad logical
 operands to one bit. Use operand width and signedness in $reduce_bool. Shift
 amounts are unsigned and shouldn't be padded. Group "is invalid" with the
 wire declaration, not its use (otherwise it is incorrectly wired to 0).

---
 backends/firrtl/firrtl.cc | 139 +++++++++++++++++++++++++++++++++-----
 1 file changed, 122 insertions(+), 17 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 4f56f498c..14fae1a83 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -28,10 +28,32 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+bool defparam, noattr;
 pool<string> used_names;
 dict<IdString, string> namecache;
 int autoid_counter;
 
+typedef unsigned FDirection;
+static const FDirection NODIRECTION = 0x0;
+static const FDirection IN = 0x1;
+static const FDirection OUT = 0x2;
+static const FDirection INOUT = 0x3;
+
+// Get a port direction with respect to a specific module.
+FDirection getPortFDirection(IdString id, Module *module)
+{
+	Wire *wire = module->wires_.at(id);
+	FDirection direction = NODIRECTION;
+	if (wire && wire->port_id)
+	{
+		if (wire->port_input)
+			direction |= IN;
+		if (wire->port_output)
+			direction |= OUT;
+	}
+	return direction;
+}
+
 string next_id()
 {
 	string new_id;
@@ -77,6 +99,8 @@ struct FirrtlWorker
 
 	dict<SigBit, pair<string, int>> reverse_wire_map;
 	string unconn_id;
+	RTLIL::Design *design;
+	std::string indent;
 
 	void register_reverse_wire_map(string id, SigSpec sig)
 	{
@@ -84,11 +108,11 @@ struct FirrtlWorker
 			reverse_wire_map[sig[i]] = make_pair(id, i);
 	}
 
-	FirrtlWorker(Module *module, std::ostream &f) : module(module), f(f)
+	FirrtlWorker(Module *module, std::ostream &f, RTLIL::Design *theDesign) : module(module), f(f), design(theDesign), indent("    ")
 	{
 	}
 
-	string make_expr(SigSpec sig)
+	string make_expr(const SigSpec &sig)
 	{
 		string expr;
 
@@ -135,6 +159,74 @@ struct FirrtlWorker
 		return expr;
 	}
 
+	std::string fid(RTLIL::IdString internal_id)
+	{
+		const char *str = internal_id.c_str();
+		return *str == '\\' ? str + 1 : str;
+	}
+
+
+	std::string cellname(RTLIL::Cell *cell)
+	{
+		return fid(cell->name).c_str();
+	}
+
+	void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
+	{
+		// TODO: Deal with cell attributes
+		if (!noattr && !cell->attributes.empty()) {
+
+		}
+		std::string cell_type = fid(cell->type);
+
+		// TODO: Deal with cell parameters
+		if (!defparam && cell->parameters.size() > 0) {
+
+		}
+
+		std::string cell_name = cellname(cell);
+		std::string cell_name_comment;
+		if (cell_name != fid(cell->name))
+			cell_name_comment = " /* " + fid(cell->name) + " */ ";
+		else
+			cell_name_comment = "";
+		// Find the module corresponding to this instance.
+		auto instModule = design->module(cell->type);
+		wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), cell_type.c_str()));
+
+		for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
+			if (it->second.size() > 0) {
+				const SigSpec &secondSig = it->second;
+				const std::string firstName = cell_name + "." + make_id(it->first);
+				const std::string secondName = make_expr(secondSig);
+				// Find the direction for this port.
+				FDirection dir = getPortFDirection(it->first, instModule);
+				std::string source, sink;
+				switch (dir) {
+					case INOUT:
+						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second));
+					case OUT:
+						source = firstName;
+						sink = secondName;
+						break;
+					case NODIRECTION:
+						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second));
+						/* FALL_THROUGH */
+					case IN:
+						source = secondName;
+						sink = firstName;
+						break;
+					default:
+						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", log_id(cell_type), log_signal(it->second), dir);
+						break;
+				}
+				wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sink.c_str(), source.c_str()));
+			}
+		}
+		wire_exprs.push_back(stringf("\n"));
+
+	}
+
 	void run()
 	{
 		f << stringf("  module %s:\n", make_id(module->name));
@@ -142,21 +234,28 @@ struct FirrtlWorker
 
 		for (auto wire : module->wires())
 		{
+			const auto wireName = make_id(wire->name);
 			if (wire->port_id)
 			{
 				if (wire->port_input && wire->port_output)
 					log_error("Module port %s.%s is inout!\n", log_id(module), log_id(wire));
 				port_decls.push_back(stringf("    %s %s: UInt<%d>\n", wire->port_input ? "input" : "output",
-						make_id(wire->name), wire->width));
+						wireName, wire->width));
 			}
 			else
 			{
-				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", make_id(wire->name), wire->width));
+				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", wireName, wire->width));
 			}
 		}
 
 		for (auto cell : module->cells())
 		{
+		  // Is this cell is a module instance?
+			if (cell->type[0] != '$')
+			{
+				process_instance(cell, wire_exprs);
+				continue;
+			}
 			if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
 			{
 				string y_id = make_id(cell->name);
@@ -169,7 +268,10 @@ struct FirrtlWorker
 					a_expr = "asSInt(" + a_expr + ")";
 				}
 
-				a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
+				// Don't use the results of logical operations (a single bit) to control padding
+				if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) {
+					a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
+				}
 
 				string primop;
                                 bool always_uint = false;
@@ -187,9 +289,12 @@ struct FirrtlWorker
                                         a_expr = stringf("xorr(%s)", a_expr.c_str());
                                 }
 				if (cell->type == "$reduce_bool") {
-                                        primop = "neq";
-                                        a_expr = stringf("%s, UInt(0)", a_expr.c_str());
-                                }
+					primop = "neq";
+					// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
+					bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
+					int a_width =  cell->parameters.at("\\A_WIDTH").as_int();
+					a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
+				}
 
 				string expr = stringf("%s(%s)", primop.c_str(), a_expr.c_str());
 
@@ -215,16 +320,16 @@ struct FirrtlWorker
 				if (cell->parameters.at("\\A_SIGNED").as_bool()) {
 					a_expr = "asSInt(" + a_expr + ")";
 				}
-				if (cell->parameters.at("\\A_SIGNED").as_bool()  & (cell->type != "$shr")) {
-					b_expr = "asSInt(" + b_expr + ")";
+				// Shift amount is always unsigned, and needn't be padded to result width.
+				if (!cell->type.in("$shr", "$sshr", "$shl", "$sshl")) {
+					if (cell->parameters.at("\\B_SIGNED").as_bool()) {
+						b_expr = "asSInt(" + b_expr + ")";
+					}
+					b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
 				}
 
 				a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
 
-				if ((cell->type != "$shl") && (cell->type != "$sshl")) {
-				        b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
-                                }
-
 				if (cell->parameters.at("\\A_SIGNED").as_bool()  & (cell->type == "$shr")) {
 					a_expr = "asUInt(" + a_expr + ")";
 				}
@@ -494,14 +599,14 @@ struct FirrtlWorker
 			if (is_valid) {
 				if (make_unconn_id) {
 					wire_decls.push_back(stringf("    wire %s: UInt<1>\n", unconn_id.c_str()));
-					cell_exprs.push_back(stringf("    %s is invalid\n", unconn_id.c_str()));
+					wire_decls.push_back(stringf("    %s is invalid\n", unconn_id.c_str()));
 				}
 				wire_exprs.push_back(stringf("    %s <= %s\n", make_id(wire->name), expr.c_str()));
 			} else {
 				if (make_unconn_id) {
 					unconn_id.clear();
 				}
-				wire_exprs.push_back(stringf("    %s is invalid\n", make_id(wire->name)));
+				wire_decls.push_back(stringf("    %s is invalid\n", make_id(wire->name)));
 			}
 		}
 
@@ -570,7 +675,7 @@ struct FirrtlBackend : public Backend {
 
 		for (auto module : design->modules())
 		{
-			FirrtlWorker worker(module, *f);
+			FirrtlWorker worker(module, *f, design);
 			worker.run();
 		}
 

From 306a010e199d9318472c9c08eb16117bd83c7257 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 25 Aug 2018 16:20:44 +0200
Subject: [PATCH 073/528] static link flag on main executable

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index c1e5c789d..18bf303b1 100644
--- a/Makefile
+++ b/Makefile
@@ -158,7 +158,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
-LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s
+LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
 LDLIBS := $(filter-out -lrt,$(LDLIBS)) 
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 CXXFLAGS += -std=c++11 -Os

From 9e845bd25460d7b8287cf3ea5147040689940f49 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 27 Aug 2018 13:27:05 +0200
Subject: [PATCH 074/528] Add ENABLE_GCOV build option

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Makefile b/Makefile
index 18bf303b1..7eb3971f7 100644
--- a/Makefile
+++ b/Makefile
@@ -19,6 +19,7 @@ ENABLE_LIBYOSYS := 0
 ENABLE_PROTOBUF := 0
 
 # other configuration flags
+ENABLE_GCOV := 0
 ENABLE_GPROF := 0
 ENABLE_DEBUG := 0
 ENABLE_NDEBUG := 0
@@ -312,6 +313,11 @@ endif
 endif
 endif
 
+ifeq ($(ENABLE_GCOV),1)
+CXXFLAGS += --coverage
+LDFLAGS += --coverage
+endif
+
 ifeq ($(ENABLE_GPROF),1)
 CXXFLAGS += -pg
 LDFLAGS += -pg
@@ -709,6 +715,11 @@ config-msys2: clean
 config-msys2-64: clean
 	echo 'CONFIG := msys2-64' > Makefile.conf
 
+config-gcov: clean
+	echo 'CONFIG := gcc' > Makefile.conf
+	echo 'ENABLE_GCOV := 1' >> Makefile.conf
+	echo 'ENABLE_DEBUG := 1' >> Makefile.conf
+
 config-gprof: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 	echo 'ENABLE_GPROF := 1' >> Makefile.conf

From ddc1761f1a443ea9560c67cfc126160ba7254a39 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 27 Aug 2018 14:22:21 +0200
Subject: [PATCH 075/528] Add "make coverage"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .gitignore                        | 4 ++++
 Makefile                          | 8 +++++++-
 frontends/ilang/.gitignore        | 2 +-
 frontends/ilang/Makefile.inc      | 7 +++----
 frontends/ilang/ilang_lexer.l     | 2 +-
 frontends/verilog/.gitignore      | 2 +-
 frontends/verilog/Makefile.inc    | 7 +++----
 frontends/verilog/verilog_lexer.l | 2 +-
 8 files changed, 21 insertions(+), 13 deletions(-)

diff --git a/.gitignore b/.gitignore
index cd624f233..4fce690ec 100644
--- a/.gitignore
+++ b/.gitignore
@@ -2,6 +2,8 @@
 *.d
 .*.swp
 *.gch
+*.gcda
+*.gcno
 /.cproject
 /.project
 /.settings
@@ -10,6 +12,8 @@
 /qtcreator.config
 /qtcreator.creator
 /qtcreator.creator.user
+/coverage.info
+/coverage_html
 /Makefile.conf
 /abc
 /viz.js
diff --git a/Makefile b/Makefile
index 7eb3971f7..39a361a5f 100644
--- a/Makefile
+++ b/Makefile
@@ -650,6 +650,12 @@ clean-abc:
 mrproper: clean
 	git clean -xdf
 
+coverage:
+	./yosys -qp 'help; help -all'
+	rm -rf coverage.info coverage_html
+	lcov --capture -d . --no-external -o coverage.info
+	genhtml coverage.info --output-directory coverage_html
+
 qtcreator:
 	{ for file in $(basename $(OBJS)); do \
 		for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \
@@ -740,6 +746,6 @@ echo-git-rev:
 -include kernel/*.d
 -include techlibs/*/*.d
 
-.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator
+.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator coverage vcxsrc mxebin
 .PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo
 
diff --git a/frontends/ilang/.gitignore b/frontends/ilang/.gitignore
index 43106a814..f586b33c7 100644
--- a/frontends/ilang/.gitignore
+++ b/frontends/ilang/.gitignore
@@ -1,4 +1,4 @@
 ilang_lexer.cc
 ilang_parser.output
 ilang_parser.tab.cc
-ilang_parser.tab.h
+ilang_parser.tab.hh
diff --git a/frontends/ilang/Makefile.inc b/frontends/ilang/Makefile.inc
index e2a476c93..6f1f0e8fc 100644
--- a/frontends/ilang/Makefile.inc
+++ b/frontends/ilang/Makefile.inc
@@ -1,15 +1,14 @@
 
 GENFILES += frontends/ilang/ilang_parser.tab.cc
-GENFILES += frontends/ilang/ilang_parser.tab.h
+GENFILES += frontends/ilang/ilang_parser.tab.hh
 GENFILES += frontends/ilang/ilang_parser.output
 GENFILES += frontends/ilang/ilang_lexer.cc
 
 frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser $<
-	$(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc
+	$(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $<
 
-frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc
+frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc
 
 frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l
 	$(Q) mkdir -p $(dir $@)
diff --git a/frontends/ilang/ilang_lexer.l b/frontends/ilang/ilang_lexer.l
index 842388548..d8e01ae4d 100644
--- a/frontends/ilang/ilang_lexer.l
+++ b/frontends/ilang/ilang_lexer.l
@@ -30,7 +30,7 @@
 #endif
 
 #include "frontends/ilang/ilang_frontend.h"
-#include "ilang_parser.tab.h"
+#include "ilang_parser.tab.hh"
 
 USING_YOSYS_NAMESPACE
 
diff --git a/frontends/verilog/.gitignore b/frontends/verilog/.gitignore
index 1d4ae9e5c..aadbcdcdd 100644
--- a/frontends/verilog/.gitignore
+++ b/frontends/verilog/.gitignore
@@ -1,4 +1,4 @@
 verilog_lexer.cc
 verilog_parser.output
 verilog_parser.tab.cc
-verilog_parser.tab.h
+verilog_parser.tab.hh
diff --git a/frontends/verilog/Makefile.inc b/frontends/verilog/Makefile.inc
index a06c1d5ab..dbaace585 100644
--- a/frontends/verilog/Makefile.inc
+++ b/frontends/verilog/Makefile.inc
@@ -1,15 +1,14 @@
 
 GENFILES += frontends/verilog/verilog_parser.tab.cc
-GENFILES += frontends/verilog/verilog_parser.tab.h
+GENFILES += frontends/verilog/verilog_parser.tab.hh
 GENFILES += frontends/verilog/verilog_parser.output
 GENFILES += frontends/verilog/verilog_lexer.cc
 
 frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
 	$(Q) mkdir -p $(dir $@)
-	$(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $<
-	$(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc
+	$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
 
-frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc
+frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
 
 frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
 	$(Q) mkdir -p $(dir $@)
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 0134416c1..83921bf0b 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -42,7 +42,7 @@
 #include "kernel/log.h"
 #include "frontends/verilog/verilog_frontend.h"
 #include "frontends/ast/ast.h"
-#include "verilog_parser.tab.h"
+#include "verilog_parser.tab.hh"
 
 USING_YOSYS_NAMESPACE
 using namespace AST;

From 380c6f0e978869099d5b2c5dd81d8065a1f5c3cc Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Mon, 27 Aug 2018 10:18:33 -0700
Subject: [PATCH 076/528] Remove unused functions.

---
 backends/firrtl/firrtl.cc | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 14fae1a83..94236d0b1 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -28,7 +28,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-bool defparam, noattr;
 pool<string> used_names;
 dict<IdString, string> namecache;
 int autoid_counter;
@@ -173,17 +172,8 @@ struct FirrtlWorker
 
 	void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
 	{
-		// TODO: Deal with cell attributes
-		if (!noattr && !cell->attributes.empty()) {
-
-		}
 		std::string cell_type = fid(cell->type);
 
-		// TODO: Deal with cell parameters
-		if (!defparam && cell->parameters.size() > 0) {
-
-		}
-
 		std::string cell_name = cellname(cell);
 		std::string cell_name_comment;
 		if (cell_name != fid(cell->name))

From 92896a58beb66d633f787c30ec291f6be8d9e0e0 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Tue, 28 Aug 2018 13:11:41 +0200
Subject: [PATCH 077/528] Remove mercurial, since it is not needed anymore

---
 .travis.yml | 5 -----
 Brewfile    | 1 -
 2 files changed, 6 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index fbb4018af..321c3325f 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -28,7 +28,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -53,7 +52,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -78,7 +76,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -104,7 +101,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
@@ -129,7 +125,6 @@ matrix:
             - tcl-dev
             - libffi-dev
             - git
-            - mercurial
             - graphviz
             - xdot
             - pkg-config
diff --git a/Brewfile b/Brewfile
index d7cd05bf1..0c58ce161 100644
--- a/Brewfile
+++ b/Brewfile
@@ -3,7 +3,6 @@ brew "flex"
 brew "gawk"
 brew "libffi"
 brew "git"
-brew "mercurial"
 brew "graphviz"
 brew "pkg-config"
 brew "python3"

From d36d11936f6725b9fc0702e9406bc55533d8e273 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Tue, 28 Aug 2018 08:17:33 -0700
Subject: [PATCH 078/528] Add GCC to osx deps (#620)

* Add GCC to osx deps

* Force gcc-7 install
---
 .travis/setup.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis/setup.sh b/.travis/setup.sh
index 81ff37742..068515786 100755
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -64,7 +64,7 @@ if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
 		brew tap Homebrew/bundle
 		brew bundle
 		brew install ccache
-		brew install gcc
+		brew install gcc@7
 		echo
 		echo -en 'travis_fold:end:before_install.brew\\r'
 		echo

From 0b7a18470bbd35214fdeff204f9c20964e69b5c5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 30 Aug 2018 12:26:26 +0200
Subject: [PATCH 079/528] Add "make ystests"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .gitignore   | 1 +
 CodingReadme | 1 +
 Makefile     | 8 ++++++++
 3 files changed, 10 insertions(+)

diff --git a/.gitignore b/.gitignore
index 4fce690ec..48ce458c7 100644
--- a/.gitignore
+++ b/.gitignore
@@ -34,3 +34,4 @@
 /libyosys.so
 /tests/unit/bintest/
 /tests/unit/objtest/
+/tests/ystests
diff --git a/CodingReadme b/CodingReadme
index 4ab132a63..b64e79178 100644
--- a/CodingReadme
+++ b/CodingReadme
@@ -373,6 +373,7 @@ Finally run all tests with "make config-{clang,gcc,gcc-4.8}":
 	cd ~yosys
 	make clean
 	make test
+	make ystests
 	make vloghtb
 	make install
 
diff --git a/Makefile b/Makefile
index 39a361a5f..7698047ec 100644
--- a/Makefile
+++ b/Makefile
@@ -585,6 +585,14 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 	@echo "  Passed \"make vloghtb\"."
 	@echo ""
 
+ystests: $(TARGETS) $(EXTRA_TARGETS)
+	rm -rf tests/ystests
+	git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests
+	+PATH="$$PWD:$$PATH" cd tests/ystests && $(MAKE)
+	@echo ""
+	@echo "  Finished \"make ystests\"."
+	@echo ""
+
 # Unit test
 unit-test: libyosys.so
 	@$(MAKE) -C $(UNITESTPATH) CXX="$(CXX)" CPPFLAGS="$(CPPFLAGS)" \

From 5d9d22f66d512d33b2c1a13c4f1a20f944e6acc3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 4 Sep 2018 20:06:10 +0200
Subject: [PATCH 080/528] Add "verific -L <int>" option

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc    | 11 +++++++++++
 frontends/verific/verific.h     |  2 ++
 frontends/verific/verificsva.cc |  5 +++--
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 1dd6d7e24..c5fa58313 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -64,6 +64,7 @@ YOSYS_NAMESPACE_BEGIN
 int verific_verbose;
 bool verific_import_pending;
 string verific_error_msg;
+int verific_sva_fsm_limit;
 
 vector<string> verific_incdirs, verific_libdirs;
 
@@ -1618,6 +1619,8 @@ struct VerificExtNets
 
 void verific_import(Design *design, std::string top)
 {
+	verific_sva_fsm_limit = 16;
+
 	std::set<Netlist*> nl_todo, nl_done;
 
 	{
@@ -1789,6 +1792,9 @@ struct VerificPass : public Pass {
 		log("  -nosva\n");
 		log("    Ignore SVA properties, do not infer checker logic.\n");
 		log("\n");
+		log("  -L <int>\n");
+		log("    Maximum number of ctrl bits for SVA checker FSMs (default=16).\n");
+		log("\n");
 		log("  -n\n");
 		log("    Keep all Verific names on instances and nets. By default only\n");
 		log("    user-declared names are preserved.\n");
@@ -1830,6 +1836,7 @@ struct VerificPass : public Pass {
 		}
 
 		verific_verbose = 0;
+		verific_sva_fsm_limit = 16;
 
 		const char *release_str = Message::ReleaseString();
 		time_t release_time = Message::ReleaseDate();
@@ -2036,6 +2043,10 @@ struct VerificPass : public Pass {
 					mode_nosva = true;
 					continue;
 				}
+				if (args[argidx] == "-L" && argidx+1 < GetSize(args)) {
+					verific_sva_fsm_limit = atoi(args[++argidx].c_str());
+					continue;
+				}
 				if (args[argidx] == "-n") {
 					mode_names = true;
 					continue;
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index cbd9314db..334a436af 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -101,6 +101,8 @@ void verific_import_sva_cover(VerificImporter *importer, Verific::Instance *inst
 void verific_import_sva_trigger(VerificImporter *importer, Verific::Instance *inst);
 bool verific_is_sva_net(VerificImporter *importer, Verific::Net *net);
 
+extern int verific_sva_fsm_limit;
+
 YOSYS_NAMESPACE_END
 
 #endif
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 85b842186..cdc9ece8c 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -466,13 +466,14 @@ struct SvaFsm
 
 		dnode.ctrl.sort_and_unify();
 
-		if (GetSize(dnode.ctrl) > 16) {
+		if (GetSize(dnode.ctrl) > verific_sva_fsm_limit) {
 			if (verific_verbose >= 2) {
 				log("    detected state explosion in DFSM generation:\n");
 				dump();
 				log("      ctrl signal: %s\n", log_signal(dnode.ctrl));
 			}
-			log_error("SVA DFSM state ctrl signal has %d (>16) bits. Stopping to prevent exponential design size explosion.\n", GetSize(dnode.ctrl));
+			log_error("SVA DFSM state ctrl signal has %d (>%d) bits. Stopping to prevent exponential design size explosion.\n",
+					GetSize(dnode.ctrl), verific_sva_fsm_limit);
 		}
 
 		for (int i = 0; i < (1 << GetSize(dnode.ctrl)); i++)

From 12440fcc8f705c117b5f91fae24b7e5c4fbf8560 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Sep 2018 00:18:01 +0200
Subject: [PATCH 081/528] Add $lut support to Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 44e4e5f97..d3262ec47 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -779,6 +779,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$lut")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		dump_const(f, cell->parameters.at("\\LUT"));
+		f << stringf(" >> ");
+		dump_attributes(f, "", cell->attributes, ' ');
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(";\n");
+		return true;
+	}
+
 	if (cell->type == "$dffsr")
 	{
 		SigSpec sig_clk = cell->getPort("\\CLK");

From 51f1bbeeb08020a9b739d2bd0cf4d79ca6e62015 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 10 Sep 2018 11:57:24 +0200
Subject: [PATCH 082/528] Add iCE40 SB_SPRAM256KA simulation model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v | 39 +++++++++++++++++++++++++++++---------
 1 file changed, 30 insertions(+), 9 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 9f73aeb07..e0a07af32 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -920,19 +920,40 @@ parameter A_SIGNED = 1'b0;
 parameter B_SIGNED = 1'b0;
 endmodule
 
-(* blackbox *)
-module SB_SPRAM256KA(
+module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
 	input [3:0] MASKWREN,
-	input WREN,
-	input CHIPSELECT,
-	input CLOCK,
-	input STANDBY,
-	input SLEEP,
-	input POWEROFF,
-	output [15:0] DATAOUT
+	input WREN, CHIPSELECT, CLOCK, STANDBY, SLEEP, POWEROFF,
+	output reg [15:0] DATAOUT
 );
+`ifndef BLACKBOX
+	reg [15:0] mem [0:16383];
+	wire off = SLEEP || !POWEROFF;
+	integer i;
+
+	always @(negedge POWEROFF) begin
+		for (i = 0; i <= 16383; i = i+1)
+			mem[i] = 'bx;
+	end
+
+	always @(posedge CLOCK, posedge off) begin
+		if (off) begin
+			DATAOUT <= 0;
+		end else
+		if (CHIPSELECT && !STANDBY && !WREN) begin
+			DATAOUT <= mem[ADDRESS];
+		end else begin
+			if (CHIPSELECT && !STANDBY && WREN) begin
+				if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
+				if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
+				if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
+				if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
+			end
+			DATAOUT <= 'bx;
+		end
+	end
+`endif
 endmodule
 
 (* blackbox *)

From 75c1f8d241d67ebb6db56516b4f9fdb0a312aa0b Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Mon, 10 Sep 2018 21:44:36 -0400
Subject: [PATCH 083/528] Minor revision to -expose in setundef pass

Adds default value option as -undef when -expose used. Not having set the value mode set can cause the setundef pass to abort.
---
 passes/cmds/setundef.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 62d940ce6..a1dfa9b5c 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -162,7 +162,6 @@ struct SetundefPass : public Pass {
 				continue;
 			}
 			if (args[argidx] == "-expose") {
-				got_value = true;
 				expose_mode = true;
 				continue;
 			}
@@ -212,6 +211,13 @@ struct SetundefPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		if (!got_value && expose_mode) {
+			log("Using default as -undef with -expose.\n");
+			got_value = true;
+			worker.next_bit_mode = MODE_UNDEF;
+			worker.next_bit_state = 0;
+		}
+
 		if (expose_mode && !undriven_mode)
 			log_cmd_error("Option -expose must be used with option -undriven.\n");
 		if (!got_value)

From 5fe16c25b81d507fa41381eca70c5aada59db25f Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Wed, 12 Sep 2018 18:33:27 -0400
Subject: [PATCH 084/528] Fixed minor typo in "sim" help message

---
 passes/sat/sim.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc
index fadffcdbc..53e248adf 100644
--- a/passes/sat/sim.cc
+++ b/passes/sat/sim.cc
@@ -778,7 +778,7 @@ struct SimPass : public Pass {
 		log("        number of cycles to simulate (default: 20)\n");
 		log("\n");
 		log("    -a\n");
-		log("        include all nets in VCD output, nut just those with public names\n");
+		log("        include all nets in VCD output, not just those with public names\n");
 		log("\n");
 		log("    -w\n");
 		log("        writeback mode: use final simulation state as new init state\n");

From f6fe73b31f6e6d8966ad4ddae860b4d79133cce2 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 18 Sep 2018 01:23:40 +0300
Subject: [PATCH 085/528] Fixed remaining cases where we check fo wire reg/wire
 incorrect assignments on Yosys-generated assignments. In this case, offending
 code was:

module top(input in, output out);
function func;
  input arg;
  func = arg;
endfunction
assign out = func(in);
endmodule
---
 frontends/ast/simplify.cc | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index a9608369c..ae46e4bc9 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1337,6 +1337,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			str.clear();
 			type = AST_ASSIGN;
 			children.push_back(children_list.at(0));
+			children.back()->was_checked = true;
 			children.push_back(node);
 			did_something = true;
 		}
@@ -1373,6 +1374,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			str.clear();
 			type = AST_ASSIGN;
 			children.push_back(children_list[0]);
+			children.back()->was_checked = true;
 			children.push_back(node);
 			did_something = true;
 		}
@@ -1531,6 +1533,7 @@ skip_dynamic_range_lvalue_expansion:;
 			wire_tmp_id->str = wire_tmp->str;
 
 			newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, wire_tmp_id, children[1]->clone()));
+			newNode->children.back()->was_checked = true;
 
 			int cursor = 0;
 			for (auto child : children[0]->children)
@@ -1816,6 +1819,7 @@ skip_dynamic_range_lvalue_expansion:;
 					AstNode *regid = new AstNode(AST_IDENTIFIER);
 					regid->str = reg->str;
 					regid->id2ast = reg;
+					regid->was_checked = true;
 
 					AstNode *rhs = nullptr;
 
@@ -2202,6 +2206,8 @@ skip_dynamic_range_lvalue_expansion:;
 
 			AstNode *always = new AstNode(AST_ALWAYS, new AstNode(AST_BLOCK,
 					new AstNode(AST_ASSIGN_EQ, lvalue, clone())));
+			always->children[0]->children[0]->was_checked = true;
+
 			current_ast_mod->children.push_back(always);
 
 			goto replace_fcall_with_id;
@@ -2251,6 +2257,7 @@ skip_dynamic_range_lvalue_expansion:;
 						AstNode *assign = child->is_input ?
 								new AstNode(AST_ASSIGN_EQ, wire_id->clone(), arg) :
 								new AstNode(AST_ASSIGN_EQ, arg, wire_id->clone());
+						assign->children[0]->was_checked = true;
 
 						for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
 							if (*it != current_block_child)
@@ -2321,6 +2328,7 @@ skip_dynamic_range_lvalue_expansion:;
 					AstNode *assign = child->is_input ?
 							new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
 							new AstNode(AST_ASSIGN_EQ, arg, wire_id);
+					assign->children[0]->was_checked = true;
 
 					for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
 						if (*it != current_block_child)
@@ -2760,6 +2768,7 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
 				block->children.push_back(new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER, new AstNode(AST_RANGE, AstNode::mkconst_int(cursor, false))), value));
 				block->children.back()->children[0]->str = memory->str;
 				block->children.back()->children[0]->id2ast = memory;
+				block->children.back()->children[0]->was_checked = true;
 			}
 
 			cursor += increment;
@@ -3021,6 +3030,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		AstNode *newNode = clone();
 		newNode->type = AST_ASSIGN_EQ;
 		async_block->children[0]->children.push_back(newNode);
+		async_block->children[0]->children.back()->children[0]->was_checked = true;
 
 		newNode = new AstNode(AST_NONE);
 		newNode->cloneInto(this);
@@ -3065,6 +3075,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 
 		AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
 		assign_addr->children[0]->str = id_addr;
+		assign_addr->children[0]->str = was_checked;
 		block->children.insert(block->children.begin()+assign_idx+1, assign_addr);
 
 		AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));
@@ -3088,6 +3099,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 		children[0]->id2ast = NULL;
 		children[0]->str = id_data;
 		type = AST_ASSIGN_EQ;
+		children[0]->was_checked = true;
 
 		did_something = true;
 	}

From efac8a45a6965bdcbb7fb810d657d2c63b6cb7fe Mon Sep 17 00:00:00 2001
From: acw1251 <acwright@mit.edu>
Date: Tue, 18 Sep 2018 13:34:30 -0400
Subject: [PATCH 086/528] Fixed typo in "verilog_write" help message

---
 backends/verilog/verilog_backend.cc | 6 +++---
 manual/command-reference-manual.tex | 4 ++--
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d3262ec47..ae9031510 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1523,7 +1523,7 @@ struct VerilogBackend : public Backend {
 		log("\n");
 		log("    -nodec\n");
 		log("        32-bit constant values are by default dumped as decimal numbers,\n");
-		log("        not bit pattern. This option decativates this feature and instead\n");
+		log("        not bit pattern. This option deactivates this feature and instead\n");
 		log("        will write out all constants in binary.\n");
 		log("\n");
 		log("    -decimal\n");
@@ -1531,13 +1531,13 @@ struct VerilogBackend : public Backend {
 		log("\n");
 		log("    -nohex\n");
 		log("        constant values that are compatible with hex output are usually\n");
-		log("        dumped as hex values. This option decativates this feature and\n");
+		log("        dumped as hex values. This option deactivates this feature and\n");
 		log("        instead will write out all constants in binary.\n");
 		log("\n");
 		log("    -nostr\n");
 		log("        Parameters and attributes that are specified as strings in the\n");
 		log("        original input will be output as strings by this back-end. This\n");
-		log("        decativates this feature and instead will write string constants\n");
+		log("        deactivates this feature and instead will write string constants\n");
 		log("        as binary numbers.\n");
 		log("\n");
 		log("    -defparam\n");
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 8af8ccdd0..fea2354e6 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -4421,13 +4421,13 @@ Write the current design to a Verilog file.
 
     -nodec
         32-bit constant values are by default dumped as decimal numbers,
-        not bit pattern. This option decativates this feature and instead
+        not bit pattern. This option deactivates this feature and instead
         will write out all constants in binary.
 
     -nostr
         Parameters and attributes that are specified as strings in the
         original input will be output as strings by this back-end. This
-        decativates this feature and instead will write string constants
+        deactivates this feature and instead will write string constants
         as binary numbers.
 
     -defparam

From c5e9034834ce0bcc6f6c611bc3ad3d244a32732f Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 19 Sep 2018 10:16:53 +0200
Subject: [PATCH 087/528] Fix Cygwin build and document needed packages

---
 Makefile        | 9 +++++++++
 README.md       | 4 ++++
 kernel/yosys.cc | 2 +-
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 7698047ec..365b92ea4 100644
--- a/Makefile
+++ b/Makefile
@@ -175,6 +175,12 @@ LD = gcc-4.8
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 
+else ifeq ($(CONFIG),cygwin)
+CXX = gcc
+LD = gcc
+CXXFLAGS += -std=gnu++11 -Os
+ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
+
 else ifeq ($(CONFIG),emcc)
 CXX = emcc
 LD = emcc
@@ -729,6 +735,9 @@ config-msys2: clean
 config-msys2-64: clean
 	echo 'CONFIG := msys2-64' > Makefile.conf
 
+config-cygwin: clean
+	echo 'CONFIG := cygwin' > Makefile.conf
+
 config-gcov: clean
 	echo 'CONFIG := gcc' > Makefile.conf
 	echo 'ENABLE_GCOV := 1' >> Makefile.conf
diff --git a/README.md b/README.md
index 424d9bbf2..41ae4ac18 100644
--- a/README.md
+++ b/README.md
@@ -69,6 +69,10 @@ On FreeBSD use the following command to install all prerequisites:
 On FreeBSD system use gmake instead of make. To run tests use:
     % MAKE=gmake CC=cc gmake test
 
+For Cygwin use the following command to install all prerequisites, or select these additional packages:
+
+	setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel
+
 There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
 as a source distribution for Visual Studio. Visit the Yosys download page for
 more information: http://www.clifford.at/yosys/download.html
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 264b1f63d..ad032899c 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -166,7 +166,7 @@ std::string vstringf(const char *fmt, va_list ap)
 	std::string string;
 	char *str = NULL;
 
-#ifdef _WIN32
+#if defined(_WIN32 )|| defined(__CYGWIN__) 
 	int sz = 64, rc;
 	while (1) {
 		va_list apc;

From bf189122a8d73f071c003a4035986cc37e2d4a31 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Sep 2018 13:55:20 +0200
Subject: [PATCH 088/528] Update Changelog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 54 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG b/CHANGELOG
index 01c78ab3b..f09e21f89 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,9 +3,62 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???
+Yosys 0.7 .. Yosys ???    (2017-07-07)
 ----------------------
 
+ * Various
+    - Many bugfixes and small improvements
+    - Added write_verilog hex dump support, add -nohex option
+    - Added "scc -set_attr"
+    - Added "verilog_defines" command
+    - Remeber defines from one read_verilog to next
+    - Added support for hierarchical defparam
+    - Added FIRRTL back-end
+    - Improved ABC default scripts
+    - Added "design -reset-vlog"
+    - Added "yosys -W regex" and "yosys -w regex"
+    - Added Verilog $rtoi and $itor support
+    - Added "check -initdrv"
+    - Added "read_blif -wideports"
+    - Added support for systemVerilog "++" and "--" operators
+    - Added support for SystemVerilog unique, unique0, and priority case
+    - Added "write_edif" options for edif "flavors"
+    - Added support for resetall compiler directive
+    - Added simple C beck-end (bitwise combinatorical only atm)
+    - Added $_ANDNOT_ and $_ORNOT_ cell types
+    - Added cell library aliases to "abc -g"
+    - Added "setundef -anyseq"
+    - Added "chtype" command
+    - Added "design -import"
+    - Added "write_table" command
+
+ * Changes in Yosys APIs
+    - Added ConstEval defaultval feature
+
+ * Formal Verification
+    - Added "write_aiger"
+    - Added "yosys-smtbmc --aig"
+    - Added "always <positive_int>" to .smtc format
+    - Added $cover cell type and support for cover properties
+    - Added $fair/$live cell type and support for liveness properties
+    - Added smtbmc support for memory vcd dumping
+    - Added "chformal" command
+    - Added "write_smt2 -stbv" and "write_smt2 -stdt"
+    - Fix equiv_simple, old behavior now available with "equiv_simple -short"
+    - Change to Yices2 as default SMT solver (it is GPL now)
+    - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
+
+ * Verific support
+    - Many improvements in Verific front-end
+    - Add proper handling of concurent SVA properties
+    - Map "const" and "rand const" to $anyseq/$anyconst
+
+ * GreenPAK Support
+    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNT, etc.
+
+ * Coolrunner-II Support
+    - Added initial Coolrunner-II support
+
  * MAX10 and Cyclone IV Support
     - Added initial version of metacommand "synth_intel".
     - Improved write_verilog command to produce VQM netlist for Quartus Prime.

From 2867bf46a9265836bcdda3429f74281530c8c26d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 21 Sep 2018 16:27:07 +0200
Subject: [PATCH 089/528] Update CHANGLELOG

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index f09e21f89..c1e93c37d 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,12 +3,13 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???    (2017-07-07)
+Yosys 0.7 .. Yosys ???    (2017-12-12)
 ----------------------
 
  * Various
     - Many bugfixes and small improvements
     - Added write_verilog hex dump support, add -nohex option
+    - Added "write_verilog -decimal"
     - Added "scc -set_attr"
     - Added "verilog_defines" command
     - Remeber defines from one read_verilog to next
@@ -31,9 +32,20 @@ Yosys 0.7 .. Yosys ???    (2017-07-07)
     - Added "chtype" command
     - Added "design -import"
     - Added "write_table" command
+    - Added "read_json" command
+    - Added "sim" command
+    - Added "extract_fa" and "extract_reduce" commands
+    - Added "extract_counter" command
+    - Added "opt_demorgan" command
+    - Added support for $size and $bits SystemVerilog functions
+    - Added "blackbox" command
+    - Added "ltp" command
+    - Added support for editline as replacement for readline
+    - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
 
  * Changes in Yosys APIs
     - Added ConstEval defaultval feature
+    - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
 
  * Formal Verification
     - Added "write_aiger"
@@ -47,17 +59,27 @@ Yosys 0.7 .. Yosys ???    (2017-07-07)
     - Fix equiv_simple, old behavior now available with "equiv_simple -short"
     - Change to Yices2 as default SMT solver (it is GPL now)
     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
+    - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
+    - Added a brand new "write_btor" command for BTOR2
 
  * Verific support
     - Many improvements in Verific front-end
-    - Add proper handling of concurent SVA properties
+    - Added proper handling of concurent SVA properties
     - Map "const" and "rand const" to $anyseq/$anyconst
+    - Added "verific -import -flatten" and "verific -import -extnets"
+    - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
+    - Remove PSL support (because PSL has been removed in upstream Verific)
+
+ * New back-ends
+    - Added initial Coolrunner-II support
+    - Added initial eASIC support
 
  * GreenPAK Support
-    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNT, etc.
+    - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 
- * Coolrunner-II Support
-    - Added initial Coolrunner-II support
+ * iCE40 Support
+    - Add "synth_ice40 -vpr"
+    - Add Support for UltraPlus cells
 
  * MAX10 and Cyclone IV Support
     - Added initial version of metacommand "synth_intel".

From 41affeeeb9935db73bb2774e74e6038a70cf667d Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 21 Sep 2018 20:43:49 +0200
Subject: [PATCH 090/528] added prefix to FDirection constants, fixing windows
 build

---
 backends/firrtl/firrtl.cc | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 94236d0b1..32410a651 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -33,22 +33,22 @@ dict<IdString, string> namecache;
 int autoid_counter;
 
 typedef unsigned FDirection;
-static const FDirection NODIRECTION = 0x0;
-static const FDirection IN = 0x1;
-static const FDirection OUT = 0x2;
-static const FDirection INOUT = 0x3;
+static const FDirection FD_NODIRECTION = 0x0;
+static const FDirection FD_IN = 0x1;
+static const FDirection FD_OUT = 0x2;
+static const FDirection FD_INOUT = 0x3;
 
 // Get a port direction with respect to a specific module.
 FDirection getPortFDirection(IdString id, Module *module)
 {
 	Wire *wire = module->wires_.at(id);
-	FDirection direction = NODIRECTION;
+	FDirection direction = FD_NODIRECTION;
 	if (wire && wire->port_id)
 	{
 		if (wire->port_input)
-			direction |= IN;
+			direction |= FD_IN;
 		if (wire->port_output)
-			direction |= OUT;
+			direction |= FD_OUT;
 	}
 	return direction;
 }
@@ -193,16 +193,16 @@ struct FirrtlWorker
 				FDirection dir = getPortFDirection(it->first, instModule);
 				std::string source, sink;
 				switch (dir) {
-					case INOUT:
+					case FD_INOUT:
 						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second));
-					case OUT:
+					case FD_OUT:
 						source = firstName;
 						sink = secondName;
 						break;
-					case NODIRECTION:
+					case FD_NODIRECTION:
 						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second));
 						/* FALL_THROUGH */
-					case IN:
+					case FD_IN:
 						source = secondName;
 						sink = firstName;
 						break;

From 138ba7126414a3d524e7edfbbce2bdf590ac8a21 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Sep 2018 09:25:40 +0200
Subject: [PATCH 091/528] Update CHANGELOG

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 37 +++++++++++++++++++++++++++++++++++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/CHANGELOG b/CHANGELOG
index c1e93c37d..5499c309a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,11 +3,13 @@ List of major changes and improvements between releases
 =======================================================
 
 
-Yosys 0.7 .. Yosys ???    (2017-12-12)
+Yosys 0.7 .. Yosys 0.8
 ----------------------
 
  * Various
     - Many bugfixes and small improvements
+    - Strip debug symbols from installed binary
+    - Replace -ignore_redef with -[no]overwrite in front-ends
     - Added write_verilog hex dump support, add -nohex option
     - Added "write_verilog -decimal"
     - Added "scc -set_attr"
@@ -17,7 +19,7 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added FIRRTL back-end
     - Improved ABC default scripts
     - Added "design -reset-vlog"
-    - Added "yosys -W regex" and "yosys -w regex"
+    - Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
     - Added Verilog $rtoi and $itor support
     - Added "check -initdrv"
     - Added "read_blif -wideports"
@@ -42,10 +44,25 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "ltp" command
     - Added support for editline as replacement for readline
     - Added warnings for driver-driver conflicts between FFs (and other cells) and constants
+    - Added "yosys -E" for creating Makefile dependencies files
+    - Added "synth -noshare"
+    - Added "memory_nordff"
+    - Added "setundef -undef -expose -anyconst"
+    - Added "expose -input"
+    - Added specify/specparam parser support (simply ignore them)
+    - Added "write_blif -inames -iattr"
+    - Added "hierarchy -simcheck"
+    - Added an option to statically link abc into yosys
+    - Added protobuf back-end
+    - Added BLIF parsing support for .conn and .cname
+    - Added read_verilog error checking for reg/wire/logic misuse
+    - Added "make coverage" and ENABLE_GCOV build option
 
  * Changes in Yosys APIs
     - Added ConstEval defaultval feature
     - Added {get,set}_src_attribute() methods on RTLIL::AttrObject
+    - Added SigSpec::is_fully_ones() and Const::is_fully_ones()
+    - Added log_file_warning() and log_file_error() functions
 
  * Formal Verification
     - Added "write_aiger"
@@ -61,6 +78,13 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "yosys-smtbmc --presat" (now default in SymbiYosys)
     - Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
     - Added a brand new "write_btor" command for BTOR2
+    - Added clk2fflogic memory support and other improvements
+    - Added "async memory write" support to write_smt2
+    - Simulate clock toggling in yosys-smtbmc VCD output
+    - Added $allseq/$allconst cells for EA-solving
+    - Make -nordff the default in "prep"
+    - Added (* gclk *) attribute
+    - Added "async2sync" pass for single-clock designs with async resets
 
  * Verific support
     - Many improvements in Verific front-end
@@ -69,16 +93,24 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added "verific -import -flatten" and "verific -import -extnets"
     - Added "verific -vlog-incdir -vlog-define -vlog-libdir"
     - Remove PSL support (because PSL has been removed in upstream Verific)
+    - Improve integration with "hierarchy" command design elaboration
+    - Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
+    - Added simpilied "read" command that automatically uses verific if available
+    - Added "verific -set-<severity> <msg_id>.."
+    - Added "verific -work <libname>"
 
  * New back-ends
     - Added initial Coolrunner-II support
     - Added initial eASIC support
+    - Added initial ECP5 support
 
  * GreenPAK Support
     - Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
 
  * iCE40 Support
     - Add "synth_ice40 -vpr"
+    - Add "synth_ice40 -nodffe"
+    - Add "synth_ice40 -json"
     - Add Support for UltraPlus cells
 
  * MAX10 and Cyclone IV Support
@@ -89,6 +121,7 @@ Yosys 0.7 .. Yosys ???    (2017-12-12)
     - Added example of implementation for DE2i-150 board.
     - Added example of implementation for MAX10 development kit.
     - Added LFSR example from Asic World.
+    - Added "dffinit -highlow" for mapping to Intel primitives
 
 
 Yosys 0.6 .. Yosys 0.7

From eb452ffb2861ceac572a4bef6dddb8db3b79deb7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Sep 2018 10:32:54 +0200
Subject: [PATCH 092/528] Added support for ommited "parameter" in Verilog-2001
 style parameter decl in SV mode

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2389d7d31..63cf646e9 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -881,9 +881,15 @@ param_decl_list:
 
 single_param_decl:
 	TOK_ID '=' expr {
-		if (astbuf1 == nullptr)
-			frontend_verilog_yyerror("syntax error");
-		AstNode *node = astbuf1->clone();
+		AstNode *node;
+		if (astbuf1 == nullptr) {
+			if (!sv_mode)
+				frontend_verilog_yyerror("syntax error");
+			node = new AstNode(AST_PARAMETER);
+			node->children.push_back(AstNode::mkconst_int(0, true));
+		} else {
+			node = astbuf1->clone();
+		}
 		node->str = *$1;
 		delete node->children[0];
 		node->children[0] = $3;

From 8fde05dfa58d87ff2e71495c77f698af19a0d80b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 24 Sep 2018 20:51:16 +0200
Subject: [PATCH 093/528] Add "read_verilog -noassert -noassume
 -assert-assumes"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_frontend.cc | 23 ++++++++++++++++++++++-
 frontends/verilog/verilog_frontend.h  |  9 +++++++++
 frontends/verilog/verilog_parser.y    | 23 ++++++++++++++++++-----
 3 files changed, 49 insertions(+), 6 deletions(-)

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 8dcc7c5aa..aeea36a2b 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -66,12 +66,21 @@ struct VerilogFrontend : public Frontend {
 		log("        enable support for SystemVerilog assertions and some Yosys extensions\n");
 		log("        replace the implicit -D SYNTHESIS with -D FORMAL\n");
 		log("\n");
+		log("    -noassert\n");
+		log("        ignore assert() statements\n");
+		log("\n");
+		log("    -noassume\n");
+		log("        ignore assume() statements\n");
+		log("\n");
 		log("    -norestrict\n");
-		log("        ignore restrict() assertions\n");
+		log("        ignore restrict() statements\n");
 		log("\n");
 		log("    -assume-asserts\n");
 		log("        treat all assert() statements like assume() statements\n");
 		log("\n");
+		log("    -assert-assumes\n");
+		log("        treat all assume() statements like assert() statements\n");
+		log("\n");
 		log("    -dump_ast1\n");
 		log("        dump abstract syntax tree (before simplification)\n");
 		log("\n");
@@ -229,6 +238,14 @@ struct VerilogFrontend : public Frontend {
 				formal_mode = true;
 				continue;
 			}
+			if (arg == "-noassert") {
+				noassert_mode = true;
+				continue;
+			}
+			if (arg == "-noassume") {
+				noassume_mode = true;
+				continue;
+			}
 			if (arg == "-norestrict") {
 				norestrict_mode = true;
 				continue;
@@ -237,6 +254,10 @@ struct VerilogFrontend : public Frontend {
 				assume_asserts_mode = true;
 				continue;
 			}
+			if (arg == "-assert-assumes") {
+				assert_assumes_mode = true;
+				continue;
+			}
 			if (arg == "-dump_ast1") {
 				flag_dump_ast1 = true;
 				continue;
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 16edc7985..523bbc897 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -54,12 +54,21 @@ namespace VERILOG_FRONTEND
 	// running in -formal mode
 	extern bool formal_mode;
 
+	// running in -noassert mode
+	extern bool noassert_mode;
+
+	// running in -noassume mode
+	extern bool noassume_mode;
+
 	// running in -norestrict mode
 	extern bool norestrict_mode;
 
 	// running in -assume-asserts mode
 	extern bool assume_asserts_mode;
 
+	// running in -assert-assumes mode
+	extern bool assert_assumes_mode;
+
 	// running in -lib mode
 	extern bool lib_mode;
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 63cf646e9..16cac1460 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -58,7 +58,8 @@ namespace VERILOG_FRONTEND {
 	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
 	bool sv_mode, formal_mode, lib_mode;
-	bool norestrict_mode, assume_asserts_mode;
+	bool noassert_mode, noassume_mode, norestrict_mode;
+	bool assume_asserts_mode, assert_assumes_mode;
 	bool current_wire_rand, current_wire_const;
 	std::istream *lexin;
 }
@@ -1281,16 +1282,28 @@ opt_stmt_label:
 
 assert:
 	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
+		if (noassert_mode)
+			delete $5;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
+		if (noassume_mode)
+			delete $5;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5));
 	} |
 	opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
+		if (noassert_mode)
+			delete $6;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
+		if (noassume_mode)
+			delete $6;
+		else
+			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6));
 	} |
 	opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));

From 80a07652f2eb5e13190f46dcc116207a0427dc65 Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Tue, 25 Sep 2018 00:32:57 +0300
Subject: [PATCH 094/528] Fixed issue #630 by fixing a minor typo in the
 previous commit (as well as a non critical minor code optimization)

---
 frontends/ast/simplify.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e741bd92a..e1c2cb26a 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -3028,8 +3028,8 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 
 		AstNode *newNode = clone();
 		newNode->type = AST_ASSIGN_EQ;
+		newNode->children[0]->was_checked = true;
 		async_block->children[0]->children.push_back(newNode);
-		async_block->children[0]->children.back()->children[0]->was_checked = true;
 
 		newNode = new AstNode(AST_NONE);
 		newNode->cloneInto(this);
@@ -3074,7 +3074,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 
 		AstNode *assign_addr = new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER), children[0]->children[0]->children[0]->clone());
 		assign_addr->children[0]->str = id_addr;
-		assign_addr->children[0]->str = was_checked;
+		assign_addr->children[0]->was_checked = true;
 		block->children.insert(block->children.begin()+assign_idx+1, assign_addr);
 
 		AstNode *case_node = new AstNode(AST_CASE, new AstNode(AST_IDENTIFIER));

From 2b89074240b42648c6fad377156b19f21fb23fb8 Mon Sep 17 00:00:00 2001
From: TK Lam <tklam@easylogic.hk>
Date: Wed, 26 Sep 2018 16:11:45 +0800
Subject: [PATCH 095/528] Fix issue #639

---
 passes/equiv/equiv_make.cc | 58 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index b1f88d55e..8590c820b 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -40,6 +40,8 @@ struct EquivMakeWorker
 	pool<SigBit> undriven_bits;
 	SigMap assign_map;
 
+	dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
+
 	void read_blacklists()
 	{
 		for (auto fn : blacklists)
@@ -278,12 +280,20 @@ struct EquivMakeWorker
 			}
 		}
 
+		init_bit2driven();
+
+	 	pool<Cell*> visited_cells;
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
 			if (!ct.cell_output(c->type, conn.first)) {
 				SigSpec old_sig = assign_map(conn.second);
 				SigSpec new_sig = rd_signal_map(old_sig);
+				
+				visited_cells.clear();
 				if (old_sig != new_sig) {
+					if (check_signal_in_fanout(visited_cells, old_sig, new_sig)) 
+						continue;
+
 					log("Changing input %s of cell %s (%s): %s -> %s\n",
 							log_id(conn.first), log_id(c), log_id(c->type),
 							log_signal(old_sig), log_signal(new_sig));
@@ -378,6 +388,54 @@ struct EquivMakeWorker
 		}
 	}
 
+	void init_bit2driven()
+	{
+		for (auto cell : equiv_mod->cells()) {
+			if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_"))
+				continue;
+			for (auto &conn : cell->connections())
+			{
+				if (yosys_celltypes.cell_input(cell->type, conn.first))
+					for (auto bit : assign_map(conn.second))
+					{
+						bit2driven[bit].insert(cell);
+					}
+			}
+		}
+	}
+
+	bool check_signal_in_fanout(pool<Cell*> visited_cells, SigBit source_bit, SigBit target_bit)
+	{
+		if (source_bit == target_bit)
+			return true;
+
+		if (bit2driven.count(source_bit) == 0)
+			return false;
+
+		auto driven_cells = bit2driven.at(source_bit);
+		for (auto driven_cell: driven_cells)
+		{
+			if (visited_cells.count(driven_cell) > 0)
+				continue;
+
+			visited_cells.insert(driven_cell);
+
+			for (auto &conn: driven_cell->connections())
+			{
+				if (yosys_celltypes.cell_input(driven_cell->type, conn.first))
+					continue;
+
+				for (auto bit: conn.second) {
+					bool is_in_fanout = check_signal_in_fanout(visited_cells, bit, target_bit);
+					if (is_in_fanout == true)
+						return true;
+				}
+			}
+		}
+
+		return false;
+	}
+
 	void run()
 	{
 		copy_to_equiv();

From b86eb3deef7d80fc5450379c80047636832ef458 Mon Sep 17 00:00:00 2001
From: tklam <tklam@easylogic.hk>
Date: Wed, 26 Sep 2018 17:57:39 +0800
Subject: [PATCH 096/528] fix bug: pass by reference

---
 passes/equiv/equiv_make.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 8590c820b..e74dab36f 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -404,7 +404,7 @@ struct EquivMakeWorker
 		}
 	}
 
-	bool check_signal_in_fanout(pool<Cell*> visited_cells, SigBit source_bit, SigBit target_bit)
+	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
 	{
 		if (source_bit == target_bit)
 			return true;

From 031824e38c737db1e47e1cde3865fd9cfd4f2a07 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 28 Sep 2018 17:20:16 +0200
Subject: [PATCH 097/528] Update to v2 YosysVS template

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 misc/create_vcxsrc.sh | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh
index 215e27c53..924d2722e 100644
--- a/misc/create_vcxsrc.sh
+++ b/misc/create_vcxsrc.sh
@@ -5,11 +5,11 @@ vcxsrc="$1-$2"
 yosysver="$2"
 gitsha="$3"
 
-rm -rf YosysVS-Tpl-v1.zip YosysVS
-wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v1.zip
+rm -rf YosysVS-Tpl-v2.zip YosysVS
+wget http://www.clifford.at/yosys/nogit/YosysVS-Tpl-v2.zip
 
-unzip YosysVS-Tpl-v1.zip
-rm -f YosysVS-Tpl-v1.zip
+unzip YosysVS-Tpl-v2.zip
+rm -f YosysVS-Tpl-v2.zip
 mv YosysVS "$vcxsrc"
 
 {

From 9f9fe94b3522d465d98fa491c5992b14d268f09d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 30 Sep 2018 18:43:35 +0200
Subject: [PATCH 098/528] Fix handling of $past 2nd argument in read_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 04c429f7f..aa3b982d8 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1781,7 +1781,7 @@ skip_dynamic_range_lvalue_expansion:;
 				if (GetSize(children) == 2)
 				{
 					AstNode *buf = children[1]->clone();
-					while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
+					while (buf->simplify(true, false, false, stage, -1, false, false)) { }
 					if (buf->type != AST_CONSTANT)
 						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant value.\n", str.c_str());
 

From fcd39e1398b950aa19c5fec157770bd7c3fa2227 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 1 Oct 2018 18:34:41 +0100
Subject: [PATCH 099/528] ecp5: Don't map ROMs to DRAM

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/dram.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/ecp5/dram.txt b/techlibs/ecp5/dram.txt
index b3252fa9a..b94357429 100644
--- a/techlibs/ecp5/dram.txt
+++ b/techlibs/ecp5/dram.txt
@@ -13,4 +13,5 @@ endbram
 
 match $__TRELLIS_DPR16X4
   make_outreg
+  min wports 1
 endmatch

From 62424ef3de67dc8077a0ca03b302966f0284730f Mon Sep 17 00:00:00 2001
From: Dan Gisselquist <zipcpu@gmail.com>
Date: Mon, 1 Oct 2018 19:41:35 +0200
Subject: [PATCH 100/528] Add read_verilog $changed support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index aa3b982d8..71eba547c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1836,7 +1836,7 @@ skip_dynamic_range_lvalue_expansion:;
 				goto apply_newNode;
 			}
 
-			if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell")
+			if (str == "\\$stable" || str == "\\$rose" || str == "\\$fell" || str == "\\$changed")
 			{
 				if (GetSize(children) != 1)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
@@ -1853,6 +1853,9 @@ skip_dynamic_range_lvalue_expansion:;
 				if (str == "\\$stable")
 					newNode = new AstNode(AST_EQ, past, present);
 
+				else if (str == "\\$changed")
+					newNode = new AstNode(AST_NE, past, present);
+
 				else if (str == "\\$rose")
 					newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present);
 

From 90e0938f9a94464ac48a8fd4acdfbf805216b763 Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Mon, 1 Oct 2018 19:03:10 -0400
Subject: [PATCH 101/528] Update to .smv backend

Splitting VAR and ASSIGN into IVAR, VAR, DEFINE and ASSIGN. This allows better handling by nuXmv for post-processing (since now only state variables are listed under VAR).
---
 Makefile            |  4 +--
 backends/smv/smv.cc | 85 +++++++++++++++++++++++++++------------------
 2 files changed, 54 insertions(+), 35 deletions(-)

diff --git a/Makefile b/Makefile
index 365b92ea4..bfe6e28c4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 
-CONFIG := clang
-# CONFIG := gcc
+# CONFIG := clang
+CONFIG := gcc
 # CONFIG := gcc-4.8
 # CONFIG := emcc
 # CONFIG := mxe
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index b8383412b..a53ee7a7c 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -42,7 +42,7 @@ struct SmvWorker
 
 	pool<Wire*> partial_assignment_wires;
 	dict<SigBit, std::pair<const char*, int>> partial_assignment_bits;
-	vector<string> assignments, invarspecs;
+	vector<string> inputvars, vars, definitions, assignments, invarspecs;
 
 	const char *cid()
 	{
@@ -195,7 +195,7 @@ struct SmvWorker
 			return rvalue(sig);
 
 		const char *temp_id = cid();
-		f << stringf("    %s : unsigned word[%d]; -- %s\n", temp_id, GetSize(sig), log_signal(sig));
+//		f << stringf("    %s : unsigned word[%d]; -- %s\n", temp_id, GetSize(sig), log_signal(sig));
 
 		int offset = 0;
 		for (auto bit : sig) {
@@ -210,14 +210,14 @@ struct SmvWorker
 	void run()
 	{
 		f << stringf("MODULE %s\n", cid(module->name));
-		f << stringf("  VAR\n");
 
 		for (auto wire : module->wires())
 		{
 			if (SigSpec(wire) != sigmap(wire))
 				partial_assignment_wires.insert(wire);
 
-			f << stringf("    %s : unsigned word[%d]; -- %s\n", cid(wire->name), wire->width, log_id(wire));
+			if (wire->port_input)
+				inputvars.push_back(stringf("%s : unsigned word[%d]; -- %s", cid(wire->name), wire->width, log_id(wire)));
 
 			if (wire->attributes.count("\\init"))
 				assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at("\\init"))));
@@ -232,7 +232,7 @@ struct SmvWorker
 				SigSpec sig_a = cell->getPort("\\A");
 				SigSpec sig_en = cell->getPort("\\EN");
 
-				invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
+				invarspecs.push_back(stringf("(!bool(%s) | bool(%s));", rvalue(sig_en), rvalue(sig_a)));
 
 				continue;
 			}
@@ -275,8 +275,8 @@ struct SmvWorker
 					const char *b_shr = rvalue_u(sig_b);
 					const char *b_shl = cid();
 
-					f << stringf("    %s : unsigned word[%d]; -- neg(%s)\n", b_shl, GetSize(sig_b), log_signal(sig_b));
-					assignments.push_back(stringf("%s := unsigned(-%s);", b_shl, rvalue_s(sig_b)));
+//					f << stringf("    %s : unsigned word[%d]; -- neg(%s)\n", b_shl, GetSize(sig_b), log_signal(sig_b));
+					definitions.push_back(stringf("%s := unsigned(-%s);", b_shl, rvalue_s(sig_b)));
 
 					string expr_shl = stringf("resize(%s << %s[%d:0], %d)", expr_a.c_str(), b_shl, shift_b_width-1, width_y);
 					string expr_shr = stringf("resize(%s >> %s[%d:0], %d)", expr_a.c_str(), b_shr, shift_b_width-1, width_y);
@@ -303,7 +303,7 @@ struct SmvWorker
 								GetSize(sig_b)-shift_b_width, width_y, expr.c_str());
 				}
 
-				assignments.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
+				definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
 
 				continue;
 			}
@@ -319,12 +319,12 @@ struct SmvWorker
 
 				if (cell->getParam("\\A_SIGNED").as_bool())
 				{
-					assignments.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort("\\Y")),
 							op.c_str(), rvalue_s(cell->getPort("\\A"), width)));
 				}
 				else
 				{
-					assignments.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")),
 							op.c_str(), rvalue_u(cell->getPort("\\A"), width)));
 				}
 
@@ -346,12 +346,12 @@ struct SmvWorker
 
 				if (cell->getParam("\\A_SIGNED").as_bool())
 				{
-					assignments.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort("\\Y")),
 							rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width)));
 				}
 				else
 				{
-					assignments.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
 							rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width)));
 				}
 
@@ -370,12 +370,12 @@ struct SmvWorker
 
 				if (cell->getParam("\\A_SIGNED").as_bool())
 				{
-					assignments.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
 							rvalue_s(cell->getPort("\\A"), width), op.c_str(), rvalue_s(cell->getPort("\\B"), width), width_y));
 				}
 				else
 				{
-					assignments.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort("\\Y")),
 							rvalue_u(cell->getPort("\\A"), width), op.c_str(), rvalue_u(cell->getPort("\\B"), width), width_y));
 				}
 
@@ -407,7 +407,7 @@ struct SmvWorker
 					expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort("\\B")), width);
 				}
 
-				assignments.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
+				definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort("\\Y")),
 						expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort("\\Y"))));
 
 				continue;
@@ -425,7 +425,7 @@ struct SmvWorker
 				if (cell->type == "$reduce_or")   expr = stringf("%s != 0ub%d_0", expr_a, width_a);
 				if (cell->type == "$reduce_bool") expr = stringf("%s != 0ub%d_0", expr_a, width_a);
 
-				assignments.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
+				definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
 				continue;
 			}
 
@@ -444,7 +444,7 @@ struct SmvWorker
 				if (cell->type == "$reduce_xnor")
 					expr = "!(" + expr + ")";
 
-				assignments.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y));
+				definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y));
 				continue;
 			}
 
@@ -462,7 +462,7 @@ struct SmvWorker
 				if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b;
 				if (cell->type == "$logic_or")  expr = expr_a + " | " + expr_b;
 
-				assignments.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
+				definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
 				continue;
 			}
 
@@ -474,7 +474,7 @@ struct SmvWorker
 				string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort("\\A")), width_a);
 				const char *expr_y = lvalue(cell->getPort("\\Y"));
 
-				assignments.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y));
+				definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a.c_str(), width_y));
 				continue;
 			}
 
@@ -490,12 +490,13 @@ struct SmvWorker
 					expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width)));
 				expr += rvalue(sig_a);
 
-				assignments.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
+				definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort("\\Y")), expr.c_str()));
 				continue;
 			}
 
 			if (cell->type == "$dff")
 			{
+				vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort("\\Q")), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))));
 				assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort("\\Q")), rvalue(cell->getPort("\\D"))));
 				continue;
 			}
@@ -503,7 +504,7 @@ struct SmvWorker
 			if (cell->type.in("$_BUF_", "$_NOT_"))
 			{
 				string op = cell->type == "$_NOT_" ? "!" : "";
-				assignments.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A"))));
+				definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort("\\Y")), op.c_str(), rvalue(cell->getPort("\\A"))));
 				continue;
 			}
 
@@ -517,49 +518,49 @@ struct SmvWorker
 				if (cell->type.in("$_XNOR_"))  op = "xnor";
 
 				if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
-					assignments.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort("\\Y")),
 							rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
 				else
 				if (cell->type.in("$_NAND_", "$_NOR_"))
-					assignments.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort("\\Y")),
 							rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
 				else
-					assignments.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
+					definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort("\\Y")),
 							rvalue(cell->getPort("\\A")), op.c_str(), rvalue(cell->getPort("\\B"))));
 				continue;
 			}
 
 			if (cell->type == "$_MUX_")
 			{
-				assignments.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")),
+				definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort("\\Y")),
 						rvalue(cell->getPort("\\S")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\A"))));
 				continue;
 			}
 
 			if (cell->type == "$_AOI3_")
 			{
-				assignments.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")),
+				definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort("\\Y")),
 						rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C"))));
 				continue;
 			}
 
 			if (cell->type == "$_OAI3_")
 			{
-				assignments.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")),
+				definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort("\\Y")),
 						rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C"))));
 				continue;
 			}
 
 			if (cell->type == "$_AOI4_")
 			{
-				assignments.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")),
+				definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort("\\Y")),
 						rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
 				continue;
 			}
 
 			if (cell->type == "$_OAI4_")
 			{
-				assignments.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")),
+				definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort("\\Y")),
 						rvalue(cell->getPort("\\A")), rvalue(cell->getPort("\\B")), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D"))));
 				continue;
 			}
@@ -567,13 +568,13 @@ struct SmvWorker
 			if (cell->type[0] == '$')
 				log_error("Found currently unsupported cell type %s (%s.%s).\n", log_id(cell->type), log_id(module), log_id(cell));
 
-			f << stringf("    %s : %s;\n", cid(cell->name), cid(cell->type));
+//			f << stringf("    %s : %s;\n", cid(cell->name), cid(cell->type));
 
 			for (auto &conn : cell->connections())
 				if (cell->output(conn.first))
-					assignments.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(conn.first)));
+					definitions.push_back(stringf("%s := %s.%s;", lvalue(conn.second), cid(cell->name), cid(conn.first)));
 				else
-					assignments.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second)));
+					definitions.push_back(stringf("%s.%s := %s;", cid(cell->name), cid(conn.first), rvalue(conn.second)));
 		}
 
 		for (Wire *wire : partial_assignment_wires)
@@ -657,7 +658,25 @@ struct SmvWorker
 				}
 			}
 
-			assignments.push_back(stringf("%s := %s;", cid(wire->name), expr.c_str()));
+			definitions.push_back(stringf("%s := %s;", cid(wire->name), expr.c_str()));
+		}
+
+		if (!inputvars.empty()) {
+			f << stringf("  IVAR\n");
+			for (const string &line : inputvars)
+				f << stringf("    %s\n", line.c_str());
+		}
+
+		if (!vars.empty()) {
+			f << stringf("  VAR\n");
+			for (const string &line : vars)
+				f << stringf("    %s\n", line.c_str());
+		}
+
+		if (!definitions.empty()) {
+			f << stringf("  DEFINE\n");
+			for (const string &line : definitions)
+				f << stringf("    %s\n", line.c_str());
 		}
 
 		if (!assignments.empty()) {

From cb214fc01d95ed9df7de10ccffa3471a1dc91659 Mon Sep 17 00:00:00 2001
From: Tom Verbeure <hombre+github@gmail.com>
Date: Tue, 2 Oct 2018 07:44:23 +0000
Subject: [PATCH 102/528] Fix for issue 594.

---
 frontends/ast/genrtlil.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 0f7e910f3..c9345ff08 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -985,7 +985,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 		use_const_chunk:
 			if (children.size() != 0) {
-				log_assert(children[0]->type == AST_RANGE);
+				if (children[0]->type != AST_RANGE)
+					log_file_error(filename, linenum, "Single range expected.\n");
 				int source_width = id2ast->range_left - id2ast->range_right + 1;
 				int source_offset = id2ast->range_right;
 				if (!children[0]->range_valid) {

From ad975fb694f32edd51b4cf05f62485798e31ef1e Mon Sep 17 00:00:00 2001
From: Tim Ansell <me@mith.ro>
Date: Wed, 3 Oct 2018 16:38:32 -0700
Subject: [PATCH 103/528] xilinx: Adding missing inout IO port to IOBUF

---
 techlibs/xilinx/cells_xtra.v | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index a2dd01ad5..f5abf3ae0 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -2225,6 +2225,7 @@ module IOBUF (...);
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
+    inout IO;
     input I, T;
 endmodule
 

From 5f1fea08d5e14ecaa1cf60eb865c60132a0ce3e1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 4 Oct 2018 11:30:55 +0200
Subject: [PATCH 104/528] Add inout ports to cells_xtra.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/xilinx/cells_xtra.sh |  4 ++--
 techlibs/xilinx/cells_xtra.v  | 12 ++++++++++++
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index c7ad16043..e7c7d17bf 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -1,13 +1,13 @@
 #!/bin/bash
 
 set -e
-libdir="/opt/Xilinx/Vivado/2015.4/data/verilog/src"
+libdir="/opt/Xilinx/Vivado/2018.1/data/verilog/src"
 
 function xtract_cell_decl()
 {
 	for dir in $libdir/xeclib $libdir/retarget; do
 		[ -f $dir/$1.v ] || continue
-		egrep '^\s*((end)?module|parameter|input|output|(end)?function|(end)?task)' $dir/$1.v |
+		egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
 			sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
 			         s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
 			         s/\s+$//; s/,$/;/; /input|output|parameter/ s/[^;]$/&;/; s/\s+/ /g;
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index f5abf3ae0..69e54233a 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -2237,6 +2237,7 @@ module IOBUF_DCIEN (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    inout IO;
     input DCITERMDISABLE;
     input I;
     input IBUFDISABLE;
@@ -2251,6 +2252,7 @@ module IOBUF_INTERMDISABLE (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    inout IO;
     input I;
     input IBUFDISABLE;
     input INTERMDISABLE;
@@ -2264,6 +2266,7 @@ module IOBUFDS (...);
     parameter IOSTANDARD = "DEFAULT";
     parameter SLEW = "SLOW";
     output O;
+    inout IO, IOB;
     input I, T;
 endmodule
 
@@ -2276,6 +2279,8 @@ module IOBUFDS_DCIEN (...);
     parameter SLEW = "SLOW";
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
+    inout IO;
+    inout IOB;
     input DCITERMDISABLE;
     input I;
     input IBUFDISABLE;
@@ -2289,6 +2294,8 @@ module IOBUFDS_DIFF_OUT (...);
     parameter IOSTANDARD = "DEFAULT";
     output O;
     output OB;
+    inout IO;
+    inout IOB;
     input I;
     input TM;
     input TS;
@@ -2303,6 +2310,8 @@ module IOBUFDS_DIFF_OUT_DCIEN (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    inout IO;
+    inout IOB;
     input DCITERMDISABLE;
     input I;
     input IBUFDISABLE;
@@ -2319,6 +2328,8 @@ module IOBUFDS_DIFF_OUT_INTERMDISABLE (...);
     parameter USE_IBUFDISABLE = "TRUE";
     output O;
     output OB;
+    inout IO;
+    inout IOB;
     input I;
     input IBUFDISABLE;
     input INTERMDISABLE;
@@ -2382,6 +2393,7 @@ module ISERDESE2 (...);
 endmodule
 
 module KEEPER (...);
+    inout O;
 endmodule
 
 module LDCE (...);

From 1355492c8966596f3694b781d6cdf12b17681bc1 Mon Sep 17 00:00:00 2001
From: Adrian Wheeldon <arandomowl@gmail.com>
Date: Thu, 4 Oct 2018 15:36:26 +0100
Subject: [PATCH 105/528] Fix IdString M in setup_stdcells()

---
 kernel/celltypes.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index fcc4fcc4b..6041168bb 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -157,7 +157,7 @@ struct CellTypes
 		IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D";
 		IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H";
 		IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L";
-		IdString M = "\\I", N = "\\N", O = "\\O", P = "\\P";
+		IdString M = "\\M", N = "\\N", O = "\\O", P = "\\P";
 		IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V";
 		IdString Y = "\\Y";
 

From 63d53006cb4394e5eefffcf1b4126b631e7384e8 Mon Sep 17 00:00:00 2001
From: Tim Ansell <me@mith.ro>
Date: Thu, 4 Oct 2018 17:15:30 -0700
Subject: [PATCH 106/528] Fix misspelling in issue_template.md

It's been bugging me :-P
---
 .github/issue_template.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/issue_template.md b/.github/issue_template.md
index 24e91a4e7..4563a71de 100644
--- a/.github/issue_template.md
+++ b/.github/issue_template.md
@@ -1,7 +1,7 @@
 ## Steps to reproduce the issue
 
 *Provide instructions for reproducing the issue. Make sure to include
-all neccessary source files. (You can simply drag&drop a .zip file into
+all necessary source files. (You can simply drag&drop a .zip file into
 the issue editor.)*
 
 ## Expected behavior

From 4b0448fc2cc707f312813b4e0826371fa384e3d9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 5 Oct 2018 09:26:10 +0200
Subject: [PATCH 107/528] Fix compiler warning in verific.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c5fa58313..06d98611a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1676,6 +1676,7 @@ YOSYS_NAMESPACE_END
 
 PRIVATE_NAMESPACE_BEGIN
 
+#ifdef YOSYS_ENABLE_VERIFIC
 bool check_noverific_env()
 {
 	const char *e = getenv("YOSYS_NOVERIFIC");
@@ -1685,6 +1686,7 @@ bool check_noverific_env()
 		return false;
 	return true;
 }
+#endif
 
 struct VerificPass : public Pass {
 	VerificPass() : Pass("verific", "load Verilog and VHDL designs using Verific") { }

From 115ca576475a2e8d30e63b339ae6a1b5db6906a6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 5 Oct 2018 09:41:18 +0200
Subject: [PATCH 108/528] Add "write_edif -attrprop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/edif/edif.cc | 39 ++++++++++++++++++++++++++++-----------
 1 file changed, 28 insertions(+), 11 deletions(-)

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 5f9ec54fd..d4e56a9eb 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -106,6 +106,9 @@ struct EdifBackend : public Backend {
 		log("        if the design contains constant nets. use \"hilomap\" to map to custom\n");
 		log("        constant drivers first)\n");
 		log("\n");
+		log("    -attrprop\n");
+		log("        create EDIF properties for cell attributes\n");
+		log("\n");
 		log("    -pvector {par|bra|ang}\n");
 		log("        sets the delimiting character for module port rename clauses to\n");
 		log("        parentheses, square brackets, or angle brackets.\n");
@@ -121,6 +124,7 @@ struct EdifBackend : public Backend {
 		log_header(design, "Executing EDIF backend.\n");
 		std::string top_module_name;
 		bool port_rename = false;
+		bool attr_properties = false;
 		std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
 		bool nogndvcc = false;
 		CellTypes ct(design);
@@ -137,6 +141,10 @@ struct EdifBackend : public Backend {
 				nogndvcc = true;
 				continue;
 			}
+			if (args[argidx] == "-attrprop") {
+				attr_properties = true;
+				continue;
+			}
 			if (args[argidx] == "-pvector" && argidx+1 < args.size()) {
 				std::string parray;
 				port_rename = true;
@@ -332,24 +340,33 @@ struct EdifBackend : public Backend {
 				*f << stringf("          (instance %s\n", EDIF_DEF(cell->name));
 				*f << stringf("            (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),
 						lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : "");
-				for (auto &p : cell->parameters)
-					if ((p.second.flags & RTLIL::CONST_FLAG_STRING) != 0)
-						*f << stringf("\n            (property %s (string \"%s\"))", EDIF_DEF(p.first), p.second.decode_string().c_str());
-					else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def())
-						*f << stringf("\n            (property %s (integer %u))", EDIF_DEF(p.first), p.second.as_int());
+
+				auto add_prop = [&](IdString name, Const val) {
+					if ((val.flags & RTLIL::CONST_FLAG_STRING) != 0)
+						*f << stringf("\n            (property %s (string \"%s\"))", EDIF_DEF(name), val.decode_string().c_str());
+					else if (val.bits.size() <= 32 && RTLIL::SigSpec(val).is_fully_def())
+						*f << stringf("\n            (property %s (integer %u))", EDIF_DEF(name), val.as_int());
 					else {
 						std::string hex_string = "";
-						for (size_t i = 0; i < p.second.bits.size(); i += 4) {
+						for (size_t i = 0; i < val.bits.size(); i += 4) {
 							int digit_value = 0;
-							if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
-							if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
-							if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
-							if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
+							if (i+0 < val.bits.size() && val.bits.at(i+0) == RTLIL::State::S1) digit_value |= 1;
+							if (i+1 < val.bits.size() && val.bits.at(i+1) == RTLIL::State::S1) digit_value |= 2;
+							if (i+2 < val.bits.size() && val.bits.at(i+2) == RTLIL::State::S1) digit_value |= 4;
+							if (i+3 < val.bits.size() && val.bits.at(i+3) == RTLIL::State::S1) digit_value |= 8;
 							char digit_str[2] = { "0123456789abcdef"[digit_value], 0 };
 							hex_string = std::string(digit_str) + hex_string;
 						}
-						*f << stringf("\n            (property %s (string \"%d'h%s\"))", EDIF_DEF(p.first), GetSize(p.second.bits), hex_string.c_str());
+						*f << stringf("\n            (property %s (string \"%d'h%s\"))", EDIF_DEF(name), GetSize(val.bits), hex_string.c_str());
 					}
+				};
+
+				for (auto &p : cell->parameters)
+					add_prop(p.first, p.second);
+				if (attr_properties)
+					for (auto &p : cell->attributes)
+						add_prop(p.first, p.second);
+
 				*f << stringf(")\n");
 				for (auto &p : cell->connections()) {
 					RTLIL::SigSpec sig = sigmap(p.second);

From 31e22c8b96eea5e833d32dea7d72dfe1556bf7e0 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 5 Oct 2018 11:35:59 +0100
Subject: [PATCH 109/528] ecp5: Add blackbox for DP16KD

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 93 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 1700694e8..c89fde1b1 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -446,3 +446,96 @@ module TRELLIS_SLICE(
 	);
 endmodule
 
+(* blackbox *)
+module DP16KD(
+  input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0,
+  input ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, ADA4, ADA3, ADA2, ADA1, ADA0,
+  input CEA, OCEA, CLKA, WEA, RSTA,
+  input CSA2, CSA1, CSA0,
+  output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0,
+
+  input DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0,
+  input ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, ADB4, ADB3, ADB2, ADB1, ADB0,
+  input CEB, OCEB, CLKB, WEB, RSTB,
+  input CSB2, CSB1, CSB0,
+  output DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0
+);
+  parameter DATA_WIDTH_A = 18;
+  parameter DATA_WIDTH_B = 18;
+
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+
+  parameter RESETMODE = "SYNC";
+  parameter ASYNC_RESET_RELEASE = "SYNC";
+
+  parameter CSDECODE_A = "0b000";
+  parameter CSDECODE_B = "0b000";
+
+  parameter GSR = "ENABLED";
+
+  parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+endmodule

From 9850de405a11fe93e4562c86be0a0830b83c2785 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 7 Oct 2018 19:48:42 +0200
Subject: [PATCH 110/528] Improve Verific importer blackbox handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 06d98611a..dba3b0f0c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -118,6 +118,18 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net)
 	return net_map.at(net);
 }
 
+bool is_blackbox(Netlist *nl)
+{
+	if (nl->IsBlackBox())
+		return true;
+
+	const char *attr = nl->GetAttValue("blackbox");
+	if (attr != nullptr && strcmp(attr, "0"))
+		return true;
+
+	return false;
+}
+
 void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
 {
 	MapIter mi;
@@ -709,7 +721,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 	netlist = nl;
 
 	if (design->has(module_name)) {
-		if (!nl->IsOperator())
+		if (!nl->IsOperator() && !is_blackbox(nl))
 			log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
 		return;
 	}
@@ -718,7 +730,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 	module->name = module_name;
 	design->add(module);
 
-	if (nl->IsBlackBox()) {
+	if (is_blackbox(nl)) {
 		log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
 		module->set_bool_attribute("\\blackbox");
 	} else {

From b111ea12286b45e51fc453e3f4d7ac906e1a9f7c Mon Sep 17 00:00:00 2001
From: Tim 'mithro' Ansell <me@mith.ro>
Date: Mon, 8 Oct 2018 16:52:12 -0700
Subject: [PATCH 111/528] xilinx: Still map LUT7/LUT8 to Xilinx specific
 primitives.

Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
---
 techlibs/xilinx/synth_xilinx.cc | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 590fe61d2..b27c08529 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -235,10 +235,9 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
+			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
 			if (vpr)
-			    Pass::call(design, "techmap -D NO_LUT -map +/xilinx/cells_map.v");
-			else
-			    Pass::call(design, "techmap -map +/xilinx/cells_map.v");
+			    Pass::call(design, "techmap -map +/xilinx/lut2lut.v");
 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
 			Pass::call(design, "clean");
 		}

From 346cbbdbdc0dbe291bfa96b8b1e6300c911c6e89 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 9 Oct 2018 14:19:04 +0100
Subject: [PATCH 112/528] ecp5: Adding BRAM initialisation and config

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore    |  3 +++
 techlibs/ecp5/Makefile.inc  | 15 +++++++++++++++
 techlibs/ecp5/bram.txt      | 29 +++++++++++++++++++++++++++++
 techlibs/ecp5/brams_init.py | 22 ++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  4 ++++
 5 files changed, 73 insertions(+)
 create mode 100644 techlibs/ecp5/.gitignore
 create mode 100644 techlibs/ecp5/bram.txt
 create mode 100755 techlibs/ecp5/brams_init.py

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
new file mode 100644
index 000000000..84d260810
--- /dev/null
+++ b/techlibs/ecp5/.gitignore
@@ -0,0 +1,3 @@
+bram_init_1_2_4.vh
+bram_init_9_18_36.vh
+brams_init.mk
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 9d3247347..95d40fccf 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -5,4 +5,19 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
+
+EXTRA_OBJS += techlibs/ecp5/brams_init.mk
+.SECONDARY: techlibs/ecp5/brams_init.mk
+
+techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
+	$(Q) mkdir -p techlibs/ecp5
+	$(P) python3 $<
+	$(Q) touch $@
+
+techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
+techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
+
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
new file mode 100644
index 000000000..9d22e4afe
--- /dev/null
+++ b/techlibs/ecp5/bram.txt
@@ -0,0 +1,29 @@
+bram $__ECP5_DP16KD
+  init 1
+
+  abits 10 @a10d18
+  dbits 18 @a10d18
+  abits 11 @a11d9
+  dbits 9  @a11d9
+  abits 12 @a12d4
+  dbits 4  @a12d4
+  abits 13 @a13d2
+  dbits 2  @a13d2
+  abits 14 @a14d1
+  dbits 1  @a14d1
+
+  groups 2
+  ports 1 1
+  wrmode 1 0
+  enable 2 1 @a10d18
+  enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
+  transp 0 2
+  clocks 1 2
+  clkpol 2 2
+endbram
+
+match $__ECP5_DP16KD
+  min bits 2048
+  min efficiency 5
+  shuffle_enable B
+endmatch
diff --git a/techlibs/ecp5/brams_init.py b/techlibs/ecp5/brams_init.py
new file mode 100755
index 000000000..6f650b2a9
--- /dev/null
+++ b/techlibs/ecp5/brams_init.py
@@ -0,0 +1,22 @@
+#!/usr/bin/env python3
+with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f:
+    for i in range(0, 0x40):
+        init_snippets = []
+        for j in range(32):
+            init_snippets.append("INIT[%4d*8 +: 8]" % (32 * i + j))
+            init_snippets.append("3'b000" if (j % 2 == 1) else "1'b0")
+        init_snippets = list(reversed(init_snippets))
+        for k in range(8, 64, 8):
+            init_snippets[k] = "\n          " + init_snippets[k]
+        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+
+with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
+    for i in range(0, 0x40):
+        init_snippets = []
+        for j in range(16):
+            init_snippets.append("INIT[%3d*18 +: 18]" % (16 * i + j))
+            init_snippets.append("2'b00")
+        init_snippets = list(reversed(init_snippets))
+        for k in range(8, 32, 8):
+            init_snippets[k] = "\n          " + init_snippets[k]
+        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index c89fde1b1..3e7e83aac 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -472,6 +472,10 @@ module DP16KD(
   parameter CSDECODE_A = "0b000";
   parameter CSDECODE_B = "0b000";
 
+  parameter WRITEMODE_A = "NORMAL";
+  parameter WRITEMODE_B = "NORMAL";
+
+
   parameter GSR = "ENABLED";
 
   parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";

From 2ef1af8b58c845f4ca070a0469fe42212bcb5eee Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 10 Oct 2018 16:11:00 +0100
Subject: [PATCH 113/528] ecp5: Script for BRAM IO connections

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore       |   5 ++
 techlibs/ecp5/bram_map.v       |   0
 techlibs/ecp5/brams_connect.py |  46 ++++++++++++
 techlibs/ecp5/cells_sim.v      | 128 ++++++++++++++++-----------------
 4 files changed, 115 insertions(+), 64 deletions(-)
 create mode 100644 techlibs/ecp5/bram_map.v
 create mode 100755 techlibs/ecp5/brams_connect.py

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
index 84d260810..3f66045f8 100644
--- a/techlibs/ecp5/.gitignore
+++ b/techlibs/ecp5/.gitignore
@@ -1,3 +1,8 @@
 bram_init_1_2_4.vh
 bram_init_9_18_36.vh
 brams_init.mk
+bram_conn_1.vh
+bram_conn_2.vh
+bram_conn_4.vh
+bram_conn_9.vh
+bram_conn_18.vh
diff --git a/techlibs/ecp5/bram_map.v b/techlibs/ecp5/bram_map.v
new file mode 100644
index 000000000..e69de29bb
diff --git a/techlibs/ecp5/brams_connect.py b/techlibs/ecp5/brams_connect.py
new file mode 100755
index 000000000..f86dcfcf0
--- /dev/null
+++ b/techlibs/ecp5/brams_connect.py
@@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+
+def write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits):
+    ada_conn = [".ADA%d(%s)" % (i, ada_bits[i]) for i in range(len(ada_bits))]
+    adb_conn = [".ADB%d(%s)" % (i, adb_bits[i]) for i in range(len(adb_bits))]
+    dia_conn = [".DIA%d(%s)" % (i, dia_bits[i]) for i in range(len(dia_bits))]
+    dob_conn = [".DOB%d(%s)" % (i, dob_bits[i]) for i in range(len(dob_bits))]
+    print("    %s," % ", ".join(ada_conn), file=f)
+    print("    %s," % ", ".join(adb_conn), file=f)
+    print("    %s," % ", ".join(dia_conn), file=f)
+    print("    %s," % ", ".join(dob_conn), file=f)
+
+with open("techlibs/ecp5/bram_conn_1.vh", "w") as f:
+    ada_bits = ["A1ADDR[%d]" % i for i in range(14)]
+    adb_bits = ["B1ADDR[%d]" % i for i in range(14)]
+    dia_bits = ["A1DATA[0]"] + ["1'b0" for i in range(17)]
+    dob_bits = ["B1DATA[0]"]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_2.vh", "w") as f:
+    ada_bits = ["1'b0"] + ["A1ADDR[%d]" % i for i in range(13)]
+    adb_bits = ["1'b0"] + ["B1ADDR[%d]" % i for i in range(13)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(2)] + ["1'b0" for i in range(16)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(2)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_4.vh", "w") as f:
+    ada_bits = ["1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(12)]
+    adb_bits = ["1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(12)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(4)] + ["1'b0" for i in range(14)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(4)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_9.vh", "w") as f:
+    ada_bits = ["1'b0", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(11)]
+    adb_bits = ["1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(11)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(9)] + ["1'b0" for i in range(9)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(9)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
+
+with open("techlibs/ecp5/bram_conn_18.vh", "w") as f:
+    ada_bits = ["A1EN[0]", "A1EN[1]", "1'b0", "1'b0"] + ["A1ADDR[%d]" % i for i in range(10)]
+    adb_bits = ["1'b0", "1'b0", "1'b0", "1'b0"] + ["B1ADDR[%d]" % i for i in range(10)]
+    dia_bits = ["A1DATA[%d]" % i for i in range(18)]
+    dob_bits = ["B1DATA[%d]" % i for i in range(18)]
+    write_bus_ports(f, ada_bits, adb_bits, dia_bits, dob_bits)
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 3e7e83aac..4732381ca 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -478,68 +478,68 @@ module DP16KD(
 
   parameter GSR = "ENABLED";
 
-  parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
-  parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+  parameter INITVAL_00 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_01 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_02 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_03 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_04 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_05 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_06 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_07 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_08 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_09 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_0F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_10 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_11 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_12 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_13 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_14 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_15 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_16 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_17 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_18 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_19 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_1F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_20 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_21 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_22 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_23 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_24 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_25 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_26 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_27 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_28 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_29 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_2F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_30 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_31 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_32 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_33 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_34 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_35 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_36 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_37 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_38 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_39 = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3A = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3B = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3C = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3D = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule

From 983fb7ff88ab5f398073e2aa1d5e44eb03d01ee3 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 10 Oct 2018 16:35:19 +0100
Subject: [PATCH 114/528] ecp5: First BRAM type maps successfully

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/.gitignore    |  1 +
 techlibs/ecp5/Makefile.inc  | 23 ++++++++++++++++--
 techlibs/ecp5/bram.txt      |  4 ++--
 techlibs/ecp5/bram_map.v    |  0
 techlibs/ecp5/brams_init.py |  4 ++--
 techlibs/ecp5/brams_map.v   | 47 +++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v   |  2 ++
 techlibs/ecp5/synth_ecp5.cc |  5 +---
 8 files changed, 76 insertions(+), 10 deletions(-)
 delete mode 100644 techlibs/ecp5/bram_map.v
 create mode 100644 techlibs/ecp5/brams_map.v

diff --git a/techlibs/ecp5/.gitignore b/techlibs/ecp5/.gitignore
index 3f66045f8..54c329735 100644
--- a/techlibs/ecp5/.gitignore
+++ b/techlibs/ecp5/.gitignore
@@ -6,3 +6,4 @@ bram_conn_2.vh
 bram_conn_4.vh
 bram_conn_9.vh
 bram_conn_18.vh
+brams_connect.mk
diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 95d40fccf..f45859392 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -5,19 +5,38 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
 
-EXTRA_OBJS += techlibs/ecp5/brams_init.mk
-.SECONDARY: techlibs/ecp5/brams_init.mk
+EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
+.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 
 techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py
 	$(Q) mkdir -p techlibs/ecp5
 	$(P) python3 $<
 	$(Q) touch $@
 
+techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py
+	$(Q) mkdir -p techlibs/ecp5
+	$(P) python3 $<
+	$(Q) touch $@
+
+
 techlibs/ecp5/bram_init_1_2_4.vh: techlibs/ecp5/brams_init.mk
 techlibs/ecp5/bram_init_9_18_36.vh: techlibs/ecp5/brams_init.mk
 
+techlibs/ecp5/bram_conn_1.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_2.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
+techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
+
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
+
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
diff --git a/techlibs/ecp5/bram.txt b/techlibs/ecp5/bram.txt
index 9d22e4afe..f223a42b8 100644
--- a/techlibs/ecp5/bram.txt
+++ b/techlibs/ecp5/bram.txt
@@ -18,8 +18,8 @@ bram $__ECP5_DP16KD
   enable 2 1 @a10d18
   enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
   transp 0 2
-  clocks 1 2
-  clkpol 2 2
+  clocks 2 3
+  clkpol 2 3
 endbram
 
 match $__ECP5_DP16KD
diff --git a/techlibs/ecp5/bram_map.v b/techlibs/ecp5/bram_map.v
deleted file mode 100644
index e69de29bb..000000000
diff --git a/techlibs/ecp5/brams_init.py b/techlibs/ecp5/brams_init.py
index 6f650b2a9..96a47bdcd 100755
--- a/techlibs/ecp5/brams_init.py
+++ b/techlibs/ecp5/brams_init.py
@@ -8,7 +8,7 @@ with open("techlibs/ecp5/bram_init_1_2_4.vh", "w") as f:
         init_snippets = list(reversed(init_snippets))
         for k in range(8, 64, 8):
             init_snippets[k] = "\n          " + init_snippets[k]
-        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+        print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
 
 with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
     for i in range(0, 0x40):
@@ -19,4 +19,4 @@ with open("techlibs/ecp5/bram_init_9_18_36.vh", "w") as f:
         init_snippets = list(reversed(init_snippets))
         for k in range(8, 32, 8):
             init_snippets[k] = "\n          " + init_snippets[k]
-        print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
+        print(".INITVAL_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
new file mode 100644
index 000000000..894f5c46f
--- /dev/null
+++ b/techlibs/ecp5/brams_map.v
@@ -0,0 +1,47 @@
+module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+	parameter CFG_ABITS = 10;
+	parameter CFG_DBITS = 18;
+	parameter CFG_ENABLE_A = 2;
+
+	parameter CLKPOL2 = 1;
+	parameter CLKPOL3 = 1;
+	parameter [18431:0] INIT = 18432'bx;
+	parameter TRANSP2 = 0;
+
+	input CLK2;
+	input CLK3;
+
+	input [CFG_ABITS-1:0] A1ADDR;
+	input [CFG_DBITS-1:0] A1DATA;
+	input [CFG_ENABLE_A-1:0] A1EN;
+
+	input [CFG_ABITS-1:0] B1ADDR;
+	output [CFG_DBITS-1:0] B1DATA;
+	input B1EN;
+
+	localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
+	localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
+
+	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL";
+
+
+	generate if (CFG_DBITS == 1) begin
+		DP16KD #(
+			`include "bram_init_1_2_4.vh"
+			.DATA_WIDTH_A(1),
+			.DATA_WIDTH_B(1),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_1.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else begin
+		wire TECHMAP_FAIL = 1'b1;
+	end endgenerate
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 4732381ca..e43632c64 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -475,6 +475,8 @@ module DP16KD(
   parameter WRITEMODE_A = "NORMAL";
   parameter WRITEMODE_B = "NORMAL";
 
+  parameter CLKAMUX = "CLKA";
+  parameter CLKBMUX = "CLKB";
 
   parameter GSR = "ENABLED";
 
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index a13dd8d41..ab56a9444 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -222,11 +222,8 @@ struct SynthEcp5Pass : public ScriptPass
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))
 		{
-			//TODO
-#if 0
-			run("memory_bram -rules +/ecp5/brams.txt");
+			run("memory_bram -rules +/ecp5/bram.txt");
 			run("techmap -map +/ecp5/brams_map.v");
-#endif
 		}
 
 		if (!nodram && check_label("dram", "(skip if -nodram)"))

From bdfead8c648db77b9350f941d6578a48bdaa2203 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 10 Oct 2018 17:18:17 +0100
Subject: [PATCH 115/528] ecp5: Adding BRAM maps for all size options

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/brams_map.v | 65 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 64 insertions(+), 1 deletion(-)

diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 894f5c46f..61dee7054 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -24,7 +24,6 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 
 	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL";
 
-
 	generate if (CFG_DBITS == 1) begin
 		DP16KD #(
 			`include "bram_init_1_2_4.vh"
@@ -41,6 +40,70 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
+	end else if (CFG_DBITS == 2) begin
+		DP16KD #(
+			`include "bram_init_1_2_4.vh"
+			.DATA_WIDTH_A(2),
+			.DATA_WIDTH_B(2),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_2.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else if (CFG_DBITS <= 4) begin
+		DP16KD #(
+			`include "bram_init_1_2_4.vh"
+			.DATA_WIDTH_A(4),
+			.DATA_WIDTH_B(4),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_4.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else if (CFG_DBITS <= 9) begin
+		DP16KD #(
+			`include "bram_init_9_18_36.vh"
+			.DATA_WIDTH_A(9),
+			.DATA_WIDTH_B(9),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_9.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
+	end else if (CFG_DBITS <= 18) begin
+		DP16KD #(
+			`include "bram_init_9_18_36.vh"
+			.DATA_WIDTH_A(18),
+			.DATA_WIDTH_B(18),
+			.CLKAMUX(CLKAMUX),
+			.CLKBMUX(CLKBMUX),
+			.WRITEMODE_A(WRITEMODE_A),
+			.GSR("DISABLED")
+		) _TECHMAP_REPLACE_ (
+			`include "bram_conn_18.vh"
+			.CLKA(CLK2), .CLKB(CLK3),
+			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.RSTA(1'b0), .RSTB(1'b0)
+		);
 	end else begin
 		wire TECHMAP_FAIL = 1'b1;
 	end endgenerate

From 812538a036f380b613d1cd3fe2f182e376150d16 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 12 Oct 2018 14:22:21 +0100
Subject: [PATCH 116/528] BRAM improvements

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/brams_map.v | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 61dee7054..7f40f8458 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -22,7 +22,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
 	localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
 
-	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "NORMAL";
+	localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
 
 	generate if (CFG_DBITS == 1) begin
 		DP16KD #(
@@ -32,12 +32,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_1.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS == 2) begin
@@ -48,12 +49,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_2.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 4) begin
@@ -64,12 +66,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_4.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 9) begin
@@ -80,12 +83,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_9.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 18) begin
@@ -96,12 +100,13 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			.CLKAMUX(CLKAMUX),
 			.CLKBMUX(CLKBMUX),
 			.WRITEMODE_A(WRITEMODE_A),
+			.WRITEMODE_B("READBEFOREWRITE"),
 			.GSR("DISABLED")
 		) _TECHMAP_REPLACE_ (
 			`include "bram_conn_18.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
-			.WEA(1'b1), .CEA(|A1EN), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
+			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
+			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else begin

From 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 11 Oct 2018 23:33:31 +0200
Subject: [PATCH 117/528] Synthesis support for SystemVerilog interfaces

This time doing the changes mostly in AST before RTLIL generation
---
 frontends/ast/ast.cc               | 133 ++++++++++++++++++++--
 frontends/ast/ast.h                |   6 +
 frontends/ast/genrtlil.cc          |  48 +++++++-
 frontends/ast/simplify.cc          |   2 +-
 frontends/verilog/verilog_lexer.l  |   8 ++
 frontends/verilog/verilog_parser.y |  60 ++++++++++
 kernel/rtlil.cc                    |  15 +++
 kernel/rtlil.h                     |   2 +
 passes/hierarchy/hierarchy.cc      | 172 +++++++++++++++++++++++++++--
 tests/simple/svinterface1.sv       |  76 +++++++++++++
 10 files changed, 501 insertions(+), 21 deletions(-)
 create mode 100644 tests/simple/svinterface1.sv

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index e79be953a..256c08776 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -905,7 +905,7 @@ RTLIL::Const AstNode::realAsConst(int width)
 // create a new AstModule from an AST_MODULE AST node
 static AstModule* process_module(AstNode *ast, bool defer)
 {
-	log_assert(ast->type == AST_MODULE);
+	log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
 
 	if (defer)
 		log("Storing AST representation for module `%s'.\n", ast->str.c_str());
@@ -916,6 +916,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	current_module->ast = NULL;
 	current_module->name = ast->str;
 	current_module->attributes["\\src"] = stringf("%s:%d", ast->filename.c_str(), ast->linenum);
+	current_module->set_bool_attribute("\\cells_not_processed");
 
 	current_ast_mod = ast;
 	AstNode *ast_before_simplify = ast->clone();
@@ -989,6 +990,8 @@ static AstModule* process_module(AstNode *ast, bool defer)
 		ignoreThisSignalsInInitial = RTLIL::SigSpec();
 	}
 
+	if (ast->type == AST_INTERFACE)
+		current_module->set_bool_attribute("\\is_interface");
 	current_module->ast = ast_before_simplify;
 	current_module->nolatches = flag_nolatches;
 	current_module->nomeminit = flag_nomeminit;
@@ -1031,7 +1034,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	log_assert(current_ast->type == AST_DESIGN);
 	for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
 	{
-		if ((*it)->type == AST_MODULE)
+		if ((*it)->type == AST_MODULE || (*it)->type == AST_INTERFACE)
 		{
 			for (auto n : design->verilog_globals)
 				(*it)->children.push_back(n->clone());
@@ -1083,8 +1086,123 @@ AstModule::~AstModule()
 		delete ast;
 }
 
+void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
+{
+	bool is_top = false;
+	AstNode *new_ast = ast->clone();
+	for (auto &intf : local_interfaces) {
+		std::string intfname = intf.first.str();
+		RTLIL::Module *intfmodule = intf.second;
+		for (auto &wire_it : intfmodule->wires_){
+			AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
+			std::string newname = log_id(wire_it.first);
+			newname = intfname + "." + newname;
+			wire->str = newname;
+			new_ast->children.push_back(wire);
+		}
+	}
+	std::string original_name = this->name.str();
+	std::string changed_name = original_name + "_before_replacing_local_interfaces";
+	design->rename(this, changed_name);
+	this->set_bool_attribute("\\to_delete");
+	if (this->get_bool_attribute("\\initial_top")) {
+		this->attributes.erase("\\initial_top");
+		is_top = true;
+	}
+	AstModule *newmod = process_module(new_ast, false);
+	design->add(newmod);
+	RTLIL::Module* mod = design->module(original_name);
+	if (is_top)
+		mod->set_bool_attribute("\\top");
+	mod->set_bool_attribute("\\interfaces_replaced_in_module");
+}
+
+// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail)
+{
+	AstNode *new_ast = NULL;
+	std::string modname = derive_common(design, parameters, &new_ast, mayfail);
+
+	// Since interfaces themselves may be instantiated with different parameters,
+	// "modname" must also take those into account, so that unique modules
+	// are derived for any variant of interface connections:
+	std::string interf_info = "";
+
+	bool has_interfaces = false;
+	for(auto &intf : interfaces) {
+		interf_info += log_id(intf.second->name);
+		has_interfaces = true;
+	}
+
+	if (has_interfaces)
+		modname += "$interfaces$" + interf_info;
+
+
+	if (!design->has(modname)) {
+		new_ast->str = modname;
+		for(auto &intf : interfaces) {
+			RTLIL::Module * intfmodule = intf.second;
+			std::string intfname = intf.first.str();
+			for (auto &wire_it : intfmodule->wires_){
+				AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
+				std::string origname = log_id(wire_it.first);
+				std::string newname = intfname + "." + origname;
+				wire->str = newname;
+				wire->is_input = true;
+				wire->is_output = true;
+				new_ast->children.push_back(wire);
+			}
+		}
+
+		design->add(process_module(new_ast, false));
+		design->module(modname)->check();
+
+		RTLIL::Module* mod = design->module(modname);
+
+		for(auto &intf : interfaces) {
+			if(mod->wires_.count(intf.first)) {
+				mod->wires_.erase(intf.first);
+				mod->fixup_ports();
+				RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name);
+				new_subcell->set_bool_attribute("\\is_interface");
+			}
+			else {
+				log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname);
+			}
+		}
+
+		if (interfaces.size() > 0) {
+			mod->set_bool_attribute("\\interfaces_replaced_in_module");
+		}
+
+	} else {
+		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
+	}
+
+	delete new_ast;
+	return modname;
+}
+
+// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail)
+{
+	AstNode *new_ast = NULL;
+	std::string modname = derive_common(design, parameters, &new_ast, mayfail);
+
+	if (!design->has(modname)) {
+		new_ast->str = modname;
+		design->add(process_module(new_ast, false));
+		design->module(modname)->check();
+	} else {
+		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
+	}
+
+	delete new_ast;
+	return modname;
+}
+
 // create a new parametric module (when needed) and return the name of the generated module
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool)
+std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool)
 {
 	std::string stripped_name = name.str();
 
@@ -1156,15 +1274,8 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 	else
 		modname = "$paramod" + stripped_name + para_info;
 
-	if (!design->has(modname)) {
-		new_ast->str = modname;
-		design->add(process_module(new_ast, false));
-		design->module(modname)->check();
-	} else {
-		log("Found cached RTLIL representation for module `%s'.\n", modname.c_str());
-	}
 
-	delete new_ast;
+	(*new_ast_out) = new_ast;
 	return modname;
 }
 
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 7e97bdb3b..6b93832b4 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -142,6 +142,9 @@ namespace AST
 		AST_NEGEDGE,
 		AST_EDGE,
 
+		AST_INTERFACE,
+		AST_INTERFACEPORT,
+		AST_INTERFACEPORTTYPE,
 		AST_PACKAGE
 	};
 
@@ -284,6 +287,9 @@ namespace AST
 		bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
 		~AstModule() YS_OVERRIDE;
 		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
+		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail) YS_OVERRIDE;
+		std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
+		void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
 		RTLIL::Module *clone() const YS_OVERRIDE;
 	};
 
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index c9345ff08..1dd1a9130 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -854,6 +854,22 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_GENCASE:
 	case AST_PACKAGE:
 		break;
+	case AST_INTERFACEPORT: {
+		// If a port in a module with unknown type is found, mark it as "is_interface=true"
+		// This is used by the hierarchy pass to know when it can replace interface connection with the individual
+		// signals.
+		RTLIL::Wire *wire = current_module->addWire(str, 1);
+		wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+		wire->start_offset = 0;
+		wire->port_id = port_id;
+		wire->port_input = true;
+		wire->port_output = true;
+		wire->set_bool_attribute("\\is_interface");
+		wire->upto = 0;
+		}
+		break;
+	case AST_INTERFACEPORTTYPE:
+		break;
 
 	// remember the parameter, needed for example in techmap
 	case AST_PARAMETER:
@@ -949,6 +965,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		{
 			RTLIL::Wire *wire = NULL;
 			RTLIL::SigChunk chunk;
+			bool is_interface = false;
 
 			int add_undef_bits_msb = 0;
 			int add_undef_bits_lsb = 0;
@@ -969,15 +986,41 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				chunk = RTLIL::Const(id2ast->children[0]->bits);
 				goto use_const_chunk;
 			}
-			else if (!id2ast || (id2ast->type != AST_WIRE && id2ast->type != AST_AUTOWIRE &&
-					id2ast->type != AST_MEMORY) || current_module->wires_.count(str) == 0)
+			else if (id2ast && (id2ast->type == AST_WIRE || id2ast->type == AST_AUTOWIRE || id2ast->type == AST_MEMORY) && current_module->wires_.count(str) != 0) {
+				RTLIL::Wire *current_wire = current_module->wire(str);
+				if (current_wire->get_bool_attribute("\\is_interface"))
+					is_interface = true;
+				// Ignore
+			}
+			// If an identifier is found that is not already known, assume that it is an interface:
+			else if (1) { // FIXME: Check if sv_mode first?
+				is_interface = true;
+			}
+			else {
 				log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n",
 						str.c_str());
+			}
 
 			if (id2ast->type == AST_MEMORY)
 				log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
 					       str.c_str());
 
+			// If identifier is an interface, create a RTLIL::SigSpec object and set is_interface to true.
+			// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
+			// with the individual signals:
+			if (is_interface) {
+				RTLIL::Wire *dummy_wire;
+				std::string dummy_wire_name = "$dummywireforinterface" + str;
+				if (current_module->wires_.count(dummy_wire_name))
+					dummy_wire = current_module->wires_[dummy_wire_name];
+				else {
+					dummy_wire = current_module->addWire(dummy_wire_name);
+					dummy_wire->set_bool_attribute("\\is_interface");
+				}
+				RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire);
+				return tmp;
+			}
+
 			wire = current_module->wires_[str];
 			chunk.wire = wire;
 			chunk.width = wire->width;
@@ -1423,6 +1466,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			RTLIL::Cell *cell = current_module->addCell(str, "");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+			cell->set_bool_attribute("\\module_not_derived");
 
 			for (auto it = children.begin(); it != children.end(); it++) {
 				AstNode *child = *it;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 71eba547c..2a561ea5f 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -71,7 +71,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 	if (stage == 0)
 	{
-		log_assert(type == AST_MODULE);
+		log_assert(type == AST_MODULE || type == AST_INTERFACE);
 		last_blocking_assignment_warn = pair<string, int>();
 
 		deep_recursion_warning = true;
diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 83921bf0b..8808c2675 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -150,6 +150,9 @@ YOSYS_NAMESPACE_END
 "specparam"    { return TOK_SPECPARAM; }
 "package"      { SV_KEYWORD(TOK_PACKAGE); }
 "endpackage"   { SV_KEYWORD(TOK_ENDPACKAGE); }
+"interface"    { SV_KEYWORD(TOK_INTERFACE); }
+"endinterface" { SV_KEYWORD(TOK_ENDINTERFACE); }
+"modport"      { SV_KEYWORD(TOK_MODPORT); }
 "parameter"    { return TOK_PARAMETER; }
 "localparam"   { return TOK_LOCALPARAM; }
 "defparam"     { return TOK_DEFPARAM; }
@@ -295,6 +298,11 @@ supply1 { return TOK_SUPPLY1; }
 	return TOK_ID;
 }
 
+[a-zA-Z_$][a-zA-Z0-9_$\.]* {
+	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
+    return TOK_ID;
+}
+
 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
 	static bool printed_warning = false;
 	if (!printed_warning) {
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 16cac1460..0ff5d576e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -106,6 +106,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
+%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_BEGIN TOK_END TOK_IF TOK_ELSE TOK_FOR TOK_WHILE TOK_REPEAT
@@ -168,6 +169,7 @@ design:
 	param_decl design |
 	localparam_decl design |
 	package design |
+	interface design |
 	/* empty */;
 
 attr:
@@ -320,6 +322,21 @@ module_arg:
 		}
 		delete $1;
 	} module_arg_opt_assignment |
+	TOK_ID {
+		astbuf1 = new AstNode(AST_INTERFACEPORT);
+		astbuf1->children.push_back(new AstNode(AST_INTERFACEPORTTYPE));
+		astbuf1->children[0]->str = *$1;
+		delete $1;
+	} TOK_ID {  /* SV interfaces */
+		if (!sv_mode)
+			frontend_verilog_yyerror("Interface found in port list (%s). This is not supported unless read_verilog is called with -sv!", $3->c_str());
+		astbuf2 = astbuf1->clone(); // really only needed if multiple instances of same type.
+		astbuf2->str = *$3;
+		delete $3;
+		astbuf2->port_id = ++port_counter;
+		ast_stack.back()->children.push_back(astbuf2);
+		delete astbuf1; // really only needed if multiple instances of same type.
+	} module_arg_opt_assignment |
 	attr wire_type range TOK_ID {
 		AstNode *node = $2;
 		node->str = *$4;
@@ -357,6 +374,33 @@ package_body:
 package_body_stmt:
 	localparam_decl;
 
+interface:
+	TOK_INTERFACE TOK_ID {
+		do_not_require_port_stubs = false;
+		AstNode *intf = new AstNode(AST_INTERFACE);
+		ast_stack.back()->children.push_back(intf);
+		ast_stack.push_back(intf);
+		current_ast_mod = intf;
+		port_stubs.clear();
+		port_counter = 0;
+		intf->str = *$2;
+		delete $2;
+	} module_para_opt module_args_opt ';' interface_body TOK_ENDINTERFACE {
+		if (port_stubs.size() != 0)
+			frontend_verilog_yyerror("Missing details for module port `%s'.",
+				port_stubs.begin()->first.c_str());
+		ast_stack.pop_back();
+		log_assert(ast_stack.size() == 1);
+		current_ast_mod = NULL;
+	};
+
+interface_body:
+	interface_body interface_body_stmt |;
+
+interface_body_stmt:
+	param_decl | localparam_decl | defparam_decl | wire_decl | always_stmt | assign_stmt |
+	modport_stmt;
+
 non_opt_delay:
 	'#' TOK_ID { delete $2; } |
 	'#' TOK_CONSTVAL { delete $2; } |
@@ -1280,6 +1324,22 @@ opt_property:
 opt_stmt_label:
 	TOK_ID ':' | /* empty */;
 
+modport_stmt:
+    TOK_MODPORT TOK_ID modport_args_opt ';'
+
+modport_args_opt:
+    '(' ')' | '(' modport_args optional_comma ')';
+
+modport_args:
+    modport_arg | modport_args ',' modport_arg;
+
+modport_arg:
+    modport_type_token TOK_ID |
+    TOK_ID
+
+modport_type_token:
+    TOK_INPUT | TOK_OUTPUT
+
 assert:
 	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
 		if (noassert_mode)
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a4fa2cf04..fadac0872 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -639,6 +639,13 @@ RTLIL::Module::~Module()
 		delete it->second;
 }
 
+void RTLIL::Module::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces)
+{
+	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
+	(void)local_interfaces; // To remove build warning
+	(void)design;           // To remove build warning
+}
+
 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
 {
 	if (mayfail)
@@ -646,6 +653,14 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLI
 	log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 }
 
+
+RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*> , bool mayfail)
+{
+	if (mayfail)
+		return RTLIL::IdString();
+	log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
+}
+
 size_t RTLIL::Module::count_id(RTLIL::IdString id)
 {
 	return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 027faf416..8a2b0a4f3 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -907,7 +907,9 @@ public:
 	Module();
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false);
+	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail = false);
 	virtual size_t count_id(RTLIL::IdString id);
+	virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces);
 
 	virtual void sort();
 	virtual void check();
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 5df69848e..dd4341127 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -145,9 +145,24 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 	std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
 	std::string filename;
 
+	dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
 	for (auto &cell_it : module->cells_)
 	{
 		RTLIL::Cell *cell = cell_it.second;
+		if(cell->get_bool_attribute("\\is_interface")) {
+			RTLIL::Module *intf_module = design->modules_[cell->type];
+			interfaces_in_module[cell->name] = intf_module;
+		}
+	}
+
+	for (auto &cell_it : module->cells_)
+	{
+		RTLIL::Cell *cell = cell_it.second;
+		bool has_interfaces_not_found = false;
+
+		std::vector<RTLIL::IdString> connections_to_remove;
+		std::vector<RTLIL::IdString> connections_to_add_name;
+		std::vector<RTLIL::SigSpec> connections_to_add_signal;
 
 		if (cell->type.substr(0, 7) == "$array:") {
 			int pos_idx = cell->type.str().find_first_of(':');
@@ -158,6 +173,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			array_cells[cell] = std::pair<int, int>(idx, num);
 			cell->type = cell->type.str().substr(pos_type + 1);
 		}
+		dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule;
 
 		if (design->modules_.count(cell->type) == 0)
 		{
@@ -200,11 +216,61 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			if (design->modules_.count(cell->type) == 0)
 				log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str());
 			did_something = true;
-		} else
+		} else {
+
+		RTLIL::Module *mod = design->module(cell->type);
+
+		// Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to
+		// some lists, so that they can be replaced further down:
+		for (auto &conn : cell->connections()) {
+			if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
+				if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) {
+					std::string interface_name_str = conn.second.bits()[0].wire->name.str();
+					interface_name_str.replace(0,23,"");
+					interface_name_str = "\\" + interface_name_str;
+					RTLIL::IdString interface_name = interface_name_str;
+					bool will_do_step = false;
+					if(module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+						if (interfaces_in_module.count(interface_name) > 0) { // Check if the interface instance is present in module
+							RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name);
+						for (auto &mod_wire : mod_replace_ports->wires_) {
+							std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
+							std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
+							connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
+							if(module->wires_.count(signal_name2) == 0) {
+								log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name));
+							}
+							else {
+								RTLIL::Wire *wire_in_parent = module->wire(signal_name2);
+								connections_to_add_signal.push_back(wire_in_parent);
+							}
+						}
+						connections_to_remove.push_back(conn.first);
+						interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name);
+					  }
+					  else will_do_step = true;
+					}
+					else will_do_step = true;
+					// If the interface instance has not already been derived in the module, we cannot complete at this stage. Set "has_interfaces_not_found"
+					// which will delay the expansion of this cell:
+					if (will_do_step) {
+						// If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error:
+						if(!(module->get_bool_attribute("\\cells_not_processed"))) {
+							log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module));
+						}
+						else {
+							// Only set has_interfaces_not_found if it would be possible to find them, since otherwiser we will end up in an infinite loop:
+							has_interfaces_not_found = true;
+						}
+					}
+				}
+			}
+		}
+		//
+
 		if (flag_check || flag_simcheck)
 		{
-			RTLIL::Module *mod = design->module(cell->type);
-			for (auto &conn : cell->connections())
+			for (auto &conn : cell->connections()) {
 				if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
 					int id = atoi(conn.first.c_str()+1);
 					if (id <= 0 || id > GetSize(mod->ports))
@@ -213,11 +279,15 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 				} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
 					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
 							log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));
+			}
 			for (auto &param : cell->parameters)
 				if (mod->avail_parameters.count(param.first) == 0 && param.first[0] != '$' && strchr(param.first.c_str(), '.') == NULL)
 					log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a parameter named '%s'.\n",
 							log_id(cell->type), log_id(module), log_id(cell), log_id(param.first));
+
 		}
+		}
+		RTLIL::Module *mod = design->modules_[cell->type];
 
 		if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
 			if (flag_simcheck)
@@ -226,14 +296,58 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			continue;
 		}
 
-		if (cell->parameters.size() == 0)
+		// If interface instances not yet found, skip cell for now, and say we did something, so that we will return back here:
+		if(has_interfaces_not_found) {
+			did_something = true; // waiting for interfaces to be handled
 			continue;
+		}
 
-		RTLIL::Module *mod = design->modules_[cell->type];
-		cell->type = mod->derive(design, cell->parameters);
+		// Do the actual replacements of the SV interface port connection with the individual signal connections:
+		for(unsigned int i=0;i<connections_to_add_name.size();i++) {
+			cell->connections_[connections_to_add_name[i]] = connections_to_add_signal[i];
+		}
+		// Remove the connection for the interface itself:
+		for(unsigned int i=0;i<connections_to_remove.size();i++) {
+			cell->connections_.erase(connections_to_remove[i]);
+		}
+
+		// If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type
+		// for the cell:
+		if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) {
+			// If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:",
+			// so that the signals of the interface are added to the parent module.
+			if (mod->get_bool_attribute("\\is_interface")) {
+				goto handle_interface_instance;
+			}
+			continue;
+		}
+
+		cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule);
 		cell->parameters.clear();
 		did_something = true;
+
+		handle_interface_instance:
+
+			// We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter
+			// an interface instance:
+			if (mod->get_bool_attribute("\\is_interface") && cell->get_bool_attribute("\\module_not_derived")) {
+				cell->set_bool_attribute("\\is_interface");
+				RTLIL::Module *derived_module = design->modules_[cell->type];
+				interfaces_in_module[cell->name] = derived_module;
+				did_something = true;
+			}
+		// We unset 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
+		cell->attributes.erase("\\module_not_derived");
 	}
+	// Setting a flag such that it can be known that we have been through all cells at least once, such that we can know whether to flag
+	// an error because of interface instances not found:
+	module->attributes.erase("\\cells_not_processed");
+
+	if (interfaces_in_module.size() > 0 && !module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+		module->reprocess_module(design, interfaces_in_module);
+		return did_something;
+	}
+
 
 	for (auto &it : array_cells)
 	{
@@ -341,6 +455,20 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 	return db.at(module);
 }
 
+RTLIL::Module *check_if_top_has_changed(Design *design, Module *top_mod)
+{
+	if(top_mod != NULL && top_mod->get_bool_attribute("\\initial_top"))
+		return top_mod;
+	else {
+		for (auto mod : design->modules()) {
+			if (mod->get_bool_attribute("\\top")) {
+				return mod;
+			}
+		}
+	}
+	return NULL;
+}
+
 struct HierarchyPass : public Pass {
 	HierarchyPass() : Pass("hierarchy", "check, expand and clean up design hierarchy") { }
 	void help() YS_OVERRIDE
@@ -568,6 +696,14 @@ struct HierarchyPass : public Pass {
 		if (flag_simcheck && top_mod == nullptr)
 			log_error("Design has no top module.\n");
 
+		if (top_mod != NULL) {
+			for (auto &mod_it : design->modules_)
+				if (mod_it.second == top_mod)
+					mod_it.second->attributes["\\initial_top"] = RTLIL::Const(1);
+				else
+					mod_it.second->attributes.erase("\\initial_top");
+		}
+
 		bool did_something = true;
 		while (did_something)
 		{
@@ -586,19 +722,41 @@ struct HierarchyPass : public Pass {
 				if (expand_module(design, module, flag_check, flag_simcheck, libdirs))
 					did_something = true;
 			}
+
+
+			RTLIL::Module *tmp_top_mod = check_if_top_has_changed(design, top_mod);
+			if (tmp_top_mod != NULL) {
+				if (tmp_top_mod != top_mod){
+					top_mod = tmp_top_mod;
+					did_something = true;
+				}
+			}
+
+			std::vector<RTLIL::Module *> modules_to_delete;
+			for(auto &mod_it : design->modules_) {
+				if (mod_it.second->get_bool_attribute("\\to_delete")) {
+					modules_to_delete.push_back(mod_it.second);
+				}
+			}
+			for(size_t i=0; i<modules_to_delete.size(); i++) {
+				design->remove(modules_to_delete[i]);
+			}
 		}
 
+
 		if (top_mod != NULL) {
 			log_header(design, "Analyzing design hierarchy..\n");
 			hierarchy_clean(design, top_mod, purge_lib);
 		}
 
 		if (top_mod != NULL) {
-			for (auto &mod_it : design->modules_)
+			for (auto &mod_it : design->modules_) {
 				if (mod_it.second == top_mod)
 					mod_it.second->attributes["\\top"] = RTLIL::Const(1);
 				else
 					mod_it.second->attributes.erase("\\top");
+				mod_it.second->attributes.erase("\\initial_top");
+			}
 		}
 
 		if (!nokeep_asserts) {
diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv
new file mode 100644
index 000000000..779d50c14
--- /dev/null
+++ b/tests/simple/svinterface1.sv
@@ -0,0 +1,76 @@
+
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    input logic [1:0] sig,
+    output logic [1:0] sig_out);
+
+  MyInterface #(.WIDTH(4)) MyInterfaceInstance();
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface(MyInterfaceInstance),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance.mysig_out;
+
+
+  assign MyInterfaceInstance.setting = 1;
+  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
+
+endmodule
+
+interface MyInterface #(
+  parameter WIDTH = 3)(
+  );
+
+  logic setting;
+  logic [WIDTH-1:0] other_setting;
+
+  logic [1:0] mysig_out;
+
+endinterface
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    MyInterface u_MyInterface,
+    input logic [1:0] sig
+
+  );
+
+  always_ff @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface.mysig_out <= 0;
+    else begin
+      if(u_MyInterface.setting)
+        u_MyInterface.mysig_out <= sig;
+      else
+        u_MyInterface.mysig_out <= ~sig;
+    end
+
+  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2(u_MyInterface),
+    .sig (sig)
+  );
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    MyInterface u_MyInterfaceInSub2,
+    input logic [1:0] sig
+
+  );
+
+endmodule

From 458a94059e6738d93a87ddb9af282d0e1d28791d Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Fri, 12 Oct 2018 20:58:37 +0200
Subject: [PATCH 118/528] Support for 'modports' for System Verilog interfaces

---
 frontends/ast/ast.cc               | 40 +++++++++++++++++++++++++++---
 frontends/ast/ast.h                |  4 ++-
 frontends/ast/genrtlil.cc          | 29 ++++++++++++++++++++++
 frontends/verilog/verilog_parser.y | 24 +++++++++++++++---
 kernel/rtlil.cc                    |  2 +-
 kernel/rtlil.h                     |  2 +-
 passes/hierarchy/hierarchy.cc      | 14 ++++++++++-
 tests/simple/svinterface1.sv       | 20 ++++++++++++---
 8 files changed, 121 insertions(+), 14 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 256c08776..10fd5277a 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1118,7 +1118,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 }
 
 // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
-RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail)
+RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail)
 {
 	AstNode *new_ast = NULL;
 	std::string modname = derive_common(design, parameters, &new_ast, mayfail);
@@ -1143,14 +1143,46 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 		for(auto &intf : interfaces) {
 			RTLIL::Module * intfmodule = intf.second;
 			std::string intfname = intf.first.str();
+			AstNode *modport = NULL;
+			if (modports.count(intfname) > 0) {
+				std::string interface_modport = modports.at(intfname).str();
+				AstModule *ast_module_of_interface = (AstModule*)intfmodule;
+				AstNode *ast_node_of_interface = ast_module_of_interface->ast;
+				for (auto &ch : ast_node_of_interface->children) {
+					if (ch->type == AST_MODPORT) {
+						if (ch->str == interface_modport) {
+							modport = ch;
+						}
+					}
+				}
+			}
 			for (auto &wire_it : intfmodule->wires_){
 				AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
 				std::string origname = log_id(wire_it.first);
 				std::string newname = intfname + "." + origname;
 				wire->str = newname;
-				wire->is_input = true;
-				wire->is_output = true;
-				new_ast->children.push_back(wire);
+				if (modport != NULL) {
+					bool found_in_modport = false;
+					for (auto &ch : modport->children) {
+						if (ch->type == AST_MODPORTMEMBER) {
+							std::string compare_name = "\\" + origname;
+							if (ch->str == compare_name) {
+								found_in_modport = true;
+								wire->is_input = ch->is_input;
+								wire->is_output = ch->is_output;
+								break;
+							}
+						}
+					}
+					if (found_in_modport) { // If not found in modport, do not create port
+						new_ast->children.push_back(wire);
+					}
+				}
+				else { // If no modport, set inout
+					wire->is_input = true;
+					wire->is_output = true;
+					new_ast->children.push_back(wire);
+				}
 			}
 		}
 
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 6b93832b4..8187b1ac6 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -145,6 +145,8 @@ namespace AST
 		AST_INTERFACE,
 		AST_INTERFACEPORT,
 		AST_INTERFACEPORTTYPE,
+		AST_MODPORT,
+		AST_MODPORTMEMBER,
 		AST_PACKAGE
 	};
 
@@ -287,7 +289,7 @@ namespace AST
 		bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
 		~AstModule() YS_OVERRIDE;
 		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail) YS_OVERRIDE;
-		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail) YS_OVERRIDE;
+		RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail) YS_OVERRIDE;
 		std::string derive_common(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, AstNode **new_ast_out, bool mayfail);
 		void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces) YS_OVERRIDE;
 		RTLIL::Module *clone() const YS_OVERRIDE;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 1dd1a9130..d87163dc2 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -853,6 +853,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_GENIF:
 	case AST_GENCASE:
 	case AST_PACKAGE:
+	case AST_MODPORT:
+	case AST_MODPORTMEMBER:
 		break;
 	case AST_INTERFACEPORT: {
 		// If a port in a module with unknown type is found, mark it as "is_interface=true"
@@ -865,6 +867,33 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		wire->port_input = true;
 		wire->port_output = true;
 		wire->set_bool_attribute("\\is_interface");
+		if (children.size() > 0) {
+			for(size_t i=0; i<children.size();i++) {
+				if(children[i]->type == AST_INTERFACEPORTTYPE) {
+					std::string name_type = children[i]->str;
+					size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
+					if (ndots == 0) {
+						wire->attributes["\\interface_type"] = name_type;
+					}
+					else {
+						std::stringstream name_type_stream(name_type);
+						std::string segment;
+						std::vector<std::string> seglist;
+						while(std::getline(name_type_stream, segment, '.')) {
+							seglist.push_back(segment);
+						}
+						if (ndots == 1) {
+							wire->attributes["\\interface_type"] = seglist[0];
+							wire->attributes["\\interface_modport"] = seglist[1];
+						}
+						else {
+							log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
+						}
+					}
+					break;
+				}
+			}
+		}
 		wire->upto = 0;
 		}
 		break;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 0ff5d576e..a6f37008a 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -61,6 +61,7 @@ namespace VERILOG_FRONTEND {
 	bool noassert_mode, noassume_mode, norestrict_mode;
 	bool assume_asserts_mode, assert_assumes_mode;
 	bool current_wire_rand, current_wire_const;
+	bool current_modport_input, current_modport_output;
 	std::istream *lexin;
 }
 YOSYS_NAMESPACE_END
@@ -1325,7 +1326,16 @@ opt_stmt_label:
 	TOK_ID ':' | /* empty */;
 
 modport_stmt:
-    TOK_MODPORT TOK_ID modport_args_opt ';'
+    TOK_MODPORT TOK_ID {
+        AstNode *modport = new AstNode(AST_MODPORT);
+        ast_stack.back()->children.push_back(modport);
+        ast_stack.push_back(modport);
+        modport->str = *$2;
+        delete $2;
+    }  modport_args_opt {
+        ast_stack.pop_back();
+        log_assert(ast_stack.size() == 2);
+    } ';'
 
 modport_args_opt:
     '(' ')' | '(' modport_args optional_comma ')';
@@ -1334,11 +1344,19 @@ modport_args:
     modport_arg | modport_args ',' modport_arg;
 
 modport_arg:
-    modport_type_token TOK_ID |
+    modport_type_token TOK_ID {
+        AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
+        ast_stack.back()->children.push_back(modport_member);
+        modport_member->str = *$2;
+        modport_member->is_input = current_modport_input;
+        modport_member->is_output = current_modport_output;
+        delete $2;
+    } |
     TOK_ID
+    /* FIXME for TOK_ID without modport_type_token */
 
 modport_type_token:
-    TOK_INPUT | TOK_OUTPUT
+    TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
 
 assert:
 	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index fadac0872..07dd4bfa0 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -654,7 +654,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLI
 }
 
 
-RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*> , bool mayfail)
+RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, dict<RTLIL::IdString, RTLIL::Module*>, dict<RTLIL::IdString, RTLIL::IdString>, bool mayfail)
 {
 	if (mayfail)
 		return RTLIL::IdString();
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8a2b0a4f3..276540aa1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -907,7 +907,7 @@ public:
 	Module();
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false);
-	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail = false);
+	virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail = false);
 	virtual size_t count_id(RTLIL::IdString id);
 	virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces);
 
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index dd4341127..f2f0d6e5b 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -174,6 +174,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			cell->type = cell->type.str().substr(pos_type + 1);
 		}
 		dict<RTLIL::IdString, RTLIL::Module*> interfaces_to_add_to_submodule;
+		dict<RTLIL::IdString, RTLIL::IdString> modports_used_in_submodule;
 
 		if (design->modules_.count(cell->type) == 0)
 		{
@@ -224,6 +225,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 		// some lists, so that they can be replaced further down:
 		for (auto &conn : cell->connections()) {
 			if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
+				//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
+				//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module
+				//}
+				const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport");
+				std::string interface_modport = "";
+				for (auto &d : interface_modport_pool) {
+					interface_modport = "\\" + d;
+				}
 				if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) {
 					std::string interface_name_str = conn.second.bits()[0].wire->name.str();
 					interface_name_str.replace(0,23,"");
@@ -247,6 +256,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 						}
 						connections_to_remove.push_back(conn.first);
 						interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name);
+						if (interface_modport != "") {
+							modports_used_in_submodule[conn.first] = interface_modport;
+						}
 					  }
 					  else will_do_step = true;
 					}
@@ -322,7 +334,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 			continue;
 		}
 
-		cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule);
+		cell->type = mod->derive(design, cell->parameters, interfaces_to_add_to_submodule, modports_used_in_submodule);
 		cell->parameters.clear();
 		did_something = true;
 
diff --git a/tests/simple/svinterface1.sv b/tests/simple/svinterface1.sv
index 779d50c14..64383a06c 100644
--- a/tests/simple/svinterface1.sv
+++ b/tests/simple/svinterface1.sv
@@ -19,7 +19,7 @@ module TopModule(
 
 
   assign MyInterfaceInstance.setting = 1;
-  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
+//  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
 
 endmodule
 
@@ -32,13 +32,25 @@ interface MyInterface #(
 
   logic [1:0] mysig_out;
 
+    modport submodule1 (
+        input  setting,
+        output other_setting,
+        output mysig_out
+    );
+
+    modport submodule2 (
+        input  setting,
+        output other_setting,
+        input  mysig_out
+    );
+
 endinterface
 
 
 module SubModule1(
     input logic clk,
     input logic rst,
-    MyInterface u_MyInterface,
+    MyInterface.submodule1 u_MyInterface,
     input logic [1:0] sig
 
   );
@@ -68,9 +80,11 @@ module SubModule2(
 
     input logic clk,
     input logic rst,
-    MyInterface u_MyInterfaceInSub2,
+    MyInterface.submodule2 u_MyInterfaceInSub2,
     input logic [1:0] sig
 
   );
 
+   assign u_MyInterfaceInSub2.other_setting[2:0] = 9;
+
 endmodule

From a36d1701dd99736b82f64ed870e7464f2deae220 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Fri, 12 Oct 2018 22:02:29 +0200
Subject: [PATCH 119/528] Fix build error with clang

---
 frontends/ast/ast.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 10fd5277a..b3f78c922 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1199,7 +1199,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 				new_subcell->set_bool_attribute("\\is_interface");
 			}
 			else {
-				log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname);
+				log_error("No port with matching name found (%s) in %s. Stopping\n", log_id(intf.first), modname.c_str());
 			}
 		}
 

From 302edf04291467469f8f48bd60edadbf1ee54798 Mon Sep 17 00:00:00 2001
From: tklam <tklam@easylogic.hk>
Date: Sat, 13 Oct 2018 23:11:19 +0800
Subject: [PATCH 120/528] stop check_signal_in_fanout from traversing FFs

---
 passes/equiv/equiv_make.cc | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index e74dab36f..e75482e9f 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -42,6 +42,14 @@ struct EquivMakeWorker
 
 	dict<SigBit, pool<Cell*>> bit2driven; // map: bit <--> and its driven cells
 
+	CellTypes comb_ct;
+
+	EquivMakeWorker()
+	{
+		comb_ct.setup_internals();
+		comb_ct.setup_stdcells();
+	}
+
 	void read_blacklists()
 	{
 		for (auto fn : blacklists)
@@ -415,9 +423,12 @@ struct EquivMakeWorker
 		auto driven_cells = bit2driven.at(source_bit);
 		for (auto driven_cell: driven_cells)
 		{
-			if (visited_cells.count(driven_cell) > 0)
+			bool is_comb = comb_ct.cell_known(cell->type);
+			if (is_comb)
 				continue;
 
+			if (visited_cells.count(driven_cell) > 0)
+				continue;
 			visited_cells.insert(driven_cell);
 
 			for (auto &conn: driven_cell->connections())

From f4343b3dc7dfb1908848b21b406f13884e8c407a Mon Sep 17 00:00:00 2001
From: tklam <tklam@easylogic.hk>
Date: Sat, 13 Oct 2018 23:24:24 +0800
Subject: [PATCH 121/528] stop check_signal_in_fanout from traversing FFs

---
 passes/equiv/equiv_make.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index e75482e9f..66ee28aff 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -423,8 +423,8 @@ struct EquivMakeWorker
 		auto driven_cells = bit2driven.at(source_bit);
 		for (auto driven_cell: driven_cells)
 		{
-			bool is_comb = comb_ct.cell_known(cell->type);
-			if (is_comb)
+			bool is_comb = comb_ct.cell_known(driven_cell->type);
+			if (!is_comb)
 				continue;
 
 			if (visited_cells.count(driven_cell) > 0)

From 455638e00dff4951e666fb91fbd80de6b9e95f9f Mon Sep 17 00:00:00 2001
From: argama <argama@gmail.com>
Date: Sun, 14 Oct 2018 01:42:48 +0800
Subject: [PATCH 122/528] detect ff/latch before processing other nodes

---
 frontends/liberty/liberty.cc | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 0a5bd84de..0018d6dac 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -634,6 +634,8 @@ struct LibertyFrontend : public Frontend {
 				}
 			}
 
+			// some liberty files do not put ff/latch at the beginning of a cell
+			// try to find "ff" or "latch" and create FF/latch before processing all other nodes 
 			for (auto node : cell->children)
 			{
 				if (!flag_lib) {
@@ -645,6 +647,21 @@ struct LibertyFrontend : public Frontend {
 							goto skip_cell;
 						}
 				}
+			}
+
+			for (auto node : cell->children)
+			{
+				/*
+				if (!flag_lib) {
+					if (node->id == "ff" && node->args.size() == 2)
+						create_ff(module, node);
+					if (node->id == "latch" && node->args.size() == 2)
+						if (!create_latch(module, node, flag_ignore_miss_data_latch)) {
+							delete module;
+							goto skip_cell;
+						}
+				}
+				*/
 
 				if (node->id == "pin" && node->args.size() == 1)
 				{

From c50afc4246d552db079aec303b0d79ae92107a67 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 13 Oct 2018 20:34:44 +0200
Subject: [PATCH 123/528] Documentation improvements etc.

- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
---
 README.md                     |  3 ++
 frontends/ast/ast.cc          | 31 +++++++++++++++--
 frontends/ast/genrtlil.cc     | 12 ++++---
 kernel/rtlil.cc               |  4 +--
 passes/hierarchy/hierarchy.cc | 65 ++++++++++++++++++++---------------
 5 files changed, 77 insertions(+), 38 deletions(-)

diff --git a/README.md b/README.md
index 41ae4ac18..8c5dd9419 100644
--- a/README.md
+++ b/README.md
@@ -452,6 +452,9 @@ from SystemVerilog:
   into a design with ``read_verilog``, all its packages are available to
   SystemVerilog files being read into the same design afterwards.
 
+- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether
+  ports are inputs or outputs are supported.
+
 
 Building the documentation
 ==========================
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index b3f78c922..7600e2912 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Ruben Undheim <ruben.undheim@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -1086,6 +1087,8 @@ AstModule::~AstModule()
 		delete ast;
 }
 
+// When an interface instance is found in a module, the whole RTLIL for the module will be rederived again
+// from AST. The interface members are copied into the AST module with the prefix of the interface.
 void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
 {
 	bool is_top = false;
@@ -1101,23 +1104,33 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 			new_ast->children.push_back(wire);
 		}
 	}
+
+	// The old module will be deleted. Rename and mark for deletion:
 	std::string original_name = this->name.str();
 	std::string changed_name = original_name + "_before_replacing_local_interfaces";
 	design->rename(this, changed_name);
 	this->set_bool_attribute("\\to_delete");
+
+	// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
+	// new module.
 	if (this->get_bool_attribute("\\initial_top")) {
 		this->attributes.erase("\\initial_top");
 		is_top = true;
 	}
+
+	// Generate RTLIL from AST for the new module and add to the design:
 	AstModule *newmod = process_module(new_ast, false);
 	design->add(newmod);
 	RTLIL::Module* mod = design->module(original_name);
 	if (is_top)
 		mod->set_bool_attribute("\\top");
+
+	// Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
 	mod->set_bool_attribute("\\interfaces_replaced_in_module");
 }
 
 // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
+// This method is used to explode the interface when the interface is a port of the module (not instantiated inside)
 RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, dict<RTLIL::IdString, RTLIL::IdString> modports, bool mayfail)
 {
 	AstNode *new_ast = NULL;
@@ -1140,9 +1153,12 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 
 	if (!design->has(modname)) {
 		new_ast->str = modname;
+
+		// Iterate over all interfaces which are ports in this module:
 		for(auto &intf : interfaces) {
 			RTLIL::Module * intfmodule = intf.second;
 			std::string intfname = intf.first.str();
+			// Check if a modport applies for the interface port:
 			AstNode *modport = NULL;
 			if (modports.count(intfname) > 0) {
 				std::string interface_modport = modports.at(intfname).str();
@@ -1150,12 +1166,13 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 				AstNode *ast_node_of_interface = ast_module_of_interface->ast;
 				for (auto &ch : ast_node_of_interface->children) {
 					if (ch->type == AST_MODPORT) {
-						if (ch->str == interface_modport) {
+						if (ch->str == interface_modport) { // Modport found
 							modport = ch;
 						}
 					}
 				}
 			}
+			// Iterate over all wires in the interface and add them to the module:
 			for (auto &wire_it : intfmodule->wires_){
 				AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
 				std::string origname = log_id(wire_it.first);
@@ -1163,10 +1180,11 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 				wire->str = newname;
 				if (modport != NULL) {
 					bool found_in_modport = false;
+					// Search for the current wire in the wire list for the current modport
 					for (auto &ch : modport->children) {
 						if (ch->type == AST_MODPORTMEMBER) {
 							std::string compare_name = "\\" + origname;
-							if (ch->str == compare_name) {
+							if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
 								found_in_modport = true;
 								wire->is_input = ch->is_input;
 								wire->is_output = ch->is_output;
@@ -1174,9 +1192,12 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 							}
 						}
 					}
-					if (found_in_modport) { // If not found in modport, do not create port
+					if (found_in_modport) {
 						new_ast->children.push_back(wire);
 					}
+					else { // If not found in modport, do not create port
+						delete wire;
+					}
 				}
 				else { // If no modport, set inout
 					wire->is_input = true;
@@ -1191,10 +1212,13 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 
 		RTLIL::Module* mod = design->module(modname);
 
+		// Now that the interfaces have been exploded, we can delete the dummy port related to every interface.
 		for(auto &intf : interfaces) {
 			if(mod->wires_.count(intf.first)) {
 				mod->wires_.erase(intf.first);
 				mod->fixup_ports();
+				// We copy the cell of the interface to the sub-module such that it can further be found if it is propagated
+				// down to sub-sub-modules etc.
 				RTLIL::Cell * new_subcell = mod->addCell(intf.first, intf.second->name);
 				new_subcell->set_bool_attribute("\\is_interface");
 			}
@@ -1203,6 +1227,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 			}
 		}
 
+		// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
 		if (interfaces.size() > 0) {
 			mod->set_bool_attribute("\\interfaces_replaced_in_module");
 		}
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d87163dc2..32b9af6e9 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -857,7 +857,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_MODPORTMEMBER:
 		break;
 	case AST_INTERFACEPORT: {
-		// If a port in a module with unknown type is found, mark it as "is_interface=true"
+		// If a port in a module with unknown type is found, mark it with the attribute 'is_interface'
 		// This is used by the hierarchy pass to know when it can replace interface connection with the individual
 		// signals.
 		RTLIL::Wire *wire = current_module->addWire(str, 1);
@@ -872,7 +872,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				if(children[i]->type == AST_INTERFACEPORTTYPE) {
 					std::string name_type = children[i]->str;
 					size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
-					if (ndots == 0) {
+					// Separate the interface instance name from any modports:
+					if (ndots == 0) { // Does not have modport
 						wire->attributes["\\interface_type"] = name_type;
 					}
 					else {
@@ -882,11 +883,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						while(std::getline(name_type_stream, segment, '.')) {
 							seglist.push_back(segment);
 						}
-						if (ndots == 1) {
+						if (ndots == 1) { // Has modport
 							wire->attributes["\\interface_type"] = seglist[0];
 							wire->attributes["\\interface_modport"] = seglist[1];
 						}
-						else {
+						else { // Erroneous port type
 							log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
 						}
 					}
@@ -1034,7 +1035,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
 					       str.c_str());
 
-			// If identifier is an interface, create a RTLIL::SigSpec object and set is_interface to true.
+			// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
 			// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
 			// with the individual signals:
 			if (is_interface) {
@@ -1495,6 +1496,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			RTLIL::Cell *cell = current_module->addCell(str, "");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
+			// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
 			cell->set_bool_attribute("\\module_not_derived");
 
 			for (auto it = children.begin(); it != children.end(); it++) {
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 07dd4bfa0..14259f8ed 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -639,11 +639,9 @@ RTLIL::Module::~Module()
 		delete it->second;
 }
 
-void RTLIL::Module::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces)
+void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
 {
 	log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name));
-	(void)local_interfaces; // To remove build warning
-	(void)design;           // To remove build warning
 }
 
 RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, dict<RTLIL::IdString, RTLIL::Const>, bool mayfail)
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index f2f0d6e5b..7e93a6f9a 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  Ruben Undheim <ruben.undheim@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -145,6 +146,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 	std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
 	std::string filename;
 
+	// Always keep track of all derived interfaces available in the current module in 'interfaces_in_module':
 	dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
 	for (auto &cell_it : module->cells_)
 	{
@@ -222,50 +224,54 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 		RTLIL::Module *mod = design->module(cell->type);
 
 		// Go over all connections and see if any of them are SV interfaces. If they are, then add the replacements to
-		// some lists, so that they can be replaced further down:
+		// some lists, so that the ports for sub-modules can be replaced further down:
 		for (auto &conn : cell->connections()) {
 			if(mod->wires_.count(conn.first) != 0 && mod->wire(conn.first)->get_bool_attribute("\\is_interface")) { // Check if the connection is present as an interface in the sub-module's port list
 				//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type");
-				//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module
+				//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
 				//}
+
+				// Find if the sub-module has set a modport for the current interface connection:
 				const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport");
 				std::string interface_modport = "";
 				for (auto &d : interface_modport_pool) {
 					interface_modport = "\\" + d;
 				}
-				if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) {
+				if(conn.second.bits().size() == 1 && conn.second.bits()[0].wire->get_bool_attribute("\\is_interface")) { // Check if the connected wire is a potential interface in the parent module
 					std::string interface_name_str = conn.second.bits()[0].wire->name.str();
-					interface_name_str.replace(0,23,"");
+					interface_name_str.replace(0,23,""); // Strip the prefix '$dummywireforinterface' from the dummy wire to get the name
 					interface_name_str = "\\" + interface_name_str;
 					RTLIL::IdString interface_name = interface_name_str;
-					bool will_do_step = false;
-					if(module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+					bool not_found_interface = false;
+					if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
 						if (interfaces_in_module.count(interface_name) > 0) { // Check if the interface instance is present in module
 							RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name);
-						for (auto &mod_wire : mod_replace_ports->wires_) {
-							std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
-							std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
-							connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
-							if(module->wires_.count(signal_name2) == 0) {
-								log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name));
+							for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists.
+								std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
+								std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
+								connections_to_add_name.push_back(RTLIL::IdString(signal_name1));
+								if(module->wires_.count(signal_name2) == 0) {
+									log_error("Could not find signal '%s' in '%s'\n", signal_name2.c_str(), log_id(module->name));
+								}
+								else {
+									RTLIL::Wire *wire_in_parent = module->wire(signal_name2);
+									connections_to_add_signal.push_back(wire_in_parent);
+								}
 							}
-							else {
-								RTLIL::Wire *wire_in_parent = module->wire(signal_name2);
-								connections_to_add_signal.push_back(wire_in_parent);
+							connections_to_remove.push_back(conn.first);
+							interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name);
+
+							// Add modports to a dict which will be passed to AstModule::derive
+							if (interface_modport != "") {
+								modports_used_in_submodule[conn.first] = interface_modport;
 							}
 						}
-						connections_to_remove.push_back(conn.first);
-						interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name);
-						if (interface_modport != "") {
-							modports_used_in_submodule[conn.first] = interface_modport;
-						}
-					  }
-					  else will_do_step = true;
+						else not_found_interface = true;
 					}
-					else will_do_step = true;
+					else not_found_interface = true;
 					// If the interface instance has not already been derived in the module, we cannot complete at this stage. Set "has_interfaces_not_found"
 					// which will delay the expansion of this cell:
-					if (will_do_step) {
+					if (not_found_interface) {
 						// If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error:
 						if(!(module->get_bool_attribute("\\cells_not_processed"))) {
 							log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module));
@@ -348,13 +354,16 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 				interfaces_in_module[cell->name] = derived_module;
 				did_something = true;
 			}
-		// We unset 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
+		// We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
 		cell->attributes.erase("\\module_not_derived");
 	}
-	// Setting a flag such that it can be known that we have been through all cells at least once, such that we can know whether to flag
-	// an error because of interface instances not found:
+	// Clear the attribute 'cells_not_processed' such that it can be known that we
+	// have been through all cells at least once, and that we can know whether
+	// to flag an error because of interface instances not found:
 	module->attributes.erase("\\cells_not_processed");
 
+
+	// If any interface instances were found in the module, we need to rederive it completely:
 	if (interfaces_in_module.size() > 0 && !module->get_bool_attribute("\\interfaces_replaced_in_module")) {
 		module->reprocess_module(design, interfaces_in_module);
 		return did_something;
@@ -736,6 +745,7 @@ struct HierarchyPass : public Pass {
 			}
 
 
+			// The top module might have changed if interface instances have been detected in it:
 			RTLIL::Module *tmp_top_mod = check_if_top_has_changed(design, top_mod);
 			if (tmp_top_mod != NULL) {
 				if (tmp_top_mod != top_mod){
@@ -744,6 +754,7 @@ struct HierarchyPass : public Pass {
 				}
 			}
 
+			// Delete modules marked as 'to_delete':
 			std::vector<RTLIL::Module *> modules_to_delete;
 			for(auto &mod_it : design->modules_) {
 				if (mod_it.second->get_bool_attribute("\\to_delete")) {

From 736105b0468f9468f00915cad60949535ce5a496 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 13 Oct 2018 20:48:55 +0200
Subject: [PATCH 124/528] Handle FIXME for modport members without type
 directly in front

---
 frontends/verilog/verilog_parser.y | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index a6f37008a..4dbe028a0 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1344,16 +1344,18 @@ modport_args:
     modport_arg | modport_args ',' modport_arg;
 
 modport_arg:
-    modport_type_token TOK_ID {
+    modport_type_token modport_member |
+    modport_member
+
+modport_member:
+    TOK_ID {
         AstNode *modport_member = new AstNode(AST_MODPORTMEMBER);
         ast_stack.back()->children.push_back(modport_member);
-        modport_member->str = *$2;
+        modport_member->str = *$1;
         modport_member->is_input = current_modport_input;
         modport_member->is_output = current_modport_output;
-        delete $2;
-    } |
-    TOK_ID
-    /* FIXME for TOK_ID without modport_type_token */
+        delete $1;
+    }
 
 modport_type_token:
     TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}

From 749b3ed62a8665f756267fafd7520beb55570df5 Mon Sep 17 00:00:00 2001
From: Aman Goel <amangoel@umich.edu>
Date: Mon, 15 Oct 2018 13:54:12 -0400
Subject: [PATCH 125/528] Minor update

---
 Makefile            | 4 ++--
 backends/smv/smv.cc | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index bfe6e28c4..365b92ea4 100644
--- a/Makefile
+++ b/Makefile
@@ -1,6 +1,6 @@
 
-# CONFIG := clang
-CONFIG := gcc
+CONFIG := clang
+# CONFIG := gcc
 # CONFIG := gcc-4.8
 # CONFIG := emcc
 # CONFIG := mxe
diff --git a/backends/smv/smv.cc b/backends/smv/smv.cc
index a53ee7a7c..f379c9c48 100644
--- a/backends/smv/smv.cc
+++ b/backends/smv/smv.cc
@@ -232,7 +232,7 @@ struct SmvWorker
 				SigSpec sig_a = cell->getPort("\\A");
 				SigSpec sig_en = cell->getPort("\\EN");
 
-				invarspecs.push_back(stringf("(!bool(%s) | bool(%s));", rvalue(sig_en), rvalue(sig_a)));
+				invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
 
 				continue;
 			}

From df4bfa0ad69c1c4ba75222616d02dae3d1abe5de Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 16 Oct 2018 12:48:39 +0100
Subject: [PATCH 126/528] ecp5: Disable LSR inversion

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/brams_map.v | 10 +++++-----
 techlibs/ecp5/cells_map.v | 32 ++++++++++++++++----------------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/techlibs/ecp5/brams_map.v b/techlibs/ecp5/brams_map.v
index 7f40f8458..b2c136863 100644
--- a/techlibs/ecp5/brams_map.v
+++ b/techlibs/ecp5/brams_map.v
@@ -38,7 +38,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_1.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS == 2) begin
@@ -55,7 +55,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_2.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 4) begin
@@ -72,7 +72,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_4.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 9) begin
@@ -89,7 +89,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_9.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else if (CFG_DBITS <= 18) begin
@@ -106,7 +106,7 @@ module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 			`include "bram_conn_18.vh"
 			.CLKA(CLK2), .CLKB(CLK3),
 			.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
-			.WEB(1'b0), .CEB(1'b1), .OCEB(B1EN),
+			.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
 			.RSTA(1'b0), .RSTB(1'b0)
 		);
 	end else begin
diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 48162a4dc..23182bdeb 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -7,40 +7,40 @@ module  \$_DFFE_PN_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .C
 module  \$_DFFE_NP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 module  \$_DFFE_PP_ (input D, C, E, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(1'b0), .DI(D), .Q(Q)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$_DFF_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$_DFF_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$_DFF_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_NN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFS_PN1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$__DFFS_NP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFS_NP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFS_PP0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFS_PP1_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$__DFFE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
-module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
-module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("INV"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_NN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
+module  \$__DFFSE_PN1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(!R), .DI(D), .Q(Q)); endmodule
 
 module  \$__DFFSE_NP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule

From 500726781bd382f269f6c48dd198ee08587641a4 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 16 Oct 2018 15:28:37 +0200
Subject: [PATCH 127/528] Update command reference manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 manual/command-reference-manual.tex | 1332 ++++++++++++++++++++++++---
 1 file changed, 1196 insertions(+), 136 deletions(-)

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index fea2354e6..bed6326e2 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -23,45 +23,47 @@ library to a target architecture.
         if no -script parameter is given, the following scripts are used:
 
         for -liberty without -constr:
-          strash; dc2; scorr; ifraig; retime -o {D}; strash; dch -f;
-               map {D}
+          strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
+               &nf {D}; &put
 
         for -liberty with -constr:
-          strash; dc2; scorr; ifraig; retime -o {D}; strash; dch -f;
-               map {D}; buffer; upsize {D}; dnsize {D}; stime -p
+          strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
+               &nf {D}; &put; buffer; upsize {D}; dnsize {D}; stime -p
 
         for -lut/-luts (only one LUT size):
-          strash; dc2; scorr; ifraig; retime -o; strash; dch -f; if; mfs;
-               lutpack
+          strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2;
+               lutpack {S}
 
         for -lut/-luts (different LUT sizes):
-          strash; dc2; scorr; ifraig; retime -o; strash; dch -f; if; mfs
+          strash; ifraig; scorr; dc2; dretime; strash; dch -f; if; mfs2
 
         for -sop:
-          strash; dc2; scorr; ifraig; retime -o; strash; dch -f;
+          strash; ifraig; scorr; dc2; dretime; strash; dch -f;
                cover {I} {P}
 
         otherwise:
-          strash; dc2; scorr; ifraig; retime -o; strash; dch -f; map
+          strash; ifraig; scorr; dc2; dretime; strash; &get -n; &dch -f;
+               &nf {D}; &put
 
     -fast
         use different default scripts that are slightly faster (at the cost
         of output quality):
 
         for -liberty without -constr:
-          retime -o {D}; map {D}
+          strash; dretime; map {D}
 
         for -liberty with -constr:
-          retime -o {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p
+          strash; dretime; map {D}; buffer; upsize {D}; dnsize {D};
+               stime -p
 
         for -lut/-luts:
-          retime -o; if
+          strash; dretime; if
 
         for -sop:
-          retime -o; cover -I {I} -P {P}
+          strash; dretime; cover -I {I} -P {P}
 
         otherwise:
-          retime -o; map
+          strash; dretime; map
 
     -liberty <file>
         generate netlists for the specified cell library (using the liberty
@@ -81,6 +83,8 @@ library to a target architecture.
     -D <picoseconds>
         set delay target. the string {D} in the default scripts above is
         replaced by this option when used, and an empty string otherwise.
+        this also replaces 'dretime' with 'dretime; retime -o {D}' in the
+        default scripts above.
 
     -I <num>
         maximum number of SOP inputs.
@@ -90,6 +94,10 @@ library to a target architecture.
         maximum number of SOP products.
         (replaces {P} in the default scripts above)
 
+    -S <num>
+        maximum number of LUT inputs shared.
+        (replaces {S} in the default scripts above, default: -S 1)
+
     -lut <width>
         generate netlist using luts of (max) the specified width.
 
@@ -107,10 +115,21 @@ library to a target architecture.
         map to sum-of-product cells and inverters
 
     -g type1,type2,...
-        Map the the specified list of gate types. Supported gates types are:
-        AND, NAND, OR, NOR, XOR, XNOR, MUX, AOI3, OAI3, AOI4, OAI4.
+        Map to the specified list of gate types. Supported gates types are:
+        AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX, AOI3, OAI3, AOI4, OAI4.
         (The NOT gate is always added to this list automatically.)
 
+        The following aliases can be used to reference common sets of gate types:
+          simple: AND OR XOR MUX
+          cmos2: NAND NOR
+          cmos3: NAND NOR AOI3 OAI3
+          cmos4: NAND NOR AOI3 OAI3 AOI4 OAI4
+          gates: AND NAND OR NOR XOR XNOR ANDNOT ORNOT
+          aig: AND NAND OR NOR ANDNOT ORNOT
+
+        Prefix a gate type with a '-' to remove it from the list. For example
+        the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.
+
     -dff
         also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
         clock domains are automatically partitioned in clock domains and each
@@ -140,8 +159,12 @@ library to a target architecture.
 When neither -liberty nor -lut is used, the Yosys standard cell library is
 loaded into ABC before the ABC script is executed.
 
-This pass does not operate on modules with unprocessed processes in it.
-(I.e. the 'proc' pass should be used first to convert processes to netlists.)
+Note that this is a logic optimization pass within Yosys that is calling ABC
+internally. This is not going to "run ABC on your design". It will instead run
+ABC on logic snippets extracted from your design. You will not get any useful
+output when passing an ABC script that writes a file. Instead write your full
+design as BLIF file with write_blif and the load that into ABC externally if
+you want to use ABC to convert your design into another format.
 
 [1] http://www.eecs.berkeley.edu/~alanmi/abc/
 \end{lstlisting}
@@ -206,6 +229,22 @@ This command adds asserts to the design that assert that all parallel muxes
         additional constrained and check the $pmux condition always.
 \end{lstlisting}
 
+\section{async2sync -- convert async FF inputs to sync circuits}
+\label{cmd:async2sync}
+\begin{lstlisting}[numbers=left,frame=single]
+    async2sync [options] [selection]
+
+This command replaces async FF inputs with sync circuits emulating the same
+behavior for when the async signals are actually synchronized to the clock.
+
+This pass assumes negative hold time for the async FF inputs. For example when
+a reset deasserts with the clock edge, then the FF output will still drive the
+reset value in the next cycle regardless of the data-in value at the time of
+the clock edge.
+
+Currently only $adff cells are supported by this pass.
+\end{lstlisting}
+
 \section{attrmap -- renaming attributes}
 \label{cmd:attrmap}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -268,6 +307,15 @@ Move or copy attributes on wires to the cells driving them.
         multiple times.
 \end{lstlisting}
 
+\section{blackbox -- change type of cells in the design}
+\label{cmd:blackbox}
+\begin{lstlisting}[numbers=left,frame=single]
+    blackbox [options] [selection]
+
+Convert modules into blackbox modules (remove contents and set the blackbox
+module attribute).
+\end{lstlisting}
+
 \section{cd -- a shortcut for 'select -module <name>'}
 \label{cmd:cd}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -284,6 +332,12 @@ to 'cd <celltype>'.
 
     cd ..
 
+Remove trailing substrings that start with '.' in current module name until
+the name of a module in the current design is generated, then switch to that
+module. Otherwise clear the current selection.
+
+    cd
+
 This is just a shortcut for 'select -clear'.
 \end{lstlisting}
 
@@ -303,10 +357,49 @@ This pass identifies the following problems in the current design:
 When called with -noinit then this command also checks for wires which have
 the 'init' attribute set.
 
+When called with -initdrv then this command also checks for wires which have
+the 'init' attribute set and aren't driven by a FF cell type.
+
 When called with -assert then the command will produce an error if any
 problems are found in the current design.
 \end{lstlisting}
 
+\section{chformal -- change formal constraints of the design}
+\label{cmd:chformal}
+\begin{lstlisting}[numbers=left,frame=single]
+    chformal [types] [mode] [options] [selection]
+
+Make changes to the formal constraints of the design. The [types] options
+the type of constraint to operate on. If none of the folling options is given,
+the command will operate on all constraint types:
+
+    -assert       $assert cells, representing assert(...) constraints
+    -assume       $assume cells, representing assume(...) constraints
+    -live         $live cells, representing assert(s_eventually ...)
+    -fair         $fair cells, representing assume(s_eventually ...)
+    -cover        $cover cells, representing cover() statements
+
+Exactly one of the following modes must be specified:
+
+    -remove
+        remove the cells and thus constraints from the design
+
+    -early
+        bypass FFs that only delay the activation of a constraint
+
+    -delay <N>
+        delay activation of the constraint by <N> clock cycles
+
+    -skip <N>
+        ignore activation of the constraint in the first <N> clock cycles
+
+    -assert2assume
+    -assume2assert
+    -live2fair
+    -fair2live
+        change the roles of cells as indicated. this options can be combined
+\end{lstlisting}
+
 \section{chparam -- re-evaluate modules with new parameters}
 \label{cmd:chparam}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -321,6 +414,20 @@ passed in double quotes (").
 List the available parameters of the selected modules.
 \end{lstlisting}
 
+\section{chtype -- change type of cells in the design}
+\label{cmd:chtype}
+\begin{lstlisting}[numbers=left,frame=single]
+    chtype [options] [selection]
+
+Change the types of cells in the design.
+
+    -set <type>
+        set the cell type to the given type
+
+    -map <old_type> <new_type>
+        change cells types that match <old_type> to <new_type>
+\end{lstlisting}
+
 \section{clean -- remove unused cells and wires}
 \label{cmd:clean}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -376,7 +483,7 @@ be selected or an active module must be set using the 'cd' command.
 This command does not operate on module with processes.
 \end{lstlisting}
 
-\section{connwrappers -- replace undef values with defined constants}
+\section{connwrappers -- match width of input-output port pairs}
 \label{cmd:connwrappers}
 \begin{lstlisting}[numbers=left,frame=single]
     connwrappers [options] [selection]
@@ -397,6 +504,14 @@ the driving cell.
 The options -signed, -unsigned, and -port can be specified multiple times.
 \end{lstlisting}
 
+\section{coolrunner2\_sop -- break \$sop cells into ANDTERM/ORTERM cells}
+\label{cmd:coolrunner2_sop}
+\begin{lstlisting}[numbers=left,frame=single]
+    coolrunner2_sop [options] [selection]
+
+Break $sop cells into ANDTERM/ORTERM cells.
+\end{lstlisting}
+
 \section{copy -- copy modules in the design}
 \label{cmd:copy}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -519,6 +634,19 @@ evaluated in the other design.
     design -copy-to <name> [-as <new_mod_name>] [selection]
 
 Copy modules from the current design into the specified one.
+
+
+    design -import <name> [-as <new_top_name>] [selection]
+
+Import the specified design into the current design. The source design must
+either have a selected top module or the selection must contain exactly one
+module that is then used as top module for this command.
+
+
+    design -reset-vlog
+
+The Verilog front-end remembers defined macros and top-level declarations
+between calls to 'read_verilog'. This command resets this memory.
 \end{lstlisting}
 
 \section{dff2dffe -- transform \$dff cells to \$dffe cells}
@@ -546,8 +674,18 @@ $_DFF_P_, $_DFF_N_ and $_MUX_.
     -direct-match <pattern>
         like -direct for all DFF cell types matching the expression.
         this will use $__DFFE_* as <external_gate_type> matching the
-        internal gate type $_DFF_*_, except for $_DFF_[NP]_, which is
-        converted to $_DFFE_[NP]_.
+        internal gate type $_DFF_*_, and $__DFFSE_* for those matching
+        $_DFFS_*_, except for $_DFF_[NP]_, which is converted to 
+        $_DFFE_[NP]_.
+\end{lstlisting}
+
+\section{dff2dffs -- process sync set/reset with SR over CE priority}
+\label{cmd:dff2dffs}
+\begin{lstlisting}[numbers=left,frame=single]
+    dff2dffs [options] [selection]
+
+Merge synchronous set/reset $_MUX_ cells to create $__DFFS_[NP][NP][01], to be run before
+dff2dffe for SR over CE priority.
 \end{lstlisting}
 
 \section{dffinit -- set INIT param on FF cells}
@@ -561,6 +699,11 @@ drives. (This is primarily used in FPGA flows.)
     -ff <cell_name> <output_port> <init_param>
         operate on the specified cell type. this option can be used
         multiple times.
+
+    -highlow
+        use the string values "high" and "low" to represent a single-bit
+        initial value of 1 or 0. (multi-bit values are not supported in this
+        mode.)
 \end{lstlisting}
 
 \section{dfflibmap -- technology mapping of flip-flops}
@@ -767,6 +910,10 @@ This command tries to prove $equiv cells using a simple direct SAT approach.
     -undef
         enable modelling of undef states
 
+    -short
+        create shorter input cones that stop at shared nodes. This yields
+        simpler SAT problems but sometimes fails to prove equivalence.
+
     -nogroup
         disabling grouping of $equiv cells by output wire
 
@@ -852,6 +999,10 @@ outputs.
         when exposing a wire, create an input/output pair and cut the internal
         signal path at that wire.
 
+    -input
+        when exposing a wire, create an input port and disconnect the internal
+        driver.
+
     -shared
         only expose those signals that are shared among the selected modules.
         this is useful for preparing modules for equivalence checking.
@@ -956,6 +1107,64 @@ tries to map the modules to the design (ascending, default value is 0).
 See 'help techmap' for a pass that does the opposite thing.
 \end{lstlisting}
 
+\section{extract\_counter -- Extract GreenPak4 counter cells}
+\label{cmd:extract_counter}
+\begin{lstlisting}[numbers=left,frame=single]
+    extract_counter [options] [selection]
+
+This pass converts non-resettable or async resettable down counters to
+counter cells. Use a target-specific 'techmap' map file to convert those cells
+to the actual target cells.
+
+    -maxwidth N
+        Only extract counters up to N bits wide
+
+    -pout X,Y,...
+        Only allow parallel output from the counter to the listed cell types
+        (if not specified, parallel outputs are not restricted)
+\end{lstlisting}
+
+\section{extract\_fa -- find and extract full/half adders}
+\label{cmd:extract_fa}
+\begin{lstlisting}[numbers=left,frame=single]
+    extract_fa [options] [selection]
+
+This pass extracts full/half adders from a gate-level design.
+
+    -fa, -ha
+        Enable cell types (fa=full adder, ha=half adder)
+        All types are enabled if none of this options is used
+
+    -d <int>
+        Set maximum depth for extracted logic cones (default=20)
+
+    -b <int>
+        Set maximum breadth for extracted logic cones (default=6)
+
+    -v
+        Verbose output
+\end{lstlisting}
+
+\section{extract\_reduce -- converts gate chains into \$reduce\_* cells}
+\label{cmd:extract_reduce}
+\begin{lstlisting}[numbers=left,frame=single]
+    extract_reduce [options] [selection]
+
+converts gate chains into $reduce_* cells
+
+This command finds chains of $_AND_, $_OR_, and $_XOR_ cells and replaces them
+with their corresponding $reduce_* cells. Because this command only operates on
+these cell types, it is recommended to map the design to only these cell types
+using the `abc -g` command. Note that, in some cases, it may be more effective
+to map the design to only $_AND_ cells, run extract_reduce, map the remaining
+parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.
+
+    -allow-off-chain
+        Allows matching of cells that have loads outside the chain. These cells
+        will be replicated and folded into the $reduce_* cell, but the original
+        cell will remain, driving its original loads.
+\end{lstlisting}
+
 \section{flatten -- flatten design}
 \label{cmd:flatten}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -1155,21 +1364,12 @@ one-hot encoding and binary encoding is supported.
             .map <old_bitpattern> <new_bitpattern>
 \end{lstlisting}
 
-\section{greenpak4\_counters -- Extract GreenPak4 counter cells}
-\label{cmd:greenpak4_counters}
-\begin{lstlisting}[numbers=left,frame=single]
-    greenpak4_counters [options] [selection]
-
-This pass converts non-resettable or async resettable down counters to GreenPak4
-counter cells (All other GreenPak4 counter modes must be instantiated manually.)
-\end{lstlisting}
-
-\section{greenpak4\_dffinv -- merge greenpak4 inverters and DFFs}
+\section{greenpak4\_dffinv -- merge greenpak4 inverters and DFF/latches}
 \label{cmd:greenpak4_dffinv}
 \begin{lstlisting}[numbers=left,frame=single]
     greenpak4_dffinv [options] [selection]
 
-Merge GP_INV cells with GP_DFF* cells.
+Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.
 \end{lstlisting}
 
 \section{help -- display help messages}
@@ -1199,6 +1399,10 @@ needed.
         also check the design hierarchy. this generates an error when
         an unknown module is used as cell type.
 
+    -simcheck
+        like -check, but also thow an error if blackbox modules are
+        instantiated, and throw an error if the design has no top module
+
     -purge_lib
         by default the hierarchy command will not remove library (blackbox)
         modules. use this option to also remove unused blackbox modules.
@@ -1212,6 +1416,11 @@ needed.
         per default this pass also converts positional arguments in cells
         to arguments using port names. this option disables this behavior.
 
+    -keep_portwidths
+        per default this pass adjusts the port width on cells that are
+        module instances when the width does not match the module port. this
+        option disables this behavior.
+
     -nokeep_asserts
         per default this pass sets the "keep" attribute on all modules
         that directly or indirectly contain one or more $assert cells. this
@@ -1416,6 +1625,18 @@ When no active module is selected, this prints a list of modules.
 When an active module is selected, this prints a list of objects in the module.
 \end{lstlisting}
 
+\section{ltp -- print longest topological path}
+\label{cmd:ltp}
+\begin{lstlisting}[numbers=left,frame=single]
+    ltp [options] [selection]
+
+This command prints the longest topological path in the design. (Only considers
+paths within a single module, so the design must be flattened.)
+
+    -noff
+        automatically exclude FF cell types
+\end{lstlisting}
+
 \section{lut2mux -- convert \$lut to \$\_MUX\_}
 \label{cmd:lut2mux}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -1582,6 +1803,15 @@ This pass adds additional circuitry that emulates the Verilog simulation
 behavior for out-of-bounds memory reads and writes.
 \end{lstlisting}
 
+\section{memory\_nordff -- extract read port FFs from memories}
+\label{cmd:memory_nordff}
+\begin{lstlisting}[numbers=left,frame=single]
+    memory_nordff [options] [selection]
+
+This pass extracts FFs from memory read ports. This results in a netlist
+similar to what one would get from calling memory_dff with -nordff.
+\end{lstlisting}
+
 \section{memory\_share -- consolidate memory ports}
 \label{cmd:memory_share}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -1745,6 +1975,15 @@ This pass only operates on completely selected modules without processes.
         also remove internal nets if they have a public name
 \end{lstlisting}
 
+\section{opt\_demorgan -- Optimize reductions with DeMorgan equivalents}
+\label{cmd:opt_demorgan}
+\begin{lstlisting}[numbers=left,frame=single]
+    opt_demorgan [selection]
+
+This pass pushes inverters through $reduce_* cells if this will reduce the
+overall gate count of the circuit
+\end{lstlisting}
+
 \section{opt\_expr -- perform const folding and simple expression rewriting}
 \label{cmd:opt_expr}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -1884,15 +2123,16 @@ on partly selected designs.
 
     -memx
         simulate verilog simulation behavior for out-of-bounds memory accesses
-        using the 'memory_memx' pass. This option implies -nordff.
+        using the 'memory_memx' pass.
 
     -nomem
         do not run any of the memory_* passes
 
-    -nordff
-        passed to 'memory_dff'. prohibits merging of FFs into memory read ports
+    -rdff
+        do not pass -nordff to 'memory_dff'. This enables merging of FFs into
+        memory read ports.
 
-     -nokeepdc
+    -nokeepdc
         do not call opt_* with -keepdc
 
     -run <from_label>[:<to_label>]
@@ -2058,6 +2298,38 @@ Note: This implementation of a quadratic wirelength placer uses exact
 dense matrix operations. It is only a toy-placer for small circuits.
 \end{lstlisting}
 
+\section{read -- load HDL designs}
+\label{cmd:read}
+\begin{lstlisting}[numbers=left,frame=single]
+    read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..
+
+Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support
+is only available via Verific.)
+
+Additional -D<macro>[=<value>] options may be added after the option indicating
+the language version (and before file names) to set additional verilog defines.
+
+
+    read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
+
+Load the specified VHDL files. (Requires Verific.)
+
+
+    read -define <macro>[=<value>]..
+
+Set global Verilog/SystemVerilog defines.
+
+
+    read -undef <macro>..
+
+Unset global Verilog/SystemVerilog defines.
+
+
+    read -incdir <directory>
+
+Add directory to global Verilog/SystemVerilog include directories.
+\end{lstlisting}
+
 \section{read\_blif -- read BLIF file}
 \label{cmd:read_blif}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -2067,6 +2339,10 @@ Load modules from a BLIF file into the current design.
 
     -sop
         Create $sop cells instead of $lut cells
+
+    -wideports
+        Merge ports that match the pattern 'name[int]' into a single
+        multi-bit port 'name'.
 \end{lstlisting}
 
 \section{read\_ilang -- read modules from ilang file}
@@ -2078,6 +2354,15 @@ Load modules from an ilang file to the current design. (ilang is a text
 representation of a design in yosys's internal format.)
 \end{lstlisting}
 
+\section{read\_json -- read JSON file}
+\label{cmd:read_json}
+\begin{lstlisting}[numbers=left,frame=single]
+    read_json [filename]
+
+Load modules from a JSON file into the current design See "help write_json"
+for a description of the file format.
+\end{lstlisting}
+
 \section{read\_liberty -- read cells from liberty file}
 \label{cmd:read_liberty}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -2088,9 +2373,13 @@ Read cells from liberty file as modules into current design.
     -lib
         only create empty blackbox modules
 
-    -ignore_redef
+    -nooverwrite
         ignore re-definitions of modules. (the default behavior is to
-        create an error message.)
+        create an error message if the existing module is not a blackbox
+        module, and overwrite the existing module if it is  a blackbox module.)
+
+    -overwrite
+        overwrite existing modules with the same name
 
     -ignore_miss_func
         ignore cells with missing function specification of outputs
@@ -2099,6 +2388,9 @@ Read cells from liberty file as modules into current design.
         ignore cells with a missing or invalid direction
         specification on a pin
 
+    -ignore_miss_data_latch
+        ignore latches with missing data and/or enable pins
+
     -setattr <attribute_name>
         set the specified attribute (to the value 1) on all loaded modules
 \end{lstlisting}
@@ -2131,6 +2423,9 @@ Verilog-2005 is supported.
     -dump_ast2
         dump abstract syntax tree (after simplification)
 
+    -no_dump_ptr
+        do not include hex memory addresses in dump (easier to diff dumps)
+
     -dump_vlog
         dump ast as Verilog code (after simplification)
 
@@ -2190,9 +2485,13 @@ Verilog-2005 is supported.
     -icells
         interpret cell types starting with '$' as internal cell types
 
-    -ignore_redef
+    -nooverwrite
         ignore re-definitions of modules. (the default behavior is to
-        create an error message.)
+        create an error message if the existing module is not a black box
+        module, and overwrite the existing module otherwise.)
+
+    -overwrite
+        overwrite existing modules with the same name
 
     -defer
         only read the abstract syntax tree and defer actual compilation
@@ -2221,6 +2520,10 @@ verilog input, but has not very good error reporting. It generally is
 recommended to use a simulator (for example Icarus Verilog) for checking
 the syntax of the code, rather than to rely on read_verilog for that.
 
+Depending on if read_verilog is run in -formal mode, either the macro
+SYNTHESIS or FORMAL is defined automatically. In addition, read_verilog
+always defines the macro YOSYS.
+
 See the Yosys README file for a list of non-standard Verilog features
 supported by the Yosys Verilog front-end.
 \end{lstlisting}
@@ -2251,6 +2554,15 @@ with public names. This ignores all selected ports.
 Rename top module.
 \end{lstlisting}
 
+\section{rmports -- remove module ports with no connections}
+\label{cmd:rmports}
+\begin{lstlisting}[numbers=left,frame=single]
+    rmports [selection]
+
+This pass identifies ports in the selected modules which are not used or
+driven and removes them.
+\end{lstlisting}
+
 \section{sat -- solve a SAT problem in the circuit}
 \label{cmd:sat}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -2457,11 +2769,9 @@ design.
         are assumed to be bidirectional 'inout' ports.
 
     -set_attr <name> <value>
-    -set_cell_attr <name> <value>
-    -set_wire_attr <name> <value>
-        set the specified attribute on all cells and/or wires that are part of
-        a logic loop. the special token {} in the value is replaced with a
-        unique identifier for the logic loop.
+        set the specified attribute on all cells that are part of a logic
+        loop. the special token {} in the value is replaced with a unique
+        identifier for the logic loop.
 
     -select
         replace the current selection with a selection of all cells and wires
@@ -2497,7 +2807,7 @@ of the design to operate on. This command can be used to modify and view this
 list of selected objects.
 
 Note that many commands support an optional [selection] argument that can be
-used to override the global selection for the command. The syntax of this
+used to YS_OVERRIDE the global selection for the command. The syntax of this
 optional argument is identical to the syntax of the <selection> argument
 described here.
 
@@ -2728,17 +3038,29 @@ The -type option can be used to change the cell type of the selected cells.
 \begin{lstlisting}[numbers=left,frame=single]
     setundef [options] [selection]
 
-This command replaced undef (x) constants with defined (0/1) constants.
+This command replaces undef (x) constants with defined (0/1) constants.
 
     -undriven
         also set undriven nets to constant values
 
+    -expose
+        also expose undriven nets as inputs (use with -undriven)
+
     -zero
         replace with bits cleared (0)
 
     -one
         replace with bits set (1)
 
+    -undef
+        replace with undef (x) bits, may be used with -undriven
+
+    -anyseq
+        replace with $anyseq drivers (for formal)
+
+    -anyconst
+        replace with $anyconst drivers (for formal)
+
     -random <seed>
         replace with random bits using the specified integer als seed
         value for the random number generator.
@@ -2821,6 +3143,7 @@ to a graphics file (usually SVG or PostScript).
 
     -viewer <viewer>
         Run the specified command with the graphics file as parameter.
+        On Windows, this pauses yosys until the viewer exits.
 
     -format <format>
         Generate a graphics file in the specified format. Use 'dot' to just
@@ -2882,7 +3205,7 @@ to a graphics file (usually SVG or PostScript).
         do not add the module name as graph title to the dot file
 
 When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
-specified, 'xdot' is used to display the schematic.
+specified, 'xdot' is used to display the schematic (POSIX systems only).
 
 The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
 unless another prefix is specified using -prefix <prefix>.
@@ -2949,6 +3272,47 @@ will use the same interface as the original $_DFF_*_ cells. The cell parameter
         map to greenpak4 shift registers.
 \end{lstlisting}
 
+\section{sim -- simulate the circuit}
+\label{cmd:sim}
+\begin{lstlisting}[numbers=left,frame=single]
+    sim [options] [top-level]
+
+This command simulates the circuit using the given top-level module.
+
+    -vcd <filename>
+        write the simulation results to the given VCD file
+
+    -clock <portname>
+        name of top-level clock input
+
+    -clockn <portname>
+        name of top-level clock input (inverse polarity)
+
+    -reset <portname>
+        name of top-level reset input (active high)
+
+    -resetn <portname>
+        name of top-level inverted reset input (active low)
+
+    -rstlen <integer>
+        number of cycles reset should stay active (default: 1)
+
+    -zinit
+        zero-initialize all uninitialized regs and memories
+
+    -n <integer>
+        number of cycles to simulate (default: 20)
+
+    -a
+        include all nets in VCD output, not just those with public names
+
+    -w
+        writeback mode: use final simulation state as new init state
+
+    -d
+        enable debug output
+\end{lstlisting}
+
 \section{simplemap -- mapping simple coarse-grain cells}
 \label{cmd:simplemap}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -2963,22 +3327,6 @@ primitives. The following internal cell types are mapped by this pass:
   $sr, $ff, $dff, $dffsr, $adff, $dlatch
 \end{lstlisting}
 
-\section{singleton -- create singleton modules}
-\label{cmd:singleton}
-\begin{lstlisting}[numbers=left,frame=single]
-    singleton [selection]
-
-By default, a module that is instantiated by several other modules is only
-kept once in the design. This preserves the original modularity of the design
-and reduces the overall size of the design in memory. But it prevents certain
-optimizations and other operations on the design. This pass creates singleton
-modules for all selected cells. The created modules are marked with the
-'singleton' attribute.
-
-This commands only operates on modules that by themself have the 'singleton'
-attribute set (the 'top' module is a singleton implicitly).
-\end{lstlisting}
-
 \section{splice -- create explicit splicing cells}
 \label{cmd:splice}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -3122,6 +3470,9 @@ on partly selected designs.
     -nordff
         passed to 'memory'. prohibits merging of FFs into memory read ports
 
+    -noshare
+        do not run SAT-based resource sharing
+
     -run <from_label>[:<to_label>]
         only run the commands between the labels (see below). an empty
         from label is synonymous to 'begin', and empty to label is
@@ -3164,6 +3515,344 @@ The following commands are executed by this synthesis command:
         check
 \end{lstlisting}
 
+\section{synth\_achronix -- synthesis for Acrhonix Speedster22i FPGAs.}
+\label{cmd:synth_achronix}
+\begin{lstlisting}[numbers=left,frame=single]
+    synth_achronix [options]
+
+This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.
+
+    -top <module>
+        use the specified module as top module (default='top')
+
+    -vout <file>
+        write the design to the specified Verilog netlist file. writing of an
+        output file is omitted if this parameter is not specified.
+
+    -run <from_label>:<to_label>
+        only run the commands between the labels (see below). an empty
+        from label is synonymous to 'begin', and empty to label is
+        synonymous to the end of the command list.
+
+    -noflatten
+        do not flatten design before synthesis
+
+    -retime
+        run 'abc' with -dff option
+
+
+The following commands are executed by this synthesis command:
+
+    begin:
+        read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v
+        hierarchy -check -top <top>
+
+    flatten:    (unless -noflatten)
+        proc
+        flatten
+        tribuf -logic
+        deminout
+
+    coarse:
+        synth -run coarse
+
+    fine:
+        opt -fast -mux_undef -undriven -fine -full
+        memory_map
+        opt -undriven -fine
+        dffsr2dff
+        dff2dffe -direct-match $_DFF_*
+        opt -fine
+        techmap -map +/techmap.v
+        opt -full
+        clean -purge
+        setundef -undriven -zero
+        abc -markgroups -dff    (only if -retime)
+
+    map_luts:
+        abc -lut 4
+        clean
+
+    map_cells:
+        iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I
+        techmap -map +/achronix/speedster22i/cells_map.v
+        clean -purge
+
+    check:
+        hierarchy -check
+        stat
+        check -noinit
+
+    vout:
+        write_verilog -nodec -attr2comment -defparam -renameprefix syn_ <file-name>
+\end{lstlisting}
+
+\section{synth\_coolrunner2 -- synthesis for Xilinx Coolrunner-II CPLDs}
+\label{cmd:synth_coolrunner2}
+\begin{lstlisting}[numbers=left,frame=single]
+    synth_coolrunner2 [options]
+
+This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.
+It is intended to be used with https://github.com/azonenberg/openfpga as the
+place-and-route.
+
+    -top <module>
+        use the specified module as top module (default='top')
+
+    -json <file>
+        write the design to the specified JSON file. writing of an output file
+        is omitted if this parameter is not specified.
+
+    -run <from_label>:<to_label>
+        only run the commands between the labels (see below). an empty
+        from label is synonymous to 'begin', and empty to label is
+        synonymous to the end of the command list.
+
+    -noflatten
+        do not flatten design before synthesis
+
+    -retime
+        run 'abc' with -dff option
+
+
+The following commands are executed by this synthesis command:
+
+    begin:
+        read_verilog -lib +/coolrunner2/cells_sim.v
+        hierarchy -check -top <top>
+
+    flatten:    (unless -noflatten)
+        proc
+        flatten
+        tribuf -logic
+
+    coarse:
+        synth -run coarse
+
+    fine:
+        opt -fast -full
+        techmap
+        techmap -map +/coolrunner2/cells_latch.v
+        dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib
+
+    map_tff:
+        abc -g AND,XOR
+        clean
+        extract -map +/coolrunner2/tff_extract.v
+
+    map_pla:
+        abc -sop -I 40 -P 56
+        clean
+
+    map_cells:
+        dfflibmap -liberty +/coolrunner2/xc2_dff.lib
+        dffinit -ff FDCP Q INIT
+        dffinit -ff FDCP_N Q INIT
+        dffinit -ff FTCP Q INIT
+        dffinit -ff FTCP_N Q INIT
+        dffinit -ff LDCP Q INIT
+        dffinit -ff LDCP_N Q INIT
+        coolrunner2_sop
+        iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO
+        attrmvcp -attr src -attr LOC t:IOBUFE n:*
+        attrmvcp -attr src -attr LOC -driven t:IBUF n:*
+        splitnets
+        clean
+
+    check:
+        hierarchy -check
+        stat
+        check -noinit
+
+    json:
+        write_json <file-name>
+\end{lstlisting}
+
+\section{synth\_easic -- synthesis for eASIC platform}
+\label{cmd:synth_easic}
+\begin{lstlisting}[numbers=left,frame=single]
+    synth_easic [options]
+
+This command runs synthesis for eASIC platform.
+
+    -top <module>
+        use the specified module as top module
+
+    -vlog <file>
+        write the design to the specified structural Verilog file. writing of
+        an output file is omitted if this parameter is not specified.
+
+    -etools <path>
+        set path to the eTools installation. (default=/opt/eTools)
+
+    -run <from_label>:<to_label>
+        only run the commands between the labels (see below). an empty
+        from label is synonymous to 'begin', and empty to label is
+        synonymous to the end of the command list.
+
+    -noflatten
+        do not flatten design before synthesis
+
+    -retime
+        run 'abc' with -dff option
+
+
+The following commands are executed by this synthesis command:
+
+    begin:
+        read_liberty -lib <etools_phys_clk_lib>
+        read_liberty -lib <etools_logic_lut_lib>
+        hierarchy -check -top <top>
+
+    flatten:    (unless -noflatten)
+        proc
+        flatten
+
+    coarse:
+        synth -run coarse
+
+    fine:
+        opt -fast -mux_undef -undriven -fine
+        memory_map
+        opt -undriven -fine
+        techmap
+        opt -fast
+        abc -dff     (only if -retime)
+        opt_clean    (only if -retime)
+
+    map:
+        dfflibmap -liberty <etools_phys_clk_lib>
+        abc -liberty <etools_logic_lut_lib>
+        opt_clean
+
+    check:
+        hierarchy -check
+        stat
+        check -noinit
+
+    vlog:
+        write_verilog -noexpr -attr2comment <file-name>
+\end{lstlisting}
+
+\section{synth\_ecp5 -- synthesis for ECP5 FPGAs}
+\label{cmd:synth_ecp5}
+\begin{lstlisting}[numbers=left,frame=single]
+    synth_ecp5 [options]
+
+This command runs synthesis for ECP5 FPGAs.
+
+    -top <module>
+        use the specified module as top module
+
+    -blif <file>
+        write the design to the specified BLIF file. writing of an output file
+        is omitted if this parameter is not specified.
+
+    -edif <file>
+        write the design to the specified EDIF file. writing of an output file
+        is omitted if this parameter is not specified.
+
+    -json <file>
+        write the design to the specified JSON file. writing of an output file
+        is omitted if this parameter is not specified.
+
+    -run <from_label>:<to_label>
+        only run the commands between the labels (see below). an empty
+        from label is synonymous to 'begin', and empty to label is
+        synonymous to the end of the command list.
+
+    -noflatten
+        do not flatten design before synthesis
+
+    -retime
+        run 'abc' with -dff option
+
+    -noccu2
+        do not use CCU2 cells in output netlist
+
+    -nodffe
+        do not use flipflops with CE in output netlist
+
+    -nobram
+        do not use BRAM cells in output netlist
+
+    -nodram
+        do not use distributed RAM cells in output netlist
+
+    -nomux
+        do not use PFU muxes to implement LUTs larger than LUT4s
+
+    -abc2
+        run two passes of 'abc' for slightly improved logic density
+
+    -vpr
+        generate an output netlist (and BLIF file) suitable for VPR
+        (this feature is experimental and incomplete)
+
+
+The following commands are executed by this synthesis command:
+
+    begin:
+        read_verilog -lib +/ecp5/cells_sim.v
+        hierarchy -check -top <top>
+
+    flatten:    (unless -noflatten)
+        proc
+        flatten
+        tribuf -logic
+        deminout
+
+    coarse:
+        synth -run coarse
+
+    bram:    (skip if -nobram)
+
+    dram:    (skip if -nodram)
+        memory_bram -rules +/ecp5/dram.txt
+        techmap -map +/ecp5/drams_map.v
+
+    fine:
+        opt -fast -mux_undef -undriven -fine
+        memory_map
+        opt -undriven -fine
+        techmap -map +/techmap.v -map +/ecp5/arith_map.v
+        abc -dff    (only if -retime)
+
+    map_ffs:
+        dffsr2dff
+        dff2dffs
+        opt_clean
+        dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*
+        techmap -D NO_LUT -map +/ecp5/cells_map.v
+        opt_expr -mux_undef
+        simplemap
+
+    map_luts:
+        abc          (only if -abc2)
+        abc -lut 4:7
+        clean
+
+    map_cells:
+        techmap -map +/ecp5/cells_map.v    (with -D NO_LUT in vpr mode)
+        clean
+
+    check:
+        hierarchy -check
+        stat
+        check -noinit
+
+    blif:
+        opt_clean -purge                                     (vpr mode)
+        write_blif -attr -cname -conn -param <file-name>     (vpr mode)
+        write_blif -gates -attr -param <file-name>           (non-vpr mode)
+
+    edif:
+        write_edif <file-name>
+
+    json:
+        write_json <file-name>
+\end{lstlisting}
+
 \section{synth\_gowin -- synthesis for Gowin FPGAs}
 \label{cmd:synth_gowin}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -3228,7 +3917,7 @@ The following commands are executed by this synthesis command:
         check -noinit
 
     vout:
-        write_verilog -attr2comment -defparam -renameprefix gen <file-name>
+        write_verilog -nodec -attr2comment -defparam -renameprefix gen <file-name>
 \end{lstlisting}
 
 \section{synth\_greenpak4 -- synthesis for GreenPAK4 FPGAs}
@@ -3237,6 +3926,8 @@ The following commands are executed by this synthesis command:
     synth_greenpak4 [options]
 
 This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
+It is intended to be used with https://github.com/azonenberg/openfpga as the
+place-and-route.
 
     -top <module>
         use the specified module as top module (default='top')
@@ -3276,12 +3967,13 @@ The following commands are executed by this synthesis command:
         synth -run coarse
 
     fine:
-        greenpak4_counters
+        extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14
         clean
         opt -fast -mux_undef -undriven -fine
         memory_map
         opt -undriven -fine
         techmap
+        techmap -map +/greenpak4/cells_latch.v
         dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
         opt -fast
         abc -dff    (only if -retime)
@@ -3323,14 +4015,18 @@ The following commands are executed by this synthesis command:
 This command runs synthesis for iCE40 FPGAs.
 
     -top <module>
-        use the specified module as top module (default='top')
+        use the specified module as top module
 
     -blif <file>
         write the design to the specified BLIF file. writing of an output file
         is omitted if this parameter is not specified.
 
     -edif <file>
-        write the design to the specified edif file. writing of an output file
+        write the design to the specified EDIF file. writing of an output file
+        is omitted if this parameter is not specified.
+
+    -json <file>
+        write the design to the specified JSON file. writing of an output file
         is omitted if this parameter is not specified.
 
     -run <from_label>:<to_label>
@@ -3347,12 +4043,19 @@ This command runs synthesis for iCE40 FPGAs.
     -nocarry
         do not use SB_CARRY cells in output netlist
 
+    -nodffe
+        do not use SB_DFFE* cells in output netlist
+
     -nobram
         do not use SB_RAM40_4K* cells in output netlist
 
     -abc2
         run two passes of 'abc' for slightly improved logic density
 
+    -vpr
+        generate an output netlist (and BLIF file) suitable for VPR
+        (this feature is experimental and incomplete)
+
 
 The following commands are executed by this synthesis command:
 
@@ -3384,7 +4087,7 @@ The following commands are executed by this synthesis command:
     map_ffs:
         dffsr2dff
         dff2dffe -direct-match $_DFF_*
-        techmap -map +/ice40/cells_map.v
+        techmap -D NO_LUT -map +/ice40/cells_map.v
         opt_expr -mux_undef
         simplemap
         ice40_ffinit
@@ -3399,7 +4102,7 @@ The following commands are executed by this synthesis command:
         clean
 
     map_cells:
-        techmap -map +/ice40/cells_map.v
+        techmap -map +/ice40/cells_map.v    (with -D NO_LUT in vpr mode)
         clean
 
     check:
@@ -3408,10 +4111,116 @@ The following commands are executed by this synthesis command:
         check -noinit
 
     blif:
-        write_blif -gates -attr -param <file-name>
+        opt_clean -purge                                     (vpr mode)
+        write_blif -attr -cname -conn -param <file-name>     (vpr mode)
+        write_blif -gates -attr -param <file-name>           (non-vpr mode)
 
     edif:
         write_edif <file-name>
+
+    json:
+        write_json <file-name>
+\end{lstlisting}
+
+\section{synth\_intel -- synthesis for Intel (Altera) FPGAs.}
+\label{cmd:synth_intel}
+\begin{lstlisting}[numbers=left,frame=single]
+    synth_intel [options]
+
+This command runs synthesis for Intel FPGAs.
+
+    -family < max10 | a10gx | cyclone10 | cyclonev | cycloneiv | cycloneive>
+        generate the synthesis netlist for the specified family.
+        MAX10 is the default target if not family argument specified.
+        For Cyclone GX devices, use cycloneiv argument; For Cyclone E, use cycloneive.
+        Cyclone V and Arria 10 GX devices are experimental, use it with a10gx argument.
+
+    -top <module>
+        use the specified module as top module (default='top')
+
+    -vqm <file>
+        write the design to the specified Verilog Quartus Mapping File. Writing of an
+        output file is omitted if this parameter is not specified.
+
+    -vpr <file>
+        write BLIF files for VPR flow experiments. The synthesized BLIF output file is not
+        compatible with the Quartus flow. Writing of an
+        output file is omitted if this parameter is not specified.
+
+    -run <from_label>:<to_label>
+        only run the commands between the labels (see below). an empty
+        from label is synonymous to 'begin', and empty to label is
+        synonymous to the end of the command list.
+
+    -noiopads
+        do not use altsyncram cells in output netlist
+
+    -nobram
+        do not use altsyncram cells in output netlist
+
+    -noflatten
+        do not flatten design before synthesis
+
+    -retime
+        run 'abc' with -dff option
+
+The following commands are executed by this synthesis command:
+
+    begin:
+
+    family:
+        read_verilog -sv -lib +/intel/max10/cells_sim.v
+        read_verilog -sv -lib +/intel/common/m9k_bb.v
+        read_verilog -sv -lib +/intel/common/altpll_bb.v
+        hierarchy -check -top <top>
+
+    flatten:    (unless -noflatten)
+        proc
+        flatten
+        tribuf -logic
+        deminout
+
+    coarse:
+        synth -run coarse
+
+    bram:    (skip if -nobram)
+        memory_bram -rules +/intel/common/brams.txt
+        techmap -map +/intel/common/brams_map.v
+
+    fine:
+        opt -fast -mux_undef -undriven -fine -full
+        memory_map
+        opt -undriven -fine
+        dffsr2dff
+        dff2dffe -direct-match $_DFF_*
+        opt -fine
+        techmap -map +/techmap.v
+        opt -full
+        clean -purge
+        setundef -undriven -zero
+        abc -markgroups -dff    (only if -retime)
+
+    map_luts:
+        abc -lut 4
+        clean
+
+    map_cells:
+        iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I    (unless -noiopads)
+        techmap -map +/intel/max10/cells_map.v
+        dffinit -highlow -ff dffeas q power_up
+        clean -purge
+
+    check:
+        hierarchy -check
+        stat
+        check -noinit
+
+    vqm:
+        write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ <file-name>
+
+    vpr:
+        opt_clean -purge
+        write_blif <file-name>
 \end{lstlisting}
 
 \section{synth\_xilinx -- synthesis for Xilinx FPGAs}
@@ -3430,6 +4239,14 @@ compatible with 7-Series Xilinx devices.
         write the design to the specified edif file. writing of an output file
         is omitted if this parameter is not specified.
 
+    -blif <file>
+        write the design to the specified BLIF file. writing of an output file
+        is omitted if this parameter is not specified.
+
+    -vpr
+        generate an output netlist (and BLIF file) suitable for VPR
+        (this feature is experimental and incomplete)
+
     -run <from_label>:<to_label>
         only run the commands between the labels (see below). an empty
         from label is synonymous to 'begin', and empty to label is
@@ -3448,7 +4265,6 @@ The following commands are executed by this synthesis command:
         read_verilog -lib +/xilinx/cells_sim.v
         read_verilog -lib +/xilinx/cells_xtra.v
         read_verilog -lib +/xilinx/brams_bb.v
-        read_verilog -lib +/xilinx/drams_bb.v
         hierarchy -check -top <top>
 
     flatten:     (only if -flatten)
@@ -3480,7 +4296,7 @@ The following commands are executed by this synthesis command:
         clean
 
     map_cells:
-        techmap -map +/xilinx/cells_map.v
+        techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)
         dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
         clean
 
@@ -3491,6 +4307,9 @@ The following commands are executed by this synthesis command:
 
     edif:     (only if -edif)
         write_edif <file-name>
+
+    blif:     (only if -blif)
+        write_blif <file-name>
 \end{lstlisting}
 
 \section{tcl -- execute a TCL script file}
@@ -3502,9 +4321,9 @@ This command executes the tcl commands in the specified file.
 Use 'yosys cmd' to run the yosys command 'cmd' from tcl.
 
 The tcl command 'yosys -import' can be used to import all yosys
-commands directly as tcl commands to the tcl shell. The yosys
-command 'proc' is wrapped using the tcl command 'procs' in order
-to avoid a name collision with the tcl builtin command 'proc'.
+commands directly as tcl commands to the tcl shell. Yosys commands
+'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'
+in order to avoid a name collision with the built in commands.
 \end{lstlisting}
 
 \section{techmap -- generic technology mapper}
@@ -3548,7 +4367,7 @@ file.
     -D <define>, -I <incdir>
         this options are passed as-is to the Verilog frontend for loading the
         map file. Note that the Verilog frontend is also called with the
-        '-ignore_redef' option set.
+        '-nooverwrite' option set.
 
 When a module in the map file has the 'techmap_celltype' attribute set, it will
 match cells with a type that match the text value of this attribute. Otherwise
@@ -3629,7 +4448,7 @@ the design is connected to a constant value. The parameter is then set to the
 constant value.
 
 A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
-of the cell that is being replaced.
+and attributes of the cell that is being replaced.
 
 See 'help extract' for a pass that does the opposite thing.
 
@@ -3795,24 +4614,134 @@ This pass transforms $mux cells with 'z' inputs to tristate buffers.
         to non-tristate logic. this option implies -merge.
 \end{lstlisting}
 
+\section{uniquify -- create unique copies of modules}
+\label{cmd:uniquify}
+\begin{lstlisting}[numbers=left,frame=single]
+    uniquify [selection]
+
+By default, a module that is instantiated by several other modules is only
+kept once in the design. This preserves the original modularity of the design
+and reduces the overall size of the design in memory. But it prevents certain
+optimizations and other operations on the design. This pass creates unique
+modules for all selected cells. The created modules are marked with the
+'unique' attribute.
+
+This commands only operates on modules that by themself have the 'unique'
+attribute set (the 'top' module is unique implicitly).
+\end{lstlisting}
+
 \section{verific -- load Verilog and VHDL designs using Verific}
 \label{cmd:verific}
 \begin{lstlisting}[numbers=left,frame=single]
-    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv} <verilog-file>..
+    verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} <verilog-file>..
 
 Load the specified Verilog/SystemVerilog files into Verific.
 
+All files specified in one call to this command are one compilation unit.
+Files passed to different calls to this command are treated as belonging to
+different compilation units.
 
-    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008} <vhdl-file>..
+Additional -D<macro>[=<value>] options may be added after the option indicating
+the language version (and before file names) to set additional verilog defines.
+The macros SYNTHESIS and VERIFIC are defined implicitly.
+
+
+    verific -formal <verilog-file>..
+
+Like -sv, but define FORMAL instead of SYNTHESIS.
+
+
+    verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>..
 
 Load the specified VHDL files into Verific.
 
 
-    verific -import [-gates] {-all | <top-module>..}
+    verific -work <libname> {-sv|-vhdl|...} <hdl-file>
+
+Load the specified Verilog/SystemVerilog/VHDL file into the specified library.
+(default library when -work is not present: "work")
+
+
+    verific -vlog-incdir <directory>..
+
+Add Verilog include directories.
+
+
+    verific -vlog-libdir <directory>..
+
+Add Verilog library directories. Verific will search in this directories to
+find undefined modules.
+
+
+    verific -vlog-define <macro>[=<value>]..
+
+Add Verilog defines.
+
+
+    verific -vlog-undef <macro>..
+
+Remove Verilog defines previously set with -vlog-define.
+
+
+    verific -set-error <msg_id>..
+    verific -set-warning <msg_id>..
+    verific -set-info <msg_id>..
+    verific -set-ignore <msg_id>..
+
+Set message severity. <msg_id> is the string in square brackets when a message
+is printed, such as VERI-1209.
+
+
+    verific -import [options] <top-module>..
 
 Elaborate the design for the specified top modules, import to Yosys and
-reset the internal state of Verific. A gate-level netlist is created
-when called with -gates.
+reset the internal state of Verific.
+
+Import options:
+
+  -all
+    Elaborate all modules, not just the hierarchy below the given top
+    modules. With this option the list of modules to import is optional.
+
+  -gates
+    Create a gate-level netlist.
+
+  -flatten
+    Flatten the design in Verific before importing.
+
+  -extnets
+    Resolve references to external nets by adding module ports as needed.
+
+  -autocover
+    Generate automatic cover statements for all asserts
+
+  -v, -vv
+    Verbose log messages. (-vv is even more verbose than -v.)
+
+The following additional import options are useful for debugging the Verific
+bindings (for Yosys and/or Verific developers):
+
+  -k
+    Keep going after an unsupported verific primitive is found. The
+    unsupported primitive is added as blockbox module to the design.
+    This will also add all SVA related cells to the design parallel to
+    the checker logic inferred by it.
+
+  -V
+    Import Verific netlist as-is without translating to Yosys cell types. 
+
+  -nosva
+    Ignore SVA properties, do not infer checker logic.
+
+  -L <int>
+    Maximum number of ctrl bits for SVA checker FSMs (default=16).
+
+  -n
+    Keep all Verific names on instances and nets. By default only
+    user-declared names are preserved.
+
+  -d <dump_file>
+    Dump the Verific netlist as a verilog file.
 
 Visit http://verific.com/ for more information on Verific.
 \end{lstlisting}
@@ -3837,40 +4766,19 @@ Push or pop the list of default options to a stack. Note that -push does
 not imply -clear.
 \end{lstlisting}
 
-\section{vhdl2verilog -- importing VHDL designs using vhdl2verilog}
-\label{cmd:vhdl2verilog}
+\section{verilog\_defines -- define and undefine verilog defines}
+\label{cmd:verilog_defines}
 \begin{lstlisting}[numbers=left,frame=single]
-    vhdl2verilog [options] <vhdl-file>..
+    verilog_defines [options]
 
-This command reads VHDL source files using the 'vhdl2verilog' tool and the
-Yosys Verilog frontend.
+Define and undefine verilog preprocessor macros.
 
-    -out <out_file>
-        do not import the vhdl2verilog output. instead write it to the
-        specified file.
+    -Dname[=definition]
+        define the preprocessor symbol 'name' and set its optional value
+        'definition'
 
-    -vhdl2verilog_dir <directory>
-        do use the specified vhdl2verilog installation. this is the directory
-        that contains the setup_env.sh file. when this option is not present,
-        it is assumed that vhdl2verilog is in the PATH environment variable.
-
-    -top <top-entity-name>
-        The name of the top entity. This option is mandatory.
-
-The following options are passed as-is to vhdl2verilog:
-
-    -arch <architecture_name>
-    -unroll_generate
-    -nogenericeval
-    -nouniquify
-    -oldparser
-    -suppress <list>
-    -quiet
-    -nobanner
-    -mapfile <file>
-
-vhdl2verilog can be obtained from:
-http://www.edautils.com/vhdl2verilog.html
+    -Uname[=definition]
+        undefine the preprocessor symbol 'name'
 \end{lstlisting}
 
 \section{wreduce -- reduce the word size of operations if possible}
@@ -3892,6 +4800,38 @@ Options:
         flows that use the 'memory_memx' pass.
 \end{lstlisting}
 
+\section{write\_aiger -- write design to AIGER file}
+\label{cmd:write_aiger}
+\begin{lstlisting}[numbers=left,frame=single]
+    write_aiger [options] [filename]
+
+Write the current design to an AIGER file. The design must be flattened and
+must not contain any cell types except $_AND_, $_NOT_, simple FF types,
+$assert and $assume cells, and $initstate cells.
+
+$assert and $assume cells are converted to AIGER bad state properties and
+invariant constraints.
+
+    -ascii
+        write ASCII version of AGIER format
+
+    -zinit
+        convert FFs to zero-initialized FFs, adding additional inputs for
+        uninitialized FFs.
+
+    -miter
+        design outputs are AIGER bad state properties
+
+    -symbols
+        include a symbol table in the generated AIGER file
+
+    -map <filename>
+        write an extra file with port and latch symbols
+
+    -vmap <filename>
+        like -map, but more verbose
+\end{lstlisting}
+
 \section{write\_blif -- write design to BLIF file}
 \label{cmd:write_blif}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -3949,6 +4889,11 @@ file *.blif when any of this options is used.
     -cname
         use the non-standard .cname statement to write cell names
 
+    -iname, -iattr
+        enable -cname and -attr functionality for .names statements
+        (the .cname and .attr statements will be included in the BLIF
+        output after the truth table for the .names statement)
+
     -blackbox
         write blackbox cells with .blackbox statement.
 
@@ -3959,9 +4904,15 @@ file *.blif when any of this options is used.
 \section{write\_btor -- write design to BTOR file}
 \label{cmd:write_btor}
 \begin{lstlisting}[numbers=left,frame=single]
-    write_btor [filename]
+    write_btor [options] [filename]
 
-Write the current design to an BTOR file.
+Write a BTOR description of the current design.
+
+  -v
+    Add comments and indentation to BTOR output file
+
+  -s
+    Output only a single bad property for all asserts
 \end{lstlisting}
 
 \section{write\_edif -- write design to EDIF netlist file}
@@ -3979,6 +4930,10 @@ Write the current design to an EDIF netlist file.
         if the design contains constant nets. use "hilomap" to map to custom
         constant drivers first)
 
+    -pvector {par|bra|ang}
+        sets the delimiting character for module port rename clauses to
+        parentheses, square brackets, or angle brackets.
+
 Unfortunately there are different "flavors" of the EDIF file format. This
 command generates EDIF files for the Xilinx place&route tools. It might be
 necessary to make small modifications to this command when a different tool
@@ -4003,6 +4958,14 @@ Inside a script the input file can also can a here-document:
     EOT
 \end{lstlisting}
 
+\section{write\_firrtl -- write design to a FIRRTL file}
+\label{cmd:write_firrtl}
+\begin{lstlisting}[numbers=left,frame=single]
+    write_firrtl [options] [filename]
+
+Write a FIRRTL netlist of the current design.
+\end{lstlisting}
+
 \section{write\_ilang -- write design to ilang file}
 \label{cmd:write_ilang}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -4123,6 +5086,10 @@ values referenced above are vectors of this integers. Signal bits that are
 connected to a constant driver are denoted as string "0" or "1" instead of
 a number.
 
+Numeric parameter and attribute values up to 32 bits are written as decimal
+values. Numbers larger than that are written as string holding the binary
+representation of the value.
+
 For example the following Verilog code:
 
     module test(input x, y);
@@ -4242,43 +5209,109 @@ Future version of Yosys might add support for additional fields in the JSON
 format. A program processing this format must ignore all unknown fields.
 \end{lstlisting}
 
+\section{write\_simplec -- convert design to simple C code}
+\label{cmd:write_simplec}
+\begin{lstlisting}[numbers=left,frame=single]
+    write_simplec [options] [filename]
+
+Write simple C code for simulating the design. The C code writen can be used to
+simulate the design in a C environment, but the purpose of this command is to
+generate code that works well with C-based formal verification.
+
+    -verbose
+        this will print the recursive walk used to export the modules.
+
+    -i8, -i16, -i32, -i64
+        set the maximum integer bit width to use in the generated code.
+
+THIS COMMAND IS UNDER CONSTRUCTION
+\end{lstlisting}
+
 \section{write\_smt2 -- write design to SMT-LIBv2 file}
 \label{cmd:write_smt2}
 \begin{lstlisting}[numbers=left,frame=single]
     write_smt2 [options] [filename]
 
 Write a SMT-LIBv2 [1] description of the current design. For a module with name
-'<mod>' this will declare the sort '<mod>_s' (state of the module) and the
-functions operating on that state.
+'<mod>' this will declare the sort '<mod>_s' (state of the module) and will
+define and declare functions operating on that state.
 
-The '<mod>_s' sort represents a module state. Additional '<mod>_n' functions
-are provided that can be used to access the values of the signals in the module.
-By default only ports, registers, and wires with the 'keep' attribute set are
-made available via such functions. With the -nobv option, multi-bit wires are
-exported as separate functions of type Bool for the individual bits. Without
--nobv multi-bit wires are exported as single functions of type BitVec.
+The following SMT2 functions are generated for a module with name '<mod>'.
+Some declarations/definitions are printed with a special comment. A prover
+using the SMT2 files can use those comments to collect all relevant metadata
+about the design.
 
-The '<mod>_t' function evaluates to 'true' when the given pair of states
-describes a valid state transition.
+    ; yosys-smt2-module <mod>
+    (declare-sort |<mod>_s| 0)
+        The sort representing a state of module <mod>.
 
-The '<mod>_a' function evaluates to 'true' when the given state satisfies
-the asserts in the module.
+    (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))
+        This function must be asserted for each state to establish the
+        design hierarchy.
 
-The '<mod>_u' function evaluates to 'true' when the given state satisfies
-the assumptions in the module.
+    ; yosys-smt2-input <wirename> <width>
+    ; yosys-smt2-output <wirename> <width>
+    ; yosys-smt2-register <wirename> <width>
+    ; yosys-smt2-wire <wirename> <width>
+    (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))
+    (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)
+        For each port, register, and wire with the 'keep' attribute set an
+        accessor function is generated. Single-bit wires are returned as Bool,
+        multi-bit wires as BitVec.
 
-The '<mod>_i' function evaluates to 'true' when the given state conforms
-to the initial state. Furthermore the '<mod>_is' function should be asserted
-to be true for initial states in addition to '<mod>_i', and should be
-asserted to be false for non-initial states.
+    ; yosys-smt2-cell <submod> <instancename>
+    (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)
+        There is a function like that for each hierarchical instance. It
+        returns the sort that represents the state of the sub-module that
+        implements the instance.
 
-For hierarchical designs, the '<mod>_h' function must be asserted for each
-state to establish the design hierarchy. The '<mod>_h <cellname>' function
-evaluates to the state corresponding to the given cell within <mod>.
+    (declare-fun |<mod>_is| (|<mod>_s|) Bool)
+        This function must be asserted 'true' for initial states, and 'false'
+        otherwise.
+
+    (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))
+        This function must be asserted 'true' for initial states. For
+        non-initial states it must be left unconstrained.
+
+    (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))
+        This function evaluates to 'true' if the states 'state' and
+        'next_state' form a valid state transition.
+
+    (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))
+        This function evaluates to 'true' if all assertions hold in the state.
+
+    (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))
+        This function evaluates to 'true' if all assumptions hold in the state.
+
+    ; yosys-smt2-assert <id> <filename:linenum>
+    (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))
+        Each $assert cell is converted into one of this functions. The function
+        evaluates to 'true' if the assert statement holds in the state.
+
+    ; yosys-smt2-assume <id> <filename:linenum>
+    (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))
+        Each $assume cell is converted into one of this functions. The function
+        evaluates to 'true' if the assume statement holds in the state.
+
+    ; yosys-smt2-cover <id> <filename:linenum>
+    (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))
+        Each $cover cell is converted into one of this functions. The function
+        evaluates to 'true' if the cover statement is activated in the state.
+
+Options:
 
     -verbose
         this will print the recursive walk used to export the modules.
 
+    -stbv
+        Use a BitVec sort to represent a state instead of an uninterpreted
+        sort. As a side-effect this will prevent use of arrays to model
+        memories.
+
+    -stdt
+        Use SMT-LIB 2.6 style datatypes to represent a state instead of an
+        uninterpreted sort.
+
     -nobv
         disable support for BitVec (FixedSizeBitVectors theory). without this
         option multi-bit wires are represented using the BitVec sort and
@@ -4394,6 +5427,25 @@ Write the current design to an SPICE netlist file.
         set the specified module as design top module
 \end{lstlisting}
 
+\section{write\_table -- write design as connectivity table}
+\label{cmd:write_table}
+\begin{lstlisting}[numbers=left,frame=single]
+    write_table [options] [filename]
+
+Write the current design as connectivity table. The output is a tab-separated
+ASCII table with the following columns:
+
+  module name
+  cell name
+  cell type
+  cell port
+  direction
+  signal
+
+module inputs and outputs are output using cell type and port '-' and with
+'pi' (primary input) or 'po' (primary output) or 'pio' as direction.
+\end{lstlisting}
+
 \section{write\_verilog -- write design to Verilog file}
 \label{cmd:write_verilog}
 \begin{lstlisting}[numbers=left,frame=single]
@@ -4424,6 +5476,14 @@ Write the current design to a Verilog file.
         not bit pattern. This option deactivates this feature and instead
         will write out all constants in binary.
 
+    -decimal
+        dump 32-bit constants in decimal and without size and radix
+
+    -nohex
+        constant values that are compatible with hex output are usually
+        dumped as hex values. This option deactivates this feature and
+        instead will write out all constants in binary.
+
     -nostr
         Parameters and attributes that are specified as strings in the
         original input will be output as strings by this back-end. This

From 097da32e1a8cfe29d64666c1b2c9b47129b07c7e Mon Sep 17 00:00:00 2001
From: argama <argama@gmail.com>
Date: Tue, 16 Oct 2018 21:33:37 +0800
Subject: [PATCH 128/528] ignore protect endprotect

---
 frontends/verilog/verilog_lexer.l | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 83921bf0b..2c4880b84 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -135,6 +135,9 @@ YOSYS_NAMESPACE_END
 		frontend_verilog_yyerror("Unsupported default nettype: %s", p);
 }
 
+"`protect"[^\n]* /* ignore `protect*/
+"`endprotect"[^\n]* /* ignore `endprotect*/
+
 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
 	frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 }

From 5706e90802fdf51a476e769790f6b5b526c57572 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 16 Oct 2018 16:22:16 +0200
Subject: [PATCH 129/528] Yosys 0.8

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 365b92ea4..d759b1145 100644
--- a/Makefile
+++ b/Makefile
@@ -99,7 +99,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.7+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 61f6811.. | wc -l; })
+YOSYS_VER := 0.8
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

From 6e00c217ae4e1509e06e586533705c13baae8a52 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 16 Oct 2018 16:44:58 +0200
Subject: [PATCH 130/528] After release is before release

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 CHANGELOG | 8 ++++++++
 Makefile  | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/CHANGELOG b/CHANGELOG
index 5499c309a..a00c2adf8 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,6 +3,14 @@ List of major changes and improvements between releases
 =======================================================
 
 
+Yosys 0.8 .. Yosys 0.8-dev
+--------------------------
+
+ * Various
+    - Added $changed support to read_verilog
+    - Added "write_edif -attrprop"
+
+
 Yosys 0.7 .. Yosys 0.8
 ----------------------
 
diff --git a/Makefile b/Makefile
index d759b1145..ec0752535 100644
--- a/Makefile
+++ b/Makefile
@@ -99,7 +99,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.8
+YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. | wc -l; })
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

From debc0d3515b917a9ed71a202d08d6afd96bfea76 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 16 Oct 2018 16:51:58 +0200
Subject: [PATCH 131/528] We have 2018 now

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 COPYING   | 2 +-
 README.md | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/COPYING b/COPYING
index a01b7b697..a121cdfe9 100644
--- a/COPYING
+++ b/COPYING
@@ -1,4 +1,4 @@
-Copyright (C) 2012 - 2017  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above
diff --git a/README.md b/README.md
index 41ae4ac18..0fba1cb46 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 ```
 yosys -- Yosys Open SYnthesis Suite
 
-Copyright (C) 2012 - 2017  Clifford Wolf <clifford@clifford.at>
+Copyright (C) 2012 - 2018  Clifford Wolf <clifford@clifford.at>
 
 Permission to use, copy, modify, and/or distribute this software for any
 purpose with or without fee is hereby granted, provided that the above

From 6ca493b88ca101f357e9de4dfdad4f3c913512c8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 17 Oct 2018 12:23:36 +0200
Subject: [PATCH 132/528] Minor code cleanups in liberty front-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/liberty/liberty.cc | 21 +++++----------------
 1 file changed, 5 insertions(+), 16 deletions(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 0018d6dac..66db43baf 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -634,11 +634,12 @@ struct LibertyFrontend : public Frontend {
 				}
 			}
 
-			// some liberty files do not put ff/latch at the beginning of a cell
-			// try to find "ff" or "latch" and create FF/latch before processing all other nodes 
-			for (auto node : cell->children)
+			if (!flag_lib)
 			{
-				if (!flag_lib) {
+				// some liberty files do not put ff/latch at the beginning of a cell
+				// try to find "ff" or "latch" and create FF/latch _before_ processing all other nodes
+				for (auto node : cell->children)
+				{
 					if (node->id == "ff" && node->args.size() == 2)
 						create_ff(module, node);
 					if (node->id == "latch" && node->args.size() == 2)
@@ -651,18 +652,6 @@ struct LibertyFrontend : public Frontend {
 
 			for (auto node : cell->children)
 			{
-				/*
-				if (!flag_lib) {
-					if (node->id == "ff" && node->args.size() == 2)
-						create_ff(module, node);
-					if (node->id == "latch" && node->args.size() == 2)
-						if (!create_latch(module, node, flag_ignore_miss_data_latch)) {
-							delete module;
-							goto skip_cell;
-						}
-				}
-				*/
-
 				if (node->id == "pin" && node->args.size() == 1)
 				{
 					LibertyAst *dir = node->find("direction");

From 22d9535a2481ffa7e05b0669bb1dc97284abf9d7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 17 Oct 2018 12:23:50 +0200
Subject: [PATCH 133/528] Update ABC to git rev c5b48bb

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index ec0752535..95d9290cb 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = ae6716b
+ABCREV = c5b48bb
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1

From a25f370191707def4d50dd42e74dec4d097a6a22 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 18 Oct 2018 12:26:53 +0200
Subject: [PATCH 134/528] Update ABC to git rev 14d985a

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 95d9290cb..a5a4f15ba 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = c5b48bb
+ABCREV = 14d985a
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1

From d5aac2650f9169b2b890854083c5502b84adf115 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Thu, 18 Oct 2018 21:27:04 +0200
Subject: [PATCH 135/528] Basic test for checking correct synthesis of
 SystemVerilog interfaces

---
 Makefile                                      |   2 +
 tests/svinterfaces/run-test.sh                |   5 +
 tests/svinterfaces/runone.sh                  |  41 +++++++
 .../{simple => svinterfaces}/svinterface1.sv  |  45 ++++++--
 tests/svinterfaces/svinterface1_ref.v         | 107 ++++++++++++++++++
 tests/svinterfaces/svinterface1_tb.v          |  57 ++++++++++
 6 files changed, 248 insertions(+), 9 deletions(-)
 create mode 100755 tests/svinterfaces/run-test.sh
 create mode 100755 tests/svinterfaces/runone.sh
 rename tests/{simple => svinterfaces}/svinterface1.sv (50%)
 create mode 100644 tests/svinterfaces/svinterface1_ref.v
 create mode 100644 tests/svinterfaces/svinterface1_tb.v

diff --git a/Makefile b/Makefile
index a5a4f15ba..090c94648 100644
--- a/Makefile
+++ b/Makefile
@@ -573,6 +573,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/bram && bash run-test.sh $(SEEDOPT)
 	+cd tests/various && bash run-test.sh
 	+cd tests/sat && bash run-test.sh
+	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
@@ -655,6 +656,7 @@ clean:
 	rm -rf tests/sat/*.log tests/techmap/*.log tests/various/*.log
 	rm -rf tests/bram/temp tests/fsm/temp tests/realmath/temp tests/share/temp tests/smv/temp
 	rm -rf vloghtb/Makefile vloghtb/refdat vloghtb/rtl vloghtb/scripts vloghtb/spec vloghtb/check_yosys vloghtb/vloghammer_tb.tar.bz2 vloghtb/temp vloghtb/log_test_*
+	rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff
 	rm -f  tests/tools/cmp_tbdata
 
 clean-abc:
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
new file mode 100755
index 000000000..1630859bd
--- /dev/null
+++ b/tests/svinterfaces/run-test.sh
@@ -0,0 +1,5 @@
+#/bin/bash -e
+
+
+
+./runone.sh  svinterface1
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
new file mode 100755
index 000000000..345801389
--- /dev/null
+++ b/tests/svinterfaces/runone.sh
@@ -0,0 +1,41 @@
+#!/bin/bash
+
+
+TESTNAME=$1
+
+STDOUTFILE=${TESTNAME}.log_stdout
+STDERRFILE=${TESTNAME}.log_stderr
+
+echo "" > $STDOUTFILE
+echo "" > $STDERRFILE
+
+echo -n "Test: ${TESTNAME} -> "
+
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
+
+rm -f a.out reference_result.txt dut_result.txt
+
+set -e
+
+iverilog -g2012 ${TESTNAME}_syn.v
+iverilog -g2012 ${TESTNAME}_ref_syn.v
+
+set +e
+
+iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
+./a.out
+mv output.txt reference_result.txt
+iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+./a.out
+mv output.txt dut_result.txt
+
+diff reference_result.txt dut_result.txt > ${TESTNAME}.diff
+RET=$?
+if [ "$RET" != "0" ] ; then
+    echo "ERROR!"
+    exit -1
+fi
+
+echo "ok"
+exit 0
diff --git a/tests/simple/svinterface1.sv b/tests/svinterfaces/svinterface1.sv
similarity index 50%
rename from tests/simple/svinterface1.sv
rename to tests/svinterfaces/svinterface1.sv
index 64383a06c..6d60b4880 100644
--- a/tests/simple/svinterface1.sv
+++ b/tests/svinterfaces/svinterface1.sv
@@ -3,8 +3,11 @@
 module TopModule(
     input logic clk,
     input logic rst,
+    output logic [21:0] outOther,
     input logic [1:0] sig,
-    output logic [1:0] sig_out);
+    input logic flip,
+    output logic [1:0] sig_out,
+    output logic [15:0] passThrough);
 
   MyInterface #(.WIDTH(4)) MyInterfaceInstance();
 
@@ -12,14 +15,16 @@ module TopModule(
     .clk(clk),
     .rst(rst),
     .u_MyInterface(MyInterfaceInstance),
+    .outOther(outOther),
     .sig (sig)
   );
 
   assign sig_out = MyInterfaceInstance.mysig_out;
 
 
-  assign MyInterfaceInstance.setting = 1;
-//  assign MyInterfaceInstance.other_setting[2:0] = 3'b101;
+  assign MyInterfaceInstance.setting = flip;
+
+  assign passThrough = MyInterfaceInstance.passThrough;
 
 endmodule
 
@@ -32,16 +37,20 @@ interface MyInterface #(
 
   logic [1:0] mysig_out;
 
+  logic [15:0] passThrough;
+
     modport submodule1 (
         input  setting,
         output other_setting,
-        output mysig_out
+        output mysig_out,
+        output passThrough
     );
 
     modport submodule2 (
         input  setting,
         output other_setting,
-        input  mysig_out
+        input  mysig_out,
+        output passThrough
     );
 
 endinterface
@@ -51,7 +60,8 @@ module SubModule1(
     input logic clk,
     input logic rst,
     MyInterface.submodule1 u_MyInterface,
-    input logic [1:0] sig
+    input logic [1:0] sig,
+    output logic [21:0] outOther
 
   );
 
@@ -71,9 +81,14 @@ module SubModule1(
     .clk(clk),
     .rst(rst),
     .u_MyInterfaceInSub2(u_MyInterface),
-    .sig (sig)
+    .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
   );
 
+    assign outOther = MyInterfaceInstanceInSub.other_setting;
+
+    assign MyInterfaceInstanceInSub.setting = 0;
+    assign MyInterfaceInstanceInSub.mysig_out = sig;
+
 endmodule
 
 module SubModule2(
@@ -81,10 +96,22 @@ module SubModule2(
     input logic clk,
     input logic rst,
     MyInterface.submodule2 u_MyInterfaceInSub2,
-    input logic [1:0] sig
+    MyInterface.submodule2 u_MyInterfaceInSub3
 
   );
 
-   assign u_MyInterfaceInSub2.other_setting[2:0] = 9;
+   always_comb begin
+      if (u_MyInterfaceInSub3.mysig_out == 2'b00)
+        u_MyInterfaceInSub3.other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
+        u_MyInterfaceInSub3.other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
+        u_MyInterfaceInSub3.other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3.other_setting[21:0] = 4000;
+   end
+
+    assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
+    assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
 
 endmodule
diff --git a/tests/svinterfaces/svinterface1_ref.v b/tests/svinterfaces/svinterface1_ref.v
new file mode 100644
index 000000000..b119f4037
--- /dev/null
+++ b/tests/svinterfaces/svinterface1_ref.v
@@ -0,0 +1,107 @@
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [15:0] passThrough,
+    output logic [21:0] outOther,
+    output logic [1:0] sig_out);
+
+
+    logic MyInterfaceInstance_setting;
+    logic [3:0] MyInterfaceInstance_other_setting;
+    logic [1:0] MyInterfaceInstance_mysig_out;
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface_setting(MyInterfaceInstance_setting),
+    .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
+    .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
+    .outOther(outOther),
+    .passThrough (passThrough),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance_mysig_out;
+
+
+  assign MyInterfaceInstance_setting = flip;
+
+endmodule
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterface_setting,
+    output logic [3:0] u_MyInterface_other_setting,
+    output logic [1:0] u_MyInterface_mysig_out,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    output logic [15:0] passThrough
+  );
+
+  always @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface_mysig_out <= 0;
+    else begin
+      if(u_MyInterface_setting)
+        u_MyInterface_mysig_out <= sig;
+      else
+        u_MyInterface_mysig_out <= ~sig;
+    end
+
+    logic MyInterfaceInstanceInSub_setting;
+    logic [21:0] MyInterfaceInstanceInSub_other_setting;
+    logic [1:0] MyInterfaceInstanceInSub_mysig_out;
+
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
+    .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
+    .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
+    .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
+    .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
+    .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
+    .passThrough (passThrough)
+  );
+    assign outOther = MyInterfaceInstanceInSub_other_setting;
+
+    assign MyInterfaceInstanceInSub_setting = 0;
+    assign MyInterfaceInstanceInSub_mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterfaceInSub2_setting,
+    output logic [3:0] u_MyInterfaceInSub2_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub2_mysig_out,
+    input logic u_MyInterfaceInSub3_setting,
+    output logic [21:0] u_MyInterfaceInSub3_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub3_mysig_out,
+    output logic [15:0] passThrough
+
+  );
+
+    always @(u_MyInterfaceInSub3_mysig_out) begin
+      if (u_MyInterfaceInSub3_mysig_out == 2'b00)
+        u_MyInterfaceInSub3_other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
+        u_MyInterfaceInSub3_other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
+        u_MyInterfaceInSub3_other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3_other_setting[21:0] = 4000;
+    end
+
+    assign passThrough[7:0] = 124;
+    assign passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface1_tb.v b/tests/svinterfaces/svinterface1_tb.v
new file mode 100644
index 000000000..44c3b5f68
--- /dev/null
+++ b/tests/svinterfaces/svinterface1_tb.v
@@ -0,0 +1,57 @@
+`timescale 1ns/10ps
+
+module svinterface1_tb;
+
+
+  logic clk;
+  logic rst;
+  logic [21:0] outOther;
+  logic [1:0] sig;
+  logic [1:0] sig_out;
+  logic flip;
+  logic [15:0] passThrough;
+  integer outfile;
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .sig_out(sig_out)
+  );
+
+  initial begin
+    clk = 0;
+    while(1) begin
+      clk = ~clk;
+      #50;
+    end
+  end
+
+  initial begin
+    outfile = $fopen("output.txt");
+    rst = 1;
+    sig = 0;
+    flip = 0;
+    @(posedge clk);
+    #(2);
+    rst = 0;
+    @(posedge clk);
+    for(int j=0;j<2;j++) begin
+      for(int i=0;i<20;i++) begin
+        #(2);
+        flip = j;
+        sig = i;
+        @(posedge clk);
+      end
+    end
+    $finish;
+  end
+
+  always @(negedge clk) begin
+    $fdisplay(outfile, "%d %d %d", outOther, sig_out, passThrough);
+  end
+
+endmodule

From 609f46eeb7b23fec2140dcfaaa5f3a8377153f43 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Thu, 18 Oct 2018 16:20:21 -0700
Subject: [PATCH 136/528] adding offset info to memories

---
 backends/verilog/verilog_backend.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ae9031510..39683922f 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -388,7 +388,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 void dump_memory(std::ostream &f, std::string indent, RTLIL::Memory *memory)
 {
 	dump_attributes(f, indent, memory->attributes);
-	f << stringf("%s" "reg [%d:0] %s [%d:0];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size-1);
+	f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), (memory->width-1), id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset);
 }
 
 void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true)
@@ -952,6 +952,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		std::string mem_id = id(cell->parameters["\\MEMID"].decode_string());
 		int abits = cell->parameters["\\ABITS"].as_int();
 		int size = cell->parameters["\\SIZE"].as_int();
+		int offset = cell->parameters["\\OFFSET"].as_int();
 		int width = cell->parameters["\\WIDTH"].as_int();
 		bool use_init = !(RTLIL::SigSpec(cell->parameters["\\INIT"]).is_fully_undef());
 
@@ -960,7 +961,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		//  initial begin
 		//    memid[0] = ...
 		//  end
-		f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size-1, 0);
+		f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset);
 		if (use_init)
 		{
 			f << stringf("%s" "initial begin\n", indent.c_str());

From c7770d9eeaf9fba0c9d07e7cce020fe89ec71600 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Thu, 18 Oct 2018 16:22:33 -0700
Subject: [PATCH 137/528] adding offset info to memories

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 39683922f..dde03f920 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -388,7 +388,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 void dump_memory(std::ostream &f, std::string indent, RTLIL::Memory *memory)
 {
 	dump_attributes(f, indent, memory->attributes);
-	f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), (memory->width-1), id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset);
+	f << stringf("%s" "reg [%d:0] %s [%d:%d];\n", indent.c_str(), memory->width-1, id(memory->name).c_str(), memory->size+memory->start_offset-1, memory->start_offset);
 }
 
 void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, bool gen_signed = true)

From 3420ae5ca5a6148c54310d065e7dcbd5a0ea1c8f Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 19 Oct 2018 14:45:45 +0100
Subject: [PATCH 138/528] memory_bram: Reset make_outreg when growing read
 ports

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/memory/memory_bram.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index e8552bbcf..8740042c4 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -623,6 +623,7 @@ grow_read_ports:;
 				pi.sig_addr = SigSpec();
 				pi.sig_data = SigSpec();
 				pi.sig_en = SigSpec();
+				pi.make_outreg = false;
 			}
 			new_portinfos.push_back(pi);
 			if (pi.dupidx == dup_count-1) {

From 677b8ed3ca70dad1dec288c274e64ebb0ef4011b Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 18 Oct 2018 19:39:48 +0100
Subject: [PATCH 139/528] ecp5: Add latch inference

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc  |  1 +
 techlibs/ecp5/latches_map.v | 11 +++++++++++
 techlibs/ecp5/synth_ecp5.cc |  3 ---
 3 files changed, 12 insertions(+), 3 deletions(-)
 create mode 100644 techlibs/ecp5/latches_map.v

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index f45859392..9b6f061bd 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -8,6 +8,7 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
diff --git a/techlibs/ecp5/latches_map.v b/techlibs/ecp5/latches_map.v
new file mode 100644
index 000000000..c28f88cf7
--- /dev/null
+++ b/techlibs/ecp5/latches_map.v
@@ -0,0 +1,11 @@
+module \$_DLATCH_N_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = E ? D : Q;
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index ab56a9444..cb6a4c3d8 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -266,10 +266,7 @@ struct SynthEcp5Pass : public ScriptPass
 			if (abc2 || help_mode) {
 				run("abc", "      (only if -abc2)");
 			}
-			//TODO
-#if 0
 			run("techmap -map +/ecp5/latches_map.v");
-#endif
 			if (nomux)
 				run("abc -lut 4");
 			else

From d29b517fef05973dda3c556a95fbfb478d6e7e50 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 18 Oct 2018 19:40:02 +0100
Subject: [PATCH 140/528] ecp5: Sim model fixes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e43632c64..6e4b0a5ac 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -265,16 +265,18 @@ module TRELLIS_IO(
 	output O
 );
 	parameter DIR = "INPUT";
+	reg T_pd;
+	always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
 
 	generate
 		if (DIR == "INPUT") begin
 			assign B = 1'bz;
 			assign O = B;
 		end else if (DIR == "OUTPUT") begin
-			assign B = T ? 1'bz : I;
+			assign B = T_pd ? 1'bz : I;
 			assign O = 1'bx;
-		end else if (DIR == "INOUT") begin
-			assign B = T ? 1'bz : I;
+		end else if (DIR == "BIDIR") begin
+			assign B = T_pd ? 1'bz : I;
 			assign O = B;
 		end else begin
 			ERROR_UNKNOWN_IO_MODE error();

From d9a438101298710b9dadd4e7a1cb0041e8ba4199 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 20 Oct 2018 11:57:39 +0200
Subject: [PATCH 141/528] Fixed memory leak

---
 frontends/ast/ast.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 7600e2912..1f2ecffde 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1120,6 +1120,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 
 	// Generate RTLIL from AST for the new module and add to the design:
 	AstModule *newmod = process_module(new_ast, false);
+	delete(new_ast);
 	design->add(newmod);
 	RTLIL::Module* mod = design->module(original_name);
 	if (is_top)

From 397dfccb304a12a40d34c4454a5cb4acee8be75f Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 20 Oct 2018 11:58:25 +0200
Subject: [PATCH 142/528] Support for SystemVerilog interfaces as a port in the
 top level module + test case

---
 frontends/ast/ast.cc                          | 108 ++++++++++++++-
 passes/hierarchy/hierarchy.cc                 |  41 +++++-
 tests/svinterfaces/run-test.sh                |   1 +
 tests/svinterfaces/runone.sh                  |   7 +-
 tests/svinterfaces/svinterface_at_top.sv      | 125 ++++++++++++++++++
 tests/svinterfaces/svinterface_at_top_ref.v   | 120 +++++++++++++++++
 tests/svinterfaces/svinterface_at_top_tb.v    |  68 ++++++++++
 .../svinterface_at_top_tb_wrapper.v           |  68 ++++++++++
 .../svinterfaces/svinterface_at_top_wrapper.v |  33 +++++
 9 files changed, 561 insertions(+), 10 deletions(-)
 create mode 100644 tests/svinterfaces/svinterface_at_top.sv
 create mode 100644 tests/svinterfaces/svinterface_at_top_ref.v
 create mode 100644 tests/svinterfaces/svinterface_at_top_tb.v
 create mode 100644 tests/svinterfaces/svinterface_at_top_tb_wrapper.v
 create mode 100644 tests/svinterfaces/svinterface_at_top_wrapper.v

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 1f2ecffde..412e04f6e 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -904,7 +904,7 @@ RTLIL::Const AstNode::realAsConst(int width)
 }
 
 // create a new AstModule from an AST_MODULE AST node
-static AstModule* process_module(AstNode *ast, bool defer)
+static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast = NULL)
 {
 	log_assert(ast->type == AST_MODULE || ast->type == AST_INTERFACE);
 
@@ -920,7 +920,11 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	current_module->set_bool_attribute("\\cells_not_processed");
 
 	current_ast_mod = ast;
-	AstNode *ast_before_simplify = ast->clone();
+	AstNode *ast_before_simplify;
+	if (original_ast != NULL)
+		ast_before_simplify = original_ast;
+	else
+		ast_before_simplify = ast->clone();
 
 	if (flag_dump_ast1) {
 		log("Dumping Verilog AST before simplification:\n");
@@ -1105,6 +1109,104 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 		}
 	}
 
+	AstNode *ast_before_replacing_interface_ports = new_ast->clone();
+
+	// Explode all interface ports. Note this will only have any effect on top
+	// level modules. Other sub-modules will have their interface ports
+	// exploded in derive(..)
+	for (size_t i =0; i<new_ast->children.size(); i++)
+	{
+		AstNode *ch2 = new_ast->children[i];
+		std::string interface_type = "";
+		std::string interface_modport = "";
+		if (ch2->type == AST_INTERFACEPORT) {
+			std::string name_port = ch2->str;
+			if (ch2->children.size() > 0) {
+				for(size_t j=0; j<ch2->children.size();j++) {
+					AstNode *ch = ch2->children[j];
+					if(ch->type == AST_INTERFACEPORTTYPE) {
+						std::string name_type = ch->str;
+						size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
+						// Separate the interface instance name from any modports:
+						if (ndots == 0) { // Does not have modport
+							interface_type = name_type;
+						}
+						else {
+							std::stringstream name_type_stream(name_type);
+							std::string segment;
+							std::vector<std::string> seglist;
+							while(std::getline(name_type_stream, segment, '.')) {
+								seglist.push_back(segment);
+							}
+							if (ndots == 1) { // Has modport
+								interface_type = seglist[0];
+								interface_modport = seglist[1];
+							}
+							else { // Erroneous port type
+								log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
+							}
+						}
+						if (design->modules_.count(interface_type) > 0) {
+							AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE);
+							celltype_for_intf->str = interface_type;
+							AstNode *cell_for_intf = new AstNode(AST_CELL, celltype_for_intf);
+							cell_for_intf->str = name_port + "_inst_from_top_dummy";
+							new_ast->children.push_back(cell_for_intf);
+
+							RTLIL::Module *intfmodule = design->modules_[interface_type];
+							AstModule *ast_module_of_interface = (AstModule*)intfmodule;
+							AstNode *ast_node_of_interface = ast_module_of_interface->ast;
+							AstNode *modport = NULL;
+							std::string interface_modport_compare_str = "\\" + interface_modport;
+							for (auto &chm : ast_node_of_interface->children) {
+								if (chm->type == AST_MODPORT) {
+									if (chm->str == interface_modport_compare_str) { // Modport found
+										modport = chm;
+									}
+								}
+							}
+
+							std::string intfname = name_port;
+							for (auto &wire_it : intfmodule->wires_){
+								AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
+								std::string origname = log_id(wire_it.first);
+								std::string newname = intfname + "." + origname;
+								wire->str = newname;
+								if (modport != NULL) {
+									bool found_in_modport = false;
+									// Search for the current wire in the wire list for the current modport
+									for (auto &ch : modport->children) {
+										if (ch->type == AST_MODPORTMEMBER) {
+											std::string compare_name = "\\" + origname;
+											if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
+												found_in_modport = true;
+												wire->is_input = ch->is_input;
+												wire->is_output = ch->is_output;
+												break;
+											}
+										}
+									}
+									if (found_in_modport) {
+										new_ast->children.push_back(wire);
+									}
+									else { // If not found in modport, do not create port
+										delete wire;
+									}
+								}
+								else { // If no modport, set inout
+									wire->is_input = true;
+									wire->is_output = true;
+									new_ast->children.push_back(wire);
+								}
+							}
+						}
+					}
+				}
+			}
+		}
+	}
+
+
 	// The old module will be deleted. Rename and mark for deletion:
 	std::string original_name = this->name.str();
 	std::string changed_name = original_name + "_before_replacing_local_interfaces";
@@ -1119,7 +1221,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 	}
 
 	// Generate RTLIL from AST for the new module and add to the design:
-	AstModule *newmod = process_module(new_ast, false);
+	AstModule *newmod = process_module(new_ast, false, ast_before_replacing_interface_ports);
 	delete(new_ast);
 	design->add(newmod);
 	RTLIL::Module* mod = design->module(original_name);
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 7e93a6f9a..9c7dad3d3 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -146,6 +146,17 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 	std::map<RTLIL::Cell*, std::pair<int, int>> array_cells;
 	std::string filename;
 
+	bool has_interface_ports = false;
+
+	// If any of the ports are actually interface ports, we will always need to
+	// reprocess the module:
+	if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+		for (auto &wire : module->wires_) {
+			if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface"))
+				has_interface_ports = true;
+		}
+	}
+
 	// Always keep track of all derived interfaces available in the current module in 'interfaces_in_module':
 	dict<RTLIL::IdString, RTLIL::Module*> interfaces_in_module;
 	for (auto &cell_it : module->cells_)
@@ -244,8 +255,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 					RTLIL::IdString interface_name = interface_name_str;
 					bool not_found_interface = false;
 					if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
-						if (interfaces_in_module.count(interface_name) > 0) { // Check if the interface instance is present in module
-							RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name);
+						int nexactmatch = interfaces_in_module.count(interface_name) > 0;
+						std::string interface_name_str2 =  interface_name_str + "_inst_from_top_dummy";
+						RTLIL::IdString interface_name2 = interface_name_str2;
+						int nmatch2 = interfaces_in_module.count(interface_name2) > 0;
+						if (nexactmatch > 0 || nmatch2 > 0) { // Check if the interface instance is present in module
+							if (nexactmatch != 0)
+								interface_name2 = interface_name;
+							RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2);
 							for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists.
 								std::string signal_name1 = conn.first.str() + "." + log_id(mod_wire.first);
 								std::string signal_name2 = interface_name.str() + "." + log_id(mod_wire.first);
@@ -259,7 +276,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 								}
 							}
 							connections_to_remove.push_back(conn.first);
-							interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name);
+							interfaces_to_add_to_submodule[conn.first] = interfaces_in_module.at(interface_name2);
 
 							// Add modports to a dict which will be passed to AstModule::derive
 							if (interface_modport != "") {
@@ -363,8 +380,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 	module->attributes.erase("\\cells_not_processed");
 
 
-	// If any interface instances were found in the module, we need to rederive it completely:
-	if (interfaces_in_module.size() > 0 && !module->get_bool_attribute("\\interfaces_replaced_in_module")) {
+	// If any interface instances or interface ports were found in the module, we need to rederive it completely:
+	if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute("\\interfaces_replaced_in_module")) {
 		module->reprocess_module(design, interfaces_in_module);
 		return did_something;
 	}
@@ -438,6 +455,20 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib)
 	for (auto &it : design->modules_)
 		if (used.count(it.second) == 0)
 			del_modules.push_back(it.second);
+		else {
+			// Now all interface ports must have been exploded, and it is hence
+			// safe to delete all of the remaining dummy interface ports:
+			pool<RTLIL::Wire*> del_wires;
+			for(auto &wire : it.second->wires_) {
+				if ((wire.second->port_input || wire.second->port_output) && wire.second->get_bool_attribute("\\is_interface")) {
+					del_wires.insert(wire.second);
+				}
+			}
+			if (del_wires.size() > 0) {
+				it.second->remove(del_wires);
+				it.second->fixup_ports();
+			}
+		}
 
 	int del_counter = 0;
 	for (auto mod : del_modules) {
diff --git a/tests/svinterfaces/run-test.sh b/tests/svinterfaces/run-test.sh
index 1630859bd..86567d1c1 100755
--- a/tests/svinterfaces/run-test.sh
+++ b/tests/svinterfaces/run-test.sh
@@ -3,3 +3,4 @@
 
 
 ./runone.sh  svinterface1
+./runone.sh  svinterface_at_top
diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
index 345801389..0adecc797 100755
--- a/tests/svinterfaces/runone.sh
+++ b/tests/svinterfaces/runone.sh
@@ -22,11 +22,14 @@ iverilog -g2012 ${TESTNAME}_syn.v
 iverilog -g2012 ${TESTNAME}_ref_syn.v
 
 set +e
-
 iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
 ./a.out
 mv output.txt reference_result.txt
-iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+if [ -f ${TESTNAME}_wrapper.v ] ; then
+    iverilog -g2012 ${TESTNAME}_tb_wrapper.v ${TESTNAME}_syn.v
+else
+    iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+fi
 ./a.out
 mv output.txt dut_result.txt
 
diff --git a/tests/svinterfaces/svinterface_at_top.sv b/tests/svinterfaces/svinterface_at_top.sv
new file mode 100644
index 000000000..b5aa8c8f5
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top.sv
@@ -0,0 +1,125 @@
+
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [1:0] sig_out,
+    MyInterface.submodule1 interfaceInstanceAtTop,
+    output logic [15:0] passThrough);
+
+  MyInterface #(.WIDTH(4)) MyInterfaceInstance();
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface(MyInterfaceInstance),
+    .u_MyInterfaceFromTop(interfaceInstanceAtTop),
+    .outOther(outOther),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance.mysig_out;
+
+
+  assign MyInterfaceInstance.setting = flip;
+
+  assign passThrough = MyInterfaceInstance.passThrough;
+
+endmodule
+
+interface MyInterface #(
+  parameter WIDTH = 3)(
+  );
+
+  logic setting;
+  logic [WIDTH-1:0] other_setting;
+
+  logic [1:0] mysig_out;
+
+  logic [15:0] passThrough;
+
+    modport submodule1 (
+        input  setting,
+        output other_setting,
+        output mysig_out,
+        output passThrough
+    );
+
+    modport submodule2 (
+        input  setting,
+        output other_setting,
+        input  mysig_out,
+        output passThrough
+    );
+
+endinterface
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    MyInterface.submodule1 u_MyInterface,
+    MyInterface.submodule1 u_MyInterfaceFromTop,
+    input logic [1:0] sig,
+    output logic [21:0] outOther
+
+  );
+
+
+  always_ff @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface.mysig_out <= 0;
+    else begin
+      if(u_MyInterface.setting)
+        u_MyInterface.mysig_out <= sig;
+      else
+        u_MyInterface.mysig_out <= ~sig;
+    end
+
+  MyInterface #(.WIDTH(22)) MyInterfaceInstanceInSub();
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceFromTopDown(u_MyInterfaceFromTop),
+    .u_MyInterfaceInSub2(u_MyInterface),
+    .u_MyInterfaceInSub3(MyInterfaceInstanceInSub)
+  );
+
+    assign outOther = MyInterfaceInstanceInSub.other_setting;
+
+    assign MyInterfaceInstanceInSub.setting = 0;
+    assign MyInterfaceInstanceInSub.mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    MyInterface.submodule2 u_MyInterfaceInSub2,
+    MyInterface.submodule1 u_MyInterfaceFromTopDown,
+    MyInterface.submodule2 u_MyInterfaceInSub3
+
+  );
+
+  assign u_MyInterfaceFromTopDown.mysig_out = u_MyInterfaceFromTop.setting ? 10 :  20;
+
+   always_comb begin
+      if (u_MyInterfaceInSub3.mysig_out == 2'b00)
+        u_MyInterfaceInSub3.other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b01)
+        u_MyInterfaceInSub3.other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3.mysig_out == 2'b10)
+        u_MyInterfaceInSub3.other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3.other_setting[21:0] = 4000;
+   end
+
+    assign u_MyInterfaceInSub2.passThrough[7:0] = 124;
+    assign u_MyInterfaceInSub2.passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_ref.v b/tests/svinterfaces/svinterface_at_top_ref.v
new file mode 100644
index 000000000..7b54a26d6
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_ref.v
@@ -0,0 +1,120 @@
+
+module TopModule(
+    input logic clk,
+    input logic rst,
+    input logic [1:0] sig,
+    input logic flip,
+    output logic [15:0] passThrough,
+    output logic [21:0] outOther,
+    input logic interfaceInstanceAtTop_setting,
+    output logic [2:0] interfaceInstanceAtTop_other_setting,
+    output logic [1:0] interfaceInstanceAtTop_mysig_out,
+    output logic [15:0] interfaceInstanceAtTop_passThrough,
+    output logic [1:0] sig_out);
+
+
+    logic MyInterfaceInstance_setting;
+    logic [3:0] MyInterfaceInstance_other_setting;
+    logic [1:0] MyInterfaceInstance_mysig_out;
+
+  SubModule1 u_SubModule1 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterface_setting(MyInterfaceInstance_setting),
+    .u_MyInterface_mysig_out(MyInterfaceInstance_mysig_out),
+    .u_MyInterface_other_setting(MyInterfaceInstance_other_setting),
+    .u_MyInterfaceFromTop_setting(interfaceInstanceAtTop_setting),
+    .u_MyInterfaceFromTop_other_setting(interfaceInstanceAtTop_other_setting),
+    .u_MyInterfaceFromTop_mysig_out(interfaceInstanceAtTop_mysig_out),
+    .u_MyInterfaceFromTop_passThrough(interfaceInstanceAtTop_passThrough),
+    .outOther(outOther),
+    .passThrough (passThrough),
+    .sig (sig)
+  );
+
+  assign sig_out = MyInterfaceInstance_mysig_out;
+
+
+  assign MyInterfaceInstance_setting = flip;
+
+endmodule
+
+
+module SubModule1(
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterface_setting,
+    output logic [3:0] u_MyInterface_other_setting,
+    output logic [1:0] u_MyInterface_mysig_out,
+    output logic [21:0] outOther,
+    input logic [1:0] sig,
+    input logic u_MyInterfaceFromTop_setting,
+    output logic [2:0]  u_MyInterfaceFromTop_other_setting,
+    output logic [1:0]  u_MyInterfaceFromTop_mysig_out,
+    output logic [14:0] u_MyInterfaceFromTop_passThrough,
+    output logic [15:0] passThrough
+  );
+
+  always @(posedge clk or posedge rst)
+    if(rst)
+      u_MyInterface_mysig_out <= 0;
+    else begin
+      if(u_MyInterface_setting)
+        u_MyInterface_mysig_out <= sig;
+      else
+        u_MyInterface_mysig_out <= ~sig;
+    end
+
+    logic MyInterfaceInstanceInSub_setting;
+    logic [21:0] MyInterfaceInstanceInSub_other_setting;
+    logic [1:0] MyInterfaceInstanceInSub_mysig_out;
+
+  assign u_MyInterfaceFromTop_mysig_out = u_MyInterfaceFromTop_setting ? 10 :  20;
+
+  SubModule2 u_SubModule2 (
+    .clk(clk),
+    .rst(rst),
+    .u_MyInterfaceInSub2_setting(u_MyInterface_setting),
+    .u_MyInterfaceInSub2_mysig_out(u_MyInterface_mysig_out),
+    .u_MyInterfaceInSub2_other_setting(u_MyInterface_other_setting),
+    .u_MyInterfaceInSub3_setting(MyInterfaceInstanceInSub_setting),
+    .u_MyInterfaceInSub3_mysig_out(MyInterfaceInstanceInSub_mysig_out),
+    .u_MyInterfaceInSub3_other_setting(MyInterfaceInstanceInSub_other_setting),
+    .passThrough (passThrough)
+  );
+    assign outOther = MyInterfaceInstanceInSub_other_setting;
+
+    assign MyInterfaceInstanceInSub_setting = 0;
+    assign MyInterfaceInstanceInSub_mysig_out = sig;
+
+endmodule
+
+module SubModule2(
+
+    input logic clk,
+    input logic rst,
+    input logic u_MyInterfaceInSub2_setting,
+    output logic [3:0] u_MyInterfaceInSub2_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub2_mysig_out,
+    input logic u_MyInterfaceInSub3_setting,
+    output logic [21:0] u_MyInterfaceInSub3_other_setting,
+    input  logic [1:0] u_MyInterfaceInSub3_mysig_out,
+    output logic [15:0] passThrough
+
+  );
+
+    always @(u_MyInterfaceInSub3_mysig_out) begin
+      if (u_MyInterfaceInSub3_mysig_out == 2'b00)
+        u_MyInterfaceInSub3_other_setting[21:0] = 1000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b01)
+        u_MyInterfaceInSub3_other_setting[21:0] = 2000;
+      else if (u_MyInterfaceInSub3_mysig_out == 2'b10)
+        u_MyInterfaceInSub3_other_setting[21:0] = 3000;
+      else
+        u_MyInterfaceInSub3_other_setting[21:0] = 4000;
+    end
+
+    assign passThrough[7:0] = 124;
+    assign passThrough[15:8] = 200;
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_tb.v b/tests/svinterfaces/svinterface_at_top_tb.v
new file mode 100644
index 000000000..bf37a148d
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_tb.v
@@ -0,0 +1,68 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_tb;
+
+
+  logic clk;
+  logic rst;
+  logic [21:0] outOther;
+  logic [1:0] sig;
+  logic [1:0] sig_out;
+  logic flip;
+  logic [15:0] passThrough;
+  integer outfile;
+
+  logic interfaceInstanceAtTop_setting;
+  logic [2:0] interfaceInstanceAtTop_other_setting;
+  logic [1:0] interfaceInstanceAtTop_mysig_out;
+  logic [15:0] interfaceInstanceAtTop_passThrough;
+
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .interfaceInstanceAtTop_setting(interfaceInstanceAtTop_setting),
+    .interfaceInstanceAtTop_other_setting(interfaceInstanceAtTop_other_setting),
+    .interfaceInstanceAtTop_mysig_out(interfaceInstanceAtTop_mysig_out),
+    .interfaceInstanceAtTop_passThrough(interfaceInstanceAtTop_passThrough),
+    .sig_out(sig_out)
+  );
+
+  initial begin
+    clk = 0;
+    while(1) begin
+      clk = ~clk;
+      #50;
+    end
+  end
+
+  initial begin
+    outfile = $fopen("output.txt");
+    rst = 1;
+    interfaceInstanceAtTop_setting = 0;
+    sig = 0;
+    flip = 0;
+    @(posedge clk);
+    #(2);
+    rst = 0;
+    @(posedge clk);
+    for(int j=0;j<2;j++) begin
+      for(int i=0;i<20;i++) begin
+        #(2);
+        flip = j;
+        sig = i;
+        @(posedge clk);
+      end
+    end
+    $finish;
+  end
+
+  always @(negedge clk) begin
+    $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
+  end
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_tb_wrapper.v b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v
new file mode 100644
index 000000000..b344a7b88
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_tb_wrapper.v
@@ -0,0 +1,68 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_tb_wrapper;
+
+
+  logic clk;
+  logic rst;
+  logic [21:0] outOther;
+  logic [1:0] sig;
+  logic [1:0] sig_out;
+  logic flip;
+  logic [15:0] passThrough;
+  integer outfile;
+
+  logic interfaceInstanceAtTop_setting;
+  logic [2:0] interfaceInstanceAtTop_other_setting;
+  logic [1:0] interfaceInstanceAtTop_mysig_out;
+  logic [15:0] interfaceInstanceAtTop_passThrough;
+
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .\interfaceInstanceAtTop.setting (interfaceInstanceAtTop_setting),
+    .\interfaceInstanceAtTop.other_setting (interfaceInstanceAtTop_other_setting),
+    .\interfaceInstanceAtTop.mysig_out (interfaceInstanceAtTop_mysig_out),
+    .\interfaceInstanceAtTop.passThrough (interfaceInstanceAtTop_passThrough),
+    .sig_out(sig_out)
+  );
+
+  initial begin
+    clk = 0;
+    while(1) begin
+      clk = ~clk;
+      #50;
+    end
+  end
+
+  initial begin
+    outfile = $fopen("output.txt");
+    rst = 1;
+    sig = 0;
+    interfaceInstanceAtTop_setting = 0;
+    flip = 0;
+    @(posedge clk);
+    #(2);
+    rst = 0;
+    @(posedge clk);
+    for(int j=0;j<2;j++) begin
+      for(int i=0;i<20;i++) begin
+        #(2);
+        flip = j;
+        sig = i;
+        @(posedge clk);
+      end
+    end
+    $finish;
+  end
+
+  always @(negedge clk) begin
+    $fdisplay(outfile, "%d %d %d %d", outOther, sig_out, passThrough, interfaceInstanceAtTop_mysig_out);
+  end
+
+endmodule
diff --git a/tests/svinterfaces/svinterface_at_top_wrapper.v b/tests/svinterfaces/svinterface_at_top_wrapper.v
new file mode 100644
index 000000000..64f906c07
--- /dev/null
+++ b/tests/svinterfaces/svinterface_at_top_wrapper.v
@@ -0,0 +1,33 @@
+`timescale 1ns/10ps
+
+module svinterface_at_top_wrapper(
+  input logic clk,
+  input logic rst,
+  output logic [21:0] outOther,
+  input logic [1:0] sig,
+  output logic [1:0] sig_out,
+  input logic flip,
+  output logic [15:0] passThrough,
+
+    input logic interfaceInstanceAtTop_setting,
+    output logic [2:0] interfaceInstanceAtTop_other_setting,
+    output logic [1:0] interfaceInstanceAtTop_mysig_out,
+    output logic [15:0] interfaceInstanceAtTop_passThrough,
+  );
+
+
+  TopModule u_dut (
+    .clk(clk),
+    .rst(rst),
+    .outOther(outOther),
+    .sig(sig),
+    .flip(flip),
+    .passThrough(passThrough),
+    .\interfaceInstanceAtTop.setting(interfaceInstanceAtTop_setting),
+    .\interfaceInstanceAtTop.other_setting(interfaceInstanceAtTop_other_setting),
+    .\interfaceInstanceAtTop.mysig_out(interfaceInstanceAtTop_mysig_out),
+    .\interfaceInstanceAtTop.passThrough(interfaceInstanceAtTop_passThrough),
+    .sig_out(sig_out)
+  );
+
+endmodule

From 436e3c0a7cbe5a482e14857e4e5a1d02b3464ae8 Mon Sep 17 00:00:00 2001
From: Ruben Undheim <ruben.undheim@gmail.com>
Date: Sat, 20 Oct 2018 12:45:51 +0200
Subject: [PATCH 143/528] Refactor code to avoid code duplication + added
 comments

---
 frontends/ast/ast.cc          | 212 ++++++++++++++++------------------
 frontends/ast/ast.h           |   5 +
 frontends/ast/genrtlil.cc     |  25 +---
 passes/hierarchy/hierarchy.cc |   7 +-
 4 files changed, 113 insertions(+), 136 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 412e04f6e..cc275959a 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -1091,6 +1091,84 @@ AstModule::~AstModule()
 		delete ast;
 }
 
+
+// An interface port with modport is specified like this:
+//    <interface_name>.<modport_name>
+// This function splits the interface_name from the modport_name, and fails if it is not a valid combination
+std::pair<std::string,std::string> AST::split_modport_from_type(std::string name_type)
+{
+	std::string interface_type = "";
+	std::string interface_modport = "";
+	size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
+	// Separate the interface instance name from any modports:
+	if (ndots == 0) { // Does not have modport
+		interface_type = name_type;
+	}
+	else {
+		std::stringstream name_type_stream(name_type);
+		std::string segment;
+		std::vector<std::string> seglist;
+		while(std::getline(name_type_stream, segment, '.')) {
+			seglist.push_back(segment);
+		}
+		if (ndots == 1) { // Has modport
+			interface_type = seglist[0];
+			interface_modport = seglist[1];
+		}
+		else { // Erroneous port type
+			log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
+		}
+	}
+	return std::pair<std::string,std::string>(interface_type, interface_modport);
+
+}
+
+AstNode * AST::find_modport(AstNode *intf, std::string name)
+{
+	for (auto &ch : intf->children)
+		if (ch->type == AST_MODPORT)
+			if (ch->str == name) // Modport found
+				return ch;
+	return NULL;
+}
+
+// Iterate over all wires in an interface and add them as wires in the AST module:
+void AST::explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport)
+{
+	for (auto &wire_it : intfmodule->wires_){
+		AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
+		std::string origname = log_id(wire_it.first);
+		std::string newname = intfname + "." + origname;
+		wire->str = newname;
+		if (modport != NULL) {
+			bool found_in_modport = false;
+			// Search for the current wire in the wire list for the current modport
+			for (auto &ch : modport->children) {
+				if (ch->type == AST_MODPORTMEMBER) {
+					std::string compare_name = "\\" + origname;
+					if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
+						found_in_modport = true;
+						wire->is_input = ch->is_input;
+						wire->is_output = ch->is_output;
+						break;
+					}
+				}
+			}
+			if (found_in_modport) {
+				module_ast->children.push_back(wire);
+			}
+			else { // If not found in modport, do not create port
+				delete wire;
+			}
+		}
+		else { // If no modport, set inout
+			wire->is_input = true;
+			wire->is_output = true;
+			module_ast->children.push_back(wire);
+		}
+	}
+}
+
 // When an interface instance is found in a module, the whole RTLIL for the module will be rederived again
 // from AST. The interface members are copied into the AST module with the prefix of the interface.
 void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module*> local_interfaces)
@@ -1111,102 +1189,47 @@ void AstModule::reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RT
 
 	AstNode *ast_before_replacing_interface_ports = new_ast->clone();
 
-	// Explode all interface ports. Note this will only have any effect on top
-	// level modules. Other sub-modules will have their interface ports
-	// exploded in derive(..)
+	// Explode all interface ports. Note this will only have an effect on 'top
+	// level' modules. Other sub-modules will have their interface ports
+	// exploded via the derive(..) function
 	for (size_t i =0; i<new_ast->children.size(); i++)
 	{
 		AstNode *ch2 = new_ast->children[i];
-		std::string interface_type = "";
-		std::string interface_modport = "";
-		if (ch2->type == AST_INTERFACEPORT) {
-			std::string name_port = ch2->str;
+		if (ch2->type == AST_INTERFACEPORT) { // Is an interface port
+			std::string name_port = ch2->str; // Name of the interface port
 			if (ch2->children.size() > 0) {
 				for(size_t j=0; j<ch2->children.size();j++) {
 					AstNode *ch = ch2->children[j];
-					if(ch->type == AST_INTERFACEPORTTYPE) {
-						std::string name_type = ch->str;
-						size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
-						// Separate the interface instance name from any modports:
-						if (ndots == 0) { // Does not have modport
-							interface_type = name_type;
-						}
-						else {
-							std::stringstream name_type_stream(name_type);
-							std::string segment;
-							std::vector<std::string> seglist;
-							while(std::getline(name_type_stream, segment, '.')) {
-								seglist.push_back(segment);
-							}
-							if (ndots == 1) { // Has modport
-								interface_type = seglist[0];
-								interface_modport = seglist[1];
-							}
-							else { // Erroneous port type
-								log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
-							}
-						}
+					if(ch->type == AST_INTERFACEPORTTYPE) { // Found the AST node containing the type of the interface
+						std::pair<std::string,std::string> res = split_modport_from_type(ch->str);
+						std::string interface_type = res.first;
+						std::string interface_modport = res.second; // Is "", if no modport
 						if (design->modules_.count(interface_type) > 0) {
+							// Add a cell to the module corresponding to the interface port such that
+							// it can further propagated down if needed:
 							AstNode *celltype_for_intf = new AstNode(AST_CELLTYPE);
 							celltype_for_intf->str = interface_type;
 							AstNode *cell_for_intf = new AstNode(AST_CELL, celltype_for_intf);
 							cell_for_intf->str = name_port + "_inst_from_top_dummy";
 							new_ast->children.push_back(cell_for_intf);
 
-							RTLIL::Module *intfmodule = design->modules_[interface_type];
+							// Get all members of this non-overridden dummy interface instance:
+							RTLIL::Module *intfmodule = design->modules_[interface_type]; // All interfaces should at this point in time (assuming
+							                                                              // reprocess_module is called from the hierarchy pass) be
+							                                                              // present in design->modules_
 							AstModule *ast_module_of_interface = (AstModule*)intfmodule;
-							AstNode *ast_node_of_interface = ast_module_of_interface->ast;
-							AstNode *modport = NULL;
 							std::string interface_modport_compare_str = "\\" + interface_modport;
-							for (auto &chm : ast_node_of_interface->children) {
-								if (chm->type == AST_MODPORT) {
-									if (chm->str == interface_modport_compare_str) { // Modport found
-										modport = chm;
-									}
-								}
-							}
-
-							std::string intfname = name_port;
-							for (auto &wire_it : intfmodule->wires_){
-								AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
-								std::string origname = log_id(wire_it.first);
-								std::string newname = intfname + "." + origname;
-								wire->str = newname;
-								if (modport != NULL) {
-									bool found_in_modport = false;
-									// Search for the current wire in the wire list for the current modport
-									for (auto &ch : modport->children) {
-										if (ch->type == AST_MODPORTMEMBER) {
-											std::string compare_name = "\\" + origname;
-											if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
-												found_in_modport = true;
-												wire->is_input = ch->is_input;
-												wire->is_output = ch->is_output;
-												break;
-											}
-										}
-									}
-									if (found_in_modport) {
-										new_ast->children.push_back(wire);
-									}
-									else { // If not found in modport, do not create port
-										delete wire;
-									}
-								}
-								else { // If no modport, set inout
-									wire->is_input = true;
-									wire->is_output = true;
-									new_ast->children.push_back(wire);
-								}
-							}
+							AstNode *modport = find_modport(ast_module_of_interface->ast, interface_modport_compare_str); // modport == NULL if no modport
+							// Iterate over all wires in the interface and add them to the module:
+							explode_interface_port(new_ast, intfmodule, name_port, modport);
 						}
+						break;
 					}
 				}
 			}
 		}
 	}
 
-
 	// The old module will be deleted. Rename and mark for deletion:
 	std::string original_name = this->name.str();
 	std::string changed_name = original_name + "_before_replacing_local_interfaces";
@@ -1267,47 +1290,10 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, dict<RTLIL::IdString, R
 				std::string interface_modport = modports.at(intfname).str();
 				AstModule *ast_module_of_interface = (AstModule*)intfmodule;
 				AstNode *ast_node_of_interface = ast_module_of_interface->ast;
-				for (auto &ch : ast_node_of_interface->children) {
-					if (ch->type == AST_MODPORT) {
-						if (ch->str == interface_modport) { // Modport found
-							modport = ch;
-						}
-					}
-				}
+				modport = find_modport(ast_node_of_interface, interface_modport);
 			}
 			// Iterate over all wires in the interface and add them to the module:
-			for (auto &wire_it : intfmodule->wires_){
-				AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(wire_it.second->width -1, true), AstNode::mkconst_int(0, true)));
-				std::string origname = log_id(wire_it.first);
-				std::string newname = intfname + "." + origname;
-				wire->str = newname;
-				if (modport != NULL) {
-					bool found_in_modport = false;
-					// Search for the current wire in the wire list for the current modport
-					for (auto &ch : modport->children) {
-						if (ch->type == AST_MODPORTMEMBER) {
-							std::string compare_name = "\\" + origname;
-							if (ch->str == compare_name) { // Found signal. The modport decides whether it is input or output
-								found_in_modport = true;
-								wire->is_input = ch->is_input;
-								wire->is_output = ch->is_output;
-								break;
-							}
-						}
-					}
-					if (found_in_modport) {
-						new_ast->children.push_back(wire);
-					}
-					else { // If not found in modport, do not create port
-						delete wire;
-					}
-				}
-				else { // If no modport, set inout
-					wire->is_input = true;
-					wire->is_output = true;
-					new_ast->children.push_back(wire);
-				}
-			}
+			explode_interface_port(new_ast, intfmodule, intfname, modport);
 		}
 
 		design->add(process_module(new_ast, false));
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 8187b1ac6..08f91c9c3 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -308,6 +308,11 @@ namespace AST
 
 	// call a DPI function
 	AstNode *dpi_call(const std::string &rtype, const std::string &fname, const std::vector<std::string> &argtypes, const std::vector<AstNode*> &args);
+
+	// Helper functions related to handling SystemVerilog interfaces
+	std::pair<std::string,std::string> split_modport_from_type(std::string name_type);
+	AstNode * find_modport(AstNode *intf, std::string name);
+	void explode_interface_port(AstNode *module_ast, RTLIL::Module * intfmodule, std::string intfname, AstNode *modport);
 }
 
 namespace AST_INTERNAL
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 32b9af6e9..8a6849faa 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -870,27 +870,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		if (children.size() > 0) {
 			for(size_t i=0; i<children.size();i++) {
 				if(children[i]->type == AST_INTERFACEPORTTYPE) {
-					std::string name_type = children[i]->str;
-					size_t ndots = std::count(name_type.begin(), name_type.end(), '.');
-					// Separate the interface instance name from any modports:
-					if (ndots == 0) { // Does not have modport
-						wire->attributes["\\interface_type"] = name_type;
-					}
-					else {
-						std::stringstream name_type_stream(name_type);
-						std::string segment;
-						std::vector<std::string> seglist;
-						while(std::getline(name_type_stream, segment, '.')) {
-							seglist.push_back(segment);
-						}
-						if (ndots == 1) { // Has modport
-							wire->attributes["\\interface_type"] = seglist[0];
-							wire->attributes["\\interface_modport"] = seglist[1];
-						}
-						else { // Erroneous port type
-							log_error("More than two '.' in signal port type (%s)\n", name_type.c_str());
-						}
-					}
+					std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
+					wire->attributes["\\interface_type"] = res.first;
+					if (res.second != "")
+						wire->attributes["\\interface_modport"] = res.second;
 					break;
 				}
 			}
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 9c7dad3d3..0c782b8ab 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -255,12 +255,15 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 					RTLIL::IdString interface_name = interface_name_str;
 					bool not_found_interface = false;
 					if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
+						// Check if the interface instance is present in module:
+						// Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'.
+						// Check for both of them here
 						int nexactmatch = interfaces_in_module.count(interface_name) > 0;
 						std::string interface_name_str2 =  interface_name_str + "_inst_from_top_dummy";
 						RTLIL::IdString interface_name2 = interface_name_str2;
 						int nmatch2 = interfaces_in_module.count(interface_name2) > 0;
-						if (nexactmatch > 0 || nmatch2 > 0) { // Check if the interface instance is present in module
-							if (nexactmatch != 0)
+						if (nexactmatch > 0 || nmatch2 > 0) {
+							if (nexactmatch != 0) // Choose the one with the plain name if it exists
 								interface_name2 = interface_name;
 							RTLIL::Module *mod_replace_ports = interfaces_in_module.at(interface_name2);
 							for (auto &mod_wire : mod_replace_ports->wires_) { // Go over all wires in interface, and add replacements to lists.

From 23b69ca32b2ef93fc4b3f724099bfecdee0af869 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 20 Oct 2018 23:48:53 +0200
Subject: [PATCH 144/528] Improve read_verilog range out of bounds warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 8a6849faa..59c309665 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1083,8 +1083,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
 									 str.c_str());
 						else
-							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting all %d result bits to undef.\n",
-									str.c_str(), chunk.width);
+							log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
+									children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
 						chunk = RTLIL::SigChunk(RTLIL::State::Sx, chunk.width);
 					} else {
 						if (chunk.width + chunk.offset > source_width) {
@@ -1097,11 +1097,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 							chunk.offset += add_undef_bits_lsb;
 						}
 						if (add_undef_bits_lsb)
-							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
-									 str.c_str(), add_undef_bits_lsb);
+							log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
+									 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
 						if (add_undef_bits_msb)
-							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
-									 str.c_str(), add_undef_bits_msb);
+							log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
+									 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
 					}
 				}
 			}

From 0ad4321781a53210c42e3450b23f289bc0a35c99 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Sat, 20 Oct 2018 17:50:21 -0700
Subject: [PATCH 145/528] solves #675

---
 kernel/rtlil.h             |  4 ++++
 passes/equiv/equiv_make.cc | 28 +++++++++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 276540aa1..3323f13f0 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1304,6 +1304,10 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
 }
 
 inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
+	if(sig.size() != 1 || sig.chunks().size() != 1) {
+    std::cout << "rtp " << sig.size() << std::endl;
+    std::cout << "rtp " << sig.chunks().size() << std::endl;
+  }
 	log_assert(sig.size() == 1 && sig.chunks().size() == 1);
 	*this = SigBit(sig.chunks().front());
 }
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 66ee28aff..8489abe7c 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -290,22 +290,28 @@ struct EquivMakeWorker
 
 		init_bit2driven();
 
-	 	pool<Cell*> visited_cells;
+		pool<Cell*>	visited_cells;
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
 			if (!ct.cell_output(c->type, conn.first)) {
 				SigSpec old_sig = assign_map(conn.second);
 				SigSpec new_sig = rd_signal_map(old_sig);
-				
-				visited_cells.clear();
-				if (old_sig != new_sig) {
-					if (check_signal_in_fanout(visited_cells, old_sig, new_sig)) 
-						continue;
 
-					log("Changing input %s of cell %s (%s): %s -> %s\n",
-							log_id(conn.first), log_id(c), log_id(c->type),
-							log_signal(old_sig), log_signal(new_sig));
-					c->setPort(conn.first, new_sig);
+				if(old_sig != new_sig) {
+					for(auto & old_bit : old_sig.bits()) {
+						SigBit new_bit = new_sig.bits()[old_bit.offset];
+
+						visited_cells.clear();
+						if (old_bit != new_bit) {
+							if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
+								continue;
+
+							log("Changing input %s of cell %s (%s): %s -> %s\n",
+									log_id(conn.first), log_id(c), log_id(c->type),
+									log_signal(old_bit), log_signal(new_bit));
+							c->setPort(conn.first, new_bit);
+						}
+					}
 				}
 			}
 
@@ -412,7 +418,7 @@ struct EquivMakeWorker
 		}
 	}
 
-	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
+	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigSpec source_bit, SigSpec target_bit)
 	{
 		if (source_bit == target_bit)
 			return true;

From ce069830c5f53643ea9e5bd26c20d13034a164d1 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Sat, 20 Oct 2018 17:57:26 -0700
Subject: [PATCH 146/528] fixing code style

---
 passes/equiv/equiv_make.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 8489abe7c..b4905f7c3 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -298,7 +298,7 @@ struct EquivMakeWorker
 				SigSpec new_sig = rd_signal_map(old_sig);
 
 				if(old_sig != new_sig) {
-					for(auto & old_bit : old_sig.bits()) {
+					for (auto &old_bit : old_sig.bits()) {
 						SigBit new_bit = new_sig.bits()[old_bit.offset];
 
 						visited_cells.clear();

From 7b964bfb83696ac66f31e560d8c0c475da2b5c10 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Sat, 20 Oct 2018 18:02:59 -0700
Subject: [PATCH 147/528] cleaning up for PR

---
 kernel/rtlil.h             | 4 ----
 passes/equiv/equiv_make.cc | 4 ++--
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 3323f13f0..276540aa1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1304,10 +1304,6 @@ inline const RTLIL::SigBit &RTLIL::SigSpecConstIterator::operator*() const {
 }
 
 inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) {
-	if(sig.size() != 1 || sig.chunks().size() != 1) {
-    std::cout << "rtp " << sig.size() << std::endl;
-    std::cout << "rtp " << sig.chunks().size() << std::endl;
-  }
 	log_assert(sig.size() == 1 && sig.chunks().size() == 1);
 	*this = SigBit(sig.chunks().front());
 }
diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index b4905f7c3..cfb4d4438 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -290,7 +290,7 @@ struct EquivMakeWorker
 
 		init_bit2driven();
 
-		pool<Cell*>	visited_cells;
+		pool<Cell*> visited_cells;
 		for (auto c : cells_list)
 		for (auto &conn : c->connections())
 			if (!ct.cell_output(c->type, conn.first)) {
@@ -418,7 +418,7 @@ struct EquivMakeWorker
 		}
 	}
 
-	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigSpec source_bit, SigSpec target_bit)
+	bool check_signal_in_fanout(pool<Cell*> & visited_cells, SigBit source_bit, SigBit target_bit)
 	{
 		if (source_bit == target_bit)
 			return true;

From 101f5234ff17c0395672a93da6ee10294212ad90 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 21 Oct 2018 19:27:02 +0100
Subject: [PATCH 148/528] ecp5: Add DSP blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/Makefile.inc  |   1 +
 techlibs/ecp5/cells_bb.v    | 116 ++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc |   2 +-
 3 files changed, 118 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/ecp5/cells_bb.v

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 9b6f061bd..b23d5c70e 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/ecp5/synth_ecp5.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
+$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_bb.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/drams_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dram.txt))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/brams_map.v))
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
new file mode 100644
index 000000000..7ef02ef6a
--- /dev/null
+++ b/techlibs/ecp5/cells_bb.v
@@ -0,0 +1,116 @@
+// ECP5 Blackbox cells
+// FIXME: Create sim models
+
+(* blackbox *)
+module MULT18X18D(
+	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17,
+	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17,
+	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17,
+	input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB,
+	input CLK0, CLK1, CLK2, CLK3,
+	input CE0, CE1, CE2, CE3,
+	input RST0, RST1, RST2, RST3,
+	input SRIA0, SRIA1, SRIA2, SRIA3, SRIA4, SRIA5, SRIA6, SRIA7, SRIA8, SRIA9, SRIA10, SRIA11, SRIA12, SRIA13, SRIA14, SRIA15, SRIA16, SRIA17,
+	input SRIB0, SRIB1, SRIB2, SRIB3, SRIB4, SRIB5, SRIB6, SRIB7, SRIB8, SRIB9, SRIB10, SRIB11, SRIB12, SRIB13, SRIB14, SRIB15, SRIB16, SRIB17,
+	output SROA0, SROA1, SROA2, SROA3, SROA4, SROA5, SROA6, SROA7, SROA8, SROA9, SROA10, SROA11, SROA12, SROA13, SROA14, SROA15, SROA16, SROA17,
+	output SROB0, SROB1, SROB2, SROB3, SROB4, SROB5, SROB6, SROB7, SROB8, SROB9, SROB10, SROB11, SROB12, SROB13, SROB14, SROB15, SROB16, SROB17,
+	output ROA0, ROA1, ROA2, ROA3, ROA4, ROA5, ROA6, ROA7, ROA8, ROA9, ROA10, ROA11, ROA12, ROA13, ROA14, ROA15, ROA16, ROA17,
+	output ROB0, ROB1, ROB2, ROB3, ROB4, ROB5, ROB6, ROB7, ROB8, ROB9, ROB10, ROB11, ROB12, ROB13, ROB14, ROB15, ROB16, ROB17,
+	output ROC0, ROC1, ROC2, ROC3, ROC4, ROC5, ROC6, ROC7, ROC8, ROC9, ROC10, ROC11, ROC12, ROC13, ROC14, ROC15, ROC16, ROC17,
+	output P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35,
+	output SIGNEDP
+);
+	parameter REG_INPUTA_CLK = "NONE";
+	parameter REG_INPUTA_CE = "CE0";
+	parameter REG_INPUTA_RST = "RST0";
+	parameter REG_INPUTB_CLK = "NONE";
+	parameter REG_INPUTB_CE = "CE0";
+	parameter REG_INPUTB_RST = "RST0";
+	parameter REG_INPUTC_CLK = "NONE";
+	parameter REG_INPUTC_CE = "CE0";
+	parameter REG_INPUTC_RST = "RST0";
+	parameter REG_PIPELINE_CLK = "NONE";
+	parameter REG_PIPELINE_CE = "CE0";
+	parameter REG_PIPELINE_RST = "RST0";
+	parameter REG_OUTPUT_CLK = "NONE";
+	parameter REG_OUTPUT_CE = "CE0";
+	parameter REG_OUTPUT_RST = "RST0";
+	parameter [127:0] CLK0_DIV = "ENABLED";
+	parameter [127:0] CLK1_DIV = "ENABLED";
+	parameter [127:0] CLK2_DIV = "ENABLED";
+	parameter [127:0] CLK3_DIV = "ENABLED";
+	parameter HIGHSPEED_CLK = "NONE";
+	parameter [127:0] GSR = "ENABLED";
+	parameter CAS_MATCH_REG = "FALSE";
+	parameter [127:0] SOURCEB_MODE = "B_SHIFT";
+	parameter [127:0] MULT_BYPASS = "DISABLED";
+	parameter [127:0] RESETMODE = "SYNC";
+endmodule
+
+(* blackbox *)
+module ALU54B(
+	input CLK0, CLK1, CLK2, CLK3,
+	input CE0, CE1, CE2, CE3,
+	input RST0, RST1, RST2, RST3,
+	input SIGNEDIA, SIGNEDIB, SIGNEDCIN,
+	input A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19, A20, A21, A22, A23, A24, A25, A26, A27, A28, A29, A30, A31, A32, A33, A34, A35,
+	input B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, B23, B24, B25, B26, B27, B28, B29, B30, B31, B32, B33, B34, B35,
+	input C0, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C32, C33, C34, C35, C36, C37, C38, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C50, C51, C52, C53,
+	input CFB0, CFB1, CFB2, CFB3, CFB4, CFB5, CFB6, CFB7, CFB8, CFB9, CFB10, CFB11, CFB12, CFB13, CFB14, CFB15, CFB16, CFB17, CFB18, CFB19, CFB20, CFB21, CFB22, CFB23, CFB24, CFB25, CFB26, CFB27, CFB28, CFB29, CFB30, CFB31, CFB32, CFB33, CFB34, CFB35, CFB36, CFB37, CFB38, CFB39, CFB40, CFB41, CFB42, CFB43, CFB44, CFB45, CFB46, CFB47, CFB48, CFB49, CFB50, CFB51, CFB52, CFB53,
+	input MA0, MA1, MA2, MA3, MA4, MA5, MA6, MA7, MA8, MA9, MA10, MA11, MA12, MA13, MA14, MA15, MA16, MA17, MA18, MA19, MA20, MA21, MA22, MA23, MA24, MA25, MA26, MA27, MA28, MA29, MA30, MA31, MA32, MA33, MA34, MA35,
+	input MB0, MB1, MB2, MB3, MB4, MB5, MB6, MB7, MB8, MB9, MB10, MB11, MB12, MB13, MB14, MB15, MB16, MB17, MB18, MB19, MB20, MB21, MB22, MB23, MB24, MB25, MB26, MB27, MB28, MB29, MB30, MB31, MB32, MB33, MB34, MB35,
+	input CIN0, CIN1, CIN2, CIN3, CIN4, CIN5, CIN6, CIN7, CIN8, CIN9, CIN10, CIN11, CIN12, CIN13, CIN14, CIN15, CIN16, CIN17, CIN18, CIN19, CIN20, CIN21, CIN22, CIN23, CIN24, CIN25, CIN26, CIN27, CIN28, CIN29, CIN30, CIN31, CIN32, CIN33, CIN34, CIN35, CIN36, CIN37, CIN38, CIN39, CIN40, CIN41, CIN42, CIN43, CIN44, CIN45, CIN46, CIN47, CIN48, CIN49, CIN50, CIN51, CIN52, CIN53,
+	input OP0, OP1, OP2, OP3, OP4, OP5, OP6, OP7, OP8, OP9, OP10,
+	output R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53,
+	output CO0, CO1, CO2, CO3, CO4, CO5, CO6, CO7, CO8, CO9, CO10, CO11, CO12, CO13, CO14, CO15, CO16, CO17, CO18, CO19, CO20, CO21, CO22, CO23, CO24, CO25, CO26, CO27, CO28, CO29, CO30, CO31, CO32, CO33, CO34, CO35, CO36, CO37, CO38, CO39, CO40, CO41, CO42, CO43, CO44, CO45, CO46, CO47, CO48, CO49, CO50, CO51, CO52, CO53,
+	output EQZ, EQZM, EQOM, EQPAT, EQPATB,
+	output OVER, UNDER, OVERUNDER,
+	output SIGNEDR
+);
+	parameter REG_INPUTC0_CLK = "NONE";
+	parameter REG_INPUTC0_CE = "CE0";
+	parameter REG_INPUTC0_RST = "RST0";
+	parameter REG_INPUTC1_CLK = "NONE";
+	parameter REG_INPUTC1_CE = "CE0";
+	parameter REG_INPUTC1_RST = "RST0";
+	parameter REG_OPCODEOP0_0_CLK = "NONE";
+	parameter REG_OPCODEOP0_0_CE = "CE0";
+	parameter REG_OPCODEOP0_0_RST = "RST0";
+	parameter REG_OPCODEOP1_0_CLK = "NONE";
+	parameter REG_OPCODEOP0_1_CLK = "NONE";
+	parameter REG_OPCODEOP0_1_CE = "CE0";
+	parameter REG_OPCODEOP0_1_RST = "RST0";
+	parameter REG_OPCODEIN_0_CLK = "NONE";
+	parameter REG_OPCODEIN_0_CE = "CE0";
+	parameter REG_OPCODEIN_0_RST = "RST0";
+	parameter REG_OPCODEIN_1_CLK = "NONE";
+	parameter REG_OPCODEIN_1_CE = "CE0";
+	parameter REG_OPCODEIN_1_RST = "RST0";
+	parameter REG_OUTPUT0_CLK = "NONE";
+	parameter REG_OUTPUT0_CE = "CE0";
+	parameter REG_OUTPUT0_RST = "RST0";
+	parameter REG_OUTPUT1_CLK = "NONE";
+	parameter REG_OUTPUT1_CE = "CE0";
+	parameter REG_OUTPUT1_RST = "RST0";
+	parameter REG_FLAG_CLK = "NONE";
+	parameter REG_FLAG_CE = "CE0";
+	parameter REG_FLAG_RST = "RST0";
+	parameter [127:0] MCPAT_SOURCE = "STATIC";
+	parameter [127:0] MASKPAT_SOURCE = "STATIC";
+	parameter MASK01 = "0x00000000000000";
+	parameter REG_INPUTCFB_CLK = "NONE";
+	parameter REG_INPUTCFB_CE = "CE0";
+	parameter REG_INPUTCFB_RST = "RST0";
+	parameter [127:0] CLK0_DIV = "ENABLED";
+	parameter [127:0] CLK1_DIV = "ENABLED";
+	parameter [127:0] CLK2_DIV = "ENABLED";
+	parameter [127:0] CLK3_DIV = "ENABLED";
+	parameter MCPAT = "0x00000000000000";
+	parameter MASKPAT = "0x00000000000000";
+	parameter RNDPAT = "0x00000000000000";
+	parameter [127:0] GSR = "ENABLED";
+	parameter [127:0] RESETMODE = "SYNC";
+	parameter MULT9_MODE = "DISABLED";
+	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
+	parameter LEGACY = "DISABLED";
+endmodule
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index cb6a4c3d8..825e131c4 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -203,7 +203,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ecp5/cells_sim.v");
+			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 

From f8b97e21f3f76dd031f82586f8af104368f03e73 Mon Sep 17 00:00:00 2001
From: rafaeltp <rafaeltp@soe.ucsc.edu>
Date: Sun, 21 Oct 2018 11:32:44 -0700
Subject: [PATCH 149/528] using [i] to access individual bits of SigSpec and
 merging bits into a tmp Sig before setting the port to new signal

---
 passes/equiv/equiv_make.cc | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index cfb4d4438..dbd8682e6 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -298,20 +298,21 @@ struct EquivMakeWorker
 				SigSpec new_sig = rd_signal_map(old_sig);
 
 				if(old_sig != new_sig) {
-					for (auto &old_bit : old_sig.bits()) {
-						SigBit new_bit = new_sig.bits()[old_bit.offset];
+					SigSpec tmp_sig = old_sig;
+					for (int i = 0; i < GetSize(old_sig); i++) {
+						SigBit old_bit = old_sig[i], new_bit = new_sig[i];
 
 						visited_cells.clear();
-						if (old_bit != new_bit) {
-							if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
-								continue;
+						if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
+							continue;
 
-							log("Changing input %s of cell %s (%s): %s -> %s\n",
-									log_id(conn.first), log_id(c), log_id(c->type),
-									log_signal(old_bit), log_signal(new_bit));
-							c->setPort(conn.first, new_bit);
-						}
+						log("Changing input %s of cell %s (%s): %s -> %s\n",
+								log_id(conn.first), log_id(c), log_id(c->type),
+								log_signal(old_bit), log_signal(new_bit));
+
+						tmp_sig[i] = new_bit;
 					}
+					c->setPort(conn.first, tmp_sig);
 				}
 			}
 

From b65932edc4a00860cafc04f962f2a08dd782b075 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Mon, 22 Oct 2018 16:20:38 +0100
Subject: [PATCH 150/528] ecp5: Remove DSP parameters that don't work

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_bb.v | 21 ---------------------
 1 file changed, 21 deletions(-)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 7ef02ef6a..8644abecd 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -27,23 +27,16 @@ module MULT18X18D(
 	parameter REG_INPUTB_CE = "CE0";
 	parameter REG_INPUTB_RST = "RST0";
 	parameter REG_INPUTC_CLK = "NONE";
-	parameter REG_INPUTC_CE = "CE0";
-	parameter REG_INPUTC_RST = "RST0";
 	parameter REG_PIPELINE_CLK = "NONE";
 	parameter REG_PIPELINE_CE = "CE0";
 	parameter REG_PIPELINE_RST = "RST0";
 	parameter REG_OUTPUT_CLK = "NONE";
-	parameter REG_OUTPUT_CE = "CE0";
-	parameter REG_OUTPUT_RST = "RST0";
 	parameter [127:0] CLK0_DIV = "ENABLED";
 	parameter [127:0] CLK1_DIV = "ENABLED";
 	parameter [127:0] CLK2_DIV = "ENABLED";
 	parameter [127:0] CLK3_DIV = "ENABLED";
-	parameter HIGHSPEED_CLK = "NONE";
 	parameter [127:0] GSR = "ENABLED";
-	parameter CAS_MATCH_REG = "FALSE";
 	parameter [127:0] SOURCEB_MODE = "B_SHIFT";
-	parameter [127:0] MULT_BYPASS = "DISABLED";
 	parameter [127:0] RESETMODE = "SYNC";
 endmodule
 
@@ -68,11 +61,7 @@ module ALU54B(
 	output SIGNEDR
 );
 	parameter REG_INPUTC0_CLK = "NONE";
-	parameter REG_INPUTC0_CE = "CE0";
-	parameter REG_INPUTC0_RST = "RST0";
 	parameter REG_INPUTC1_CLK = "NONE";
-	parameter REG_INPUTC1_CE = "CE0";
-	parameter REG_INPUTC1_RST = "RST0";
 	parameter REG_OPCODEOP0_0_CLK = "NONE";
 	parameter REG_OPCODEOP0_0_CE = "CE0";
 	parameter REG_OPCODEOP0_0_RST = "RST0";
@@ -87,20 +76,11 @@ module ALU54B(
 	parameter REG_OPCODEIN_1_CE = "CE0";
 	parameter REG_OPCODEIN_1_RST = "RST0";
 	parameter REG_OUTPUT0_CLK = "NONE";
-	parameter REG_OUTPUT0_CE = "CE0";
-	parameter REG_OUTPUT0_RST = "RST0";
 	parameter REG_OUTPUT1_CLK = "NONE";
-	parameter REG_OUTPUT1_CE = "CE0";
-	parameter REG_OUTPUT1_RST = "RST0";
 	parameter REG_FLAG_CLK = "NONE";
-	parameter REG_FLAG_CE = "CE0";
-	parameter REG_FLAG_RST = "RST0";
 	parameter [127:0] MCPAT_SOURCE = "STATIC";
 	parameter [127:0] MASKPAT_SOURCE = "STATIC";
 	parameter MASK01 = "0x00000000000000";
-	parameter REG_INPUTCFB_CLK = "NONE";
-	parameter REG_INPUTCFB_CE = "CE0";
-	parameter REG_INPUTCFB_RST = "RST0";
 	parameter [127:0] CLK0_DIV = "ENABLED";
 	parameter [127:0] CLK1_DIV = "ENABLED";
 	parameter [127:0] CLK2_DIV = "ENABLED";
@@ -110,7 +90,6 @@ module ALU54B(
 	parameter RNDPAT = "0x00000000000000";
 	parameter [127:0] GSR = "ENABLED";
 	parameter [127:0] RESETMODE = "SYNC";
-	parameter MULT9_MODE = "DISABLED";
 	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
 	parameter LEGACY = "DISABLED";
 endmodule

From 9ed77f5ba853a316cf88221fa142e188f84765f0 Mon Sep 17 00:00:00 2001
From: whentze <muvlon@hentzes.de>
Date: Mon, 22 Oct 2018 19:40:22 +0200
Subject: [PATCH 151/528] fix unhandled std::out_of_range when calling yosys
 with 3-character argument

---
 kernel/yosys.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index ad032899c..21eeadaaf 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -821,7 +821,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen
 			command = "verilog";
 		else if (filename.size() > 2 && filename.substr(filename.size()-3) == ".sv")
 			command = "verilog -sv";
-		else if (filename.size() > 2 && filename.substr(filename.size()-4) == ".vhd")
+		else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".vhd")
 			command = "vhdl";
 		else if (filename.size() > 4 && filename.substr(filename.size()-5) == ".blif")
 			command = "blif";
@@ -833,7 +833,7 @@ void run_frontend(std::string filename, std::string command, std::string *backen
 			command = "ilang";
 		else if (filename.size() > 3 && filename.substr(filename.size()-3) == ".ys")
 			command = "script";
-		else if (filename.size() > 2 && filename.substr(filename.size()-4) == ".tcl")
+		else if (filename.size() > 3 && filename.substr(filename.size()-4) == ".tcl")
 			command = "tcl";
 		else if (filename == "-")
 			command = "script";

From 536ae16c3abcf3fef1dd14df8733bf51fa1bce1a Mon Sep 17 00:00:00 2001
From: Udi Finkelstein <github@udifink.com>
Date: Thu, 25 Oct 2018 02:37:56 +0300
Subject: [PATCH 152/528] Rename the generic "Syntax error" message from the
 Verilog/SystemVerilog parser into unique, meaningful info on the error. Also
 add 13 compilation examples that triggers each of these messages.

---
 frontends/verilog/verilog_parser.y | 28 ++++++++++++++--------------
 tests/errors/syntax_err01.v        |  4 ++++
 tests/errors/syntax_err02.v        |  7 +++++++
 tests/errors/syntax_err03.v        |  7 +++++++
 tests/errors/syntax_err04.v        |  4 ++++
 tests/errors/syntax_err05.v        |  4 ++++
 tests/errors/syntax_err06.v        |  6 ++++++
 tests/errors/syntax_err07.v        |  6 ++++++
 tests/errors/syntax_err08.v        |  6 ++++++
 tests/errors/syntax_err09.v        |  3 +++
 tests/errors/syntax_err10.v        |  3 +++
 tests/errors/syntax_err11.v        |  3 +++
 tests/errors/syntax_err12.v        |  7 +++++++
 tests/errors/syntax_err13.v        |  4 ++++
 14 files changed, 78 insertions(+), 14 deletions(-)
 create mode 100644 tests/errors/syntax_err01.v
 create mode 100644 tests/errors/syntax_err02.v
 create mode 100644 tests/errors/syntax_err03.v
 create mode 100644 tests/errors/syntax_err04.v
 create mode 100644 tests/errors/syntax_err05.v
 create mode 100644 tests/errors/syntax_err06.v
 create mode 100644 tests/errors/syntax_err07.v
 create mode 100644 tests/errors/syntax_err08.v
 create mode 100644 tests/errors/syntax_err09.v
 create mode 100644 tests/errors/syntax_err10.v
 create mode 100644 tests/errors/syntax_err11.v
 create mode 100644 tests/errors/syntax_err12.v
 create mode 100644 tests/errors/syntax_err13.v

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4dbe028a0..f8eee5d22 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -305,7 +305,7 @@ module_arg_opt_assignment:
 			else
 				ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
 		} else
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
 	} |
 	/* empty */;
 
@@ -672,7 +672,7 @@ task_func_port:
 		astbuf2 = $3;
 		if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
 			if (astbuf2) {
-				frontend_verilog_yyerror("Syntax error.");
+				frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions (task/function arguments)");
 			} else {
 				astbuf2 = new AstNode(AST_RANGE);
 				astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
@@ -680,7 +680,7 @@ task_func_port:
 			}
 		}
 		if (astbuf2 && astbuf2->children.size() != 2)
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("task/function argument range must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
 	} wire_name | wire_name;
 
 task_func_body:
@@ -883,7 +883,7 @@ param_signed:
 param_integer:
 	TOK_INTEGER {
 		if (astbuf1->children.size() != 1)
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("Internal error in param_integer - should not happen?");
 		astbuf1->children.push_back(new AstNode(AST_RANGE));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(31, true));
 		astbuf1->children.back()->children.push_back(AstNode::mkconst_int(0, true));
@@ -893,7 +893,7 @@ param_integer:
 param_real:
 	TOK_REAL {
 		if (astbuf1->children.size() != 1)
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("Parameter already declared as integer, cannot set to real.");
 		astbuf1->children.push_back(new AstNode(AST_REALVALUE));
 	} | /* empty */;
 
@@ -901,7 +901,7 @@ param_range:
 	range {
 		if ($1 != NULL) {
 			if (astbuf1->children.size() != 1)
-				frontend_verilog_yyerror("Syntax error.");
+				frontend_verilog_yyerror("integer/real parameters should not have a range.");
 			astbuf1->children.push_back($1);
 		}
 	};
@@ -930,7 +930,7 @@ single_param_decl:
 		AstNode *node;
 		if (astbuf1 == nullptr) {
 			if (!sv_mode)
-				frontend_verilog_yyerror("syntax error");
+				frontend_verilog_yyerror("In pure Verilog (not SystemVerilog), parameter/localparam with an initializer must use the parameter/localparam keyword");
 			node = new AstNode(AST_PARAMETER);
 			node->children.push_back(AstNode::mkconst_int(0, true));
 		} else {
@@ -966,7 +966,7 @@ wire_decl:
 		astbuf2 = $3;
 		if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) {
 			if (astbuf2) {
-				frontend_verilog_yyerror("Syntax error.");
+				frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions.");
 			} else {
 				astbuf2 = new AstNode(AST_RANGE);
 				astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true));
@@ -974,7 +974,7 @@ wire_decl:
 			}
 		}
 		if (astbuf2 && astbuf2->children.size() != 2)
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [<expr>:<expr>], [<expr>+:<expr>], or [<expr>-:<expr>]");
 	} wire_name_list {
 		delete astbuf1;
 		if (astbuf2 != NULL)
@@ -1068,7 +1068,7 @@ wire_name_and_opt_assign:
 wire_name:
 	TOK_ID range_or_multirange {
 		if (astbuf1 == nullptr)
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("Internal error - should not happen - no AST_WIRE node.");
 		AstNode *node = astbuf1->clone();
 		node->str = *$1;
 		append_attr_clone(node, albuf);
@@ -1076,7 +1076,7 @@ wire_name:
 			node->children.push_back(astbuf2->clone());
 		if ($2 != NULL) {
 			if (node->is_input || node->is_output)
-				frontend_verilog_yyerror("Syntax error.");
+				frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions.");
 			if (!astbuf2) {
 				AstNode *rng = new AstNode(AST_RANGE);
 				rng->children.push_back(AstNode::mkconst_int(0, true));
@@ -1478,7 +1478,7 @@ behavioral_stmt:
 			node->str = *$3;
 	} behavioral_stmt_list TOK_END opt_label {
 		if ($3 != NULL && $7 != NULL && *$3 != *$7)
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("Begin label (%s) and end label (%s) doesn't match.", $3->c_str()+1, $7->c_str()+1);
 		if ($3 != NULL)
 			delete $3;
 		if ($7 != NULL)
@@ -1794,7 +1794,7 @@ basic_expr:
 	} |
 	'(' expr ')' TOK_CONSTVAL {
 		if ($4->substr(0, 1) != "'")
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("Cast operation must be applied on sized constants e.g. (<expr>)<constval> , while %s is not a sized constant.", $4->c_str());
 		AstNode *bits = $2;
 		AstNode *val = const2ast(*$4, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
 		if (val == NULL)
@@ -1804,7 +1804,7 @@ basic_expr:
 	} |
 	hierarchical_id TOK_CONSTVAL {
 		if ($2->substr(0, 1) != "'")
-			frontend_verilog_yyerror("Syntax error.");
+			frontend_verilog_yyerror("Cast operation must be applied on sized constants, e.g. <ID>\'d0, while %s is not a sized constant.", $2->c_str());
 		AstNode *bits = new AstNode(AST_IDENTIFIER);
 		bits->str = *$1;
 		AstNode *val = const2ast(*$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back(), !lib_mode);
diff --git a/tests/errors/syntax_err01.v b/tests/errors/syntax_err01.v
new file mode 100644
index 000000000..68e9b1d50
--- /dev/null
+++ b/tests/errors/syntax_err01.v
@@ -0,0 +1,4 @@
+module a;
+integer [31:0]w;
+endmodule
+
diff --git a/tests/errors/syntax_err02.v b/tests/errors/syntax_err02.v
new file mode 100644
index 000000000..c72e976a8
--- /dev/null
+++ b/tests/errors/syntax_err02.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input integer [3:0]x
+);
+endtask
+endmodule
+
diff --git a/tests/errors/syntax_err03.v b/tests/errors/syntax_err03.v
new file mode 100644
index 000000000..6eec44ade
--- /dev/null
+++ b/tests/errors/syntax_err03.v
@@ -0,0 +1,7 @@
+module a;
+task to (
+  input [3]x
+);
+endtask
+endmodule
+
diff --git a/tests/errors/syntax_err04.v b/tests/errors/syntax_err04.v
new file mode 100644
index 000000000..d488e5dbb
--- /dev/null
+++ b/tests/errors/syntax_err04.v
@@ -0,0 +1,4 @@
+module a;
+wire [3]x;
+endmodule
+
diff --git a/tests/errors/syntax_err05.v b/tests/errors/syntax_err05.v
new file mode 100644
index 000000000..8a1f11532
--- /dev/null
+++ b/tests/errors/syntax_err05.v
@@ -0,0 +1,4 @@
+module a;
+input x[2:0];
+endmodule
+
diff --git a/tests/errors/syntax_err06.v b/tests/errors/syntax_err06.v
new file mode 100644
index 000000000..b35a1dea2
--- /dev/null
+++ b/tests/errors/syntax_err06.v
@@ -0,0 +1,6 @@
+module a;
+initial
+begin : label1
+end: label2
+endmodule
+
diff --git a/tests/errors/syntax_err07.v b/tests/errors/syntax_err07.v
new file mode 100644
index 000000000..62bcc6b3e
--- /dev/null
+++ b/tests/errors/syntax_err07.v
@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = (4)55;
+endmodule
+
diff --git a/tests/errors/syntax_err08.v b/tests/errors/syntax_err08.v
new file mode 100644
index 000000000..d41bfd6c9
--- /dev/null
+++ b/tests/errors/syntax_err08.v
@@ -0,0 +1,6 @@
+module a;
+wire [5:0]x;
+wire [3:0]y;
+assign y = x 55;
+endmodule
+
diff --git a/tests/errors/syntax_err09.v b/tests/errors/syntax_err09.v
new file mode 100644
index 000000000..1e472eb94
--- /dev/null
+++ b/tests/errors/syntax_err09.v
@@ -0,0 +1,3 @@
+module a(input wire x = 1'b0);
+endmodule
+
diff --git a/tests/errors/syntax_err10.v b/tests/errors/syntax_err10.v
new file mode 100644
index 000000000..d3280405c
--- /dev/null
+++ b/tests/errors/syntax_err10.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer [2:0]x=0;
+endmodule
diff --git a/tests/errors/syntax_err11.v b/tests/errors/syntax_err11.v
new file mode 100644
index 000000000..f3cde9dfc
--- /dev/null
+++ b/tests/errors/syntax_err11.v
@@ -0,0 +1,3 @@
+module a;
+parameter integer real x=0;
+endmodule
diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v
new file mode 100644
index 000000000..f9b5d5b0b
--- /dev/null
+++ b/tests/errors/syntax_err12.v
@@ -0,0 +1,7 @@
+interface iface;
+endinterface
+
+module a (
+  iface x = 1'b0
+);
+endmodule
diff --git a/tests/errors/syntax_err13.v b/tests/errors/syntax_err13.v
new file mode 100644
index 000000000..b5c942fca
--- /dev/null
+++ b/tests/errors/syntax_err13.v
@@ -0,0 +1,4 @@
+module a #(p = 0)
+();
+endmodule
+

From 5ab58d49308a670178a404e6e11bd8758f33c16d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 25 Oct 2018 13:20:00 +0200
Subject: [PATCH 153/528] Fix minor typo in error message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index f8eee5d22..1fe08903c 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1478,7 +1478,7 @@ behavioral_stmt:
 			node->str = *$3;
 	} behavioral_stmt_list TOK_END opt_label {
 		if ($3 != NULL && $7 != NULL && *$3 != *$7)
-			frontend_verilog_yyerror("Begin label (%s) and end label (%s) doesn't match.", $3->c_str()+1, $7->c_str()+1);
+			frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
 		if ($3 != NULL)
 			delete $3;
 		if ($7 != NULL)

From 6732e566321b828c83b563d24a10ac31c6d03e28 Mon Sep 17 00:00:00 2001
From: Jon Burgess <jburgess777@gmail.com>
Date: Sun, 28 Oct 2018 14:49:09 +0000
Subject: [PATCH 154/528] Avoid assert when label is an empty string

Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:

$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.

802             if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
---
 kernel/yosys.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 21eeadaaf..f002955ad 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -799,7 +799,7 @@ static void handle_label(std::string &command, bool &from_to_active, const std::
 	while (pos < GetSize(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n')
 		label += command[pos++];
 
-	if (label.back() == ':' && GetSize(label) > 1)
+	if (GetSize(label) > 1 && label.back() == ':')
 	{
 		label = label.substr(0, GetSize(label)-1);
 		command = command.substr(pos);

From cf79fd43761b6501f392ee6ad4ed0f961b93a56f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 31 Oct 2018 15:28:57 +0100
Subject: [PATCH 155/528] Basic SmartFusion2 and IGLOO2 synthesis support

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/sf2/Makefile.inc |   7 ++
 techlibs/sf2/arith_map.v  |  21 ++++
 techlibs/sf2/cells_map.v  |  68 +++++++++++++
 techlibs/sf2/cells_sim.v  |  75 ++++++++++++++
 techlibs/sf2/synth_sf2.cc | 206 ++++++++++++++++++++++++++++++++++++++
 5 files changed, 377 insertions(+)
 create mode 100644 techlibs/sf2/Makefile.inc
 create mode 100644 techlibs/sf2/arith_map.v
 create mode 100644 techlibs/sf2/cells_map.v
 create mode 100644 techlibs/sf2/cells_sim.v
 create mode 100644 techlibs/sf2/synth_sf2.cc

diff --git a/techlibs/sf2/Makefile.inc b/techlibs/sf2/Makefile.inc
new file mode 100644
index 000000000..cade49f37
--- /dev/null
+++ b/techlibs/sf2/Makefile.inc
@@ -0,0 +1,7 @@
+
+OBJS += techlibs/sf2/synth_sf2.o
+
+$(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v))
+$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v))
+$(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_sim.v))
+
diff --git a/techlibs/sf2/arith_map.v b/techlibs/sf2/arith_map.v
new file mode 100644
index 000000000..462d3ce50
--- /dev/null
+++ b/techlibs/sf2/arith_map.v
@@ -0,0 +1,21 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+
+// nothing here yet
diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v
new file mode 100644
index 000000000..7585323a8
--- /dev/null
+++ b/techlibs/sf2/cells_map.v
@@ -0,0 +1,68 @@
+// module  \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
+
+module  \$_DFF_P_ (input D, C, output Q);
+  SLE _TECHMAP_REPLACE_ (
+    .D(D),
+    .CLK(C),
+    .EN(1'b1),
+    .ALn(1'b1),
+    .ADn(1'b1),
+    .SLn(1'b1),
+    .SD(1'b0),
+    .LAT(1'b0),
+    .Q(Q)
+  );
+endmodule
+
+// module  \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
+// module  \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
+// 
+// module  \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
+// module  \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
+// 
+// module  \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
+// module  \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
+// module  \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
+// module  \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
+// 
+// module  \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
+// module  \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
+// module  \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
+// module  \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
+// 
+// module  \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+// module  \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+// module  \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
+// module  \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
+// 
+// module  \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+// module  \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+// module  \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
+// module  \$__DFFE_PP1 (input D, C, E, R, output Q); SB_DFFES  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]));
+    end else
+    if (WIDTH == 2) begin
+      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]));
+    end else
+    if (WIDTH == 3) begin
+      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]));
+    end else
+    if (WIDTH == 4) begin
+      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule
+`endif
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
new file mode 100644
index 000000000..89b8c55fd
--- /dev/null
+++ b/techlibs/sf2/cells_sim.v
@@ -0,0 +1,75 @@
+module SLE (
+	output Q,
+	input ADn,
+	input ALn,
+	input CLK,
+	input D,
+	input LAT,
+	input SD,
+	input EN,
+	input SLn
+);
+	reg q_latch, q_ff;
+
+	always @(posedge CLK, negedge ALn) begin
+		if (!ALn) begin
+			q_ff <= !ADn;
+		end else if (EN) begin
+			if (!SLn)
+				q_ff <= SD;
+			else
+				q_ff <= D;
+		end
+	end
+
+	always @* begin
+		if (!ALn) begin
+			q_latch <= !ADn;
+		end else if (CLK && EN) begin
+			if (!SLn)
+				q_ff <= SD;
+			else
+				q_ff <= D;
+		end
+	end
+
+	assign Q = LAT ? q_latch : q_ff;
+endmodule
+
+module CFG1 (
+	output O,
+	input A
+);
+	parameter [1:0] INIT = 2'h0;
+	assign O = INIT >> A;
+endmodule
+
+module CFG2 (
+	output O,
+	input A,
+	input B
+);
+	parameter [3:0] INIT = 4'h0;
+	assign O = INIT >> {B, A};
+endmodule
+
+module CFG3 (
+	output O,
+	input A,
+	input B,
+	input C
+);
+	parameter [7:0] INIT = 8'h0;
+	assign O = INIT >> {C, B, A};
+endmodule
+
+module CFG4 (
+	output O,
+	input A,
+	input B,
+	input C,
+	input D
+);
+	parameter [15:0] INIT = 16'h0;
+	assign O = INIT >> {D, C, B, A};
+endmodule
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
new file mode 100644
index 000000000..2676ea657
--- /dev/null
+++ b/techlibs/sf2/synth_sf2.cc
@@ -0,0 +1,206 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthSf2Pass : public ScriptPass
+{
+	SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { }
+
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_sf2 [options]\n");
+		log("\n");
+		log("This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        write the design to the specified EDIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, edif_file, json_file;
+	bool flatten, retime;
+
+	void clear_flags() YS_OVERRIDE
+	{
+		top_opt = "-auto-top";
+		edif_file = "";
+		json_file = "";
+		flatten = true;
+		retime = false;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+		log_header(design, "Executing SYNTH_SF2 pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() YS_OVERRIDE
+	{
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib +/sf2/cells_sim.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		{
+			run("proc");
+			run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+		}
+
+		if (check_label("coarse"))
+		{
+			run("synth -run coarse");
+		}
+
+		if (check_label("fine"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine");
+			run("techmap -map +/techmap.v -map +/sf2/arith_map.v");
+			if (retime || help_mode)
+				run("abc -dff", "(only if -retime)");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("dffsr2dff");
+			run("techmap -D NO_LUT -map +/sf2/cells_map.v");
+			run("opt_expr -mux_undef");
+			run("simplemap");
+			// run("sf2_ffinit");
+			// run("sf2_ffssr");
+			// run("sf2_opt -full");
+		}
+
+		if (check_label("map_luts"))
+		{
+			run("abc -lut 4");
+			run("clean");
+		}
+
+		if (check_label("map_cells"))
+		{
+			run("techmap -map +/sf2/cells_map.v");
+			run("clean");
+		}
+
+		if (check_label("check"))
+		{
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+		}
+
+		if (check_label("edif"))
+		{
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthSf2Pass;
+
+PRIVATE_NAMESPACE_END

From d084fb4c3f389b99c08909666d8e953017cb7656 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 31 Oct 2018 15:36:53 +0100
Subject: [PATCH 156/528] Fix sf2 LUT interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/sf2/cells_map.v |  8 ++++----
 techlibs/sf2/cells_sim.v | 16 ++++++++--------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v
index 7585323a8..5b8888294 100644
--- a/techlibs/sf2/cells_map.v
+++ b/techlibs/sf2/cells_map.v
@@ -50,16 +50,16 @@ module \$lut (A, Y);
 
   generate
     if (WIDTH == 1) begin
-      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]));
+      CFG1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]));
     end else
     if (WIDTH == 2) begin
-      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]));
+      CFG2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]));
     end else
     if (WIDTH == 3) begin
-      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]));
+      CFG3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]));
     end else
     if (WIDTH == 4) begin
-      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
+      CFG4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Y(Y), .A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
     end else begin
       wire _TECHMAP_FAIL_ = 1;
     end
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index 89b8c55fd..b03b2c750 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -37,39 +37,39 @@ module SLE (
 endmodule
 
 module CFG1 (
-	output O,
+	output Y,
 	input A
 );
 	parameter [1:0] INIT = 2'h0;
-	assign O = INIT >> A;
+	assign Y = INIT >> A;
 endmodule
 
 module CFG2 (
-	output O,
+	output Y,
 	input A,
 	input B
 );
 	parameter [3:0] INIT = 4'h0;
-	assign O = INIT >> {B, A};
+	assign Y = INIT >> {B, A};
 endmodule
 
 module CFG3 (
-	output O,
+	output Y,
 	input A,
 	input B,
 	input C
 );
 	parameter [7:0] INIT = 8'h0;
-	assign O = INIT >> {C, B, A};
+	assign Y = INIT >> {C, B, A};
 endmodule
 
 module CFG4 (
-	output O,
+	output Y,
 	input A,
 	input B,
 	input C,
 	input D
 );
 	parameter [15:0] INIT = 16'h0;
-	assign O = INIT >> {D, C, B, A};
+	assign Y = INIT >> {D, C, B, A};
 endmodule

From b6781c6f4ba20ba14d1649a993fc09691921de2b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 1 Nov 2018 11:40:58 +0100
Subject: [PATCH 157/528] Add support for signed $shift/$shiftx in smt2
 back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smt2.cc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index e2777ae04..418f8d766 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -554,7 +554,9 @@ struct Smt2Worker
 
 			if (cell->type.in("$shift", "$shiftx")) {
 				if (cell->getParam("\\B_SIGNED").as_bool()) {
-					/* FIXME */
+					return export_bvop(cell, stringf("(ite (bvsge B #b%0*d) "
+							"(bvlshr A B) (bvlshr A (bvneg B)))",
+							GetSize(cell->getPort("\\B")), 0), 's');
 				} else {
 					return export_bvop(cell, "(bvlshr A B)", 's');
 				}

From d86ea6badd1911064138c32fc8e65934f923f90e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 1 Nov 2018 15:25:24 +0100
Subject: [PATCH 158/528] Do not generate "reg assigned in a continuous
 assignment" warnings for "rand reg"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e56a62563..fcadd329a 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -450,8 +450,21 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				children[0]->id2ast->is_reg = true; // if logic type is used in a block asignment
 			if ((type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) && !children[0]->id2ast->is_reg)
 				log_warning("wire '%s' is assigned in a block at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
-			if (type == AST_ASSIGN && children[0]->id2ast->is_reg)
-				log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
+			if (type == AST_ASSIGN && children[0]->id2ast->is_reg) {
+				bool is_rand_reg = false;
+				if (children[1]->type == AST_FCALL) {
+					if (children[1]->str == "\\$anyconst")
+						is_rand_reg = true;
+					if (children[1]->str == "\\$anyseq")
+						is_rand_reg = true;
+					if (children[1]->str == "\\$allconst")
+						is_rand_reg = true;
+					if (children[1]->str == "\\$allseq")
+						is_rand_reg = true;
+				}
+				if (!is_rand_reg)
+					log_warning("reg '%s' is assigned in a continuous assignment at %s:%d.\n", children[0]->str.c_str(), filename.c_str(), linenum);
+			}
 			children[0]->was_checked = true;
 		}
 		break;

From d1e8249f9acd6e65e9804f5998906c6ce1915ec1 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstrumnets.com>
Date: Sat, 3 Nov 2018 18:07:51 +0100
Subject: [PATCH 159/528] Report an error when a liberty file contains pin
 references that reference non-existing pins

---
 passes/techmap/dfflibmap.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 416ed2bd5..421073485 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -100,6 +100,9 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name,
 	for (auto child : cell->children)
 		if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name)
 			return true;
+
+	log_error("Malformed liberty file - cannot find pin '%s' in cell '%s'.\n", pin_name.c_str(), cell->args[0].c_str());
+
 	return false;
 }
 

From 04cd17969657dc7402d79e054ea390f98e159083 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstrumnets.com>
Date: Sat, 3 Nov 2018 18:38:49 +0100
Subject: [PATCH 160/528] Liberty file newline handling is more relaxed. More
 descriptive error message

---
 passes/techmap/libparse.cc | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index d3b1ff02f..bb09117e2 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -159,7 +159,7 @@ int LibertyParser::lexer(std::string &str)
 
 	if (c == '\n') {
 		line++;
-		return ';';
+		return 'n';
 	}
 
 	// if (c >= 32 && c < 255)
@@ -175,7 +175,7 @@ LibertyAst *LibertyParser::parse()
 
 	int tok = lexer(str);
 
-	while (tok == ';')
+	while (tok == 'n')
 		tok = lexer(str);
 
 	if (tok == '}' || tok < 0)
@@ -194,6 +194,9 @@ LibertyAst *LibertyParser::parse()
 		if (tok == ';')
 			break;
 
+		if (tok == 'n')
+			continue;
+
 		if (tok == ':' && ast->value.empty()) {
 			tok = lexer(ast->value);
 			if (tok != 'v')
@@ -249,14 +252,14 @@ LibertyAst *LibertyParser::parse()
 
 void LibertyParser::error()
 {
-	log_error("Syntax error in line %d.\n", line);
+	log_error("Syntax error in liberty file on line %d.\n", line);
 }
 
 #else
 
 void LibertyParser::error()
 {
-	fprintf(stderr, "Syntax error in line %d.\n", line);
+	fprintf(stderr, "Syntax error in liberty file on line %d.\n", line);
 	exit(1);
 }
 

From 39f891aebce87b4a6124c2f7dc5b6b2d04ec2899 Mon Sep 17 00:00:00 2001
From: ZipCPU <dgisselq@ieee.org>
Date: Sat, 3 Nov 2018 13:39:32 -0400
Subject: [PATCH 161/528] Make  and  dependent upon LSB only

---
 frontends/ast/simplify.cc | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index fcadd329a..9688b77bc 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1874,10 +1874,16 @@ skip_dynamic_range_lvalue_expansion:;
 					newNode = new AstNode(AST_NE, past, present);
 
 				else if (str == "\\$rose")
-					newNode = new AstNode(AST_LOGIC_AND, new AstNode(AST_LOGIC_NOT, past), present);
+					newNode = new AstNode(AST_LOGIC_AND,
+						new AstNode(AST_LOGIC_NOT,
+							new AstNode(AST_BIT_AND, past, mkconst_int(1,false))),
+							new AstNode(AST_BIT_AND, present, mkconst_int(1,false)));
 
 				else if (str == "\\$fell")
-					newNode = new AstNode(AST_LOGIC_AND, past, new AstNode(AST_LOGIC_NOT, present));
+					newNode = new AstNode(AST_LOGIC_AND,
+						new AstNode(AST_BIT_AND, past, mkconst_int(1,false)),
+						new AstNode(AST_LOGIC_NOT,
+							new AstNode(AST_BIT_AND, present, mkconst_int(1,false))));
 
 				else
 					log_abort();

From 64e0582c292ca1f3a64c01d9a1faa96ef2f74588 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 4 Nov 2018 10:19:32 +0100
Subject: [PATCH 162/528] Various indenting fixes in AST front-end (mostly
 space vs tab issues)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/ast.cc      |  9 ++--
 frontends/ast/genrtlil.cc | 88 +++++++++++++++------------------------
 frontends/ast/simplify.cc | 71 +++++++++++++++----------------
 3 files changed, 69 insertions(+), 99 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index cc275959a..2c1561552 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -172,8 +172,7 @@ bool AstNode::get_bool_attribute(RTLIL::IdString id)
 
 	AstNode *attr = attributes.at(id);
 	if (attr->type != AST_CONSTANT)
-		log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n",
-			       id.c_str());
+		log_file_error(attr->filename, attr->linenum, "Attribute `%s' with non-constant value!\n", id.c_str());
 
 	return attr->integer != 0;
 }
@@ -969,8 +968,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 
 		for (auto &attr : ast->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
-					       attr.first.c_str());
+				log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 			current_module->attributes[attr.first] = attr.second->asAttrConst();
 		}
 		for (size_t i = 0; i < ast->children.size(); i++) {
@@ -1061,8 +1059,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 			if (design->has((*it)->str)) {
 				RTLIL::Module *existing_mod = design->module((*it)->str);
 				if (!nooverwrite && !overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
-					log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n",
-						       (*it)->str.c_str());
+					log_file_error((*it)->filename, (*it)->linenum, "Re-definition of module `%s'!\n", (*it)->str.c_str());
 				} else if (nooverwrite) {
 					log("Ignoring re-definition of module `%s' at %s:%d.\n",
 							(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 59c309665..9531dd356 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -55,8 +55,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 	if (gen_attributes)
 		for (auto &attr : that->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
-					       attr.first.c_str());
+				log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 			cell->attributes[attr.first] = attr.second->asAttrConst();
 		}
 
@@ -89,8 +88,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 	if (that != NULL)
 		for (auto &attr : that->attributes) {
 			if (attr.second->type != AST_CONSTANT)
-				log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
-					       attr.first.c_str());
+				log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 			cell->attributes[attr.first] = attr.second->asAttrConst();
 		}
 
@@ -117,8 +115,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
-			log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
-				       attr.first.c_str());
+			log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 		cell->attributes[attr.first] = attr.second->asAttrConst();
 	}
 
@@ -152,8 +149,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 
 	for (auto &attr : that->attributes) {
 		if (attr.second->type != AST_CONSTANT)
-			log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n",
-				       attr.first.c_str());
+			log_file_error(that->filename, that->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 		cell->attributes[attr.first] = attr.second->asAttrConst();
 	}
 
@@ -480,8 +476,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 				for (auto &attr : ast->attributes) {
 					if (attr.second->type != AST_CONSTANT)
-						log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n",
-							       attr.first.c_str());
+						log_file_error(ast->filename, ast->linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 					sw->attributes[attr.first] = attr.second->asAttrConst();
 				}
 
@@ -648,8 +643,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
-						       str.c_str());
+					log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
 				this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
 				delete left_at_zero_ast;
 				delete right_at_zero_ast;
@@ -778,7 +772,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
 				if (children[0]->type != AST_CONSTANT)
 					log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
-						       RTLIL::unescape_id(str).c_str());
+							RTLIL::unescape_id(str).c_str());
 				width_hint = max(width_hint, int(children[0]->asInt(true)));
 			}
 			break;
@@ -799,8 +793,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	default:
 		for (auto f : log_files)
 			current_ast->dumpAst(f, "verilog-ast> ");
-		log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n",
-			       type2str(type).c_str());
+		log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
 	}
 
 	if (*found_real)
@@ -892,11 +885,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// create an RTLIL::Wire for an AST_WIRE node
 	case AST_WIRE: {
 			if (current_module->wires_.count(str) != 0)
-				log_file_error(filename, linenum, "Re-definition of signal `%s'!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Re-definition of signal `%s'!\n", str.c_str());
 			if (!range_valid)
-				log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Signal `%s' with non-constant width!\n", str.c_str());
 
 			log_assert(range_left >= range_right || (range_left == -1 && range_right == 0));
 
@@ -910,8 +901,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
-						       attr.first.c_str());
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 				wire->attributes[attr.first] = attr.second->asAttrConst();
 			}
 		}
@@ -920,16 +910,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// create an RTLIL::Memory for an AST_MEMORY node
 	case AST_MEMORY: {
 			if (current_module->memories.count(str) != 0)
-				log_file_error(filename, linenum, "Re-definition of memory `%s'!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Re-definition of memory `%s'!\n", str.c_str());
 
 			log_assert(children.size() >= 2);
 			log_assert(children[0]->type == AST_RANGE);
 			log_assert(children[1]->type == AST_RANGE);
 
 			if (!children[0]->range_valid || !children[1]->range_valid)
-				log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Memory `%s' with non-constant width or size!\n", str.c_str());
 
 			RTLIL::Memory *memory = new RTLIL::Memory;
 			memory->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -946,8 +934,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
-						       attr.first.c_str());
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 				memory->attributes[attr.first] = attr.second->asAttrConst();
 			}
 		}
@@ -966,8 +953,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	case AST_REALVALUE:
 		{
 			RTLIL::SigSpec sig = realAsConst(width_hint);
-			log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
-					 realvalue, log_signal(sig));
+			log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
 			return sig;
 		}
 
@@ -994,8 +980,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			}
 			else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {
 				if (id2ast->children[0]->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n",
-						       str.c_str());
+					log_file_error(filename, linenum, "Parameter %s does not evaluate to constant value!\n", str.c_str());
 				chunk = RTLIL::Const(id2ast->children[0]->bits);
 				goto use_const_chunk;
 			}
@@ -1010,13 +995,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				is_interface = true;
 			}
 			else {
-				log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n",
-						str.c_str());
+				log_file_error(filename, linenum, "Identifier `%s' doesn't map to any signal!\n", str.c_str());
 			}
 
 			if (id2ast->type == AST_MEMORY)
-				log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Identifier `%s' does map to an unexpanded memory!\n", str.c_str());
 
 			// If identifier is an interface, create a RTLIL::SigSpec with a dummy wire with a attribute called 'is_interface'
 			// This makes it possible for the hierarchy pass to see what are interface connections and then replace them
@@ -1051,8 +1034,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					while (left_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 					while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 					if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-						log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
-							       str.c_str());
+						log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
 					int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
 					AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
 							children[0]->children[1]->clone() : children[0]->children[0]->clone());
@@ -1081,7 +1063,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					if (chunk.offset >= source_width || chunk.offset + chunk.width < 0) {
 						if (chunk.width == 1)
 							log_file_warning(filename, linenum, "Range select out of bounds on signal `%s': Setting result bit to undef.\n",
-									 str.c_str());
+									str.c_str());
 						else
 							log_file_warning(filename, linenum, "Range select [%d:%d] out of bounds on signal `%s': Setting all %d result bits to undef.\n",
 									children[0]->range_left, children[0]->range_right, str.c_str(), chunk.width);
@@ -1098,10 +1080,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						}
 						if (add_undef_bits_lsb)
 							log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d LSB bits to undef.\n",
-									 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
+									children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_lsb);
 						if (add_undef_bits_msb)
 							log_file_warning(filename, linenum, "Range [%d:%d] select out of bounds on signal `%s': Setting %d MSB bits to undef.\n",
-									 children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
+									children[0]->range_left, children[0]->range_right, str.c_str(), add_undef_bits_msb);
 					}
 				}
 			}
@@ -1436,8 +1418,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
-						       attr.first.c_str());
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 
@@ -1459,9 +1440,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 						new_right.append(right[i]);
 					}
 				log_file_warning(filename, linenum, "Ignoring assignment to constant bits:\n"
-						 "    old assignment: %s = %s\n    new assignment: %s = %s.\n",
-						 log_signal(left), log_signal(right),
-						 log_signal(new_left), log_signal(new_right));
+						"    old assignment: %s = %s\n    new assignment: %s = %s.\n",
+						log_signal(left), log_signal(right),
+						log_signal(new_left), log_signal(new_right));
 				left = new_left;
 				right = new_right;
 			}
@@ -1494,14 +1475,14 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					IdString paraname = child->str.empty() ? stringf("$%d", ++para_counter) : child->str;
 					if (child->children[0]->type == AST_REALVALUE) {
 						log_file_warning(filename, linenum, "Replacing floating point parameter %s.%s = %f with string.\n",
-								 log_id(cell), log_id(paraname), child->children[0]->realvalue);
+								log_id(cell), log_id(paraname), child->children[0]->realvalue);
 						auto strnode = AstNode::mkconst_str(stringf("%f", child->children[0]->realvalue));
 						strnode->cloneInto(child->children[0]);
 						delete strnode;
 					}
 					if (child->children[0]->type != AST_CONSTANT)
 						log_file_error(filename, linenum, "Parameter %s.%s with non-constant value!\n",
-							       log_id(cell), log_id(paraname));
+								log_id(cell), log_id(paraname));
 					cell->parameters[paraname] = child->children[0]->asParaConst();
 					continue;
 				}
@@ -1522,8 +1503,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			}
 			for (auto &attr : attributes) {
 				if (attr.second->type != AST_CONSTANT)
-					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n",
-						       attr.first.c_str());
+					log_file_error(filename, linenum, "Attribute `%s' with non-constant value!\n", attr.first.c_str());
 				cell->attributes[attr.first] = attr.second->asAttrConst();
 			}
 		}
@@ -1551,18 +1531,17 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 				if (GetSize(children) > 1)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 0.\n",
-						       RTLIL::unescape_id(str).c_str(), GetSize(children));
+							RTLIL::unescape_id(str).c_str(), GetSize(children));
 
 				if (GetSize(children) == 1) {
 					if (children[0]->type != AST_CONSTANT)
 						log_file_error(filename, linenum, "System function %s called with non-const argument!\n",
-							       RTLIL::unescape_id(str).c_str());
+								RTLIL::unescape_id(str).c_str());
 					width = children[0]->asInt(true);
 				}
 
 				if (width <= 0)
-					log_file_error(filename, linenum, "Failed to detect width of %s!\n",
-						       RTLIL::unescape_id(str).c_str());
+					log_file_error(filename, linenum, "Failed to detect width of %s!\n", RTLIL::unescape_id(str).c_str());
 
 				Cell *cell = current_module->addCell(myid, str.substr(1));
 				cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
@@ -1589,8 +1568,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		for (auto f : log_files)
 			current_ast->dumpAst(f, "verilog-ast> ");
 		type_name = type2str(type);
-		log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n",
-			       type_name.c_str());
+		log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
 	}
 
 	return RTLIL::SigSpec();
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 9688b77bc..bb4c9735d 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -196,7 +196,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		int nargs = GetSize(children);
 		if (nargs < 1)
 			log_file_error(filename, linenum, "System task `%s' got %d arguments, expected >= 1.\n",
-				       str.c_str(), int(children.size()));
+					str.c_str(), int(children.size()));
 
 		// First argument is the format string
 		AstNode *node_string = children[0];
@@ -240,7 +240,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 					case 'X':
 						if (next_arg >= GetSize(children))
 							log_file_error(filename, linenum, "Missing argument for %%%c format specifier in system task `%s'.\n",
-								       cformat, str.c_str());
+									cformat, str.c_str());
 
 						node_arg = children[next_arg++];
 						while (node_arg->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -745,7 +745,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 
 		if (current_scope.at(modname)->type != AST_CELL)
 			log_file_error(filename, linenum, "Defparam argument `%s . %s` does not match a cell!\n",
-				       RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str());
+					RTLIL::unescape_id(modname).c_str(), RTLIL::unescape_id(paramname).c_str());
 
 		AstNode *paraset = new AstNode(AST_PARASET, children[1]->clone(), GetSize(children) > 2 ? children[2]->clone() : NULL);
 		paraset->str = paramname;
@@ -893,7 +893,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			if (children[0]->type == AST_REALVALUE) {
 				RTLIL::Const constvalue = children[0]->realAsConst(width);
 				log_file_warning(filename, linenum, "converting real value %e to binary %s.\n",
-						 children[0]->realvalue, log_signal(constvalue));
+						children[0]->realvalue, log_signal(constvalue));
 				delete children[0];
 				children[0] = mkconst_bits(constvalue.bits, sign_hint);
 				did_something = true;
@@ -1312,8 +1312,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_PRIMITIVE)
 	{
 		if (children.size() < 2)
-			log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n",
-				       str.c_str());
+			log_file_error(filename, linenum, "Insufficient number of arguments for primitive `%s'!\n", str.c_str());
 
 		std::vector<AstNode*> children_list;
 		for (auto child : children) {
@@ -1328,8 +1327,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		if (str == "bufif0" || str == "bufif1" || str == "notif0" || str == "notif1")
 		{
 			if (children_list.size() != 3)
-				log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Invalid number of arguments for primitive `%s'!\n", str.c_str());
 
 			std::vector<RTLIL::State> z_const(1, RTLIL::State::Sz);
 
@@ -1416,8 +1414,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			while (left_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { }
 			while (right_at_zero_ast->simplify(true, true, false, stage, -1, false, false)) { }
 			if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
-				log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n",
-					       str.c_str());
+				log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
 			result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
 		}
 		did_something = true;
@@ -1788,11 +1785,11 @@ skip_dynamic_range_lvalue_expansion:;
 
 				if (GetSize(children) != 1 && GetSize(children) != 2)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n",
-						       RTLIL::unescape_id(str).c_str(), int(children.size()));
+							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				if (!current_always_clocked)
 					log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n",
-						       RTLIL::unescape_id(str).c_str());
+							RTLIL::unescape_id(str).c_str());
 
 				if (GetSize(children) == 2)
 				{
@@ -1857,11 +1854,11 @@ skip_dynamic_range_lvalue_expansion:;
 			{
 				if (GetSize(children) != 1)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
-						       RTLIL::unescape_id(str).c_str(), int(children.size()));
+							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				if (!current_always_clocked)
 					log_file_error(filename, linenum, "System function %s is only allowed in clocked blocks.\n",
-						       RTLIL::unescape_id(str).c_str());
+							RTLIL::unescape_id(str).c_str());
 
 				AstNode *present = children.at(0)->clone();
 				AstNode *past = clone();
@@ -1875,15 +1872,13 @@ skip_dynamic_range_lvalue_expansion:;
 
 				else if (str == "\\$rose")
 					newNode = new AstNode(AST_LOGIC_AND,
-						new AstNode(AST_LOGIC_NOT,
-							new AstNode(AST_BIT_AND, past, mkconst_int(1,false))),
+							new AstNode(AST_LOGIC_NOT, new AstNode(AST_BIT_AND, past, mkconst_int(1,false))),
 							new AstNode(AST_BIT_AND, present, mkconst_int(1,false)));
 
 				else if (str == "\\$fell")
 					newNode = new AstNode(AST_LOGIC_AND,
-						new AstNode(AST_BIT_AND, past, mkconst_int(1,false)),
-						new AstNode(AST_LOGIC_NOT,
-							new AstNode(AST_BIT_AND, present, mkconst_int(1,false))));
+							new AstNode(AST_BIT_AND, past, mkconst_int(1,false)),
+							new AstNode(AST_LOGIC_NOT, new AstNode(AST_BIT_AND, present, mkconst_int(1,false))));
 
 				else
 					log_abort();
@@ -1901,7 +1896,7 @@ skip_dynamic_range_lvalue_expansion:;
 			{
 				if (children.size() != 1)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
-						       RTLIL::unescape_id(str).c_str(), int(children.size()));
+							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				AstNode *buf = children[0]->clone();
 				while (buf->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -1926,11 +1921,11 @@ skip_dynamic_range_lvalue_expansion:;
 			{
 				if (str == "\\$bits" && children.size() != 1)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
-						       RTLIL::unescape_id(str).c_str(), int(children.size()));
+							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				if (str == "\\$size" && children.size() != 1 && children.size() != 2)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 1 or 2.\n",
-						       RTLIL::unescape_id(str).c_str(), int(children.size()));
+							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				int dim = 1;
 				if (str == "\\$size" && children.size() == 2) {
@@ -2004,18 +1999,18 @@ skip_dynamic_range_lvalue_expansion:;
 				if (func_with_two_arguments) {
 					if (children.size() != 2)
 						log_file_error(filename, linenum, "System function %s got %d arguments, expected 2.\n",
-							       RTLIL::unescape_id(str).c_str(), int(children.size()));
+								RTLIL::unescape_id(str).c_str(), int(children.size()));
 				} else {
 					if (children.size() != 1)
 						log_file_error(filename, linenum, "System function %s got %d arguments, expected 1.\n",
-							       RTLIL::unescape_id(str).c_str(), int(children.size()));
+								RTLIL::unescape_id(str).c_str(), int(children.size()));
 				}
 
 				if (children.size() >= 1) {
 					while (children[0]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (!children[0]->isConst())
 						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n",
-							       RTLIL::unescape_id(str).c_str());
+								RTLIL::unescape_id(str).c_str());
 					int child_width_hint = width_hint;
 					bool child_sign_hint = sign_hint;
 					children[0]->detectSignWidth(child_width_hint, child_sign_hint);
@@ -2026,7 +2021,7 @@ skip_dynamic_range_lvalue_expansion:;
 					while (children[1]->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
 					if (!children[1]->isConst())
 						log_file_error(filename, linenum, "Failed to evaluate system function `%s' with non-constant argument.\n",
-							       RTLIL::unescape_id(str).c_str());
+								RTLIL::unescape_id(str).c_str());
 					int child_width_hint = width_hint;
 					bool child_sign_hint = sign_hint;
 					children[1]->detectSignWidth(child_width_hint, child_sign_hint);
@@ -2114,7 +2109,7 @@ skip_dynamic_range_lvalue_expansion:;
 			{
 				if (GetSize(children) < 2 || GetSize(children) > 4)
 					log_file_error(filename, linenum, "System function %s got %d arguments, expected 2-4.\n",
-						       RTLIL::unescape_id(str).c_str(), int(children.size()));
+							RTLIL::unescape_id(str).c_str(), int(children.size()));
 
 				AstNode *node_filename = children[0]->clone();
 				while (node_filename->simplify(true, false, false, stage, width_hint, sign_hint, false)) { }
@@ -3278,12 +3273,12 @@ void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &varia
 		if (!children.empty()) {
 			if (children.size() != 1 || children.at(0)->type != AST_RANGE)
 				log_file_error(filename, linenum, "Memory access in constant function is not supported\n%s:%d: ...called from here.\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 			children.at(0)->replace_variables(variables, fcall);
 			while (simplify(true, false, false, 1, -1, false, true)) { }
 			if (!children.at(0)->range_valid)
 				log_file_error(filename, linenum, "Non-constant range\n%s:%d: ... called from here.\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 			offset = min(children.at(0)->range_left, children.at(0)->range_right);
 			width = min(std::abs(children.at(0)->range_left - children.at(0)->range_right) + 1, width);
 		}
@@ -3323,7 +3318,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 			while (child->simplify(true, false, false, 1, -1, false, true)) { }
 			if (!child->range_valid)
 				log_file_error(child->filename, child->linenum, "Can't determine size of variable %s\n%s:%d: ... called from here.\n",
-					       child->str.c_str(), fcall->filename.c_str(), fcall->linenum);
+						child->str.c_str(), fcall->filename.c_str(), fcall->linenum);
 			variables[child->str].val = RTLIL::Const(RTLIL::State::Sx, abs(child->range_left - child->range_right)+1);
 			variables[child->str].offset = min(child->range_left, child->range_right);
 			variables[child->str].is_signed = child->is_signed;
@@ -3367,15 +3362,15 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 
 			if (stmt->children.at(1)->type != AST_CONSTANT)
 				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here. X\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 
 			if (stmt->children.at(0)->type != AST_IDENTIFIER)
 				log_file_error(stmt->filename, stmt->linenum, "Unsupported composite left hand side in constant function\n%s:%d: ... called from here.\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 
 			if (!variables.count(stmt->children.at(0)->str))
 				log_file_error(stmt->filename, stmt->linenum, "Assignment to non-local variable in constant function\n%s:%d: ... called from here.\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 
 			if (stmt->children.at(0)->children.empty()) {
 				variables[stmt->children.at(0)->str].val = stmt->children.at(1)->bitsAsConst(variables[stmt->children.at(0)->str].val.bits.size());
@@ -3383,7 +3378,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 				AstNode *range = stmt->children.at(0)->children.at(0);
 				if (!range->range_valid)
 					log_file_error(range->filename, range->linenum, "Non-constant range\n%s:%d: ... called from here.\n",
-						       fcall->filename.c_str(), fcall->linenum);
+							fcall->filename.c_str(), fcall->linenum);
 				int offset = min(range->range_left, range->range_right);
 				int width = std::abs(range->range_left - range->range_right) + 1;
 				varinfo_t &v = variables[stmt->children.at(0)->str];
@@ -3415,7 +3410,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 
 			if (cond->type != AST_CONSTANT)
 				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 
 			if (cond->asBool()) {
 				block->children.insert(block->children.begin(), stmt->children.at(1)->clone());
@@ -3436,7 +3431,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 
 			if (num->type != AST_CONSTANT)
 				log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
-					       fcall->filename.c_str(), fcall->linenum);
+						fcall->filename.c_str(), fcall->linenum);
 
 			block->children.erase(block->children.begin());
 			for (int i = 0; i < num->bitsAsConst().as_int(); i++)
@@ -3474,7 +3469,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 
 					if (cond->type != AST_CONSTANT)
 						log_file_error(stmt->filename, stmt->linenum, "Non-constant expression in constant function\n%s:%d: ... called from here.\n",
-							       fcall->filename.c_str(), fcall->linenum);
+								fcall->filename.c_str(), fcall->linenum);
 
 					found_match = cond->asBool();
 					delete cond;
@@ -3504,7 +3499,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
 		}
 
 		log_file_error(stmt->filename, stmt->linenum, "Unsupported language construct in constant function\n%s:%d: ... called from here.\n",
-			       fcall->filename.c_str(), fcall->linenum);
+				fcall->filename.c_str(), fcall->linenum);
 		log_abort();
 	}
 

From d0acea4f2e6c98f09246584c2ac0903acc254093 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 4 Nov 2018 14:41:28 +0100
Subject: [PATCH 163/528] Add proper error message for when smtbmc "append"
 fails

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtbmc.py | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 6af2a5ac1..b944ee004 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -1259,7 +1259,11 @@ elif covermode:
                     smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i))
                     smt_assert_consequent(get_constr_expr(constr_assumes, i))
                 print_msg("Re-solving with appended steps..")
-                assert smt_check_sat() == "sat"
+                if smt_check_sat() == "unsat":
+                    print("%s Cannot appended steps without violating assumptions!" % smt.timestamp())
+                    found_failed_assert = True
+                    retstatus = False
+                    break
 
             reached_covers = smt.bv2bin(smt.get("(covers_%d s%d)" % (coveridx, step)))
             assert len(reached_covers) == len(cover_desc)
@@ -1377,7 +1381,11 @@ else:  # not tempind, covermode
                             smt_assert_antecedent("(|%s_h| s%d)" % (topmod, i))
                             smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i))
                             smt_assert_consequent(get_constr_expr(constr_assumes, i))
-                            assert smt_check_sat() == "sat"
+                    print_msg("Re-solving with appended steps..")
+                    if smt_check_sat() == "unsat":
+                        print("%s Cannot appended steps without violating assumptions!" % smt.timestamp())
+                        retstatus = False
+                        break
                     print_anyconsts(step)
                     for i in range(step, last_check_step+1):
                         print_failed_asserts(i)

From 36ea98385f30107369479d2e682c544863c4f1af Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 4 Nov 2018 15:57:17 +0100
Subject: [PATCH 164/528] Add warning for SV "restrict" without "property"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_parser.y | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 1fe08903c..5ab1b62df 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -125,7 +125,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label tok_prim_wrapper hierarchical_id
-%type <boolean> opt_signed unique_case_attr
+%type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
 
 // operator precedence from low to high
@@ -1320,7 +1320,12 @@ opt_label:
 	};
 
 opt_property:
-	TOK_PROPERTY | /* empty */;
+	TOK_PROPERTY {
+		$$ = true;
+	} |
+	/* empty */ {
+		$$ = false;
+	};
 
 opt_stmt_label:
 	TOK_ID ':' | /* empty */;
@@ -1399,12 +1404,16 @@ assert:
 			delete $5;
 		else
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
+		if (!$3)
+			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
 	} |
 	opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (norestrict_mode)
 			delete $6;
 		else
 			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
+		if (!$3)
+			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
 	};
 
 assert_property:

From 2b935421718c9a8d8f2183d9cb4a4973c078bcfa Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@fb.com>
Date: Sun, 4 Nov 2018 21:58:09 -0800
Subject: [PATCH 165/528] Use conservative stack size for SMT2 on MacOS

---
 backends/smt2/smtio.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 3fc823e3e..e8ed5e63b 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -32,10 +32,15 @@ from threading import Thread
 if os.name == "posix":
     smtio_reclimit = 64 * 1024
     smtio_stacksize = 128 * 1024 * 1024
+    smtio_stacklimit = resource.RLIM_INFINITY
+    if os.uname().sysname == "Darwin":
+        # MacOS has rather conservative stack limits
+        smtio_stacksize = 16 * 1024 * 1024
+        smtio_stacklimit = resource.getrlimit(resource.RLIMIT_STACK)[1]
     if sys.getrecursionlimit() < smtio_reclimit:
         sys.setrecursionlimit(smtio_reclimit)
     if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize:
-        resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, -1))
+        resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, smtio_stacklimit))
 
 
 # currently running solvers (so we can kill them)

From 719e29404a74db8f994c9c3dc0d6b6e8d7f114a7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 5 Nov 2018 12:33:21 +0100
Subject: [PATCH 166/528] Allow square brackets in liberty identifiers

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/liberty/liberty.cc | 3 ++-
 passes/techmap/libparse.cc   | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 66db43baf..4acfbf1cb 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -36,7 +36,8 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
 
 	int id_len = 0;
 	while (('a' <= expr[id_len] && expr[id_len] <= 'z') || ('A' <= expr[id_len] && expr[id_len] <= 'Z') ||
-			('0' <= expr[id_len] && expr[id_len] <= '9') || expr[id_len] == '.' || expr[id_len] == '_') id_len++;
+			('0' <= expr[id_len] && expr[id_len] <= '9') || expr[id_len] == '.' ||
+			expr[id_len] == '_' || expr[id_len] == '[' || expr[id_len] == ']') id_len++;
 
 	if (id_len == 0)
 		log_error("Expected identifier at `%s'.\n", expr);
diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index bb09117e2..3927a657b 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -90,11 +90,11 @@ int LibertyParser::lexer(std::string &str)
 		c = f.get();
 	} while (c == ' ' || c == '\t' || c == '\r');
 
-	if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') {
+	if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') {
 		str = c;
 		while (1) {
 			c = f.get();
-			if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.')
+			if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']')
 				str += c;
 			else
 				break;

From 79075d123f749ad39bf35f658f00a79a24efcf98 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 6 Nov 2018 10:05:23 +0100
Subject: [PATCH 167/528] Improve stack rlimit code in smtio.py

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtio.py | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index e8ed5e63b..e417b7758 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -31,16 +31,16 @@ from threading import Thread
 # does not run out of stack frames when parsing large expressions
 if os.name == "posix":
     smtio_reclimit = 64 * 1024
-    smtio_stacksize = 128 * 1024 * 1024
-    smtio_stacklimit = resource.RLIM_INFINITY
-    if os.uname().sysname == "Darwin":
-        # MacOS has rather conservative stack limits
-        smtio_stacksize = 16 * 1024 * 1024
-        smtio_stacklimit = resource.getrlimit(resource.RLIMIT_STACK)[1]
     if sys.getrecursionlimit() < smtio_reclimit:
         sys.setrecursionlimit(smtio_reclimit)
-    if resource.getrlimit(resource.RLIMIT_STACK)[0] < smtio_stacksize:
-        resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, smtio_stacklimit))
+
+    smtio_stacksize = 128 * 1024 * 1024
+    current_rlimit_stack = resource.getrlimit(resource.RLIMIT_STACK)
+    if current_rlimit_stack[0] != resource.RLIM_INFINITY:
+        if current_rlimit_stack[1] != resource.RLIM_INFINITY:
+            smtio_stacksize = min(smtio_stacksize, smtio_stacklimit)
+        if current_rlimit_stack[0] < smtio_stacksize:
+            resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, current_rlimit_stack[1]))
 
 
 # currently running solvers (so we can kill them)

From 4c50e3abb9b39fe088cc0a08c63fcadb8abdabb7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 6 Nov 2018 10:09:03 +0100
Subject: [PATCH 168/528] Fix for improved smtio.py rlimit code

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtio.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index e417b7758..108f6bcfe 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -38,7 +38,7 @@ if os.name == "posix":
     current_rlimit_stack = resource.getrlimit(resource.RLIMIT_STACK)
     if current_rlimit_stack[0] != resource.RLIM_INFINITY:
         if current_rlimit_stack[1] != resource.RLIM_INFINITY:
-            smtio_stacksize = min(smtio_stacksize, smtio_stacklimit)
+            smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1])
         if current_rlimit_stack[0] < smtio_stacksize:
             resource.setrlimit(resource.RLIMIT_STACK, (smtio_stacksize, current_rlimit_stack[1]))
 

From 60ecc5c70ceb0c089e2054514138e7b0388a7722 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 6 Nov 2018 11:10:27 +0100
Subject: [PATCH 169/528] Update ABC rev to 4d56acf

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 090c94648..fd708b7de 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 14d985a
+ABCREV = 4d56acf
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1

From f6c4485a3ac315fbed76f1a2e1f22df7afb36886 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 6 Nov 2018 11:11:05 +0100
Subject: [PATCH 170/528] Run solver in non-incremental mode whem smtio.py is
 configured for non-incremental solving

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtio.py | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index e8ed5e63b..4c3245984 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -163,19 +163,28 @@ class SmtIo:
             self.unroll = False
 
         if self.solver == "yices":
-            self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts
+            if self.noincr:
+                self.popen_vargs = ['yices-smt2'] + self.solver_opts
+            else:
+                self.popen_vargs = ['yices-smt2', '--incremental'] + self.solver_opts
 
         if self.solver == "z3":
             self.popen_vargs = ['z3', '-smt2', '-in'] + self.solver_opts
 
         if self.solver == "cvc4":
-            self.popen_vargs = ['cvc4', '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
+            if self.noincr:
+                self.popen_vargs = ['cvc4', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
+            else:
+                self.popen_vargs = ['cvc4', '--incremental', '--lang', 'smt2.6' if self.logic_dt else 'smt2'] + self.solver_opts
 
         if self.solver == "mathsat":
             self.popen_vargs = ['mathsat'] + self.solver_opts
 
         if self.solver == "boolector":
-            self.popen_vargs = ['boolector', '--smt2', '-i'] + self.solver_opts
+            if self.noincr:
+                self.popen_vargs = ['boolector', '--smt2'] + self.solver_opts
+            else:
+                self.popen_vargs = ['boolector', '--smt2', '-i'] + self.solver_opts
             self.unroll = True
 
         if self.solver == "abc":

From cfc9b9147c3d737781f197a825b019584c2695a5 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstrumnets.com>
Date: Tue, 6 Nov 2018 12:11:52 +0100
Subject: [PATCH 171/528] DFFLIBMAP: changed 'missing pin' error into a warning
 with additional reason/info.

---
 passes/techmap/dfflibmap.cc | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 421073485..b0528d473 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -101,7 +101,16 @@ static bool parse_pin(LibertyAst *cell, LibertyAst *attr, std::string &pin_name,
 		if (child->id == "pin" && child->args.size() == 1 && child->args[0] == pin_name)
 			return true;
 
-	log_error("Malformed liberty file - cannot find pin '%s' in cell '%s'.\n", pin_name.c_str(), cell->args[0].c_str());
+	/* If we end up here, the pin specified in the attribute does not exist, which is an error,
+	   or, the attribute contains an expression which we do not yet support.
+       For now, we'll simply produce a warning to let the user know something is up.
+	*/
+	if (pin_name.find_first_of("^*|&") == std::string::npos) {
+		log_warning("Malformed liberty file - cannot find pin '%s' in cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
+	}
+	else {
+		log_warning("Found unsupported expression '%s' in pin attribute of cell '%s' - skipping.\n", pin_name.c_str(), cell->args[0].c_str());
+	}
 
 	return false;
 }

From b54bf7c0f9720526dffce684ef1353b81f99547c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 7 Nov 2018 15:32:34 +0100
Subject: [PATCH 172/528] Limit stack size to 16 MB on Darwin

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtio.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 108f6bcfe..afbcf1fc4 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -34,9 +34,12 @@ if os.name == "posix":
     if sys.getrecursionlimit() < smtio_reclimit:
         sys.setrecursionlimit(smtio_reclimit)
 
-    smtio_stacksize = 128 * 1024 * 1024
     current_rlimit_stack = resource.getrlimit(resource.RLIMIT_STACK)
     if current_rlimit_stack[0] != resource.RLIM_INFINITY:
+        smtio_stacksize = 128 * 1024 * 1024
+        if os.uname().sysname == "Darwin":
+            # MacOS has rather conservative stack limits
+            smtio_stacksize = 16 * 1024 * 1024
         if current_rlimit_stack[1] != resource.RLIM_INFINITY:
             smtio_stacksize = min(smtio_stacksize, current_rlimit_stack[1])
         if current_rlimit_stack[0] < smtio_stacksize:

From 1f51332808b5dce76d74a64bd84e4e51c65f6998 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 7 Nov 2018 14:56:38 +0000
Subject: [PATCH 173/528] ecp5: Adding some blackbox cells

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v  | 390 ++++++++++++++++++++++++++++++++++++++
 techlibs/ecp5/cells_sim.v |   2 +-
 2 files changed, 391 insertions(+), 1 deletion(-)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 8644abecd..401b976d8 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -93,3 +93,393 @@ module ALU54B(
 	parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED";
 	parameter LEGACY = "DISABLED";
 endmodule
+
+(* blackbox *)
+module EHXPLLL (
+	input CLKI, CLKFB,
+	input PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG,
+	input STDBY, PLLWAKESYNC,
+	input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3,
+	output CLKOP, CLKOS, CLKOS2, CLKOS3,
+	output LOCK, INTLOCK,
+	output REFCLK, CLKINTFB
+);
+	parameter CLKI_DIV = 1;
+	parameter CLKFB_DIV = 1;
+	parameter CLKOP_DIV = 8;
+	parameter CLKOS_DIV = 8;
+	parameter CLKOS2_DIV = 8;
+	parameter CLKOS3_DIV = 8;
+	parameter CLKOP_ENABLE = "ENABLED";
+	parameter CLKOS_ENABLE = "DISABLED";
+	parameter CLKOS2_ENABLE = "DISABLED";
+	parameter CLKOS3_ENABLE = "DISABLED";
+	parameter CLKOP_CPHASE = 0;
+	parameter CLKOS_CPHASE = 0;
+	parameter CLKOS2_CPHASE = 0;
+	parameter CLKOS3_CPHASE = 0;
+	parameter CLKOP_FPHASE = 0;
+	parameter CLKOS_FPHASE = 0;
+	parameter CLKOS2_FPHASE = 0;
+	parameter CLKOS3_FPHASE = 0;
+	parameter FEEDBK_PATH = "CLKOP";
+	parameter CLKOP_TRIM_POL = "RISING";
+	parameter CLKOP_TRIM_DELAY = 0;
+	parameter CLKOS_TRIM_POL = "RISING";
+	parameter CLKOS_TRIM_DELAY = 0;
+	parameter OUTDIVIDER_MUXA = "DIVA";
+	parameter OUTDIVIDER_MUXB = "DIVB";
+	parameter OUTDIVIDER_MUXC = "DIVC";
+	parameter OUTDIVIDER_MUXD = "DIVD";
+	parameter PLL_LOCK_MODE = 0;
+	parameter PLL_LOCK_DELAY = 200;
+	parameter STDBY_ENABLE = "DISABLED";
+	parameter REFIN_RESET = "DISABLED";
+	parameter SYNC_ENABLE = "DISABLED";
+	parameter INT_LOCK_STICKY = "ENABLED";
+	parameter DPHASE_SOURCE = "DISABLED";
+	parameter PLLRST_ENA = "DISABLED";
+	parameter INTFB_WAKE = "DISABLED";
+endmodule
+
+(* blackbox *)
+module DTR(
+	input STARTPULSE,
+	output DTROUT7, DTROUT6, DTROUT5, DTROUT4, DTROUT3, DTROUT2, DTROUT1, DTROUT0
+);
+endmodule
+
+(* blackbox *)
+module OSCG(
+	output OSC
+);
+parameter DIV = 128;
+endmodule
+
+(* blackbox *)
+module IDDRX1F(
+	input D, SCLK, RST,
+	output Q0, Q1
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX1F(
+	input SCLK, RST, D0, D1,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module CLKDIVF(
+	input CLKI, RST, ALIGNWD,
+	output CDIVX
+);
+	parameter GSR = "DISABLED";
+	parameter DIV = "2.0";
+endmodule
+
+(* blackbox *)
+module DCCA(
+	input CLKI, CE,
+	output CLKO
+);
+endmodule
+
+(* blackbox *) (* keep *)
+module DCUA(
+	input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN,
+	input D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND,
+	input CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK,
+	input CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3,
+	input CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7,
+	input CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11,
+	input CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15,
+	input CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19,
+	input CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23,
+	input CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX,
+	input CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP,
+	input CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE,
+	input CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST,
+	input CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX,
+	input D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7,
+	input D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX,
+	input CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE,
+	input D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0,
+	input D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE,
+	input D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6,D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11,
+	output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND,
+	output CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK,
+	output CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1,
+	output CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5,
+	output CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9,
+	output CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13,
+	output CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17,
+	output CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21,
+	output CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON,
+	output CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN,
+	output CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED,
+	output CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3,
+	output D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7,
+	output D_COUT0, D_COUT1, D_COUT2, D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, D_COUT19,
+
+	input  D_REFCLKI,
+	output D_FFS_PLOL
+);
+	parameter CH0_AUTO_CALIB_EN = "0b0";
+	parameter CH0_AUTO_FACQ_EN = "0b0";
+	parameter CH0_BAND_THRESHOLD = "0b000000";
+	parameter CH0_CALIB_CK_MODE = "0b0";
+	parameter CH0_CC_MATCH_1 = "0b0000000000";
+	parameter CH0_CC_MATCH_2 = "0b0000000000";
+	parameter CH0_CC_MATCH_3 = "0b0000000000";
+	parameter CH0_CC_MATCH_4 = "0b0000000000";
+	parameter CH0_CDR_CNT4SEL = "0b00";
+	parameter CH0_CDR_CNT8SEL = "0b00";
+	parameter CH0_CTC_BYPASS = "0b0";
+	parameter CH0_DCOATDCFG = "0b00";
+	parameter CH0_DCOATDDLY = "0b00";
+	parameter CH0_DCOBYPSATD = "0b0";
+	parameter CH0_DCOCALDIV = "0b000";
+	parameter CH0_DCOCTLGI = "0b000";
+	parameter CH0_DCODISBDAVOID = "0b0";
+	parameter CH0_DCOFLTDAC = "0b00";
+	parameter CH0_DCOFTNRG = "0b000";
+	parameter CH0_DCOIOSTUNE = "0b000";
+	parameter CH0_DCOITUNE = "0b00";
+	parameter CH0_DCOITUNE4LSB = "0b000";
+	parameter CH0_DCOIUPDNX2 = "0b0";
+	parameter CH0_DCONUOFLSB = "0b000";
+	parameter CH0_DCOSCALEI = "0b00";
+	parameter CH0_DCOSTARTVAL = "0b000";
+	parameter CH0_DCOSTEP = "0b00";
+	parameter CH0_DEC_BYPASS = "0b0";
+	parameter CH0_ENABLE_CG_ALIGN = "0b0";
+	parameter CH0_ENC_BYPASS = "0b0";
+	parameter CH0_FF_RX_F_CLK_DIS = "0b0";
+	parameter CH0_FF_RX_H_CLK_EN = "0b0";
+	parameter CH0_FF_TX_F_CLK_DIS = "0b0";
+	parameter CH0_FF_TX_H_CLK_EN = "0b0";
+	parameter CH0_GE_AN_ENABLE = "0b0";
+	parameter CH0_INVERT_RX = "0b0";
+	parameter CH0_INVERT_TX = "0b0";
+	parameter CH0_LDR_CORE2TX_SEL = "0b0";
+	parameter CH0_LDR_RX2CORE_SEL = "0b0";
+	parameter CH0_LEQ_OFFSET_SEL = "0b0";
+	parameter CH0_LEQ_OFFSET_TRIM = "0b000";
+	parameter CH0_LSM_DISABLE = "0b0";
+	parameter CH0_MATCH_2_ENABLE = "0b0";
+	parameter CH0_MATCH_4_ENABLE = "0b0";
+	parameter CH0_MIN_IPG_CNT = "0b00";
+	parameter CH0_PCIE_EI_EN = "0b0";
+	parameter CH0_PCIE_MODE = "0b0";
+	parameter CH0_PCS_DET_TIME_SEL = "0b00";
+	parameter CH0_PDEN_SEL = "0b0";
+	parameter CH0_PRBS_ENABLE = "0b0";
+	parameter CH0_PRBS_LOCK = "0b0";
+	parameter CH0_PRBS_SELECTION = "0b0";
+	parameter CH0_RATE_MODE_RX = "0b0";
+	parameter CH0_RATE_MODE_TX = "0b0";
+	parameter CH0_RCV_DCC_EN = "0b0";
+	parameter CH0_REG_BAND_OFFSET = "0b0000";
+	parameter CH0_REG_BAND_SEL = "0b000000";
+	parameter CH0_REG_IDAC_EN = "0b0";
+	parameter CH0_REG_IDAC_SEL = "0b0000000000";
+	parameter CH0_REQ_EN = "0b0";
+	parameter CH0_REQ_LVL_SET = "0b00";
+	parameter CH0_RIO_MODE = "0b0";
+	parameter CH0_RLOS_SEL = "0b0";
+	parameter CH0_RPWDNB = "0b0";
+	parameter CH0_RTERM_RX = "0b00000";
+	parameter CH0_RTERM_TX = "0b00000";
+	parameter CH0_RXIN_CM = "0b00";
+	parameter CH0_RXTERM_CM = "0b00";
+	parameter CH0_RX_DCO_CK_DIV = "0b000";
+	parameter CH0_RX_DIV11_SEL = "0b0";
+	parameter CH0_RX_GEAR_BYPASS = "0b0";
+	parameter CH0_RX_GEAR_MODE = "0b0";
+	parameter CH0_RX_LOS_CEQ = "0b00";
+	parameter CH0_RX_LOS_EN = "0b0";
+	parameter CH0_RX_LOS_HYST_EN = "0b0";
+	parameter CH0_RX_LOS_LVL = "0b000";
+	parameter CH0_RX_RATE_SEL = "0b0000";
+	parameter CH0_RX_SB_BYPASS = "0b0";
+	parameter CH0_SB_BYPASS = "0b0";
+	parameter CH0_SEL_SD_RX_CLK = "0b0";
+	parameter CH0_TDRV_DAT_SEL = "0b00";
+	parameter CH0_TDRV_POST_EN = "0b0";
+	parameter CH0_TDRV_PRE_EN = "0b0";
+	parameter CH0_TDRV_SLICE0_CUR = "0b000";
+	parameter CH0_TDRV_SLICE0_SEL = "0b00";
+	parameter CH0_TDRV_SLICE1_CUR = "0b000";
+	parameter CH0_TDRV_SLICE1_SEL = "0b00";
+	parameter CH0_TDRV_SLICE2_CUR = "0b00";
+	parameter CH0_TDRV_SLICE2_SEL = "0b00";
+	parameter CH0_TDRV_SLICE3_CUR = "0b00";
+	parameter CH0_TDRV_SLICE3_SEL = "0b00";
+	parameter CH0_TDRV_SLICE4_CUR = "0b00";
+	parameter CH0_TDRV_SLICE4_SEL = "0b00";
+	parameter CH0_TDRV_SLICE5_CUR = "0b00";
+	parameter CH0_TDRV_SLICE5_SEL = "0b00";
+	parameter CH0_TPWDNB = "0b0";
+	parameter CH0_TX_CM_SEL = "0b00";
+	parameter CH0_TX_DIV11_SEL = "0b0";
+	parameter CH0_TX_GEAR_BYPASS = "0b0";
+	parameter CH0_TX_GEAR_MODE = "0b0";
+	parameter CH0_TX_POST_SIGN = "0b0";
+	parameter CH0_TX_PRE_SIGN = "0b0";
+	parameter CH0_UC_MODE = "0b0";
+	parameter CH0_UDF_COMMA_A = "0b0000000000";
+	parameter CH0_UDF_COMMA_B = "0b0000000000";
+	parameter CH0_UDF_COMMA_MASK = "0b0000000000";
+	parameter CH0_WA_BYPASS = "0b0";
+	parameter CH0_WA_MODE = "0b0";
+	parameter CH1_AUTO_CALIB_EN = "0b0";
+	parameter CH1_AUTO_FACQ_EN = "0b0";
+	parameter CH1_BAND_THRESHOLD = "0b000000";
+	parameter CH1_CALIB_CK_MODE = "0b0";
+	parameter CH1_CC_MATCH_1 = "0b0000000000";
+	parameter CH1_CC_MATCH_2 = "0b0000000000";
+	parameter CH1_CC_MATCH_3 = "0b0000000000";
+	parameter CH1_CC_MATCH_4 = "0b0000000000";
+	parameter CH1_CDR_CNT4SEL = "0b00";
+	parameter CH1_CDR_CNT8SEL = "0b00";
+	parameter CH1_CTC_BYPASS = "0b0";
+	parameter CH1_DCOATDCFG = "0b00";
+	parameter CH1_DCOATDDLY = "0b00";
+	parameter CH1_DCOBYPSATD = "0b0";
+	parameter CH1_DCOCALDIV = "0b000";
+	parameter CH1_DCOCTLGI = "0b000";
+	parameter CH1_DCODISBDAVOID = "0b0";
+	parameter CH1_DCOFLTDAC = "0b00";
+	parameter CH1_DCOFTNRG = "0b000";
+	parameter CH1_DCOIOSTUNE = "0b000";
+	parameter CH1_DCOITUNE = "0b00";
+	parameter CH1_DCOITUNE4LSB = "0b000";
+	parameter CH1_DCOIUPDNX2 = "0b0";
+	parameter CH1_DCONUOFLSB = "0b000";
+	parameter CH1_DCOSCALEI = "0b00";
+	parameter CH1_DCOSTARTVAL = "0b000";
+	parameter CH1_DCOSTEP = "0b00";
+	parameter CH1_DEC_BYPASS = "0b0";
+	parameter CH1_ENABLE_CG_ALIGN = "0b0";
+	parameter CH1_ENC_BYPASS = "0b0";
+	parameter CH1_FF_RX_F_CLK_DIS = "0b0";
+	parameter CH1_FF_RX_H_CLK_EN = "0b0";
+	parameter CH1_FF_TX_F_CLK_DIS = "0b0";
+	parameter CH1_FF_TX_H_CLK_EN = "0b0";
+	parameter CH1_GE_AN_ENABLE = "0b0";
+	parameter CH1_INVERT_RX = "0b0";
+	parameter CH1_INVERT_TX = "0b0";
+	parameter CH1_LDR_CORE2TX_SEL = "0b0";
+	parameter CH1_LDR_RX2CORE_SEL = "0b0";
+	parameter CH1_LEQ_OFFSET_SEL = "0b0";
+	parameter CH1_LEQ_OFFSET_TRIM = "0b000";
+	parameter CH1_LSM_DISABLE = "0b0";
+	parameter CH1_MATCH_2_ENABLE = "0b0";
+	parameter CH1_MATCH_4_ENABLE = "0b0";
+	parameter CH1_MIN_IPG_CNT = "0b00";
+	parameter CH1_PCIE_EI_EN = "0b0";
+	parameter CH1_PCIE_MODE = "0b0";
+	parameter CH1_PCS_DET_TIME_SEL = "0b00";
+	parameter CH1_PDEN_SEL = "0b0";
+	parameter CH1_PRBS_ENABLE = "0b0";
+	parameter CH1_PRBS_LOCK = "0b0";
+	parameter CH1_PRBS_SELECTION = "0b0";
+	parameter CH1_RATE_MODE_RX = "0b0";
+	parameter CH1_RATE_MODE_TX = "0b0";
+	parameter CH1_RCV_DCC_EN = "0b0";
+	parameter CH1_REG_BAND_OFFSET = "0b0000";
+	parameter CH1_REG_BAND_SEL = "0b000000";
+	parameter CH1_REG_IDAC_EN = "0b0";
+	parameter CH1_REG_IDAC_SEL = "0b0000000000";
+	parameter CH1_REQ_EN = "0b0";
+	parameter CH1_REQ_LVL_SET = "0b00";
+	parameter CH1_RIO_MODE = "0b0";
+	parameter CH1_RLOS_SEL = "0b0";
+	parameter CH1_RPWDNB = "0b0";
+	parameter CH1_RTERM_RX = "0b00000";
+	parameter CH1_RTERM_TX = "0b00000";
+	parameter CH1_RXIN_CM = "0b00";
+	parameter CH1_RXTERM_CM = "0b00";
+	parameter CH1_RX_DCO_CK_DIV = "0b000";
+	parameter CH1_RX_DIV11_SEL = "0b0";
+	parameter CH1_RX_GEAR_BYPASS = "0b0";
+	parameter CH1_RX_GEAR_MODE = "0b0";
+	parameter CH1_RX_LOS_CEQ = "0b00";
+	parameter CH1_RX_LOS_EN = "0b0";
+	parameter CH1_RX_LOS_HYST_EN = "0b0";
+	parameter CH1_RX_LOS_LVL = "0b000";
+	parameter CH1_RX_RATE_SEL = "0b0000";
+	parameter CH1_RX_SB_BYPASS = "0b0";
+	parameter CH1_SB_BYPASS = "0b0";
+	parameter CH1_SEL_SD_RX_CLK = "0b0";
+	parameter CH1_TDRV_DAT_SEL = "0b00";
+	parameter CH1_TDRV_POST_EN = "0b0";
+	parameter CH1_TDRV_PRE_EN = "0b0";
+	parameter CH1_TDRV_SLICE0_CUR = "0b000";
+	parameter CH1_TDRV_SLICE0_SEL = "0b00";
+	parameter CH1_TDRV_SLICE1_CUR = "0b000";
+	parameter CH1_TDRV_SLICE1_SEL = "0b00";
+	parameter CH1_TDRV_SLICE2_CUR = "0b00";
+	parameter CH1_TDRV_SLICE2_SEL = "0b00";
+	parameter CH1_TDRV_SLICE3_CUR = "0b00";
+	parameter CH1_TDRV_SLICE3_SEL = "0b00";
+	parameter CH1_TDRV_SLICE4_CUR = "0b00";
+	parameter CH1_TDRV_SLICE4_SEL = "0b00";
+	parameter CH1_TDRV_SLICE5_CUR = "0b00";
+	parameter CH1_TDRV_SLICE5_SEL = "0b00";
+	parameter CH1_TPWDNB = "0b0";
+	parameter CH1_TX_CM_SEL = "0b00";
+	parameter CH1_TX_DIV11_SEL = "0b0";
+	parameter CH1_TX_GEAR_BYPASS = "0b0";
+	parameter CH1_TX_GEAR_MODE = "0b0";
+	parameter CH1_TX_POST_SIGN = "0b0";
+	parameter CH1_TX_PRE_SIGN = "0b0";
+	parameter CH1_UC_MODE = "0b0";
+	parameter CH1_UDF_COMMA_A = "0b0000000000";
+	parameter CH1_UDF_COMMA_B = "0b0000000000";
+	parameter CH1_UDF_COMMA_MASK = "0b0000000000";
+	parameter CH1_WA_BYPASS = "0b0";
+	parameter CH1_WA_MODE = "0b0";
+	parameter D_BITCLK_FROM_ND_EN = "0b0";
+	parameter D_BITCLK_LOCAL_EN = "0b0";
+	parameter D_BITCLK_ND_EN = "0b0";
+	parameter D_BUS8BIT_SEL = "0b0";
+	parameter D_CDR_LOL_SET = "0b00";
+	parameter D_CMUSETBIASI = "0b00";
+	parameter D_CMUSETI4CPP = "0b0000";
+	parameter D_CMUSETI4CPZ = "0b0000";
+	parameter D_CMUSETI4VCO = "0b00";
+	parameter D_CMUSETICP4P = "0b00";
+	parameter D_CMUSETICP4Z = "0b000";
+	parameter D_CMUSETINITVCT = "0b00";
+	parameter D_CMUSETISCL4VCO = "0b000";
+	parameter D_CMUSETP1GM = "0b000";
+	parameter D_CMUSETP2AGM = "0b000";
+	parameter D_CMUSETZGM = "0b000";
+	parameter D_DCO_CALIB_TIME_SEL = "0b00";
+	parameter D_HIGH_MARK = "0b0000";
+	parameter D_IB_PWDNB = "0b0";
+	parameter D_ISETLOS = "0b00000000";
+	parameter D_LOW_MARK = "0b0000";
+	parameter D_MACROPDB = "0b0";
+	parameter D_PD_ISET = "0b00";
+	parameter D_PLL_LOL_SET = "0b00";
+	parameter D_REFCK_MODE = "0b000";
+	parameter D_REQ_ISET = "0b000";
+	parameter D_RG_EN = "0b0";
+	parameter D_RG_SET = "0b00";
+	parameter D_SETICONST_AUX = "0b00";
+	parameter D_SETICONST_CH = "0b00";
+	parameter D_SETIRPOLY_AUX = "0b00";
+	parameter D_SETIRPOLY_CH = "0b00";
+	parameter D_SETPLLRC = "0b000000";
+	parameter D_SYNC_LOCAL_EN = "0b0";
+	parameter D_SYNC_ND_EN = "0b0";
+	parameter D_TXPLL_PWDNB = "0b0";
+	parameter D_TX_VCO_CK_DIV = "0b000";
+	parameter D_XGE_MODE = "0b0";
+endmodule
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 6e4b0a5ac..507ab1beb 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -257,7 +257,7 @@ assign O = I;
 endmodule
 
 // ---------------------------------------
-
+(* keep *)
 module TRELLIS_IO(
 	inout B,
 	input I,

From 4e846694f76d48f77b44a109d8ed478c8071ebd6 Mon Sep 17 00:00:00 2001
From: Arjen Roodselaar <arjen@fb.com>
Date: Wed, 7 Nov 2018 23:18:47 -0800
Subject: [PATCH 174/528] Use appropriate static libraries when building with
 Verific on MacOS

---
 Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Makefile b/Makefile
index fd708b7de..cb9880754 100644
--- a/Makefile
+++ b/Makefile
@@ -359,8 +359,12 @@ ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
 VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
+ifeq ($(OS), Darwin)
+LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz
+else
 LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz
 endif
+endif
 
 ifeq ($(ENABLE_PROTOBUF),1)
 LDLIBS += $(shell pkg-config --cflags --libs protobuf)

From 05d2e5d773cff71b668d7bb96a509ece835ebf6a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 8 Nov 2018 09:58:47 +0100
Subject: [PATCH 175/528] Fix "make ystests" to use correct Yosys binary

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index fd708b7de..290a3a50b 100644
--- a/Makefile
+++ b/Makefile
@@ -595,7 +595,7 @@ vloghtb: $(TARGETS) $(EXTRA_TARGETS)
 ystests: $(TARGETS) $(EXTRA_TARGETS)
 	rm -rf tests/ystests
 	git clone https://github.com/YosysHQ/yosys-tests.git tests/ystests
-	+PATH="$$PWD:$$PATH" cd tests/ystests && $(MAKE)
+	+$(MAKE) PATH="$$PWD:$$PATH" -C tests/ystests
 	@echo ""
 	@echo "  Finished \"make ystests\"."
 	@echo ""

From 960c8794fa0da7c0ea8b6bf39bf309425fab17b3 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 9 Nov 2018 15:18:30 +0000
Subject: [PATCH 176/528] ecp5: Add blackboxes for ancillary DCU cells

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 401b976d8..2585c14a9 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -483,3 +483,21 @@ module DCUA(
 	parameter D_TX_VCO_CK_DIV = "0b000";
 	parameter D_XGE_MODE = "0b0";
 endmodule
+
+(* blackbox *)
+module EXTREFB (
+	input  REFCLKP, REFCLKN,
+	output REFCLKO
+);
+	parameter REFCK_PWDNB = "0b0";
+	parameter REFCK_RTERM = "0b0";
+	parameter REFCK_DCBIAS_EN = "0b0";
+endmodule
+
+(* blackbox *)
+module PCSCLKDIV (
+	input CLKI, RST, SEL2, SEL1, SEL0,
+	output CDIV1, CDIVX
+);
+	parameter GSR = "DISABLED";
+endmodule

From fae3e645a25550be1879b9320a82f1abc54a668e Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 9 Nov 2018 18:25:42 +0000
Subject: [PATCH 177/528] ecp5: Add 'fake' DCU parameters

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 2585c14a9..057f9d737 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -482,6 +482,17 @@ module DCUA(
 	parameter D_TXPLL_PWDNB = "0b0";
 	parameter D_TX_VCO_CK_DIV = "0b000";
 	parameter D_XGE_MODE = "0b0";
+
+// These parameters don't do anything but are
+// needed for compatability with Diamond
+	parameter D_TX_MAX_RATE = "2.5";
+	parameter D_RX_MAX_RATE = "2.5";
+	parameter CH0_TXAMPLITUDE = "0d1300";
+	parameter CH1_TXAMPLITUDE = "0d1300";
+	parameter CH0_PROTOCOL = "8B10B";
+	parameter CH1_PROTOCOL = "8B10B";
+	parameter CH0_CDR_MAX_RATE = "2.5";
+	parameter CH1_CDR_MAX_RATE = "2.5";
 endmodule
 
 (* blackbox *)

From 5387ccb041f4acafc96c7b3fcf8db04dddfb8ab5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 9 Nov 2018 21:03:13 +0100
Subject: [PATCH 178/528] Set Verific flag vhdl_support_variable_slice=1

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index dba3b0f0c..971f0b24a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1835,6 +1835,7 @@ struct VerificPass : public Pass {
 			Message::RegisterCallBackMsg(msg_func);
 			RuntimeFlags::SetVar("db_preserve_user_nets", 1);
 			RuntimeFlags::SetVar("db_allow_external_nets", 1);
+			RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
 			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);

From 99a14b0e37a383de39136807f9eb09e18fa859b9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sat, 10 Nov 2018 12:37:45 -0800
Subject: [PATCH 179/528] Add support for Xilinx PS7 block

---
 techlibs/xilinx/cells_xtra.sh |   1 +
 techlibs/xilinx/cells_xtra.v  | 623 ++++++++++++++++++++++++++++++++++
 2 files changed, 624 insertions(+)

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index e7c7d17bf..0480410f5 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -112,6 +112,7 @@ function xtract_cell_decl()
 	xtract_cell_decl PHY_CONTROL
 	xtract_cell_decl PLLE2_ADV
 	xtract_cell_decl PLLE2_BASE
+	xtract_cell_decl PS7
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
 	# xtract_cell_decl RAM128X1D
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 69e54233a..8d8b91ddc 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3057,6 +3057,629 @@ module PLLE2_BASE (...);
     input RST;
 endmodule
 
+module PS7 (...);
+    output DMA0DAVALID;
+    output DMA0DRREADY;
+    output DMA0RSTN;
+    output DMA1DAVALID;
+    output DMA1DRREADY;
+    output DMA1RSTN;
+    output DMA2DAVALID;
+    output DMA2DRREADY;
+    output DMA2RSTN;
+    output DMA3DAVALID;
+    output DMA3DRREADY;
+    output DMA3RSTN;
+    output EMIOCAN0PHYTX;
+    output EMIOCAN1PHYTX;
+    output EMIOENET0GMIITXEN;
+    output EMIOENET0GMIITXER;
+    output EMIOENET0MDIOMDC;
+    output EMIOENET0MDIOO;
+    output EMIOENET0MDIOTN;
+    output EMIOENET0PTPDELAYREQRX;
+    output EMIOENET0PTPDELAYREQTX;
+    output EMIOENET0PTPPDELAYREQRX;
+    output EMIOENET0PTPPDELAYREQTX;
+    output EMIOENET0PTPPDELAYRESPRX;
+    output EMIOENET0PTPPDELAYRESPTX;
+    output EMIOENET0PTPSYNCFRAMERX;
+    output EMIOENET0PTPSYNCFRAMETX;
+    output EMIOENET0SOFRX;
+    output EMIOENET0SOFTX;
+    output EMIOENET1GMIITXEN;
+    output EMIOENET1GMIITXER;
+    output EMIOENET1MDIOMDC;
+    output EMIOENET1MDIOO;
+    output EMIOENET1MDIOTN;
+    output EMIOENET1PTPDELAYREQRX;
+    output EMIOENET1PTPDELAYREQTX;
+    output EMIOENET1PTPPDELAYREQRX;
+    output EMIOENET1PTPPDELAYREQTX;
+    output EMIOENET1PTPPDELAYRESPRX;
+    output EMIOENET1PTPPDELAYRESPTX;
+    output EMIOENET1PTPSYNCFRAMERX;
+    output EMIOENET1PTPSYNCFRAMETX;
+    output EMIOENET1SOFRX;
+    output EMIOENET1SOFTX;
+    output EMIOI2C0SCLO;
+    output EMIOI2C0SCLTN;
+    output EMIOI2C0SDAO;
+    output EMIOI2C0SDATN;
+    output EMIOI2C1SCLO;
+    output EMIOI2C1SCLTN;
+    output EMIOI2C1SDAO;
+    output EMIOI2C1SDATN;
+    output EMIOPJTAGTDO;
+    output EMIOPJTAGTDTN;
+    output EMIOSDIO0BUSPOW;
+    output EMIOSDIO0CLK;
+    output EMIOSDIO0CMDO;
+    output EMIOSDIO0CMDTN;
+    output EMIOSDIO0LED;
+    output EMIOSDIO1BUSPOW;
+    output EMIOSDIO1CLK;
+    output EMIOSDIO1CMDO;
+    output EMIOSDIO1CMDTN;
+    output EMIOSDIO1LED;
+    output EMIOSPI0MO;
+    output EMIOSPI0MOTN;
+    output EMIOSPI0SCLKO;
+    output EMIOSPI0SCLKTN;
+    output EMIOSPI0SO;
+    output EMIOSPI0SSNTN;
+    output EMIOSPI0STN;
+    output EMIOSPI1MO;
+    output EMIOSPI1MOTN;
+    output EMIOSPI1SCLKO;
+    output EMIOSPI1SCLKTN;
+    output EMIOSPI1SO;
+    output EMIOSPI1SSNTN;
+    output EMIOSPI1STN;
+    output EMIOTRACECTL;
+    output EMIOUART0DTRN;
+    output EMIOUART0RTSN;
+    output EMIOUART0TX;
+    output EMIOUART1DTRN;
+    output EMIOUART1RTSN;
+    output EMIOUART1TX;
+    output EMIOUSB0VBUSPWRSELECT;
+    output EMIOUSB1VBUSPWRSELECT;
+    output EMIOWDTRSTO;
+    output EVENTEVENTO;
+    output MAXIGP0ARESETN;
+    output MAXIGP0ARVALID;
+    output MAXIGP0AWVALID;
+    output MAXIGP0BREADY;
+    output MAXIGP0RREADY;
+    output MAXIGP0WLAST;
+    output MAXIGP0WVALID;
+    output MAXIGP1ARESETN;
+    output MAXIGP1ARVALID;
+    output MAXIGP1AWVALID;
+    output MAXIGP1BREADY;
+    output MAXIGP1RREADY;
+    output MAXIGP1WLAST;
+    output MAXIGP1WVALID;
+    output SAXIACPARESETN;
+    output SAXIACPARREADY;
+    output SAXIACPAWREADY;
+    output SAXIACPBVALID;
+    output SAXIACPRLAST;
+    output SAXIACPRVALID;
+    output SAXIACPWREADY;
+    output SAXIGP0ARESETN;
+    output SAXIGP0ARREADY;
+    output SAXIGP0AWREADY;
+    output SAXIGP0BVALID;
+    output SAXIGP0RLAST;
+    output SAXIGP0RVALID;
+    output SAXIGP0WREADY;
+    output SAXIGP1ARESETN;
+    output SAXIGP1ARREADY;
+    output SAXIGP1AWREADY;
+    output SAXIGP1BVALID;
+    output SAXIGP1RLAST;
+    output SAXIGP1RVALID;
+    output SAXIGP1WREADY;
+    output SAXIHP0ARESETN;
+    output SAXIHP0ARREADY;
+    output SAXIHP0AWREADY;
+    output SAXIHP0BVALID;
+    output SAXIHP0RLAST;
+    output SAXIHP0RVALID;
+    output SAXIHP0WREADY;
+    output SAXIHP1ARESETN;
+    output SAXIHP1ARREADY;
+    output SAXIHP1AWREADY;
+    output SAXIHP1BVALID;
+    output SAXIHP1RLAST;
+    output SAXIHP1RVALID;
+    output SAXIHP1WREADY;
+    output SAXIHP2ARESETN;
+    output SAXIHP2ARREADY;
+    output SAXIHP2AWREADY;
+    output SAXIHP2BVALID;
+    output SAXIHP2RLAST;
+    output SAXIHP2RVALID;
+    output SAXIHP2WREADY;
+    output SAXIHP3ARESETN;
+    output SAXIHP3ARREADY;
+    output SAXIHP3AWREADY;
+    output SAXIHP3BVALID;
+    output SAXIHP3RLAST;
+    output SAXIHP3RVALID;
+    output SAXIHP3WREADY;
+    output [11:0] MAXIGP0ARID;
+    output [11:0] MAXIGP0AWID;
+    output [11:0] MAXIGP0WID;
+    output [11:0] MAXIGP1ARID;
+    output [11:0] MAXIGP1AWID;
+    output [11:0] MAXIGP1WID;
+    output [1:0] DMA0DATYPE;
+    output [1:0] DMA1DATYPE;
+    output [1:0] DMA2DATYPE;
+    output [1:0] DMA3DATYPE;
+    output [1:0] EMIOUSB0PORTINDCTL;
+    output [1:0] EMIOUSB1PORTINDCTL;
+    output [1:0] EVENTSTANDBYWFE;
+    output [1:0] EVENTSTANDBYWFI;
+    output [1:0] MAXIGP0ARBURST;
+    output [1:0] MAXIGP0ARLOCK;
+    output [1:0] MAXIGP0ARSIZE;
+    output [1:0] MAXIGP0AWBURST;
+    output [1:0] MAXIGP0AWLOCK;
+    output [1:0] MAXIGP0AWSIZE;
+    output [1:0] MAXIGP1ARBURST;
+    output [1:0] MAXIGP1ARLOCK;
+    output [1:0] MAXIGP1ARSIZE;
+    output [1:0] MAXIGP1AWBURST;
+    output [1:0] MAXIGP1AWLOCK;
+    output [1:0] MAXIGP1AWSIZE;
+    output [1:0] SAXIACPBRESP;
+    output [1:0] SAXIACPRRESP;
+    output [1:0] SAXIGP0BRESP;
+    output [1:0] SAXIGP0RRESP;
+    output [1:0] SAXIGP1BRESP;
+    output [1:0] SAXIGP1RRESP;
+    output [1:0] SAXIHP0BRESP;
+    output [1:0] SAXIHP0RRESP;
+    output [1:0] SAXIHP1BRESP;
+    output [1:0] SAXIHP1RRESP;
+    output [1:0] SAXIHP2BRESP;
+    output [1:0] SAXIHP2RRESP;
+    output [1:0] SAXIHP3BRESP;
+    output [1:0] SAXIHP3RRESP;
+    output [28:0] IRQP2F;
+    output [2:0] EMIOSDIO0BUSVOLT;
+    output [2:0] EMIOSDIO1BUSVOLT;
+    output [2:0] EMIOSPI0SSON;
+    output [2:0] EMIOSPI1SSON;
+    output [2:0] EMIOTTC0WAVEO;
+    output [2:0] EMIOTTC1WAVEO;
+    output [2:0] MAXIGP0ARPROT;
+    output [2:0] MAXIGP0AWPROT;
+    output [2:0] MAXIGP1ARPROT;
+    output [2:0] MAXIGP1AWPROT;
+    output [2:0] SAXIACPBID;
+    output [2:0] SAXIACPRID;
+    output [2:0] SAXIHP0RACOUNT;
+    output [2:0] SAXIHP1RACOUNT;
+    output [2:0] SAXIHP2RACOUNT;
+    output [2:0] SAXIHP3RACOUNT;
+    output [31:0] EMIOTRACEDATA;
+    output [31:0] FTMTP2FDEBUG;
+    output [31:0] MAXIGP0ARADDR;
+    output [31:0] MAXIGP0AWADDR;
+    output [31:0] MAXIGP0WDATA;
+    output [31:0] MAXIGP1ARADDR;
+    output [31:0] MAXIGP1AWADDR;
+    output [31:0] MAXIGP1WDATA;
+    output [31:0] SAXIGP0RDATA;
+    output [31:0] SAXIGP1RDATA;
+    output [3:0] EMIOSDIO0DATAO;
+    output [3:0] EMIOSDIO0DATATN;
+    output [3:0] EMIOSDIO1DATAO;
+    output [3:0] EMIOSDIO1DATATN;
+    output [3:0] FCLKCLK;
+    output [3:0] FCLKRESETN;
+    output [3:0] FTMTF2PTRIGACK;
+    output [3:0] FTMTP2FTRIG;
+    output [3:0] MAXIGP0ARCACHE;
+    output [3:0] MAXIGP0ARLEN;
+    output [3:0] MAXIGP0ARQOS;
+    output [3:0] MAXIGP0AWCACHE;
+    output [3:0] MAXIGP0AWLEN;
+    output [3:0] MAXIGP0AWQOS;
+    output [3:0] MAXIGP0WSTRB;
+    output [3:0] MAXIGP1ARCACHE;
+    output [3:0] MAXIGP1ARLEN;
+    output [3:0] MAXIGP1ARQOS;
+    output [3:0] MAXIGP1AWCACHE;
+    output [3:0] MAXIGP1AWLEN;
+    output [3:0] MAXIGP1AWQOS;
+    output [3:0] MAXIGP1WSTRB;
+    output [5:0] SAXIGP0BID;
+    output [5:0] SAXIGP0RID;
+    output [5:0] SAXIGP1BID;
+    output [5:0] SAXIGP1RID;
+    output [5:0] SAXIHP0BID;
+    output [5:0] SAXIHP0RID;
+    output [5:0] SAXIHP0WACOUNT;
+    output [5:0] SAXIHP1BID;
+    output [5:0] SAXIHP1RID;
+    output [5:0] SAXIHP1WACOUNT;
+    output [5:0] SAXIHP2BID;
+    output [5:0] SAXIHP2RID;
+    output [5:0] SAXIHP2WACOUNT;
+    output [5:0] SAXIHP3BID;
+    output [5:0] SAXIHP3RID;
+    output [5:0] SAXIHP3WACOUNT;
+    output [63:0] EMIOGPIOO;
+    output [63:0] EMIOGPIOTN;
+    output [63:0] SAXIACPRDATA;
+    output [63:0] SAXIHP0RDATA;
+    output [63:0] SAXIHP1RDATA;
+    output [63:0] SAXIHP2RDATA;
+    output [63:0] SAXIHP3RDATA;
+    output [7:0] EMIOENET0GMIITXD;
+    output [7:0] EMIOENET1GMIITXD;
+    output [7:0] SAXIHP0RCOUNT;
+    output [7:0] SAXIHP0WCOUNT;
+    output [7:0] SAXIHP1RCOUNT;
+    output [7:0] SAXIHP1WCOUNT;
+    output [7:0] SAXIHP2RCOUNT;
+    output [7:0] SAXIHP2WCOUNT;
+    output [7:0] SAXIHP3RCOUNT;
+    output [7:0] SAXIHP3WCOUNT;
+    inout DDRCASB;
+    inout DDRCKE;
+    inout DDRCKN;
+    inout DDRCKP;
+    inout DDRCSB;
+    inout DDRDRSTB;
+    inout DDRODT;
+    inout DDRRASB;
+    inout DDRVRN;
+    inout DDRVRP;
+    inout DDRWEB;
+    inout PSCLK;
+    inout PSPORB;
+    inout PSSRSTB;
+    inout [14:0] DDRA;
+    inout [2:0] DDRBA;
+    inout [31:0] DDRDQ;
+    inout [3:0] DDRDM;
+    inout [3:0] DDRDQSN;
+    inout [3:0] DDRDQSP;
+    inout [53:0] MIO;
+    input DMA0ACLK;
+    input DMA0DAREADY;
+    input DMA0DRLAST;
+    input DMA0DRVALID;
+    input DMA1ACLK;
+    input DMA1DAREADY;
+    input DMA1DRLAST;
+    input DMA1DRVALID;
+    input DMA2ACLK;
+    input DMA2DAREADY;
+    input DMA2DRLAST;
+    input DMA2DRVALID;
+    input DMA3ACLK;
+    input DMA3DAREADY;
+    input DMA3DRLAST;
+    input DMA3DRVALID;
+    input EMIOCAN0PHYRX;
+    input EMIOCAN1PHYRX;
+    input EMIOENET0EXTINTIN;
+    input EMIOENET0GMIICOL;
+    input EMIOENET0GMIICRS;
+    input EMIOENET0GMIIRXCLK;
+    input EMIOENET0GMIIRXDV;
+    input EMIOENET0GMIIRXER;
+    input EMIOENET0GMIITXCLK;
+    input EMIOENET0MDIOI;
+    input EMIOENET1EXTINTIN;
+    input EMIOENET1GMIICOL;
+    input EMIOENET1GMIICRS;
+    input EMIOENET1GMIIRXCLK;
+    input EMIOENET1GMIIRXDV;
+    input EMIOENET1GMIIRXER;
+    input EMIOENET1GMIITXCLK;
+    input EMIOENET1MDIOI;
+    input EMIOI2C0SCLI;
+    input EMIOI2C0SDAI;
+    input EMIOI2C1SCLI;
+    input EMIOI2C1SDAI;
+    input EMIOPJTAGTCK;
+    input EMIOPJTAGTDI;
+    input EMIOPJTAGTMS;
+    input EMIOSDIO0CDN;
+    input EMIOSDIO0CLKFB;
+    input EMIOSDIO0CMDI;
+    input EMIOSDIO0WP;
+    input EMIOSDIO1CDN;
+    input EMIOSDIO1CLKFB;
+    input EMIOSDIO1CMDI;
+    input EMIOSDIO1WP;
+    input EMIOSPI0MI;
+    input EMIOSPI0SCLKI;
+    input EMIOSPI0SI;
+    input EMIOSPI0SSIN;
+    input EMIOSPI1MI;
+    input EMIOSPI1SCLKI;
+    input EMIOSPI1SI;
+    input EMIOSPI1SSIN;
+    input EMIOSRAMINTIN;
+    input EMIOTRACECLK;
+    input EMIOUART0CTSN;
+    input EMIOUART0DCDN;
+    input EMIOUART0DSRN;
+    input EMIOUART0RIN;
+    input EMIOUART0RX;
+    input EMIOUART1CTSN;
+    input EMIOUART1DCDN;
+    input EMIOUART1DSRN;
+    input EMIOUART1RIN;
+    input EMIOUART1RX;
+    input EMIOUSB0VBUSPWRFAULT;
+    input EMIOUSB1VBUSPWRFAULT;
+    input EMIOWDTCLKI;
+    input EVENTEVENTI;
+    input FPGAIDLEN;
+    input FTMDTRACEINCLOCK;
+    input FTMDTRACEINVALID;
+    input MAXIGP0ACLK;
+    input MAXIGP0ARREADY;
+    input MAXIGP0AWREADY;
+    input MAXIGP0BVALID;
+    input MAXIGP0RLAST;
+    input MAXIGP0RVALID;
+    input MAXIGP0WREADY;
+    input MAXIGP1ACLK;
+    input MAXIGP1ARREADY;
+    input MAXIGP1AWREADY;
+    input MAXIGP1BVALID;
+    input MAXIGP1RLAST;
+    input MAXIGP1RVALID;
+    input MAXIGP1WREADY;
+    input SAXIACPACLK;
+    input SAXIACPARVALID;
+    input SAXIACPAWVALID;
+    input SAXIACPBREADY;
+    input SAXIACPRREADY;
+    input SAXIACPWLAST;
+    input SAXIACPWVALID;
+    input SAXIGP0ACLK;
+    input SAXIGP0ARVALID;
+    input SAXIGP0AWVALID;
+    input SAXIGP0BREADY;
+    input SAXIGP0RREADY;
+    input SAXIGP0WLAST;
+    input SAXIGP0WVALID;
+    input SAXIGP1ACLK;
+    input SAXIGP1ARVALID;
+    input SAXIGP1AWVALID;
+    input SAXIGP1BREADY;
+    input SAXIGP1RREADY;
+    input SAXIGP1WLAST;
+    input SAXIGP1WVALID;
+    input SAXIHP0ACLK;
+    input SAXIHP0ARVALID;
+    input SAXIHP0AWVALID;
+    input SAXIHP0BREADY;
+    input SAXIHP0RDISSUECAP1EN;
+    input SAXIHP0RREADY;
+    input SAXIHP0WLAST;
+    input SAXIHP0WRISSUECAP1EN;
+    input SAXIHP0WVALID;
+    input SAXIHP1ACLK;
+    input SAXIHP1ARVALID;
+    input SAXIHP1AWVALID;
+    input SAXIHP1BREADY;
+    input SAXIHP1RDISSUECAP1EN;
+    input SAXIHP1RREADY;
+    input SAXIHP1WLAST;
+    input SAXIHP1WRISSUECAP1EN;
+    input SAXIHP1WVALID;
+    input SAXIHP2ACLK;
+    input SAXIHP2ARVALID;
+    input SAXIHP2AWVALID;
+    input SAXIHP2BREADY;
+    input SAXIHP2RDISSUECAP1EN;
+    input SAXIHP2RREADY;
+    input SAXIHP2WLAST;
+    input SAXIHP2WRISSUECAP1EN;
+    input SAXIHP2WVALID;
+    input SAXIHP3ACLK;
+    input SAXIHP3ARVALID;
+    input SAXIHP3AWVALID;
+    input SAXIHP3BREADY;
+    input SAXIHP3RDISSUECAP1EN;
+    input SAXIHP3RREADY;
+    input SAXIHP3WLAST;
+    input SAXIHP3WRISSUECAP1EN;
+    input SAXIHP3WVALID;
+    input [11:0] MAXIGP0BID;
+    input [11:0] MAXIGP0RID;
+    input [11:0] MAXIGP1BID;
+    input [11:0] MAXIGP1RID;
+    input [19:0] IRQF2P;
+    input [1:0] DMA0DRTYPE;
+    input [1:0] DMA1DRTYPE;
+    input [1:0] DMA2DRTYPE;
+    input [1:0] DMA3DRTYPE;
+    input [1:0] MAXIGP0BRESP;
+    input [1:0] MAXIGP0RRESP;
+    input [1:0] MAXIGP1BRESP;
+    input [1:0] MAXIGP1RRESP;
+    input [1:0] SAXIACPARBURST;
+    input [1:0] SAXIACPARLOCK;
+    input [1:0] SAXIACPARSIZE;
+    input [1:0] SAXIACPAWBURST;
+    input [1:0] SAXIACPAWLOCK;
+    input [1:0] SAXIACPAWSIZE;
+    input [1:0] SAXIGP0ARBURST;
+    input [1:0] SAXIGP0ARLOCK;
+    input [1:0] SAXIGP0ARSIZE;
+    input [1:0] SAXIGP0AWBURST;
+    input [1:0] SAXIGP0AWLOCK;
+    input [1:0] SAXIGP0AWSIZE;
+    input [1:0] SAXIGP1ARBURST;
+    input [1:0] SAXIGP1ARLOCK;
+    input [1:0] SAXIGP1ARSIZE;
+    input [1:0] SAXIGP1AWBURST;
+    input [1:0] SAXIGP1AWLOCK;
+    input [1:0] SAXIGP1AWSIZE;
+    input [1:0] SAXIHP0ARBURST;
+    input [1:0] SAXIHP0ARLOCK;
+    input [1:0] SAXIHP0ARSIZE;
+    input [1:0] SAXIHP0AWBURST;
+    input [1:0] SAXIHP0AWLOCK;
+    input [1:0] SAXIHP0AWSIZE;
+    input [1:0] SAXIHP1ARBURST;
+    input [1:0] SAXIHP1ARLOCK;
+    input [1:0] SAXIHP1ARSIZE;
+    input [1:0] SAXIHP1AWBURST;
+    input [1:0] SAXIHP1AWLOCK;
+    input [1:0] SAXIHP1AWSIZE;
+    input [1:0] SAXIHP2ARBURST;
+    input [1:0] SAXIHP2ARLOCK;
+    input [1:0] SAXIHP2ARSIZE;
+    input [1:0] SAXIHP2AWBURST;
+    input [1:0] SAXIHP2AWLOCK;
+    input [1:0] SAXIHP2AWSIZE;
+    input [1:0] SAXIHP3ARBURST;
+    input [1:0] SAXIHP3ARLOCK;
+    input [1:0] SAXIHP3ARSIZE;
+    input [1:0] SAXIHP3AWBURST;
+    input [1:0] SAXIHP3AWLOCK;
+    input [1:0] SAXIHP3AWSIZE;
+    input [2:0] EMIOTTC0CLKI;
+    input [2:0] EMIOTTC1CLKI;
+    input [2:0] SAXIACPARID;
+    input [2:0] SAXIACPARPROT;
+    input [2:0] SAXIACPAWID;
+    input [2:0] SAXIACPAWPROT;
+    input [2:0] SAXIACPWID;
+    input [2:0] SAXIGP0ARPROT;
+    input [2:0] SAXIGP0AWPROT;
+    input [2:0] SAXIGP1ARPROT;
+    input [2:0] SAXIGP1AWPROT;
+    input [2:0] SAXIHP0ARPROT;
+    input [2:0] SAXIHP0AWPROT;
+    input [2:0] SAXIHP1ARPROT;
+    input [2:0] SAXIHP1AWPROT;
+    input [2:0] SAXIHP2ARPROT;
+    input [2:0] SAXIHP2AWPROT;
+    input [2:0] SAXIHP3ARPROT;
+    input [2:0] SAXIHP3AWPROT;
+    input [31:0] FTMDTRACEINDATA;
+    input [31:0] FTMTF2PDEBUG;
+    input [31:0] MAXIGP0RDATA;
+    input [31:0] MAXIGP1RDATA;
+    input [31:0] SAXIACPARADDR;
+    input [31:0] SAXIACPAWADDR;
+    input [31:0] SAXIGP0ARADDR;
+    input [31:0] SAXIGP0AWADDR;
+    input [31:0] SAXIGP0WDATA;
+    input [31:0] SAXIGP1ARADDR;
+    input [31:0] SAXIGP1AWADDR;
+    input [31:0] SAXIGP1WDATA;
+    input [31:0] SAXIHP0ARADDR;
+    input [31:0] SAXIHP0AWADDR;
+    input [31:0] SAXIHP1ARADDR;
+    input [31:0] SAXIHP1AWADDR;
+    input [31:0] SAXIHP2ARADDR;
+    input [31:0] SAXIHP2AWADDR;
+    input [31:0] SAXIHP3ARADDR;
+    input [31:0] SAXIHP3AWADDR;
+    input [3:0] DDRARB;
+    input [3:0] EMIOSDIO0DATAI;
+    input [3:0] EMIOSDIO1DATAI;
+    input [3:0] FCLKCLKTRIGN;
+    input [3:0] FTMDTRACEINATID;
+    input [3:0] FTMTF2PTRIG;
+    input [3:0] FTMTP2FTRIGACK;
+    input [3:0] SAXIACPARCACHE;
+    input [3:0] SAXIACPARLEN;
+    input [3:0] SAXIACPARQOS;
+    input [3:0] SAXIACPAWCACHE;
+    input [3:0] SAXIACPAWLEN;
+    input [3:0] SAXIACPAWQOS;
+    input [3:0] SAXIGP0ARCACHE;
+    input [3:0] SAXIGP0ARLEN;
+    input [3:0] SAXIGP0ARQOS;
+    input [3:0] SAXIGP0AWCACHE;
+    input [3:0] SAXIGP0AWLEN;
+    input [3:0] SAXIGP0AWQOS;
+    input [3:0] SAXIGP0WSTRB;
+    input [3:0] SAXIGP1ARCACHE;
+    input [3:0] SAXIGP1ARLEN;
+    input [3:0] SAXIGP1ARQOS;
+    input [3:0] SAXIGP1AWCACHE;
+    input [3:0] SAXIGP1AWLEN;
+    input [3:0] SAXIGP1AWQOS;
+    input [3:0] SAXIGP1WSTRB;
+    input [3:0] SAXIHP0ARCACHE;
+    input [3:0] SAXIHP0ARLEN;
+    input [3:0] SAXIHP0ARQOS;
+    input [3:0] SAXIHP0AWCACHE;
+    input [3:0] SAXIHP0AWLEN;
+    input [3:0] SAXIHP0AWQOS;
+    input [3:0] SAXIHP1ARCACHE;
+    input [3:0] SAXIHP1ARLEN;
+    input [3:0] SAXIHP1ARQOS;
+    input [3:0] SAXIHP1AWCACHE;
+    input [3:0] SAXIHP1AWLEN;
+    input [3:0] SAXIHP1AWQOS;
+    input [3:0] SAXIHP2ARCACHE;
+    input [3:0] SAXIHP2ARLEN;
+    input [3:0] SAXIHP2ARQOS;
+    input [3:0] SAXIHP2AWCACHE;
+    input [3:0] SAXIHP2AWLEN;
+    input [3:0] SAXIHP2AWQOS;
+    input [3:0] SAXIHP3ARCACHE;
+    input [3:0] SAXIHP3ARLEN;
+    input [3:0] SAXIHP3ARQOS;
+    input [3:0] SAXIHP3AWCACHE;
+    input [3:0] SAXIHP3AWLEN;
+    input [3:0] SAXIHP3AWQOS;
+    input [4:0] SAXIACPARUSER;
+    input [4:0] SAXIACPAWUSER;
+    input [5:0] SAXIGP0ARID;
+    input [5:0] SAXIGP0AWID;
+    input [5:0] SAXIGP0WID;
+    input [5:0] SAXIGP1ARID;
+    input [5:0] SAXIGP1AWID;
+    input [5:0] SAXIGP1WID;
+    input [5:0] SAXIHP0ARID;
+    input [5:0] SAXIHP0AWID;
+    input [5:0] SAXIHP0WID;
+    input [5:0] SAXIHP1ARID;
+    input [5:0] SAXIHP1AWID;
+    input [5:0] SAXIHP1WID;
+    input [5:0] SAXIHP2ARID;
+    input [5:0] SAXIHP2AWID;
+    input [5:0] SAXIHP2WID;
+    input [5:0] SAXIHP3ARID;
+    input [5:0] SAXIHP3AWID;
+    input [5:0] SAXIHP3WID;
+    input [63:0] EMIOGPIOI;
+    input [63:0] SAXIACPWDATA;
+    input [63:0] SAXIHP0WDATA;
+    input [63:0] SAXIHP1WDATA;
+    input [63:0] SAXIHP2WDATA;
+    input [63:0] SAXIHP3WDATA;
+    input [7:0] EMIOENET0GMIIRXD;
+    input [7:0] EMIOENET1GMIIRXD;
+    input [7:0] SAXIACPWSTRB;
+    input [7:0] SAXIHP0WSTRB;
+    input [7:0] SAXIHP1WSTRB;
+    input [7:0] SAXIHP2WSTRB;
+    input [7:0] SAXIHP3WSTRB;
+endmodule
+
 module PULLDOWN (...);
     output O;
 endmodule

From d1372873e8dfdb219b7c55eb7540cf063ae00971 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 11 Nov 2018 19:37:31 +0100
Subject: [PATCH 180/528] Update ABC to git rev 68da3cf

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 4b39e9c8b..e3a5f2de2 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 4d56acf
+ABCREV = 68da3cf
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1

From 82aaf6d9086176c746bb157f33fd085a2e03e461 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 12 Nov 2018 09:27:33 +0100
Subject: [PATCH 181/528] Add "write_aiger -I -O -B"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/aiger/aiger.cc | 38 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc
index c323691a3..dfe506c66 100644
--- a/backends/aiger/aiger.cc
+++ b/backends/aiger/aiger.cc
@@ -100,7 +100,7 @@ struct AigerWriter
 		return aig_map.at(bit);
 	}
 
-	AigerWriter(Module *module, bool zinit_mode) : module(module), zinit_mode(zinit_mode), sigmap(module)
+	AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
 	{
 		pool<SigBit> undriven_bits;
 		pool<SigBit> unused_bits;
@@ -293,6 +293,10 @@ struct AigerWriter
 			aig_map[bit] = 2*aig_m;
 		}
 
+		if (imode && input_bits.empty()) {
+			aig_m++, aig_i++;
+		}
+
 		if (zinit_mode)
 		{
 			for (auto it : ff_map) {
@@ -371,6 +375,11 @@ struct AigerWriter
 			aig_outputs.push_back(bit2aig(bit));
 		}
 
+		if (omode && output_bits.empty()) {
+			aig_o++;
+			aig_outputs.push_back(0);
+		}
+
 		for (auto it : asserts) {
 			aig_b++;
 			int bit_a = bit2aig(it.first);
@@ -378,6 +387,11 @@ struct AigerWriter
 			aig_outputs.push_back(mkgate(bit_a^1, bit_en));
 		}
 
+		if (bmode && asserts.empty()) {
+			aig_b++;
+			aig_outputs.push_back(0);
+		}
+
 		for (auto it : assumes) {
 			aig_c++;
 			int bit_a = bit2aig(it.first);
@@ -689,6 +703,11 @@ struct AigerBackend : public Backend {
 		log("    -vmap <filename>\n");
 		log("        like -map, but more verbose\n");
 		log("\n");
+		log("    -I, -O, -B\n");
+		log("        If the design contains no input/output/assert then create one\n");
+		log("        dummy input/output/bad_state pin to make the tools reading the\n");
+		log("        AIGER file happy.\n");
+		log("\n");
 	}
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -697,6 +716,9 @@ struct AigerBackend : public Backend {
 		bool miter_mode = false;
 		bool symbols_mode = false;
 		bool verbose_map = false;
+		bool imode = false;
+		bool omode = false;
+		bool bmode = false;
 		std::string map_filename;
 
 		log_header(design, "Executing AIGER backend.\n");
@@ -729,6 +751,18 @@ struct AigerBackend : public Backend {
 				verbose_map = true;
 				continue;
 			}
+			if (args[argidx] == "-I") {
+				imode = true;
+				continue;
+			}
+			if (args[argidx] == "-O") {
+				omode = true;
+				continue;
+			}
+			if (args[argidx] == "-B") {
+				bmode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);
@@ -738,7 +772,7 @@ struct AigerBackend : public Backend {
 		if (top_module == nullptr)
 			log_error("Can't find top module in current design!\n");
 
-		AigerWriter writer(top_module, zinit_mode);
+		AigerWriter writer(top_module, zinit_mode, imode, omode, bmode);
 		writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
 
 		if (!map_filename.empty()) {

From 9228f015a30be6363555d80c2f9342f9cc51177c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 13 Nov 2018 17:22:28 +0100
Subject: [PATCH 182/528] Update ABC to git rev 2ddc57d

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index e3a5f2de2..b33166059 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@ OBJS = kernel/version_$(GIT_REV).o
 # is just a symlink to your actual ABC working directory, as 'make mrproper'
 # will remove the 'abc' directory and you do not want to accidentally
 # delete your work on ABC..
-ABCREV = 68da3cf
+ABCREV = 2ddc57d
 ABCPULL = 1
 ABCURL ?= https://github.com/berkeley-abc/abc
 ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1

From c472467be912aad65a0e49364dd5a9a6402291b1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Dani=C3=ABl=20W=2E=20Crompton?= <daniel.crompton@gmail.com>
Date: Mon, 19 Nov 2018 21:46:18 +0100
Subject: [PATCH 183/528] Using awk rather than gawk

---
 Makefile | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Makefile b/Makefile
index b33166059..acabb3ee2 100644
--- a/Makefile
+++ b/Makefile
@@ -72,6 +72,7 @@ PKG_CONFIG ?= pkg-config
 SED ?= sed
 BISON ?= bison
 STRIP ?= strip
+AWK ?= awk
 
 ifeq ($(OS), Darwin)
 PLUGIN_LDFLAGS += -undefined dynamic_lookup
@@ -395,8 +396,8 @@ endef
 ifeq ($(PRETTY), 1)
 P_STATUS = 0
 P_OFFSET = 0
-P_UPDATE = $(eval P_STATUS=$(shell echo $(OBJS) yosys$(EXE) | gawk 'BEGIN { RS = " "; I = $(P_STATUS)+0; } $$1 == "$@" && NR > I { I = NR; } END { print I; }'))
-P_SHOW = [$(shell gawk "BEGIN { N=$(words $(OBJS) yosys$(EXE)); printf \"%3d\", $(P_OFFSET)+90*$(P_STATUS)/N; exit; }")%]
+P_UPDATE = $(eval P_STATUS=$(shell echo $(OBJS) yosys$(EXE) | $(AWK) 'BEGIN { RS = " "; I = $(P_STATUS)+0; } $$1 == "$@" && NR > I { I = NR; } END { print I; }'))
+P_SHOW = [$(shell $(AWK) "BEGIN { N=$(words $(OBJS) yosys$(EXE)); printf \"%3d\", $(P_OFFSET)+90*$(P_STATUS)/N; exit; }")%]
 P = @echo "$(if $(findstring $@,$(TARGETS) $(EXTRA_TARGETS)),$(eval P_OFFSET = 10))$(call P_UPDATE)$(call P_SHOW) Building $@";
 Q = @
 S = -s

From ab97eddee9b0ea0a772660731fe4c3270d2564e5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 20 Nov 2018 17:56:47 +0100
Subject: [PATCH 184/528] Add iteration limit to "opt_muxtree"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/opt_muxtree.cc | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index 87c7ce9b2..375697dc8 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -36,6 +36,7 @@ struct OptMuxtreeWorker
 	RTLIL::Module *module;
 	SigMap assign_map;
 	int removed_count;
+	int glob_abort_cnt = 100000;
 
 	struct bitinfo_t {
 		bool seen_non_mux;
@@ -293,6 +294,9 @@ struct OptMuxtreeWorker
 
 	void eval_mux_port(knowledge_t &knowledge, int mux_idx, int port_idx, bool do_replace_known, bool do_enable_ports, int abort_count)
 	{
+		if (glob_abort_cnt == 0)
+			return;
+
 		muxinfo_t &muxinfo = mux2info[mux_idx];
 
 		if (do_enable_ports)
@@ -315,7 +319,7 @@ struct OptMuxtreeWorker
 			knowledge.visited_muxes[m] = true;
 			parent_muxes.push_back(m);
 		}
-		for (int m : parent_muxes)
+		for (int m : parent_muxes) {
 			if (root_enable_muxes.at(m))
 				continue;
 			else if (root_muxes.at(m)) {
@@ -327,6 +331,9 @@ struct OptMuxtreeWorker
 					eval_mux(knowledge, m, false, do_enable_ports, abort_count - 1);
 			} else
 				eval_mux(knowledge, m, do_replace_known, do_enable_ports, abort_count);
+			if (glob_abort_cnt == 0)
+				return;
+		}
 		for (int m : parent_muxes)
 			knowledge.visited_muxes[m] = false;
 
@@ -390,6 +397,12 @@ struct OptMuxtreeWorker
 
 	void eval_mux(knowledge_t &knowledge, int mux_idx, bool do_replace_known, bool do_enable_ports, int abort_count)
 	{
+		if (glob_abort_cnt == 0) {
+			log("  Giving up (too many iterations)\n");
+			return;
+		}
+		glob_abort_cnt--;
+
 		muxinfo_t &muxinfo = mux2info[mux_idx];
 
 		// set input ports to constants if we find known active or inactive signals
@@ -433,6 +446,9 @@ struct OptMuxtreeWorker
 				if (knowledge.known_inactive.at(portinfo.ctrl_sig))
 					continue;
 			eval_mux_port(knowledge, mux_idx, port_idx, do_replace_known, do_enable_ports, abort_count);
+
+			if (glob_abort_cnt == 0)
+				return;
 		}
 	}
 

From 86ce43999eaed10c3b9d141bb2f66bf98ad45eb6 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Sat, 24 Nov 2018 18:49:23 +0100
Subject: [PATCH 185/528] Make return value of $clog2 signed

As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index bb4c9735d..55abe165f 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1913,7 +1913,7 @@ skip_dynamic_range_lvalue_expansion:;
 					if (arg_value.bits.at(i) == RTLIL::State::S1)
 						result = i + 1;
 
-				newNode = mkconst_int(result, false);
+				newNode = mkconst_int(result, true);
 				goto apply_newNode;
 			}
 

From 8d3ab626ea39ed109ab061d69684a66fc2322ff2 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Thu, 15 Nov 2018 02:48:44 +0100
Subject: [PATCH 186/528] dff2dffe: Add option for unmap to only remove DFFE
 with low CE signal use

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 passes/techmap/dff2dffe.cc | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 3291f5a4a..3f5b48c75 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -263,10 +263,14 @@ struct Dff2dffePass : public Pass {
 		log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n");
 		log("$_DFF_P_, $_DFF_N_ and $_MUX_.\n");
 		log("\n");
-		log("    -unmap\n");
+		log("    -unmap");
 		log("        operate in the opposite direction: replace $dffe cells with combinations\n");
 		log("        of $dff and $mux cells. the options below are ignore in unmap mode.\n");
 		log("\n");
+		log("    -unmap-mince N\n");
+		log("        Same as -unmap but only unmap $dffe where the clock enable port\n");
+		log("        signal is used by less $dffe than the specified number\n");
+		log("\n");
 		log("    -direct <internal_gate_type> <external_gate_type>\n");
 		log("        map directly to external gate type. <internal_gate_type> can\n");
 		log("        be any internal gate-level FF cell (except $_DFFE_??_). the\n");
@@ -289,6 +293,7 @@ struct Dff2dffePass : public Pass {
 		log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
 
 		bool unmap_mode = false;
+		int min_ce_use = -1;
 		dict<IdString, IdString> direct_dict;
 
 		size_t argidx;
@@ -297,6 +302,11 @@ struct Dff2dffePass : public Pass {
 				unmap_mode = true;
 				continue;
 			}
+			if (args[argidx] == "-unmap-mince" && argidx + 1 < args.size()) {
+				unmap_mode = true;
+				min_ce_use = std::stoi(args[++argidx]);
+				continue;
+			}
 			if (args[argidx] == "-direct" && argidx + 2 < args.size()) {
 				string direct_from = RTLIL::escape_id(args[++argidx]);
 				string direct_to = RTLIL::escape_id(args[++argidx]);
@@ -343,8 +353,21 @@ struct Dff2dffePass : public Pass {
 			if (!mod->has_processes_warn())
 			{
 				if (unmap_mode) {
+					SigMap sigmap(mod);
 					for (auto cell : mod->selected_cells()) {
 						if (cell->type == "$dffe") {
+							if (min_ce_use >= 0) {
+								int ce_use = 0;
+								for (auto cell_other : mod->selected_cells()) {
+									if (cell_other->type != cell->type)
+										continue;
+									if (sigmap(cell->getPort("\\EN")) == sigmap(cell_other->getPort("\\EN")))
+										ce_use++;
+								}
+								if (ce_use >= min_ce_use)
+									continue;
+							}
+
 							RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort("\\D")));
 							mod->addDff(NEW_ID, cell->getPort("\\CLK"), tmp, cell->getPort("\\Q"), cell->getParam("\\CLK_POLARITY").as_bool());
 							if (cell->getParam("\\EN_POLARITY").as_bool())
@@ -355,6 +378,18 @@ struct Dff2dffePass : public Pass {
 							continue;
 						}
 						if (cell->type.substr(0, 7) == "$_DFFE_") {
+							if (min_ce_use >= 0) {
+								int ce_use = 0;
+								for (auto cell_other : mod->selected_cells()) {
+									if (cell_other->type != cell->type)
+										continue;
+									if (sigmap(cell->getPort("\\E")) == sigmap(cell_other->getPort("\\E")))
+										ce_use++;
+								}
+								if (ce_use >= min_ce_use)
+									continue;
+							}
+
 							bool clk_pol = cell->type.substr(7, 1) == "P";
 							bool en_pol = cell->type.substr(8, 1) == "P";
 							RTLIL::SigSpec tmp = mod->addWire(NEW_ID);

From 3e5ab50a73ec05badee2a8808cc0953a34dc9ae2 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Thu, 15 Nov 2018 02:49:35 +0100
Subject: [PATCH 187/528] ice40: Add option to only use CE if it'd be use by
 more than X FFs

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/synth_ice40.cc | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index b0687e5e3..93965a55d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -69,6 +69,10 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -nodffe\n");
 		log("        do not use SB_DFFE* cells in output netlist\n");
 		log("\n");
+		log("    -dffe_min_ce_use <min_ce_use>\n");
+		log("        do not use SB_DFFE* cells if the resulting CE line would go to less\n");
+		log("        than min_ce_use SB_DFFE*in output netlist\n");
+		log("\n");
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
 		log("\n");
@@ -87,6 +91,7 @@ struct SynthIce40Pass : public ScriptPass
 
 	string top_opt, blif_file, edif_file, json_file;
 	bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
+	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -96,6 +101,7 @@ struct SynthIce40Pass : public ScriptPass
 		json_file = "";
 		nocarry = false;
 		nodffe = false;
+		min_ce_use = -1;
 		nobram = false;
 		flatten = true;
 		retime = false;
@@ -155,6 +161,10 @@ struct SynthIce40Pass : public ScriptPass
 				nodffe = true;
 				continue;
 			}
+			if (args[argidx] == "-dffe_min_ce_use" && argidx+1 < args.size()) {
+				min_ce_use = std::stoi(args[++argidx]);
+				continue;
+			}
 			if (args[argidx] == "-nobram") {
 				nobram = true;
 				continue;
@@ -228,6 +238,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("dffsr2dff");
 			if (!nodffe)
 				run("dff2dffe -direct-match $_DFF_*");
+			if (min_ce_use >= 0) {
+				run("opt_merge");
+				run(stringf("dff2dffe -unmap-mince %d", min_ce_use));
+			}
 			run("techmap -D NO_LUT -map +/ice40/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");

From e90195b737912f6cffcc1b8720c7d72e746d8854 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 29 Nov 2018 05:07:40 +0100
Subject: [PATCH 188/528] Improve ConstEval error handling for non-eval cell
 types

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/celltypes.h | 19 ++++++++++++-------
 kernel/consteval.h |  9 +++++++--
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 6041168bb..8b8a56111 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -257,7 +257,7 @@ struct CellTypes
 		return v;
 	}
 
-	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
+	static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
 	{
 		if (type == "$sshr" && !signed1)
 			type = "$shr";
@@ -329,10 +329,15 @@ struct CellTypes
 		if (type == "$_ORNOT_")
 			return const_or(arg1, eval_not(arg2), false, false, 1);
 
+		if (errp != nullptr) {
+			*errp = true;
+			return State::Sm;
+		}
+
 		log_abort();
 	}
 
-	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
+	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
 	{
 		if (cell->type == "$slice") {
 			RTLIL::Const ret;
@@ -415,10 +420,10 @@ struct CellTypes
 		bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
 		bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
 		int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
-		return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
+		return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
 	}
 
-	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3)
+	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
 	{
 		if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
 			RTLIL::Const ret = arg1;
@@ -436,10 +441,10 @@ struct CellTypes
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
 
 		log_assert(arg3.bits.size() == 0);
-		return eval(cell, arg1, arg2);
+		return eval(cell, arg1, arg2, errp);
 	}
 
-	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4)
+	static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
 	{
 		if (cell->type == "$_AOI4_")
 			return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
@@ -447,7 +452,7 @@ struct CellTypes
 			return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
 
 		log_assert(arg4.bits.size() == 0);
-		return eval(cell, arg1, arg2, arg3);
+		return eval(cell, arg1, arg2, arg3, errp);
 	}
 };
 
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 0229f5045..154373a8d 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -321,8 +321,13 @@ struct ConstEval
 			if (sig_d.size() > 0 && !eval(sig_d, undef, cell))
 				return false;
 
-			set(sig_y, CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(),
-					sig_c.as_const(), sig_d.as_const()));
+			bool eval_err = false;
+			RTLIL::Const eval_ret = CellTypes::eval(cell, sig_a.as_const(), sig_b.as_const(), sig_c.as_const(), sig_d.as_const(), &eval_err);
+
+			if (eval_err)
+				return false;
+
+			set(sig_y, eval_ret);
 		}
 
 		return true;

From 83bce9f59c2ae54038f1cf2938fd095e7039c38a Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 1 Dec 2018 18:28:54 +0100
Subject: [PATCH 189/528] Initial support for Anlogic FPGA

---
 techlibs/anlogic/Makefile.inc     |    8 +
 techlibs/anlogic/anlogic_eqn.cc   |  113 ++++
 techlibs/anlogic/arith_map.v      |   84 +++
 techlibs/anlogic/cells_map.v      |   49 ++
 techlibs/anlogic/cells_sim.v      |  103 +++
 techlibs/anlogic/eagle_bb.v       | 1028 +++++++++++++++++++++++++++++
 techlibs/anlogic/synth_anlogic.cc |  205 ++++++
 7 files changed, 1590 insertions(+)
 create mode 100644 techlibs/anlogic/Makefile.inc
 create mode 100644 techlibs/anlogic/anlogic_eqn.cc
 create mode 100644 techlibs/anlogic/arith_map.v
 create mode 100644 techlibs/anlogic/cells_map.v
 create mode 100644 techlibs/anlogic/cells_sim.v
 create mode 100644 techlibs/anlogic/eagle_bb.v
 create mode 100644 techlibs/anlogic/synth_anlogic.cc

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
new file mode 100644
index 000000000..750dced31
--- /dev/null
+++ b/techlibs/anlogic/Makefile.inc
@@ -0,0 +1,8 @@
+
+OBJS += techlibs/anlogic/synth_anlogic.o
+OBJS += techlibs/anlogic/anlogic_eqn.o
+
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
new file mode 100644
index 000000000..c025c65c4
--- /dev/null
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -0,0 +1,113 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct AnlogicEqnPass : public Pass {
+	AnlogicEqnPass() : Pass("anlogic_eqn", "Anlogic: Calculate equations for luts") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    anlogic_eqn [selection]\n");
+		log("\n");
+		log("Calculate equations for luts since bitstream generator depends on it.\n");
+		log("\n");
+	}
+
+	Const init2eqn(Const init, int inputs)
+	{
+		std::string init_bits = init.as_string();
+		const char* names[] = { "A" , "B", "C", "D", "E", "F" };
+
+		std::string eqn;
+		int width = (int)pow(2,inputs);
+		for(int i=0;i<width;i++)
+		{
+			if (init_bits[width-1-i]=='1')
+			{
+				eqn += "(";
+				for(int j=0;j<inputs;j++)
+				{
+					if (i & (1<<j))
+						eqn += names[j];
+					else
+						eqn += std::string("~") + names[j];
+					
+					if (j!=(inputs-1)) eqn += "*";
+				}
+				eqn += ")+";
+			}
+		}
+		if (eqn.empty()) return Const("0");		
+		eqn = eqn.substr(0, eqn.length()-1);
+		return Const(eqn);
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ANLOGIC_EQN pass (calculate equations for luts).\n");
+
+		extra_args(args, args.size(), design);
+
+		size_t cnt = 0;
+		for (auto module : design->selected_modules())
+		{
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type == "\\AL_MAP_LUT1")
+				{
+					cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1));
+					cnt++;
+				}
+				if (cell->type == "\\AL_MAP_LUT2")
+				{
+					cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2));
+					cnt++;
+				}
+				if (cell->type == "\\AL_MAP_LUT3")
+				{
+					cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3));
+					cnt++;
+				}
+				if (cell->type == "\\AL_MAP_LUT4")
+				{
+					cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4));
+					cnt++;
+				}
+				if (cell->type == "\\AL_MAP_LUT5")
+				{
+					cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5));
+					cnt++;
+				}
+				if (cell->type == "\\AL_MAP_LUT6")
+				{
+					cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6));
+					cnt++;
+				}
+			}
+		}
+		log_header(design, "Updated %lu of AL_MAP_LUT* elements with equation.\n", cnt);
+	}
+} AnlogicEqnPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v
new file mode 100644
index 000000000..11cd140ec
--- /dev/null
+++ b/techlibs/anlogic/arith_map.v
@@ -0,0 +1,84 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_anlogic_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH  = 1;
+	parameter B_WIDTH  = 1;
+	parameter Y_WIDTH  = 1;
+
+	input [A_WIDTH-1:0] A;
+	input [B_WIDTH-1:0] B;
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	output CO;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+	wire [Y_WIDTH+1:0] COx;
+	wire [Y_WIDTH+1:0] C = {COx, CI};
+
+    wire dummy;
+	(* keep *)
+    AL_MAP_ADDER #(
+    	.ALUTYPE("ADD_CARRY"))
+    adder_cin  (
+        .a(C[0]),
+        .o({COx[0], dummy})
+	);
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+	  if(i==Y_WIDTH-1) begin
+	  		(* keep *)
+			AL_MAP_ADDER #(
+				.ALUTYPE("ADD"))
+			adder_cout  (
+				.c(C[Y_WIDTH]),
+				.o(COx[Y_WIDTH])
+			);				
+            assign CO = COx[Y_WIDTH];
+          end
+	  else
+	  begin
+	  	(* keep *)
+	    AL_MAP_ADDER #(
+            .ALUTYPE("ADD")
+        ) adder_i (
+            .a(AA[i]),
+            .b(BB[i]),
+            .c(C[i+1]),
+            .o({COx[i+1],Y[i]})
+        );
+		end		
+	  end: slice
+	endgenerate
+	/* End implementation */
+	assign X = AA ^ BB;
+endmodule
\ No newline at end of file
diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
new file mode 100644
index 000000000..36b920ef0
--- /dev/null
+++ b/techlibs/anlogic/cells_map.v
@@ -0,0 +1,49 @@
+module  \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(1'b0)); endmodule
+
+module  \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+
+`ifndef NO_LUT
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      AL_MAP_LUT1 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]));
+    end else
+    if (WIDTH == 2) begin
+      AL_MAP_LUT2 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]));
+    end else
+    if (WIDTH == 3) begin
+      AL_MAP_LUT3 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]));
+    end else
+    if (WIDTH == 4) begin
+      AL_MAP_LUT4 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]));
+    end else
+    if (WIDTH == 5) begin
+      AL_MAP_LUT5 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]));
+    end else
+    if (WIDTH == 6) begin
+      AL_MAP_LUT6 #(.EQN(""),.INIT(LUT)) _TECHMAP_REPLACE_ (.o(Y), .a(A[0]), .b(A[1]), .c(A[2]), .d(A[3]), .e(A[4]), .f(A[5]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule
+`endif
diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v
new file mode 100644
index 000000000..60a367928
--- /dev/null
+++ b/techlibs/anlogic/cells_sim.v
@@ -0,0 +1,103 @@
+module AL_MAP_SEQ (
+	output q,
+	input ce,
+	input clk,
+	input sr,
+	input d
+);
+	parameter DFFMODE = "FF"; //FF,LATCH
+	parameter REGSET = "RESET"; //RESET/SET
+	parameter SRMUX = "SR"; //SR/INV
+	parameter SRMODE = "SYNC"; //SYNC/ASYNC
+endmodule
+
+module AL_MAP_LUT1 (
+	output o,
+	input a
+);
+	parameter [1:0] INIT = 2'h0;
+	parameter EQN = "(A)";
+	assign Y = INIT >> A;
+endmodule
+
+module AL_MAP_LUT2 (
+	output o,
+	input a,
+	input b
+);
+	parameter [3:0] INIT = 4'h0;
+	parameter EQN = "(A)";
+	assign o = INIT >> {b, a};
+endmodule
+
+module AL_MAP_LUT3 (
+	output o,
+	input a,
+	input b,
+	input c
+);
+	parameter [7:0] INIT = 8'h0;
+	parameter EQN = "(A)";
+	assign o = INIT >> {c, b, a};
+endmodule
+
+module AL_MAP_LUT4 (
+	output o,
+	input a,
+	input b,
+	input c,
+	input d
+);
+	parameter [15:0] INIT = 16'h0;
+	parameter EQN = "(A)";
+	assign o = INIT >> {d, c, b, a};
+endmodule
+
+module AL_MAP_LUT5 (
+	output o,
+	input a,
+	input b,
+	input c,
+	input d,
+	input e
+);
+	parameter [31:0] INIT = 32'h0;
+	parameter EQN = "(A)";
+	assign o = INIT >> {e, d, c, b, a};
+endmodule
+
+
+module AL_MAP_LUT6 (
+	output o,
+	input a,
+	input b,
+	input c,
+	input d,
+	input e,
+	input f
+);
+	parameter [63:0] INIT = 64'h0;
+	parameter EQN = "(A)";
+	assign o = INIT >> {f, e, d, c, b, a};
+endmodule
+
+module AL_MAP_ALU2B (
+   input cin,
+   input a0, b0, c0, d0,
+   input a1, b1, c1, d1,
+   output s0, s1, cout
+);
+	parameter [15:0] INIT0 = 16'h0000;
+	parameter [15:0] INIT1 = 16'h0000;
+	parameter FUNC0 = "NO";
+	parameter FUNC1 = "NO";
+endmodule
+
+module AL_MAP_ADDER (
+  input a,
+  input b,
+  input c,
+  output [1:0] o
+);
+	parameter ALUTYPE = "ADD";
+endmodule
diff --git a/techlibs/anlogic/eagle_bb.v b/techlibs/anlogic/eagle_bb.v
new file mode 100644
index 000000000..7cbec331a
--- /dev/null
+++ b/techlibs/anlogic/eagle_bb.v
@@ -0,0 +1,1028 @@
+// Anlogic Eagle - Blackbox cells
+// FIXME: Create sim models
+
+(* blackbox *)
+module EG_LOGIC_BUF(
+  output o,
+  input i
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BUFG(
+  output o,
+  input i
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BUFIO(
+  input clki,
+  input rst,
+  input coe,
+  output clko,
+  output clkdiv1,
+  output clkdivx
+);
+  parameter GSR = "DISABLE";
+  parameter DIV = 2;
+  parameter STOPCLK = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BUFGMUX(
+  output o,
+  input i0,
+  input i1,
+  input s
+);
+  parameter INIT_OUT = "0";
+  parameter PRESELECT_I0 = "TRUE";
+  parameter PRESELECT_I1 = "FALSE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_MBOOT(
+  input rebootn,
+  input [7:0] dynamic_addr  
+);
+  parameter ADDR_SOURCE_SEL = "STATIC";
+  parameter STATIC_ADDR = 8'b00000000;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_DNA(
+  output dout,
+  input  clk,
+  input  din,
+  input  shift_en
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_GCTRL(
+  output done,
+  output highz
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_GSRN(
+  input gsrn,
+  input sync_clk
+);
+  parameter GSRN_SYNC_SEL = "DISABLE";
+  parameter USR_GSRN_EN = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_CCLK(
+  output cclk,
+  input  en
+);
+  parameter FREQ = "4.5";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_IDELAY(
+  output o,
+  input i
+);
+  parameter INDEL = 0;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_IDDR(
+  output q1,
+  output q0,
+  input clk,
+  input d,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+  parameter PIPEMODE = "PIPED";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODDR(
+  output q,
+  input clk,
+  input d1,
+  input d0,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_IDDRx2(
+  output q3,
+  output q2,
+  output q1,
+  output q0,
+  input pclk,
+  input sclk,
+  input d,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODELAY(
+  output o,
+  input i
+);
+  parameter OUTDEL = 0;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODDRx2(
+  output q,
+  input pclk,
+  input sclk,
+  input d3,
+  input d2,
+  input d1,
+  input d0,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODDRx2l(
+  output q,
+  input sclk,
+  input d3,
+  input d2,
+  input d1,
+  input d0,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_FIFO(
+  input rst,
+  input [DATA_WIDTH_W-1:0] di,
+  output [DATA_WIDTH_R-1:0] do,
+  input clkw,
+  input we,
+  input clkr,
+  input re,
+  input ore,
+  input [2:0] csw,
+  input [2:0] csr,
+  output empty_flag,
+  output aempty_flag,
+  output full_flag,
+  output afull_flag
+);
+  parameter DATA_WIDTH_W = 9;
+  parameter DATA_WIDTH_R = DATA_WIDTH_W;
+  parameter DATA_DEPTH_W = 1024;
+  parameter DATA_DEPTH_R = DATA_WIDTH_W * DATA_DEPTH_W / DATA_WIDTH_R;
+  parameter MODE = "FIFO8K";
+  parameter REGMODE_W = "NOREG";
+  parameter REGMODE_R = "NOREG";
+  parameter E = 0;
+  parameter AE = 6;
+  parameter AF = DATA_DEPTH_W - 6;
+  parameter F = DATA_DEPTH_W;
+  parameter GSR = "DISABLE";
+  parameter RESETMODE = "ASYNC";
+  parameter ASYNC_RESET_RELEASE = "SYNC";
+  parameter ENDIAN = "LITTLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_DRAM(
+  input [DATA_WIDTH_W-1:0] di,
+  input [ADDR_WIDTH_W-1:0] waddr,
+  input wclk,
+  input we,
+  output [DATA_WIDTH_R-1:0] do,
+  input [ADDR_WIDTH_R-1:0] raddr
+);
+  parameter DATA_WIDTH_W = 9;
+  parameter ADDR_WIDTH_W = 10;
+  parameter DATA_DEPTH_W = 2 ** ADDR_WIDTH_W;
+  parameter DATA_WIDTH_R = 9;
+  parameter ADDR_WIDTH_R = 10;
+  parameter DATA_DEPTH_R = 2 ** ADDR_WIDTH_R;
+  parameter INIT_FILE = "NONE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_DRAM16X4(
+  input [3:0] di,
+  input [3:0] waddr,
+  input wclk,
+  input we,
+  input [3:0]raddr,
+  output [3:0]do
+);
+  parameter INIT_D0=16'h0000;
+  parameter INIT_D1=16'h0000;
+  parameter INIT_D2=16'h0000;
+  parameter INIT_D3=16'h0000;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_MULT(
+  output [OUTPUT_WIDTH-1:0] p,
+  input [INPUT_WIDTH_A-1:0] a,
+  input [INPUT_WIDTH_B-1:0] b,
+  input cea,
+  input ceb,
+  input cepd,
+  input clk,
+  input rstan,
+  input rstbn,
+  input rstpdn
+); 
+  parameter INPUT_WIDTH_A = 18;
+  parameter INPUT_WIDTH_B = 18;
+  parameter OUTPUT_WIDTH = 36;
+  parameter INPUTFORMAT = "SIGNED";
+  parameter INPUTREGA = "ENABLE";
+  parameter INPUTREGB = "ENABLE";
+  parameter OUTPUTREG = "ENABLE";
+  parameter SRMODE = "ASYNC";
+  parameter IMPLEMENT = "AUTO";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_SEQ_DIV(
+  input clk,
+  input rst,
+  input start,
+  input [NUMER_WIDTH-1:0] numer,
+  input [DENOM_WIDTH-1:0] denom,
+  output [NUMER_WIDTH-1:0] quotient,
+  output [DENOM_WIDTH-1:0] remain,
+  output done
+);
+	parameter NUMER_WIDTH = 16;
+  parameter DENOM_WIDTH = 16;
+endmodule
+
+(* blackbox *)
+module EG_PHY_BRAM(
+  output [8:0] doa,
+  output [8:0] dob,
+  input [8:0] dia,
+  input [8:0] dib,
+  input [2:0] csa,
+  input [2:0] csb,
+  input cea,
+  input ocea,
+  input clka,
+  input wea,
+  input rsta,
+  input ceb,
+  input oceb,
+  input clkb,
+  input web,
+  input rstb,
+  input [12:0] addra,
+  input [12:0] addrb
+);
+  parameter MODE = "DP8K";
+  parameter DATA_WIDTH_A = "9";
+  parameter DATA_WIDTH_B = "9";
+  parameter READBACK = "OFF";
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+  parameter WRITEMODE_A = "NORMAL";
+  parameter WRITEMODE_B = "NORMAL";
+  parameter GSR = "ENABLE";
+  parameter RESETMODE = "SYNC";
+  parameter ASYNC_RESET_RELEASE = "SYNC";
+  parameter CEAMUX = "SIG";
+  parameter CEBMUX = "SIG";
+  parameter OCEAMUX = "SIG";
+  parameter OCEBMUX = "SIG";
+  parameter RSTAMUX = "SIG";
+  parameter RSTBMUX = "SIG";
+  parameter CLKAMUX = "SIG";
+  parameter CLKBMUX = "SIG";
+  parameter WEAMUX = "SIG";
+  parameter WEBMUX = "SIG";
+  parameter CSA0 = "SIG" ;
+  parameter CSA1 = "SIG" ;
+  parameter CSA2 = "SIG" ;
+  parameter CSB0 = "SIG" ;
+  parameter CSB1 = "SIG" ;
+  parameter CSB2 = "SIG" ;
+  parameter INIT_FILE = "NONE";
+  parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+endmodule
+
+(* blackbox *)
+module EG_PHY_BRAM32K(
+  output [15:0] doa,
+  output [15:0] dob,
+  input [15:0] dia,
+  input [15:0] dib,
+  input [10:0] addra,
+  input [10:0] addrb,
+  input bytea,
+  input bytewea,
+  input byteb,
+  input byteweb,
+  input csa,
+  input wea,
+  input csb,
+  input web,
+  input clka,
+  input rsta,
+  input clkb,
+  input rstb,
+  input ocea,
+  input oceb
+);
+  parameter MODE = "DP16K";
+  parameter DATA_WIDTH_A = "16";
+  parameter DATA_WIDTH_B = "16";
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+  parameter WRITEMODE_A = "NORMAL";
+  parameter WRITEMODE_B = "NORMAL";
+  parameter SRMODE = "SYNC";
+  parameter CSAMUX = "SIG";
+  parameter CSBMUX = "SIG";
+  parameter OCEAMUX = "SIG";
+  parameter OCEBMUX = "SIG";
+  parameter RSTAMUX = "SIG";
+  parameter RSTBMUX = "SIG";
+  parameter CLKAMUX = "SIG";
+  parameter CLKBMUX = "SIG";
+  parameter WEAMUX = "SIG";
+  parameter WEBMUX = "SIG";
+  parameter READBACK = "OFF";
+  parameter INIT_FILE = "";
+  parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+  parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
+endmodule
+
+(* blackbox *)
+module EG_PHY_FIFO(
+  input [8:0] dia,
+  input [8:0] dib,
+  input [2:0] csr,
+  input [2:0] csw,
+  input we,
+  input re,
+  input clkw,
+  input clkr,
+  input rst,
+  input rprst,
+  input orea,
+  input oreb,
+  output [8:0] dob,
+  output [8:0] doa,
+  output empty_flag,
+  output aempty_flag,
+  output afull_flag,
+  output full_flag
+);
+  parameter MODE = "FIFO8K";
+  parameter DATA_WIDTH_A = "18";
+  parameter DATA_WIDTH_B = "18";
+  parameter READBACK = "OFF";
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+  parameter [13:0] AE = 14'b00000001100000;
+  parameter [13:0] AF = 14'b01111110010000;
+  parameter [13:0] F = 14'b01111111110000;
+  parameter [13:0] AEP1 = 14'b00000001110000;
+  parameter [13:0] AFM1 = 14'b01111110000000;
+  parameter [13:0] FM1  = 14'b01111111100000;   
+  parameter [4:0] E = 5'b00000;
+  parameter [5:0] EP1 = 6'b010000;
+  parameter GSR = "ENABLE";
+  parameter RESETMODE = "ASYNC";
+  parameter ASYNC_RESET_RELEASE = "SYNC";
+  parameter CEA = "SIG";
+  parameter CEB = "SIG";
+  parameter OCEA = "SIG";
+  parameter OCEB = "SIG";
+  parameter RSTA = "SIG";
+  parameter RSTB = "SIG";
+  parameter CLKA = "SIG";
+  parameter CLKB = "SIG";
+  parameter WEA = "SIG";
+  parameter WEB = "SIG";
+  parameter CSA0 = "SIG";
+  parameter CSA1 = "SIG";
+  parameter CSA2 = "SIG";
+  parameter CSB0 = "SIG";
+  parameter CSB1 = "SIG";
+  parameter CSB2 = "SIG";
+endmodule
+
+(* blackbox *)
+module EG_PHY_MULT18(
+  output [17:0] acout,
+  output [17:0] bcout,
+  output [35:0] p,
+  input signeda,
+  input signedb,
+  input [17:0] a,
+  input [17:0] b,
+  input [17:0] acin,
+  input [17:0] bcin,
+  input cea,
+  input ceb,
+  input cepd,
+  input clk,
+  input rstan,
+  input rstbn,
+  input rstpdn,
+  input sourcea,
+  input sourceb  
+); 
+  parameter INPUTREGA = "ENABLE";
+  parameter INPUTREGB = "ENABLE";
+  parameter OUTPUTREG = "ENABLE";
+  parameter SRMODE = "ASYNC";
+  parameter MODE = "MULT18X18C";
+  parameter CEAMUX = "SIG";
+  parameter CEBMUX = "SIG";
+  parameter CEPDMUX = "SIG";
+  parameter RSTANMUX = "SIG";
+  parameter RSTBNMUX = "SIG";
+  parameter RSTPDNMUX = "SIG";
+  parameter CLKMUX = "SIG";
+  parameter SIGNEDAMUX = "SIG";
+  parameter SIGNEDBMUX = "SIG";
+  parameter SOURCEAMUX = "SIG";
+  parameter SOURCEBMUX = "SIG";
+endmodule
+
+(* blackbox *)
+module EG_PHY_GCLK(
+  input clki,
+  output clko
+);    
+endmodule
+
+(* blackbox *)
+module EG_PHY_IOCLK(
+  input clki,
+  input stop,
+  output clko
+);
+  parameter STOPCLK = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_PHY_CLKDIV(
+  output clkdiv1,
+  output clkdivx,
+  input clki,
+  input rst,
+  input rls
+);    
+  parameter GSR = "DISABLE";
+  parameter DIV = 2;
+endmodule
+
+(* blackbox *)
+module EG_PHY_CONFIG(
+  output jrstn,
+  output [1:0] jrti,
+  output jshift,
+  output jtck,
+  output jtdi,
+  output jupdate,
+  output [1:0] jscanen,
+  output jtms,
+  input [1:0] jtdo,
+  input [7:0] jtag8_ipa,
+  input [7:0] jtag8_ipb,
+  output done,
+  output highz,
+  output cclk,
+  input	cclk_en,
+  input gsrn_sync_clk,
+  input usr_gsrn,
+  output dna_dout,
+  input	dna_clk,
+  input	dna_din,
+  input	dna_shift_en,
+  input	mboot_rebootn,
+  input [7:0]	mboot_dynamic_addr
+);  
+  parameter MBOOT_AUTO_SEL = "DISABLE";
+  parameter ADDR_SOURCE_SEL = "STATIC";
+  parameter STATIC_ADDR = 8'b0;
+  parameter DONE_PERSISTN = "ENABLE";
+  parameter INIT_PERSISTN = "ENABLE";
+  parameter PROGRAMN_PERSISTN = "DISABLE";
+  parameter JTAG_PERSISTN = "DISABLE";
+  parameter GSRN_SYNC_SEL = "DISABLE";
+  parameter FREQ = "2.5";
+  parameter USR_GSRN_EN = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_PHY_OSC(
+  input osc_dis,
+  output osc_clk
+);    
+  parameter STDBY = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_PHY_PWRMNT(
+    output pwr_dwn_n,
+    input sel_pwr,
+    input pwr_mnt_pd
+);
+  parameter MNT_LVL = 0;
+endmodule
+
+(* blackbox *)
+module EG_PHY_DDR_8M_16(
+  input clk,
+  input clk_n,
+  input ras_n,
+  input cas_n,
+  input we_n,
+  input cs_n,
+  input [11:0] addr,
+  input [1:0] ba,
+  inout [15:0] dq,
+  input ldqs,
+  input udqs,
+  input ldm,
+  input udm,
+  input cke
+);
+endmodule
+
+(* blackbox *)
+module EG_PHY_SDRAM_2M_32(
+  input clk,
+  input ras_n,
+  input cas_n,
+  input we_n,
+  input [10:0] addr,
+  input [1:0] ba,
+  inout [31:0] dq,
+  input cs_n,
+  input dm0,
+  input dm1,
+  input dm2,
+  input dm3,
+  input cke
+);
+endmodule
+
+(* blackbox *)
+module EG_PHY_PAD(
+  input ipad,
+  output opad,
+  inout bpad,
+  input rst,
+  input ce,
+  input isclk,
+  input ipclk,
+  input osclk,
+  input opclk,
+  input ts,
+  input [3:0] do,
+  output di,
+  output [3:0] diq
+);
+  parameter DEDCLK = "DISABLE";
+  parameter GSR = "ENABLE";
+  parameter SRMODE = "SYNC";
+  parameter TSMUX = "1";
+  parameter INSCLKMUX = "0";
+  parameter INPCLKMUX = "CLK";
+  parameter INCEMUX = "CE";
+  parameter INRSTMUX = "0";
+  parameter IN_REGSET = "RESET";
+  parameter IN_DFFMODE = "NONE";
+  parameter IDDRMODE = "OFF";
+  parameter IDDRPIPEMODE = "NONE";
+  parameter INDELMUX = "NODEL";
+  parameter INDEL = 0;
+  parameter OUTSCLKMUX = "0";
+  parameter OUTPCLKMUX = "CLK";
+  parameter OUTCEMUX = "CE";
+  parameter OUTRSTMUX = "0";
+  parameter DO_REGSET = "RESET";
+  parameter DO_DFFMODE = "NONE";
+  parameter ODDRMODE = "OFF";
+  parameter OUTDELMUX = "NODEL";
+  parameter OUTDEL = 0;
+  parameter TO_REGSET = "RESET";
+  parameter TO_DFFMODE = "NONE";
+  parameter MODE = "IN";
+  parameter DRIVE = "NONE";
+  parameter IOTYPE = "LVCMOS25";
+endmodule
+
+(* blackbox *)
+module EG_PHY_MSLICE(
+  input [1:0] a,
+  input [1:0] b,
+  input [1:0] c,
+  input [1:0] d,
+  input [1:0] mi,
+  input clk,
+  input ce,
+  input sr,
+  input fci,
+  output [1:0] f,
+  output [1:0] fx,
+  output [1:0] q,
+  output fco,
+  input dpram_mode,
+  input [1:0] dpram_di,
+  input dpram_we,
+  input dpram_wclk,
+  input [3:0] dpram_waddr
+);
+  parameter INIT_LUT0 = 16'h0000;
+  parameter INIT_LUT1 = 16'h0000;
+  parameter MODE = "LOGIC";
+  parameter ALUTYPE = "ADD";
+  parameter MSFXMUX = "OFF";
+  parameter GSR = "ENABLE";
+  parameter TESTMODE = "OFF";
+  parameter CEMUX = "CE";
+  parameter SRMUX = "SR";
+  parameter CLKMUX = "CLK";
+  parameter SRMODE = "ASYNC";
+  parameter DFFMODE = "FF";
+  parameter REG0_SD = "MI";
+  parameter REG1_SD = "MI";
+  parameter REG0_REGSET = "SET";
+  parameter REG1_REGSET = "SET";
+endmodule
+
+(* blackbox *)
+module EG_PHY_LSLICE(
+  input [1:0] a,
+  input [1:0] b,
+  input [1:0] c,
+  input [1:0] d,
+  input [1:0] e,
+  input [1:0] mi,
+  input clk,
+  input ce,
+  input sr,
+  input fci,
+  output [1:0] f,
+  output [1:0] fx,
+  output [1:0] q,
+  output fco,
+  output [3:0] dpram_di,
+  output [3:0] dpram_waddr,
+  output dpram_wclk,
+  output dpram_we,
+  output dpram_mode
+);
+  parameter INIT_LUTF0 = 16'h0000;
+  parameter INIT_LUTG0 = 16'h0000;
+  parameter INIT_LUTF1 = 16'h0000;
+  parameter INIT_LUTG1 = 16'h0000;
+  parameter MODE = "LOGIC";
+  parameter GSR = "ENABLE";
+  parameter TESTMODE = "OFF";
+  parameter CEMUX = "1";
+  parameter SRMUX = "SR";
+  parameter CLKMUX = "CLK";
+  parameter SRMODE = "ASYNC";
+  parameter DFFMODE = "FF";
+  parameter REG0_SD = "MI";
+  parameter REG1_SD = "MI";
+  parameter REG0_REGSET = "SET";
+  parameter REG1_REGSET = "SET";
+  parameter DEMUX0 = "D";
+  parameter DEMUX1 = "D";
+  parameter CMIMUX0 = "C";
+  parameter CMIMUX1 = "C";
+  parameter LSFMUX0 = "LUTF";
+  parameter LSFXMUX0 = "LUTG";
+  parameter LSFMUX1 = "LUTF";
+  parameter LSFXMUX1 = "LUTG";
+endmodule
+
+(* blackbox *)
+module EG_PHY_PLL(
+  output [4:0] clkc,
+  output extlock,
+  input stdby,
+  input refclk,
+  input fbclk,
+  input reset,
+  output psdone,
+  input psclk,
+  input psdown,
+  input psstep,
+  input [2:0] psclksel,
+  output [7:0] do,
+  input dclk,
+  input dcs,
+  input dwe,
+  input [7:0] di,
+  input [5:0] daddr
+);
+  parameter DYNCFG = "DISABLE";
+  parameter IF_ESCLKSTSW = "DISABLE";
+  parameter REFCLK_SEL = "INTERNAL";
+  parameter FIN = "100.0000";
+  parameter REFCLK_DIV = 1;
+  parameter FBCLK_DIV = 1;
+  parameter CLKC0_DIV = 1;
+  parameter CLKC1_DIV = 1;
+  parameter CLKC2_DIV = 1;
+  parameter CLKC3_DIV = 1;
+  parameter CLKC4_DIV = 1;
+  parameter CLKC0_ENABLE = "DISABLE";
+  parameter CLKC1_ENABLE = "DISABLE";
+  parameter CLKC2_ENABLE = "DISABLE";
+  parameter CLKC3_ENABLE = "DISABLE";
+  parameter CLKC4_ENABLE = "DISABLE";
+  parameter CLKC0_DIV2_ENABLE = "DISABLE";
+  parameter CLKC1_DIV2_ENABLE = "DISABLE";
+  parameter CLKC2_DIV2_ENABLE = "DISABLE";
+  parameter CLKC3_DIV2_ENABLE = "DISABLE";
+  parameter CLKC4_DIV2_ENABLE = "DISABLE";
+  parameter FEEDBK_MODE = "NORMAL";
+  parameter FEEDBK_PATH = "VCO_PHASE_0";  
+  parameter STDBY_ENABLE = "ENABLE";
+  parameter CLKC0_FPHASE = 0;
+  parameter CLKC1_FPHASE = 0;
+  parameter CLKC2_FPHASE = 0;
+  parameter CLKC3_FPHASE = 0;
+  parameter CLKC4_FPHASE = 0;
+  parameter CLKC0_CPHASE = 1;
+  parameter CLKC1_CPHASE = 1;
+  parameter CLKC2_CPHASE = 1;
+  parameter CLKC3_CPHASE = 1;
+  parameter CLKC4_CPHASE = 1;
+  parameter GMC_GAIN = 7;
+  parameter GMC_TEST = 14;
+  parameter ICP_CURRENT = 14;
+  parameter KVCO = 7;
+  parameter LPF_CAPACITOR = 3;
+  parameter LPF_RESISTOR = 1;
+  parameter PLLRST_ENA = "ENABLE";
+  parameter PLLMRST_ENA = "DISABLE";
+  parameter PLLC2RST_ENA = "DISABLE";
+  parameter PLLC34RST_ENA = "DISABLE";
+  parameter PREDIV_MUXC0 = "VCO";
+  parameter PREDIV_MUXC1 = "VCO";
+  parameter PREDIV_MUXC2 = "VCO";
+  parameter PREDIV_MUXC3 = "VCO";
+  parameter PREDIV_MUXC4 = "VCO";
+  parameter ODIV_MUXC0 = "DIV";
+  parameter ODIV_MUXC1 = "DIV";
+  parameter ODIV_MUXC2 = "DIV";
+  parameter ODIV_MUXC3 = "DIV";
+  parameter ODIV_MUXC4 = "DIV";
+  parameter FREQ_LOCK_ACCURACY = 2;
+  parameter PLL_LOCK_MODE = 0;
+  parameter INTFB_WAKE = "DISABLE";
+  parameter DPHASE_SOURCE = "DISABLE";
+  parameter VCO_NORESET = "DISABLE";
+  parameter STDBY_VCO_ENA = "DISABLE";
+  parameter NORESET = "DISABLE";
+  parameter SYNC_ENABLE = "ENABLE";
+  parameter DERIVE_PLL_CLOCKS = "DISABLE";
+  parameter GEN_BASIC_CLOCK = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BRAM(
+  output [DATA_WIDTH_A-1:0] doa,
+  output [DATA_WIDTH_B-1:0] dob,
+  input [DATA_WIDTH_A-1:0] dia,
+  input [DATA_WIDTH_B-1:0] dib,
+  input cea,
+  input ocea,
+  input clka,
+  input wea,
+  input rsta,
+  input ceb,
+  input oceb,
+  input clkb,
+  input web,
+  input rstb,
+  input [BYTE_A - 1 : 0] bea,
+  input [BYTE_B - 1 : 0] beb,
+  input [ADDR_WIDTH_A-1:0] addra,
+  input [ADDR_WIDTH_B-1:0] addrb
+);
+  parameter DATA_WIDTH_A = 9;
+  parameter DATA_WIDTH_B = DATA_WIDTH_A;
+  parameter ADDR_WIDTH_A = 10;
+  parameter ADDR_WIDTH_B = ADDR_WIDTH_A;
+  parameter DATA_DEPTH_A = 2 ** ADDR_WIDTH_A;
+  parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B;
+  parameter BYTE_ENABLE = 0;
+  parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE;
+  parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;  
+  parameter MODE = "DP";
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+  parameter WRITEMODE_A = "NORMAL";
+  parameter WRITEMODE_B = "NORMAL";
+  parameter RESETMODE = "SYNC";
+  parameter DEBUGGABLE = "NO";
+  parameter PACKABLE = "NO";
+  parameter FORCE_KEEP = "OFF";
+  parameter INIT_FILE = "NONE";
+  parameter FILL_ALL = "NONE";
+  parameter IMPLEMENT = "9K";
+endmodule     
+
+(* blackbox *)
+module EG_PHY_ADC(
+  input clk,
+  input pd,
+  input [2:0] s,
+  input soc,
+  output eoc,
+  output [11:0] dout
+);
+  parameter CH0 = "DISABLE";
+  parameter CH1 = "DISABLE";
+  parameter CH2 = "DISABLE";
+  parameter CH3 = "DISABLE";
+  parameter CH4 = "DISABLE";
+  parameter CH5 = "DISABLE";
+  parameter CH6 = "DISABLE";
+  parameter CH7 = "DISABLE";
+  parameter VREF = "DISABLE";
+endmodule
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
new file mode 100644
index 000000000..f4ef88770
--- /dev/null
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -0,0 +1,205 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  Miodrag Milanovic <miodrag@symbioticeda.com>
+ *  Copyright (C) 2018  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/celltypes.h"
+#include "kernel/rtlil.h"
+#include "kernel/log.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SynthAnlogicPass : public ScriptPass
+{
+	SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { }
+
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    synth_anlogic [options]\n");
+		log("\n");
+		log("This command runs synthesis for Anlogic FPGAs.\n");
+		log("\n");
+		log("    -top <module>\n");
+		log("        use the specified module as top module\n");
+		log("\n");
+		log("    -edif <file>\n");
+		log("        write the design to the specified EDIF file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -json <file>\n");
+		log("        write the design to the specified JSON file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to 'begin', and empty to label is\n");
+		log("        synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
+		log("    -retime\n");
+		log("        run 'abc' with -dff option\n");
+		log("\n");
+		log("\n");
+		log("The following commands are executed by this synthesis command:\n");
+		help_script();
+		log("\n");
+	}
+
+	string top_opt, edif_file, json_file;
+	bool flatten, retime;
+
+	void clear_flags() YS_OVERRIDE
+	{
+		top_opt = "-auto-top";
+		edif_file = "";
+		json_file = "";
+		flatten = true;
+		retime = false;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-top" && argidx+1 < args.size()) {
+				top_opt = "-top " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-edif" && argidx+1 < args.size()) {
+				edif_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-json" && argidx+1 < args.size()) {
+				json_file = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-run" && argidx+1 < args.size()) {
+				size_t pos = args[argidx+1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos+1);
+				continue;
+			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}
+			if (args[argidx] == "-retime") {
+				retime = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!design->full_selection())
+			log_cmd_error("This comannd only operates on fully selected designs!\n");
+
+		log_header(design, "Executing SYNTH_ANLOGIC pass.\n");
+		log_push();
+
+		run_script(design, run_from, run_to);
+
+		log_pop();
+	}
+
+	void script() YS_OVERRIDE
+	{
+		if (check_label("begin"))
+		{
+			run("read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v");
+			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+		}
+
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
+		{
+			run("proc");
+			run("flatten");
+			run("tribuf -logic");
+			run("deminout");
+		}
+
+		if (check_label("coarse"))
+		{
+			run("synth -run coarse");
+		}
+
+		if (check_label("fine"))
+		{
+			run("opt -fast -mux_undef -undriven -fine");
+			run("memory_map");
+			run("opt -undriven -fine");
+			run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
+			if (retime || help_mode)
+				run("abc -dff", "(only if -retime)");
+		}
+
+		if (check_label("map_ffs"))
+		{
+			run("dffsr2dff");
+			run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
+			run("opt_expr -mux_undef");
+			run("simplemap");
+		}
+
+		if (check_label("map_luts"))
+		{
+			run("abc -lut 6");
+			run("clean");
+		}
+
+		if (check_label("map_cells"))
+		{
+			run("techmap -map +/anlogic/cells_map.v");
+			run("clean");
+			run("anlogic_eqn");
+		}
+
+		if (check_label("check"))
+		{
+			run("hierarchy -check");
+			run("stat");
+			run("check -noinit");
+		}
+
+		if (check_label("edif"))
+		{
+			if (!edif_file.empty() || help_mode)
+				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("json"))
+		{
+			if (!json_file.empty() || help_mode)
+				run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
+		}
+	}
+} SynthAnlogicPass;
+
+PRIVATE_NAMESPACE_END

From 43030db5fff285de85096aaf5578b0548659f6b7 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 2 Dec 2018 11:57:50 +0100
Subject: [PATCH 190/528] Leave only real black box cells

---
 techlibs/anlogic/eagle_bb.v | 312 ------------------------------------
 1 file changed, 312 deletions(-)

diff --git a/techlibs/anlogic/eagle_bb.v b/techlibs/anlogic/eagle_bb.v
index 7cbec331a..48442db2f 100644
--- a/techlibs/anlogic/eagle_bb.v
+++ b/techlibs/anlogic/eagle_bb.v
@@ -1,274 +1,6 @@
 // Anlogic Eagle - Blackbox cells
 // FIXME: Create sim models
 
-(* blackbox *)
-module EG_LOGIC_BUF(
-  output o,
-  input i
-);
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_BUFG(
-  output o,
-  input i
-);
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_BUFIO(
-  input clki,
-  input rst,
-  input coe,
-  output clko,
-  output clkdiv1,
-  output clkdivx
-);
-  parameter GSR = "DISABLE";
-  parameter DIV = 2;
-  parameter STOPCLK = "DISABLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_BUFGMUX(
-  output o,
-  input i0,
-  input i1,
-  input s
-);
-  parameter INIT_OUT = "0";
-  parameter PRESELECT_I0 = "TRUE";
-  parameter PRESELECT_I1 = "FALSE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_MBOOT(
-  input rebootn,
-  input [7:0] dynamic_addr  
-);
-  parameter ADDR_SOURCE_SEL = "STATIC";
-  parameter STATIC_ADDR = 8'b00000000;
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_DNA(
-  output dout,
-  input  clk,
-  input  din,
-  input  shift_en
-);
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_GCTRL(
-  output done,
-  output highz
-);
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_GSRN(
-  input gsrn,
-  input sync_clk
-);
-  parameter GSRN_SYNC_SEL = "DISABLE";
-  parameter USR_GSRN_EN = "DISABLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_CCLK(
-  output cclk,
-  input  en
-);
-  parameter FREQ = "4.5";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_IDELAY(
-  output o,
-  input i
-);
-  parameter INDEL = 0;
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_IDDR(
-  output q1,
-  output q0,
-  input clk,
-  input d,
-  input rst
-);
-  parameter ASYNCRST = "ENABLE";
-  parameter PIPEMODE = "PIPED";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_ODDR(
-  output q,
-  input clk,
-  input d1,
-  input d0,
-  input rst
-);
-  parameter ASYNCRST = "ENABLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_IDDRx2(
-  output q3,
-  output q2,
-  output q1,
-  output q0,
-  input pclk,
-  input sclk,
-  input d,
-  input rst
-);
-  parameter ASYNCRST = "ENABLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_ODELAY(
-  output o,
-  input i
-);
-  parameter OUTDEL = 0;
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_ODDRx2(
-  output q,
-  input pclk,
-  input sclk,
-  input d3,
-  input d2,
-  input d1,
-  input d0,
-  input rst
-);
-  parameter ASYNCRST = "ENABLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_ODDRx2l(
-  output q,
-  input sclk,
-  input d3,
-  input d2,
-  input d1,
-  input d0,
-  input rst
-);
-  parameter ASYNCRST = "ENABLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_FIFO(
-  input rst,
-  input [DATA_WIDTH_W-1:0] di,
-  output [DATA_WIDTH_R-1:0] do,
-  input clkw,
-  input we,
-  input clkr,
-  input re,
-  input ore,
-  input [2:0] csw,
-  input [2:0] csr,
-  output empty_flag,
-  output aempty_flag,
-  output full_flag,
-  output afull_flag
-);
-  parameter DATA_WIDTH_W = 9;
-  parameter DATA_WIDTH_R = DATA_WIDTH_W;
-  parameter DATA_DEPTH_W = 1024;
-  parameter DATA_DEPTH_R = DATA_WIDTH_W * DATA_DEPTH_W / DATA_WIDTH_R;
-  parameter MODE = "FIFO8K";
-  parameter REGMODE_W = "NOREG";
-  parameter REGMODE_R = "NOREG";
-  parameter E = 0;
-  parameter AE = 6;
-  parameter AF = DATA_DEPTH_W - 6;
-  parameter F = DATA_DEPTH_W;
-  parameter GSR = "DISABLE";
-  parameter RESETMODE = "ASYNC";
-  parameter ASYNC_RESET_RELEASE = "SYNC";
-  parameter ENDIAN = "LITTLE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_DRAM(
-  input [DATA_WIDTH_W-1:0] di,
-  input [ADDR_WIDTH_W-1:0] waddr,
-  input wclk,
-  input we,
-  output [DATA_WIDTH_R-1:0] do,
-  input [ADDR_WIDTH_R-1:0] raddr
-);
-  parameter DATA_WIDTH_W = 9;
-  parameter ADDR_WIDTH_W = 10;
-  parameter DATA_DEPTH_W = 2 ** ADDR_WIDTH_W;
-  parameter DATA_WIDTH_R = 9;
-  parameter ADDR_WIDTH_R = 10;
-  parameter DATA_DEPTH_R = 2 ** ADDR_WIDTH_R;
-  parameter INIT_FILE = "NONE";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_DRAM16X4(
-  input [3:0] di,
-  input [3:0] waddr,
-  input wclk,
-  input we,
-  input [3:0]raddr,
-  output [3:0]do
-);
-  parameter INIT_D0=16'h0000;
-  parameter INIT_D1=16'h0000;
-  parameter INIT_D2=16'h0000;
-  parameter INIT_D3=16'h0000;
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_MULT(
-  output [OUTPUT_WIDTH-1:0] p,
-  input [INPUT_WIDTH_A-1:0] a,
-  input [INPUT_WIDTH_B-1:0] b,
-  input cea,
-  input ceb,
-  input cepd,
-  input clk,
-  input rstan,
-  input rstbn,
-  input rstpdn
-); 
-  parameter INPUT_WIDTH_A = 18;
-  parameter INPUT_WIDTH_B = 18;
-  parameter OUTPUT_WIDTH = 36;
-  parameter INPUTFORMAT = "SIGNED";
-  parameter INPUTREGA = "ENABLE";
-  parameter INPUTREGB = "ENABLE";
-  parameter OUTPUTREG = "ENABLE";
-  parameter SRMODE = "ASYNC";
-  parameter IMPLEMENT = "AUTO";
-endmodule
-
-(* blackbox *)
-module EG_LOGIC_SEQ_DIV(
-  input clk,
-  input rst,
-  input start,
-  input [NUMER_WIDTH-1:0] numer,
-  input [DENOM_WIDTH-1:0] denom,
-  output [NUMER_WIDTH-1:0] quotient,
-  output [DENOM_WIDTH-1:0] remain,
-  output done
-);
-	parameter NUMER_WIDTH = 16;
-  parameter DENOM_WIDTH = 16;
-endmodule
-
 (* blackbox *)
 module EG_PHY_BRAM(
   output [8:0] doa,
@@ -963,50 +695,6 @@ module EG_PHY_PLL(
   parameter GEN_BASIC_CLOCK = "DISABLE";
 endmodule
 
-(* blackbox *)
-module EG_LOGIC_BRAM(
-  output [DATA_WIDTH_A-1:0] doa,
-  output [DATA_WIDTH_B-1:0] dob,
-  input [DATA_WIDTH_A-1:0] dia,
-  input [DATA_WIDTH_B-1:0] dib,
-  input cea,
-  input ocea,
-  input clka,
-  input wea,
-  input rsta,
-  input ceb,
-  input oceb,
-  input clkb,
-  input web,
-  input rstb,
-  input [BYTE_A - 1 : 0] bea,
-  input [BYTE_B - 1 : 0] beb,
-  input [ADDR_WIDTH_A-1:0] addra,
-  input [ADDR_WIDTH_B-1:0] addrb
-);
-  parameter DATA_WIDTH_A = 9;
-  parameter DATA_WIDTH_B = DATA_WIDTH_A;
-  parameter ADDR_WIDTH_A = 10;
-  parameter ADDR_WIDTH_B = ADDR_WIDTH_A;
-  parameter DATA_DEPTH_A = 2 ** ADDR_WIDTH_A;
-  parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B;
-  parameter BYTE_ENABLE = 0;
-  parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE;
-  parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;  
-  parameter MODE = "DP";
-  parameter REGMODE_A = "NOREG";
-  parameter REGMODE_B = "NOREG";
-  parameter WRITEMODE_A = "NORMAL";
-  parameter WRITEMODE_B = "NORMAL";
-  parameter RESETMODE = "SYNC";
-  parameter DEBUGGABLE = "NO";
-  parameter PACKABLE = "NO";
-  parameter FORCE_KEEP = "OFF";
-  parameter INIT_FILE = "NONE";
-  parameter FILL_ALL = "NONE";
-  parameter IMPLEMENT = "9K";
-endmodule     
-
 (* blackbox *)
 module EG_PHY_ADC(
   input clk,

From 819ca7309620b3791c7b93de44990ffb4fceb30f Mon Sep 17 00:00:00 2001
From: Diego H <dhdezr@gmail.com>
Date: Mon, 3 Dec 2018 20:08:35 -0600
Subject: [PATCH 191/528] Changes in GoWin synth commands and ALU primitive
 support

---
 techlibs/gowin/Makefile.inc       |  1 +
 techlibs/gowin/arith_map.v        | 59 +++++++++++++++++++++++++++++++
 techlibs/gowin/cells_sim.v        |  6 ++++
 techlibs/gowin/synth_gowin.cc     | 21 ++++++++---
 techlibs/intel/common/brams_map.v | 16 ++++-----
 5 files changed, 91 insertions(+), 12 deletions(-)
 create mode 100644 techlibs/gowin/arith_map.v

diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc
index 679d7eff5..2f82def7d 100644
--- a/techlibs/gowin/Makefile.inc
+++ b/techlibs/gowin/Makefile.inc
@@ -3,4 +3,5 @@ OBJS += techlibs/gowin/synth_gowin.o
 
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
 $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
+$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
 
diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
new file mode 100644
index 000000000..25e789e4a
--- /dev/null
+++ b/techlibs/gowin/arith_map.v
@@ -0,0 +1,59 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018  David Shah <dave@ds0.me>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
+   parameter A_SIGNED = 0;
+   parameter B_SIGNED = 0;
+   parameter A_WIDTH = 1;
+   parameter B_WIDTH = 1;
+   parameter Y_WIDTH = 1;
+   
+   input [A_WIDTH-1:0] A;
+   input [B_WIDTH-1:0] B;
+   output [Y_WIDTH-1:0] X, Y;
+   
+   input 		CI, BI;
+   output [Y_WIDTH-1:0] CO;
+   
+   wire 		_TECHMAP_FAIL_ = Y_WIDTH <= 2;
+   
+   wire [Y_WIDTH-1:0] 	A_buf, B_buf;
+   \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+   \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+   
+   wire [Y_WIDTH-1:0] 	AA = A_buf;
+   wire [Y_WIDTH-1:0] 	BB = BI ? ~B_buf : B_buf;
+   wire [Y_WIDTH-1:0] 	C = {CO, CI};
+   
+   genvar 		i;
+   generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
+      ALU #(.ALU_MODE(32'b0))
+      alu(.I0(AA[i]),
+	  .I1(BB[i]),
+	  .I3(1'b0),
+	  .CIN(C[i]),
+	  .COUT(CO[i]),
+	  .SUM(Y[i])
+	  );
+   end endgenerate
+   assign X = AA ^ BB;
+endmodule
+
diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v
index 947942626..14441c2fc 100644
--- a/techlibs/gowin/cells_sim.v
+++ b/techlibs/gowin/cells_sim.v
@@ -57,3 +57,9 @@ endmodule
 module GSR (input GSRI);
 	wire GSRO = GSRI;
 endmodule
+
+module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM);
+   parameter [3:0] ALU_MODE = 0; // default 0 = ADD
+   assign  {COUT, SUM} = CIN + I1 + I0;
+endmodule // alu
+
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 793f345be..e3d924e26 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -49,6 +49,9 @@ struct SynthGowinPass : public ScriptPass
 		log("        from label is synonymous to 'begin', and empty to label is\n");
 		log("        synonymous to the end of the command list.\n");
 		log("\n");
+		log("    -nobram\n");
+		log("        do not use BRAM cells in output netlist\n");
+		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
@@ -59,13 +62,14 @@ struct SynthGowinPass : public ScriptPass
 	}
 
 	string top_opt, vout_file;
-	bool retime;
+	bool retime, nobram;
 
 	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		vout_file = "";
 		retime = false;
+                nobram = true;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -96,6 +100,10 @@ struct SynthGowinPass : public ScriptPass
 				retime = true;
 				continue;
 			}
+			if (args[argidx] == "-nobram") {
+				nobram = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -119,7 +127,7 @@ struct SynthGowinPass : public ScriptPass
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (check_label("flatten"))
+		if (check_label("flatten") && check_label("flatten", "(unless -noflatten)"))
 		{
 			run("proc");
 			run("flatten");
@@ -131,13 +139,18 @@ struct SynthGowinPass : public ScriptPass
 		{
 			run("synth -run coarse");
 		}
-
+		if (!nobram && check_label("bram", "(skip if -nobram)"))
+		{
+			run("memory_bram -rules +/gowin/bram.txt");
+			run("techmap -map +/gowin/brams_map.v");
+		}
 		if (check_label("fine"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
-			run("techmap");
+			run("techmap -map +/techmap.v -map +/gowin/arith_map.v");
+			run("opt -fine");
 			run("clean -purge");
 			run("splitnets -ports");
 			run("setundef -undriven -zero");
diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v
index fae4af2ab..d0f07c1de 100644
--- a/techlibs/intel/common/brams_map.v
+++ b/techlibs/intel/common/brams_map.v
@@ -2,8 +2,8 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
 
    parameter CFG_ABITS = 8;
    parameter CFG_DBITS = 36;
-   parameter ABITS = "1";
-   parameter DBITS = "1";
+   parameter ABITS = 1;
+   parameter DBITS = 1;
    parameter CLKPOL2 = 1;
    parameter CLKPOL3 = 1;
 
@@ -63,21 +63,21 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
                  .width_byteena_a                (1), // Forced value
                  .numwords_b                     ( NUMWORDS     ),
                  .numwords_a                     ( NUMWORDS     ),
-                 .widthad_b                      ( CFG_ABITS    ),
-                 .width_b                        ( CFG_DBITS    ),
-                 .widthad_a                      ( CFG_ABITS    ),
-                 .width_a                        ( CFG_DBITS    )
+                 .widthad_b                      ( CFG_DBITS    ),
+                 .width_b                        ( CFG_ABITS    ),
+                 .widthad_a                      ( CFG_DBITS    ),
+                 .width_a                        ( CFG_ABITS    )
                  ) _TECHMAP_REPLACE_ (
                                       .data_a(B1DATA),
                                       .address_a(B1ADDR),
                                       .wren_a(B1EN),
                                       .rden_a(A1EN),
                                       .q_a(A1DATA),
-                                      .data_b(1'b0),
+                                      .data_b(B1DATA),
                                       .address_b(0),
                                       .wren_b(1'b0),
                                       .rden_b(1'b0),
-                                      .q_b(1'b0),
+                                      .q_b(),
                                       .clock0(CLK2),
                                       .clock1(1'b1), // Unused in single port mode
                                       .clocken0(1'b1),

From c800e3bb163550f83ac677676a89f701f5f36052 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 4 Dec 2018 23:30:23 +0100
Subject: [PATCH 192/528] Fix typo

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/techmap/dff2dffe.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 3f5b48c75..7e1040963 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -263,7 +263,7 @@ struct Dff2dffePass : public Pass {
 		log("more feedback paths to $dffe cells. It also works on gate-level cells such as\n");
 		log("$_DFF_P_, $_DFF_N_ and $_MUX_.\n");
 		log("\n");
-		log("    -unmap");
+		log("    -unmap\n");
 		log("        operate in the opposite direction: replace $dffe cells with combinations\n");
 		log("        of $dff and $mux cells. the options below are ignore in unmap mode.\n");
 		log("\n");

From 323480d66b541c3296f869f75bb33ed2ceeb8753 Mon Sep 17 00:00:00 2001
From: Sergiusz Bazanski <q3k@q3k.org>
Date: Wed, 5 Dec 2018 11:50:58 +0100
Subject: [PATCH 193/528] travis/osx: fix, use clang instead of gcc

---
 .travis.yml      | 4 ++--
 .travis/setup.sh | 1 -
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 321c3325f..8aacbb8b1 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -134,9 +134,9 @@ matrix:
 
     # Latest clang on Mac OS X
     - os: osx
-      osx_image: xcode8
+      osx_image: xcode9.4
       env:
-        - MATRIX_EVAL="CONFIG=gcc && CC=gcc-7 && CXX=g++-7"
+        - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++"
 
 before_install:
   - ./.travis/setup.sh
diff --git a/.travis/setup.sh b/.travis/setup.sh
index 068515786..d689cd2bd 100755
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -64,7 +64,6 @@ if [[ "$TRAVIS_OS_NAME" == "osx" ]]; then
 		brew tap Homebrew/bundle
 		brew bundle
 		brew install ccache
-		brew install gcc@7
 		echo
 		echo -en 'travis_fold:end:before_install.brew\\r'
 		echo

From 1719aa88acf9f6d52caa81384bc50237605157e3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 4 Dec 2018 19:43:33 +0000
Subject: [PATCH 194/528] Extract ice40_unlut pass from ice40_opt.

Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
---
 techlibs/ice40/Makefile.inc   |   1 +
 techlibs/ice40/ice40_opt.cc   |  15 +----
 techlibs/ice40/ice40_unlut.cc | 106 ++++++++++++++++++++++++++++++++++
 3 files changed, 109 insertions(+), 13 deletions(-)
 create mode 100644 techlibs/ice40/ice40_unlut.cc

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 14761c6c8..2750901c8 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -3,6 +3,7 @@ OBJS += techlibs/ice40/synth_ice40.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
+OBJS += techlibs/ice40/ice40_unlut.o
 
 GENFILES += techlibs/ice40/brams_init1.vh
 GENFILES += techlibs/ice40/brams_init2.vh
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index 162740059..f528607d6 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -33,7 +33,7 @@ static SigBit get_bit_or_zero(const SigSpec &sig)
 	return sig[0];
 }
 
-static void run_ice40_opts(Module *module, bool unlut_mode)
+static void run_ice40_opts(Module *module)
 {
 	pool<SigBit> optimized_co;
 	vector<Cell*> sb_lut_cells;
@@ -95,9 +95,6 @@ static void run_ice40_opts(Module *module, bool unlut_mode)
 		inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
 		sigmap.apply(inbits);
 
-		if (unlut_mode)
-			goto remap_lut;
-
 		if (optimized_co.count(inbits[0])) goto remap_lut;
 		if (optimized_co.count(inbits[1])) goto remap_lut;
 		if (optimized_co.count(inbits[2])) goto remap_lut;
@@ -152,14 +149,10 @@ struct Ice40OptPass : public Pass {
 		log("        opt_clean\n");
 		log("    while <changed design>\n");
 		log("\n");
-		log("When called with the option -unlut, this command will transform all already\n");
-		log("mapped SB_LUT4 cells back to logic.\n");
-		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string opt_expr_args = "-mux_undef -undriven";
-		bool unlut_mode = false;
 
 		log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n");
 		log_push();
@@ -170,10 +163,6 @@ struct Ice40OptPass : public Pass {
 				opt_expr_args += " -full";
 				continue;
 			}
-			if (args[argidx] == "-unlut") {
-				unlut_mode = true;
-				continue;
-			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -184,7 +173,7 @@ struct Ice40OptPass : public Pass {
 
 			log_header(design, "Running ICE40 specific optimizations.\n");
 			for (auto module : design->selected_modules())
-				run_ice40_opts(module, unlut_mode);
+				run_ice40_opts(module);
 
 			Pass::call(design, "opt_expr " + opt_expr_args);
 			Pass::call(design, "opt_merge");
diff --git a/techlibs/ice40/ice40_unlut.cc b/techlibs/ice40/ice40_unlut.cc
new file mode 100644
index 000000000..2428a8e78
--- /dev/null
+++ b/techlibs/ice40/ice40_unlut.cc
@@ -0,0 +1,106 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static SigBit get_bit_or_zero(const SigSpec &sig)
+{
+	if (GetSize(sig) == 0)
+		return State::S0;
+	return sig[0];
+}
+
+static void run_ice40_unlut(Module *module)
+{
+	SigMap sigmap(module);
+
+	for (auto cell : module->selected_cells())
+	{
+		if (cell->type == "\\SB_LUT4")
+		{
+			SigSpec inbits;
+
+			inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
+			inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
+			sigmap.apply(inbits);
+
+			log("Mapping SB_LUT4 cell %s.%s to $lut.\n", log_id(module), log_id(cell));
+
+			cell->type ="$lut";
+			cell->setParam("\\WIDTH", 4);
+			cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
+			cell->unsetParam("\\LUT_INIT");
+
+			cell->setPort("\\A", SigSpec({
+				get_bit_or_zero(cell->getPort("\\I3")),
+				get_bit_or_zero(cell->getPort("\\I2")),
+				get_bit_or_zero(cell->getPort("\\I1")),
+				get_bit_or_zero(cell->getPort("\\I0"))
+			}));
+			cell->setPort("\\Y", cell->getPort("\\O")[0]);
+			cell->unsetPort("\\I0");
+			cell->unsetPort("\\I1");
+			cell->unsetPort("\\I2");
+			cell->unsetPort("\\I3");
+			cell->unsetPort("\\O");
+
+			cell->check();
+		}
+	}
+}
+
+struct Ice40UnlutPass : public Pass {
+	Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_unlut [options] [selection]\n");
+		log("\n");
+		log("This command transforms all SB_LUT4 cells to generic $lut cells.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_UNLUT pass (convert SB_LUT4 to $lut).\n");
+		log_push();
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-???") {
+			//  continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_ice40_unlut(module);
+	}
+} Ice40UnlutPass;
+
+PRIVATE_NAMESPACE_END

From 9e072ec21f9985126e1cfeb04fa7f2bc963790b3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 00:23:22 +0000
Subject: [PATCH 195/528] opt_lut: new pass, to combine LUTs for tighter
 packing.

---
 Makefile                |   3 +-
 passes/opt/Makefile.inc |   1 +
 passes/opt/opt_lut.cpp  | 274 ++++++++++++++++++++++++++++++++++++++++
 tests/opt/.gitignore    |   1 +
 tests/opt/ice40_carry.v |   3 +
 tests/opt/opt_lut.v     |  18 +++
 tests/opt/opt_lut.ys    |  15 +++
 tests/opt/run-test.sh   |   6 +
 8 files changed, 320 insertions(+), 1 deletion(-)
 create mode 100644 passes/opt/opt_lut.cpp
 create mode 100644 tests/opt/.gitignore
 create mode 100644 tests/opt/ice40_carry.v
 create mode 100644 tests/opt/opt_lut.v
 create mode 100644 tests/opt/opt_lut.ys
 create mode 100755 tests/opt/run-test.sh

diff --git a/Makefile b/Makefile
index b33166059..053796e9d 100644
--- a/Makefile
+++ b/Makefile
@@ -160,7 +160,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
 else ifeq ($(CONFIG),gcc-static)
 LD = $(CXX)
 LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
-LDLIBS := $(filter-out -lrt,$(LDLIBS)) 
+LDLIBS := $(filter-out -lrt,$(LDLIBS))
 CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
 CXXFLAGS += -std=c++11 -Os
 ABCMKARGS = CC="$(CC)" CXX="$(CXX)" LD="$(LD)" ABC_USE_LIBSTDCXX=1 LIBS="-lm -lpthread -static" OPTFLAGS="-O" \
@@ -578,6 +578,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/various && bash run-test.sh
 	+cd tests/sat && bash run-test.sh
 	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
+	+cd tests/opt && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""
diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc
index 0d01e9d35..0f596b1f4 100644
--- a/passes/opt/Makefile.inc
+++ b/passes/opt/Makefile.inc
@@ -6,6 +6,7 @@ OBJS += passes/opt/opt_reduce.o
 OBJS += passes/opt/opt_rmdff.o
 OBJS += passes/opt/opt_clean.o
 OBJS += passes/opt/opt_expr.o
+OBJS += passes/opt/opt_lut.o
 
 ifneq ($(SMALL),1)
 OBJS += passes/opt/share.o
diff --git a/passes/opt/opt_lut.cpp b/passes/opt/opt_lut.cpp
new file mode 100644
index 000000000..4d6d491f7
--- /dev/null
+++ b/passes/opt/opt_lut.cpp
@@ -0,0 +1,274 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  whitequark <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/modtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static bool evaluate_lut(SigMap &sigmap, RTLIL::Cell *lut, dict<SigBit, bool> inputs)
+{
+	SigSpec lut_input = sigmap(lut->getPort("\\A"));
+	int lut_width = lut->getParam("\\WIDTH").as_int();
+	Const lut_table = lut->getParam("\\LUT");
+	int lut_index = 0;
+
+	for (int i = 0; i < lut_width; i++)
+	{
+		SigBit input = sigmap(lut_input[i]);
+		if (inputs.count(input))
+		{
+			lut_index |= inputs[input] << i;
+		}
+		else
+		{
+			lut_index |= SigSpec(lut_input[i]).as_bool() << i;
+		}
+	}
+
+	return lut_table.extract(lut_index).as_int();
+}
+
+static void run_lut_opts(Module *module)
+{
+	ModIndex index(module);
+	SigMap sigmap(module);
+
+	log("Discovering LUTs.\n");
+
+	pool<RTLIL::Cell*> luts;
+	dict<RTLIL::Cell*, int> luts_arity;
+	for (auto cell : module->selected_cells())
+	{
+		if (cell->type == "$lut")
+		{
+			int lut_width = cell->getParam("\\WIDTH").as_int();
+			SigSpec lut_input = cell->getPort("\\A");
+			int lut_arity = 0;
+
+			for (auto &bit : lut_input)
+			{
+				if (bit.wire)
+					lut_arity++;
+			}
+
+			log("Found $lut cell %s.%s with WIDTH=%d implementing %d-LUT.\n", log_id(module), log_id(cell), lut_width, lut_arity);
+			luts.insert(cell);
+			luts_arity[cell] = lut_arity;
+		}
+	}
+
+	log("\n");
+	log("Combining LUTs.\n");
+
+	pool<RTLIL::Cell*> worklist = luts;
+	while (worklist.size())
+	{
+		auto lutA = worklist.pop();
+		SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
+		SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
+		int lutA_width = lutA->getParam("\\WIDTH").as_int();
+		int lutA_arity = luts_arity[lutA];
+
+		auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y"));
+		if (lutA_output_ports.size() != 2)
+			continue;
+
+		for (auto port : lutA_output_ports)
+		{
+			if (port.cell == lutA)
+				continue;
+
+			if (luts.count(port.cell))
+			{
+				auto lutB = port.cell;
+				SigSpec lutB_input = sigmap(lutB->getPort("\\A"));
+				SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]);
+				int lutB_width = lutB->getParam("\\WIDTH").as_int();
+				int lutB_arity = luts_arity[lutB];
+
+				log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
+
+				pool<SigBit> lutA_inputs;
+				pool<SigBit> lutB_inputs;
+				for (auto &bit : lutA_input)
+				{
+					if (bit.wire)
+						lutA_inputs.insert(sigmap(bit));
+				}
+				for (auto &bit : lutB_input)
+				{
+					if(bit.wire)
+						lutB_inputs.insert(sigmap(bit));
+				}
+
+				pool<SigBit> common_inputs;
+				for (auto &bit : lutA_inputs)
+				{
+					if (lutB_inputs.count(bit))
+						common_inputs.insert(bit);
+				}
+
+				int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
+				log("  Cell A is a %d-LUT. Cell B is a %d-LUT. Cells share %zu input(s) and can be merged into one %d-LUT.\n", lutA_arity, lutB_arity, common_inputs.size(), lutM_arity);
+
+				int combine = -1;
+				if (combine == -1)
+				{
+					if (lutM_arity > lutA_width)
+					{
+						log("  Not combining LUTs into cell A (combined LUT too wide).\n");
+					}
+					else if (lutB->get_bool_attribute("\\lut_keep"))
+					{
+						log("  Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
+					}
+					else combine = 0;
+				}
+				if (combine == -1)
+				{
+					if (lutM_arity > lutB_width)
+					{
+						log("  Not combining LUTs into cell B (combined LUT too wide).\n");
+					}
+					else if (lutA->get_bool_attribute("\\lut_keep"))
+					{
+						log("  Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
+					}
+					else combine = 1;
+				}
+
+				RTLIL::Cell *lutM, *lutR;
+				pool<SigBit> lutM_inputs, lutR_inputs;
+				if (combine == 0)
+				{
+					log("  Combining LUTs into cell A.\n");
+					lutM = lutA;
+					lutM_inputs = lutA_inputs;
+					lutR = lutB;
+					lutR_inputs = lutB_inputs;
+				}
+				else if (combine == 1)
+				{
+					log("  Combining LUTs into cell B.\n");
+					lutM = lutB;
+					lutM_inputs = lutB_inputs;
+					lutR = lutA;
+					lutR_inputs = lutA_inputs;
+				}
+				else
+				{
+					log("  Cannot combine LUTs.\n");
+					continue;
+				}
+
+				pool<SigBit> lutR_unique;
+				for (auto &bit : lutR_inputs)
+				{
+					if (!common_inputs.count(bit) && bit != lutA_output)
+						lutR_unique.insert(bit);
+				}
+
+				int lutM_width = lutM->getParam("\\WIDTH").as_int();
+				SigSpec lutM_input = sigmap(lutM->getPort("\\A"));
+				std::vector<SigBit> lutM_new_inputs;
+				for (int i = 0; i < lutM_width; i++)
+				{
+					if ((!lutM_input[i].wire || sigmap(lutM_input[i]) == lutA_output) && lutR_unique.size())
+					{
+						SigBit new_input = lutR_unique.pop();
+						log("    Connecting input %d as %s.\n", i, log_signal(new_input));
+						lutM_new_inputs.push_back(new_input);
+					}
+					else if (sigmap(lutM_input[i]) == lutA_output)
+					{
+						log("    Disconnecting input %d.\n", i);
+						lutM_new_inputs.push_back(SigBit());
+					}
+					else
+					{
+						log("    Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
+						lutM_new_inputs.push_back(lutM_input[i]);
+					}
+				}
+				log_assert(lutR_unique.size() == 0);
+
+				RTLIL::Const lutM_new_table(State::Sx, 1 << lutM_width);
+				for (int eval = 0; eval < 1 << lutM_width; eval++)
+				{
+					dict<SigBit, bool> eval_inputs;
+					for (size_t i = 0; i < lutM_new_inputs.size(); i++)
+					{
+						eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
+					}
+					eval_inputs[lutA_output] = evaluate_lut(sigmap, lutA, eval_inputs);
+					lutM_new_table[eval] = (RTLIL::State) evaluate_lut(sigmap, lutB, eval_inputs);
+				}
+
+				log("  Old truth table: %s.\n", lutM->getParam("\\LUT").as_string().c_str());
+				log("  New truth table: %s.\n", lutM_new_table.as_string().c_str());
+
+				lutM->setParam("\\LUT", lutM_new_table);
+				lutM->setPort("\\A", lutM_new_inputs);
+				lutM->setPort("\\Y", lutB_output);
+
+				luts_arity[lutM] = lutM_arity;
+				luts.erase(lutR);
+				luts_arity.erase(lutR);
+				lutR->module->remove(lutR);
+
+				worklist.insert(lutM);
+				worklist.erase(lutR);
+			}
+		}
+	}
+}
+
+struct OptLutPass : public Pass {
+	OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    opt_lut [options] [selection]\n");
+		log("\n");
+		log("This pass combines cascaded $lut cells with unused inputs.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-???") {
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_lut_opts(module);
+	}
+} OptLutPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/tests/opt/.gitignore b/tests/opt/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/opt/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
new file mode 100644
index 000000000..ed938932a
--- /dev/null
+++ b/tests/opt/ice40_carry.v
@@ -0,0 +1,3 @@
+module SB_CARRY (output CO, input I0, I1, CI);
+    assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
diff --git a/tests/opt/opt_lut.v b/tests/opt/opt_lut.v
new file mode 100644
index 000000000..b13db367d
--- /dev/null
+++ b/tests/opt/opt_lut.v
@@ -0,0 +1,18 @@
+module top(
+    input [8:0] a,
+    input [8:0] b,
+    output [8:0] o1,
+    output [2:0] o2,
+    input [2:0] c,
+    input [2:0] d,
+    output [2:0] o3,
+    output [2:0] o4,
+    input s
+);
+
+assign o1 = (s ? 0 : a + b);
+assign o2 = (s ? a : a - b);
+assign o3 = (s ? 4'b1111 : d + c);
+assign o4 = (s ? d : c - d);
+
+endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
new file mode 100644
index 000000000..1c7dc1473
--- /dev/null
+++ b/tests/opt/opt_lut.ys
@@ -0,0 +1,15 @@
+read_verilog opt_lut.v
+synth_ice40
+ice40_unlut
+design -save preopt
+
+opt_lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+techmap -map ice40_carry.v
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/opt/run-test.sh b/tests/opt/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/opt/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done

From ea4870b12690bd313852c952f4fd17efaf63abb6 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 00:28:03 +0000
Subject: [PATCH 196/528] synth_ice40: add -relut option, to run ice40_unlut
 and opt_lut.

---
 techlibs/ice40/synth_ice40.cc | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 93965a55d..7094db50d 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -63,6 +63,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
+		log("    -relut\n");
+		log("        combine LUTs after synthesis\n");
+		log("\n");
 		log("    -nocarry\n");
 		log("        do not use SB_CARRY cells in output netlist\n");
 		log("\n");
@@ -90,7 +93,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool nocarry, nodffe, nobram, flatten, retime, abc2, vpr;
+	bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -105,6 +108,7 @@ struct SynthIce40Pass : public ScriptPass
 		nobram = false;
 		flatten = true;
 		retime = false;
+		relut = false;
 		abc2 = false;
 		vpr = false;
 	}
@@ -153,6 +157,10 @@ struct SynthIce40Pass : public ScriptPass
 				retime = true;
 				continue;
 			}
+			if (args[argidx] == "-relut") {
+				relut = true;
+				continue;
+			}
 			if (args[argidx] == "-nocarry") {
 				nocarry = true;
 				continue;
@@ -259,6 +267,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/ice40/latches_map.v");
 			run("abc -lut 4");
 			run("clean");
+			if (relut || help_mode) {
+				run("ice40_unlut", "(only if -relut)");
+				run("opt_lut", "    (only if -relut)");
+			}
 		}
 
 		if (check_label("map_cells"))

From e54c7e951c5659ae6ebb4dfe9c42adfe0498dc4b Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 12:26:41 +0000
Subject: [PATCH 197/528] opt_lut: refactor to use a worker. NFC.

---
 passes/opt/opt_lut.cpp | 365 +++++++++++++++++++++--------------------
 1 file changed, 186 insertions(+), 179 deletions(-)

diff --git a/passes/opt/opt_lut.cpp b/passes/opt/opt_lut.cpp
index 4d6d491f7..f33b23cf4 100644
--- a/passes/opt/opt_lut.cpp
+++ b/passes/opt/opt_lut.cpp
@@ -24,223 +24,228 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static bool evaluate_lut(SigMap &sigmap, RTLIL::Cell *lut, dict<SigBit, bool> inputs)
+struct OptLutWorker
 {
-	SigSpec lut_input = sigmap(lut->getPort("\\A"));
-	int lut_width = lut->getParam("\\WIDTH").as_int();
-	Const lut_table = lut->getParam("\\LUT");
-	int lut_index = 0;
+	RTLIL::Module *module;
+	ModIndex index;
+	SigMap sigmap;
 
-	for (int i = 0; i < lut_width; i++)
+	bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
 	{
-		SigBit input = sigmap(lut_input[i]);
-		if (inputs.count(input))
+		SigSpec lut_input = sigmap(lut->getPort("\\A"));
+		int lut_width = lut->getParam("\\WIDTH").as_int();
+		Const lut_table = lut->getParam("\\LUT");
+		int lut_index = 0;
+
+		for (int i = 0; i < lut_width; i++)
 		{
-			lut_index |= inputs[input] << i;
-		}
-		else
-		{
-			lut_index |= SigSpec(lut_input[i]).as_bool() << i;
-		}
-	}
-
-	return lut_table.extract(lut_index).as_int();
-}
-
-static void run_lut_opts(Module *module)
-{
-	ModIndex index(module);
-	SigMap sigmap(module);
-
-	log("Discovering LUTs.\n");
-
-	pool<RTLIL::Cell*> luts;
-	dict<RTLIL::Cell*, int> luts_arity;
-	for (auto cell : module->selected_cells())
-	{
-		if (cell->type == "$lut")
-		{
-			int lut_width = cell->getParam("\\WIDTH").as_int();
-			SigSpec lut_input = cell->getPort("\\A");
-			int lut_arity = 0;
-
-			for (auto &bit : lut_input)
+			SigBit input = sigmap(lut_input[i]);
+			if (inputs.count(input))
 			{
-				if (bit.wire)
-					lut_arity++;
+				lut_index |= inputs[input] << i;
+			}
+			else
+			{
+				lut_index |= SigSpec(lut_input[i]).as_bool() << i;
 			}
-
-			log("Found $lut cell %s.%s with WIDTH=%d implementing %d-LUT.\n", log_id(module), log_id(cell), lut_width, lut_arity);
-			luts.insert(cell);
-			luts_arity[cell] = lut_arity;
 		}
+
+		return lut_table.extract(lut_index).as_int();
 	}
 
-	log("\n");
-	log("Combining LUTs.\n");
-
-	pool<RTLIL::Cell*> worklist = luts;
-	while (worklist.size())
+	OptLutWorker(RTLIL::Module *module) :
+		module(module), index(module), sigmap(module)
 	{
-		auto lutA = worklist.pop();
-		SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
-		SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
-		int lutA_width = lutA->getParam("\\WIDTH").as_int();
-		int lutA_arity = luts_arity[lutA];
+		pool<RTLIL::Cell*> luts;
+		dict<RTLIL::Cell*, int> luts_arity;
 
-		auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y"));
-		if (lutA_output_ports.size() != 2)
-			continue;
-
-		for (auto port : lutA_output_ports)
+		log("Discovering LUTs.\n");
+		for (auto cell : module->selected_cells())
 		{
-			if (port.cell == lutA)
-				continue;
-
-			if (luts.count(port.cell))
+			if (cell->type == "$lut")
 			{
-				auto lutB = port.cell;
-				SigSpec lutB_input = sigmap(lutB->getPort("\\A"));
-				SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]);
-				int lutB_width = lutB->getParam("\\WIDTH").as_int();
-				int lutB_arity = luts_arity[lutB];
+				int lut_width = cell->getParam("\\WIDTH").as_int();
+				SigSpec lut_input = cell->getPort("\\A");
+				int lut_arity = 0;
 
-				log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
-
-				pool<SigBit> lutA_inputs;
-				pool<SigBit> lutB_inputs;
-				for (auto &bit : lutA_input)
+				for (auto &bit : lut_input)
 				{
 					if (bit.wire)
-						lutA_inputs.insert(sigmap(bit));
-				}
-				for (auto &bit : lutB_input)
-				{
-					if(bit.wire)
-						lutB_inputs.insert(sigmap(bit));
+						lut_arity++;
 				}
 
-				pool<SigBit> common_inputs;
-				for (auto &bit : lutA_inputs)
-				{
-					if (lutB_inputs.count(bit))
-						common_inputs.insert(bit);
-				}
+				log("Found $lut cell %s.%s with WIDTH=%d implementing %d-LUT.\n", log_id(module), log_id(cell), lut_width, lut_arity);
+				luts.insert(cell);
+				luts_arity[cell] = lut_arity;
+			}
+		}
 
-				int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
-				log("  Cell A is a %d-LUT. Cell B is a %d-LUT. Cells share %zu input(s) and can be merged into one %d-LUT.\n", lutA_arity, lutB_arity, common_inputs.size(), lutM_arity);
+		log("\n");
+		log("Combining LUTs.\n");
 
-				int combine = -1;
-				if (combine == -1)
-				{
-					if (lutM_arity > lutA_width)
-					{
-						log("  Not combining LUTs into cell A (combined LUT too wide).\n");
-					}
-					else if (lutB->get_bool_attribute("\\lut_keep"))
-					{
-						log("  Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
-					}
-					else combine = 0;
-				}
-				if (combine == -1)
-				{
-					if (lutM_arity > lutB_width)
-					{
-						log("  Not combining LUTs into cell B (combined LUT too wide).\n");
-					}
-					else if (lutA->get_bool_attribute("\\lut_keep"))
-					{
-						log("  Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
-					}
-					else combine = 1;
-				}
+		pool<RTLIL::Cell*> worklist = luts;
+		while (worklist.size())
+		{
+			auto lutA = worklist.pop();
+			SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
+			SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
+			int lutA_width = lutA->getParam("\\WIDTH").as_int();
+			int lutA_arity = luts_arity[lutA];
 
-				RTLIL::Cell *lutM, *lutR;
-				pool<SigBit> lutM_inputs, lutR_inputs;
-				if (combine == 0)
-				{
-					log("  Combining LUTs into cell A.\n");
-					lutM = lutA;
-					lutM_inputs = lutA_inputs;
-					lutR = lutB;
-					lutR_inputs = lutB_inputs;
-				}
-				else if (combine == 1)
-				{
-					log("  Combining LUTs into cell B.\n");
-					lutM = lutB;
-					lutM_inputs = lutB_inputs;
-					lutR = lutA;
-					lutR_inputs = lutA_inputs;
-				}
-				else
-				{
-					log("  Cannot combine LUTs.\n");
+			auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y"));
+			if (lutA_output_ports.size() != 2)
+				continue;
+
+			for (auto port : lutA_output_ports)
+			{
+				if (port.cell == lutA)
 					continue;
-				}
 
-				pool<SigBit> lutR_unique;
-				for (auto &bit : lutR_inputs)
+				if (luts.count(port.cell))
 				{
-					if (!common_inputs.count(bit) && bit != lutA_output)
-						lutR_unique.insert(bit);
-				}
+					auto lutB = port.cell;
+					SigSpec lutB_input = sigmap(lutB->getPort("\\A"));
+					SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]);
+					int lutB_width = lutB->getParam("\\WIDTH").as_int();
+					int lutB_arity = luts_arity[lutB];
 
-				int lutM_width = lutM->getParam("\\WIDTH").as_int();
-				SigSpec lutM_input = sigmap(lutM->getPort("\\A"));
-				std::vector<SigBit> lutM_new_inputs;
-				for (int i = 0; i < lutM_width; i++)
-				{
-					if ((!lutM_input[i].wire || sigmap(lutM_input[i]) == lutA_output) && lutR_unique.size())
+					log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
+
+					pool<SigBit> lutA_inputs;
+					pool<SigBit> lutB_inputs;
+					for (auto &bit : lutA_input)
 					{
-						SigBit new_input = lutR_unique.pop();
-						log("    Connecting input %d as %s.\n", i, log_signal(new_input));
-						lutM_new_inputs.push_back(new_input);
+						if (bit.wire)
+							lutA_inputs.insert(sigmap(bit));
 					}
-					else if (sigmap(lutM_input[i]) == lutA_output)
+					for (auto &bit : lutB_input)
 					{
-						log("    Disconnecting input %d.\n", i);
-						lutM_new_inputs.push_back(SigBit());
+						if(bit.wire)
+							lutB_inputs.insert(sigmap(bit));
+					}
+
+					pool<SigBit> common_inputs;
+					for (auto &bit : lutA_inputs)
+					{
+						if (lutB_inputs.count(bit))
+							common_inputs.insert(bit);
+					}
+
+					int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
+					log("  Cell A is a %d-LUT. Cell B is a %d-LUT. Cells share %zu input(s) and can be merged into one %d-LUT.\n", lutA_arity, lutB_arity, common_inputs.size(), lutM_arity);
+
+					int combine = -1;
+					if (combine == -1)
+					{
+						if (lutM_arity > lutA_width)
+						{
+							log("  Not combining LUTs into cell A (combined LUT too wide).\n");
+						}
+						else if (lutB->get_bool_attribute("\\lut_keep"))
+						{
+							log("  Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
+						}
+						else combine = 0;
+					}
+					if (combine == -1)
+					{
+						if (lutM_arity > lutB_width)
+						{
+							log("  Not combining LUTs into cell B (combined LUT too wide).\n");
+						}
+						else if (lutA->get_bool_attribute("\\lut_keep"))
+						{
+							log("  Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
+						}
+						else combine = 1;
+					}
+
+					RTLIL::Cell *lutM, *lutR;
+					pool<SigBit> lutM_inputs, lutR_inputs;
+					if (combine == 0)
+					{
+						log("  Combining LUTs into cell A.\n");
+						lutM = lutA;
+						lutM_inputs = lutA_inputs;
+						lutR = lutB;
+						lutR_inputs = lutB_inputs;
+					}
+					else if (combine == 1)
+					{
+						log("  Combining LUTs into cell B.\n");
+						lutM = lutB;
+						lutM_inputs = lutB_inputs;
+						lutR = lutA;
+						lutR_inputs = lutA_inputs;
 					}
 					else
 					{
-						log("    Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
-						lutM_new_inputs.push_back(lutM_input[i]);
+						log("  Cannot combine LUTs.\n");
+						continue;
 					}
-				}
-				log_assert(lutR_unique.size() == 0);
 
-				RTLIL::Const lutM_new_table(State::Sx, 1 << lutM_width);
-				for (int eval = 0; eval < 1 << lutM_width; eval++)
-				{
-					dict<SigBit, bool> eval_inputs;
-					for (size_t i = 0; i < lutM_new_inputs.size(); i++)
+					pool<SigBit> lutR_unique;
+					for (auto &bit : lutR_inputs)
 					{
-						eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
+						if (!common_inputs.count(bit) && bit != lutA_output)
+							lutR_unique.insert(bit);
 					}
-					eval_inputs[lutA_output] = evaluate_lut(sigmap, lutA, eval_inputs);
-					lutM_new_table[eval] = (RTLIL::State) evaluate_lut(sigmap, lutB, eval_inputs);
+
+					int lutM_width = lutM->getParam("\\WIDTH").as_int();
+					SigSpec lutM_input = sigmap(lutM->getPort("\\A"));
+					std::vector<SigBit> lutM_new_inputs;
+					for (int i = 0; i < lutM_width; i++)
+					{
+						if ((!lutM_input[i].wire || sigmap(lutM_input[i]) == lutA_output) && lutR_unique.size())
+						{
+							SigBit new_input = lutR_unique.pop();
+							log("    Connecting input %d as %s.\n", i, log_signal(new_input));
+							lutM_new_inputs.push_back(new_input);
+						}
+						else if (sigmap(lutM_input[i]) == lutA_output)
+						{
+							log("    Disconnecting input %d.\n", i);
+							lutM_new_inputs.push_back(SigBit());
+						}
+						else
+						{
+							log("    Leaving input %d as %s.\n", i, log_signal(lutM_input[i]));
+							lutM_new_inputs.push_back(lutM_input[i]);
+						}
+					}
+					log_assert(lutR_unique.size() == 0);
+
+					RTLIL::Const lutM_new_table(State::Sx, 1 << lutM_width);
+					for (int eval = 0; eval < 1 << lutM_width; eval++)
+					{
+						dict<SigBit, bool> eval_inputs;
+						for (size_t i = 0; i < lutM_new_inputs.size(); i++)
+						{
+							eval_inputs[lutM_new_inputs[i]] = (eval >> i) & 1;
+						}
+						eval_inputs[lutA_output] = evaluate_lut(lutA, eval_inputs);
+						lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
+					}
+
+					log("  Old truth table: %s.\n", lutM->getParam("\\LUT").as_string().c_str());
+					log("  New truth table: %s.\n", lutM_new_table.as_string().c_str());
+
+					lutM->setParam("\\LUT", lutM_new_table);
+					lutM->setPort("\\A", lutM_new_inputs);
+					lutM->setPort("\\Y", lutB_output);
+
+					luts_arity[lutM] = lutM_arity;
+					luts.erase(lutR);
+					luts_arity.erase(lutR);
+					lutR->module->remove(lutR);
+
+					worklist.insert(lutM);
+					worklist.erase(lutR);
 				}
-
-				log("  Old truth table: %s.\n", lutM->getParam("\\LUT").as_string().c_str());
-				log("  New truth table: %s.\n", lutM_new_table.as_string().c_str());
-
-				lutM->setParam("\\LUT", lutM_new_table);
-				lutM->setPort("\\A", lutM_new_inputs);
-				lutM->setPort("\\Y", lutB_output);
-
-				luts_arity[lutM] = lutM_arity;
-				luts.erase(lutR);
-				luts_arity.erase(lutR);
-				lutR->module->remove(lutR);
-
-				worklist.insert(lutM);
-				worklist.erase(lutR);
 			}
 		}
 	}
-}
+};
 
 struct OptLutPass : public Pass {
 	OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
@@ -267,7 +272,9 @@ struct OptLutPass : public Pass {
 		extra_args(args, argidx, design);
 
 		for (auto module : design->selected_modules())
-			run_lut_opts(module);
+		{
+			OptLutWorker worker(module);
+		}
 	}
 } OptLutPass;
 

From 59eea0183ffaa453f77c6d439a9df8c1087c0fe0 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 12:35:27 +0000
Subject: [PATCH 198/528] opt_lut: collect and display statistics.

---
 passes/opt/opt_lut.cpp | 37 +++++++++++++++++++++++++++++++++----
 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/passes/opt/opt_lut.cpp b/passes/opt/opt_lut.cpp
index f33b23cf4..b043f6c10 100644
--- a/passes/opt/opt_lut.cpp
+++ b/passes/opt/opt_lut.cpp
@@ -30,6 +30,11 @@ struct OptLutWorker
 	ModIndex index;
 	SigMap sigmap;
 
+	pool<RTLIL::Cell*> luts;
+	dict<RTLIL::Cell*, int> luts_arity;
+
+	int combined_count = 0;
+
 	bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
 	{
 		SigSpec lut_input = sigmap(lut->getPort("\\A"));
@@ -53,12 +58,27 @@ struct OptLutWorker
 		return lut_table.extract(lut_index).as_int();
 	}
 
+	void show_stats_by_arity()
+	{
+		dict<int, int> arity_counts;
+		int max_arity = 0;
+		for (auto lut_arity : luts_arity)
+		{
+			max_arity = max(max_arity, lut_arity.second);
+			arity_counts[lut_arity.second]++;
+		}
+
+		log("Number of LUTs: %6zu\n", luts.size());
+		for (int arity = 1; arity <= max_arity; arity++)
+		{
+			if (arity_counts[arity])
+				log("  %d-LUT: %13d\n", arity, arity_counts[arity]);
+		}
+	}
+
 	OptLutWorker(RTLIL::Module *module) :
 		module(module), index(module), sigmap(module)
 	{
-		pool<RTLIL::Cell*> luts;
-		dict<RTLIL::Cell*, int> luts_arity;
-
 		log("Discovering LUTs.\n");
 		for (auto cell : module->selected_cells())
 		{
@@ -79,10 +99,10 @@ struct OptLutWorker
 				luts_arity[cell] = lut_arity;
 			}
 		}
+		show_stats_by_arity();
 
 		log("\n");
 		log("Combining LUTs.\n");
-
 		pool<RTLIL::Cell*> worklist = luts;
 		while (worklist.size())
 		{
@@ -241,9 +261,12 @@ struct OptLutWorker
 
 					worklist.insert(lutM);
 					worklist.erase(lutR);
+
+					combined_count++;
 				}
 			}
 		}
+		show_stats_by_arity();
 	}
 };
 
@@ -271,10 +294,16 @@ struct OptLutPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
+		int total_count = 0;
 		for (auto module : design->selected_modules())
 		{
 			OptLutWorker worker(module);
+			total_count += worker.combined_count;
 		}
+		if (total_count)
+			design->scratchpad_set_bool("opt.did_something", true);
+		log("\n");
+		log("Combined %d LUTs.\n", total_count);
 	}
 } OptLutPass;
 

From e6034840702effa2ff0c2eee0cca046b5c097e86 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 13:14:44 +0000
Subject: [PATCH 199/528] opt_lut: always prefer to eliminate 1-LUTs.

These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
---
 passes/opt/opt_lut.cpp | 60 +++++++++++++++++++++++++++++-------------
 1 file changed, 41 insertions(+), 19 deletions(-)

diff --git a/passes/opt/opt_lut.cpp b/passes/opt/opt_lut.cpp
index b043f6c10..0eb6b13e5 100644
--- a/passes/opt/opt_lut.cpp
+++ b/passes/opt/opt_lut.cpp
@@ -154,35 +154,57 @@ struct OptLutWorker
 					int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
 					log("  Cell A is a %d-LUT. Cell B is a %d-LUT. Cells share %zu input(s) and can be merged into one %d-LUT.\n", lutA_arity, lutB_arity, common_inputs.size(), lutM_arity);
 
-					int combine = -1;
-					if (combine == -1)
+					const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
+					int combine_mask = 0;
+					if (lutM_arity > lutA_width)
 					{
-						if (lutM_arity > lutA_width)
-						{
-							log("  Not combining LUTs into cell A (combined LUT too wide).\n");
-						}
-						else if (lutB->get_bool_attribute("\\lut_keep"))
-						{
-							log("  Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
-						}
-						else combine = 0;
+						log("  Not combining LUTs into cell A (combined LUT wider than cell A).\n");
 					}
-					if (combine == -1)
+					else if (lutB->get_bool_attribute("\\lut_keep"))
 					{
-						if (lutM_arity > lutB_width)
+						log("  Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
+					}
+					else
+					{
+						combine_mask |= COMBINE_A;
+					}
+					if (lutM_arity > lutB_width)
+					{
+						log("  Not combining LUTs into cell B (combined LUT wider than cell B).\n");
+					}
+					else if (lutA->get_bool_attribute("\\lut_keep"))
+					{
+						log("  Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
+					}
+					else
+					{
+						combine_mask |= COMBINE_B;
+					}
+
+					int combine = combine_mask;
+					if (combine == COMBINE_EITHER)
+					{
+						log("  Can combine into either cell.\n");
+						if (lutA_arity == 1)
 						{
-							log("  Not combining LUTs into cell B (combined LUT too wide).\n");
+							log("    Cell A is a buffer or inverter, combining into cell B.\n");
+							combine = COMBINE_B;
 						}
-						else if (lutA->get_bool_attribute("\\lut_keep"))
+						else if (lutB_arity == 1)
 						{
-							log("  Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
+							log("    Cell B is a buffer or inverter, combining into cell A.\n");
+							combine = COMBINE_A;
+						}
+						else
+						{
+							log("    Arbitrarily combining into cell A.\n");
+							combine = COMBINE_A;
 						}
-						else combine = 1;
 					}
 
 					RTLIL::Cell *lutM, *lutR;
 					pool<SigBit> lutM_inputs, lutR_inputs;
-					if (combine == 0)
+					if (combine == COMBINE_A)
 					{
 						log("  Combining LUTs into cell A.\n");
 						lutM = lutA;
@@ -190,7 +212,7 @@ struct OptLutWorker
 						lutR = lutB;
 						lutR_inputs = lutB_inputs;
 					}
-					else if (combine == 1)
+					else if (combine == COMBINE_B)
 					{
 						log("  Combining LUTs into cell B.\n");
 						lutM = lutB;

From 45cb6200af13469724de42656f2c1f0f61c8766a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 15:26:40 +0000
Subject: [PATCH 200/528] opt_lut: add -dlogic, to avoid disturbing logic such
 as carry chains.

---
 passes/opt/opt_lut.cpp        | 180 ++++++++++++++++++++++++++++++----
 techlibs/ice40/synth_ice40.cc |   4 +-
 tests/opt/opt_lut.ys          |   2 +-
 3 files changed, 166 insertions(+), 20 deletions(-)

diff --git a/passes/opt/opt_lut.cpp b/passes/opt/opt_lut.cpp
index 0eb6b13e5..befe346a3 100644
--- a/passes/opt/opt_lut.cpp
+++ b/passes/opt/opt_lut.cpp
@@ -26,12 +26,15 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct OptLutWorker
 {
+	dict<IdString, dict<int, IdString>> &dlogic;
 	RTLIL::Module *module;
 	ModIndex index;
 	SigMap sigmap;
 
 	pool<RTLIL::Cell*> luts;
 	dict<RTLIL::Cell*, int> luts_arity;
+	dict<RTLIL::Cell*, pool<RTLIL::Cell*>> luts_dlogics;
+	dict<RTLIL::Cell*, pool<int>> luts_dlogic_inputs;
 
 	int combined_count = 0;
 
@@ -61,23 +64,37 @@ struct OptLutWorker
 	void show_stats_by_arity()
 	{
 		dict<int, int> arity_counts;
+		dict<IdString, int> dlogic_counts;
 		int max_arity = 0;
+
 		for (auto lut_arity : luts_arity)
 		{
 			max_arity = max(max_arity, lut_arity.second);
 			arity_counts[lut_arity.second]++;
 		}
 
-		log("Number of LUTs: %6zu\n", luts.size());
+		for (auto &lut_dlogics : luts_dlogics)
+		{
+			for (auto &lut_dlogic : lut_dlogics.second)
+			{
+				dlogic_counts[lut_dlogic->type]++;
+			}
+		}
+
+		log("Number of LUTs: %8zu\n", luts.size());
 		for (int arity = 1; arity <= max_arity; arity++)
 		{
 			if (arity_counts[arity])
-				log("  %d-LUT: %13d\n", arity, arity_counts[arity]);
+				log("  %d-LUT %16d\n", arity, arity_counts[arity]);
+		}
+		for (auto &dlogic_count : dlogic_counts)
+		{
+			log("  with %-12s %4d\n", dlogic_count.first.c_str(), dlogic_count.second);
 		}
 	}
 
-	OptLutWorker(RTLIL::Module *module) :
-		module(module), index(module), sigmap(module)
+	OptLutWorker(dict<IdString, dict<int, IdString>> &dlogic, RTLIL::Module *module) :
+		dlogic(dlogic), module(module), index(module), sigmap(module)
 	{
 		log("Discovering LUTs.\n");
 		for (auto cell : module->selected_cells())
@@ -88,15 +105,84 @@ struct OptLutWorker
 				SigSpec lut_input = cell->getPort("\\A");
 				int lut_arity = 0;
 
-				for (auto &bit : lut_input)
+				log("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, log_id(module), log_id(cell));
+				luts.insert(cell);
+
+				// First, find all dedicated logic we're connected to. This results in an overapproximation
+				// of such connections.
+				pool<RTLIL::Cell*> lut_all_dlogics;
+				for (int i = 0; i < lut_width; i++)
 				{
-					if (bit.wire)
+					SigBit bit = lut_input[i];
+					for (auto &port : index.query_ports(bit))
+					{
+						if (dlogic.count(port.cell->type))
+						{
+							auto &dlogic_map = dlogic[port.cell->type];
+							if (dlogic_map.count(i))
+							{
+								if (port.port == dlogic_map[i])
+								{
+									lut_all_dlogics.insert(port.cell);
+								}
+							}
+						}
+					}
+				}
+
+				// Second, make sure that the connection to dedicated logic is legal. If it is not legal,
+				// it means one of the two things:
+				//   * The connection is spurious. I.e. this is dedicated logic that will be packed
+				//     with some other LUT, and it just happens to be conected to this LUT as well.
+				//   * The connection is illegal.
+				// In either of these cases, we don't need to concern ourselves with preserving the connection
+				// between this LUT and this dedicated logic cell.
+				pool<RTLIL::Cell*> lut_legal_dlogics;
+				pool<int> lut_dlogic_inputs;
+				for (auto lut_dlogic : lut_all_dlogics)
+				{
+					auto &dlogic_map = dlogic[lut_dlogic->type];
+					bool legal = true;
+					for (auto &dlogic_conn : dlogic_map)
+					{
+						if (lut_width <= dlogic_conn.first)
+						{
+							log("  LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
+							log("    LUT input A[%d] not present.\n", dlogic_conn.first);
+							legal = false;
+							break;
+						}
+						if (sigmap(lut_input[dlogic_conn.first]) != sigmap(lut_dlogic->getPort(dlogic_conn.second)))
+						{
+							log("  LUT has illegal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
+							log("    LUT input A[%d] (wire %s) not connected to %s port %s (wire %s).\n", dlogic_conn.first, log_signal(lut_input[dlogic_conn.first]), lut_dlogic->type.c_str(), dlogic_conn.second.c_str(), log_signal(lut_dlogic->getPort(dlogic_conn.second)));
+							legal = false;
+							break;
+						}
+					}
+
+					if (legal)
+					{
+						log("  LUT has legal connection to %s cell %s.%s.\n", lut_dlogic->type.c_str(), log_id(module), log_id(lut_dlogic));
+						lut_legal_dlogics.insert(lut_dlogic);
+						for (auto &dlogic_conn : dlogic_map)
+							lut_dlogic_inputs.insert(dlogic_conn.first);
+					}
+				}
+
+				// Third, determine LUT arity. An n-wide LUT that has k constant inputs and m inputs shared with dedicated
+				// logic implements an (n-k-m)-ary function.
+				for (int i = 0; i < lut_width; i++)
+				{
+					SigBit bit = lut_input[i];
+					if (bit.wire || lut_dlogic_inputs.count(i))
 						lut_arity++;
 				}
 
-				log("Found $lut cell %s.%s with WIDTH=%d implementing %d-LUT.\n", log_id(module), log_id(cell), lut_width, lut_arity);
-				luts.insert(cell);
+				log("  Cell implements a %d-LUT.\n", lut_arity);
 				luts_arity[cell] = lut_arity;
+				luts_dlogics[cell] = lut_legal_dlogics;
+				luts_dlogic_inputs[cell] = lut_dlogic_inputs;
 			}
 		}
 		show_stats_by_arity();
@@ -111,12 +197,13 @@ struct OptLutWorker
 			SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
 			int lutA_width = lutA->getParam("\\WIDTH").as_int();
 			int lutA_arity = luts_arity[lutA];
+			pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
 
 			auto lutA_output_ports = index.query_ports(lutA->getPort("\\Y"));
 			if (lutA_output_ports.size() != 2)
 				continue;
 
-			for (auto port : lutA_output_ports)
+			for (auto &port : lutA_output_ports)
 			{
 				if (port.cell == lutA)
 					continue;
@@ -128,6 +215,7 @@ struct OptLutWorker
 					SigSpec lutB_output = sigmap(lutB->getPort("\\Y")[0]);
 					int lutB_width = lutB->getParam("\\WIDTH").as_int();
 					int lutB_arity = luts_arity[lutB];
+					pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
 
 					log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
 
@@ -140,7 +228,7 @@ struct OptLutWorker
 					}
 					for (auto &bit : lutB_input)
 					{
-						if(bit.wire)
+						if (bit.wire)
 							lutB_inputs.insert(sigmap(bit));
 					}
 
@@ -152,7 +240,15 @@ struct OptLutWorker
 					}
 
 					int lutM_arity = lutA_arity + lutB_arity - 1 - common_inputs.size();
-					log("  Cell A is a %d-LUT. Cell B is a %d-LUT. Cells share %zu input(s) and can be merged into one %d-LUT.\n", lutA_arity, lutB_arity, common_inputs.size(), lutM_arity);
+					if (lutA_dlogic_inputs.size())
+						log("  Cell A is a %d-LUT with %zu dedicated connections. ", lutA_arity, lutA_dlogic_inputs.size());
+					else
+						log("  Cell A is a %d-LUT. ", lutA_arity);
+					if (lutB_dlogic_inputs.size())
+						log("Cell B is a %d-LUT with %zu dedicated connections.\n", lutB_arity, lutB_dlogic_inputs.size());
+					else
+						log("Cell B is a %d-LUT.\n", lutB_arity);
+					log("  Cells share %zu input(s) and can be merged into one %d-LUT.\n", common_inputs.size(), lutM_arity);
 
 					const int COMBINE_A = 1, COMBINE_B = 2, COMBINE_EITHER = COMBINE_A | COMBINE_B;
 					int combine_mask = 0;
@@ -160,6 +256,10 @@ struct OptLutWorker
 					{
 						log("  Not combining LUTs into cell A (combined LUT wider than cell A).\n");
 					}
+					else if (lutB_dlogic_inputs.size() > 0)
+					{
+						log("  Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
+					}
 					else if (lutB->get_bool_attribute("\\lut_keep"))
 					{
 						log("  Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
@@ -172,6 +272,10 @@ struct OptLutWorker
 					{
 						log("  Not combining LUTs into cell B (combined LUT wider than cell B).\n");
 					}
+					else if (lutA_dlogic_inputs.size() > 0)
+					{
+						log("  Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
+					}
 					else if (lutA->get_bool_attribute("\\lut_keep"))
 					{
 						log("  Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
@@ -204,11 +308,13 @@ struct OptLutWorker
 
 					RTLIL::Cell *lutM, *lutR;
 					pool<SigBit> lutM_inputs, lutR_inputs;
+					pool<int> lutM_dlogic_inputs;
 					if (combine == COMBINE_A)
 					{
 						log("  Combining LUTs into cell A.\n");
 						lutM = lutA;
 						lutM_inputs = lutA_inputs;
+						lutM_dlogic_inputs = lutA_dlogic_inputs;
 						lutR = lutB;
 						lutR_inputs = lutB_inputs;
 					}
@@ -217,6 +323,7 @@ struct OptLutWorker
 						log("  Combining LUTs into cell B.\n");
 						lutM = lutB;
 						lutM_inputs = lutB_inputs;
+						lutM_dlogic_inputs = lutB_dlogic_inputs;
 						lutR = lutA;
 						lutR_inputs = lutA_inputs;
 					}
@@ -238,7 +345,13 @@ struct OptLutWorker
 					std::vector<SigBit> lutM_new_inputs;
 					for (int i = 0; i < lutM_width; i++)
 					{
-						if ((!lutM_input[i].wire || sigmap(lutM_input[i]) == lutA_output) && lutR_unique.size())
+						bool input_unused = false;
+						if (sigmap(lutM_input[i]) == lutA_output)
+							input_unused = true;
+						if (!lutM_input[i].wire && !lutM_dlogic_inputs.count(i))
+							input_unused = true;
+
+						if (input_unused && lutR_unique.size())
 						{
 							SigBit new_input = lutR_unique.pop();
 							log("    Connecting input %d as %s.\n", i, log_signal(new_input));
@@ -246,7 +359,7 @@ struct OptLutWorker
 						}
 						else if (sigmap(lutM_input[i]) == lutA_output)
 						{
-							log("    Disconnecting input %d.\n", i);
+							log("    Disconnecting cascade input %d.\n", i);
 							lutM_new_inputs.push_back(SigBit());
 						}
 						else
@@ -292,26 +405,59 @@ struct OptLutWorker
 	}
 };
 
+static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
+{
+	size_t start = 0, end = 0;
+	while ((end = text.find(sep, start)) != std::string::npos) {
+		tokens.push_back(text.substr(start, end - start));
+		start = end + 1;
+	}
+	tokens.push_back(text.substr(start));
+}
+
 struct OptLutPass : public Pass {
 	OptLutPass() : Pass("opt_lut", "optimize LUT cells") { }
 	void help() YS_OVERRIDE
 	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    opt_lut [options] [selection]\n");
 		log("\n");
 		log("This pass combines cascaded $lut cells with unused inputs.\n");
 		log("\n");
+		log("    -dlogic <type>:<cell-port>=<LUT-input>[:<cell-port>=<LUT-input>...]\n");
+		log("        preserve connections to dedicated logic cell <type> that has ports\n");
+		log("        <cell-port> connected to LUT inputs <LUT-input>. this includes\n");
+		log("        the case where both LUT and dedicated logic input are connected to\n");
+		log("        the same constant.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
 
+		dict<IdString, dict<int, IdString>> dlogic;
+
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-???") {
-			// 	continue;
-			// }
+			if (args[argidx] == "-dlogic" && argidx+1 < args.size()) {
+				std::vector<std::string> tokens;
+				split(tokens, args[++argidx], ':');
+				if (tokens.size() < 2)
+					log_cmd_error("The -dlogic option requires at least one connection.\n");
+				IdString type = "\\" + tokens[0];
+				for (auto it = tokens.begin() + 1; it != tokens.end(); ++it) {
+					std::vector<std::string> conn_tokens;
+					split(conn_tokens, *it, '=');
+					if (conn_tokens.size() != 2)
+						log_cmd_error("Invalid format of -dlogic signal mapping.\n");
+					IdString logic_port = "\\" + conn_tokens[0];
+					int lut_input = atoi(conn_tokens[1].c_str());
+					dlogic[type][lut_input] = logic_port;
+				}
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -319,7 +465,7 @@ struct OptLutPass : public Pass {
 		int total_count = 0;
 		for (auto module : design->selected_modules())
 		{
-			OptLutWorker worker(module);
+			OptLutWorker worker(dlogic, module);
 			total_count += worker.combined_count;
 		}
 		if (total_count)
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 7094db50d..cc4627cd3 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -268,8 +268,8 @@ struct SynthIce40Pass : public ScriptPass
 			run("abc -lut 4");
 			run("clean");
 			if (relut || help_mode) {
-				run("ice40_unlut", "(only if -relut)");
-				run("opt_lut", "    (only if -relut)");
+				run("ice40_unlut", "                            (only if -relut)");
+				run("opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3", "(only if -relut)");
 			}
 		}
 
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 1c7dc1473..86ad93bb3 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -3,7 +3,7 @@ synth_ice40
 ice40_unlut
 design -save preopt
 
-opt_lut
+opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
 design -stash postopt
 
 design -copy-from preopt -as preopt top

From 2d98db73e39f17865ae26cdd00cf7c112521649f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 5 Dec 2018 18:03:58 +0100
Subject: [PATCH 201/528] Rename opt_lut.cpp to opt_lut.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/{opt_lut.cpp => opt_lut.cc} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename passes/opt/{opt_lut.cpp => opt_lut.cc} (100%)

diff --git a/passes/opt/opt_lut.cpp b/passes/opt/opt_lut.cc
similarity index 100%
rename from passes/opt/opt_lut.cpp
rename to passes/opt/opt_lut.cc

From 12596b5003bcc6180cda04ce2aaaa2a8145f8a9b Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 04:32:01 +0000
Subject: [PATCH 202/528] Fix typo.

---
 techlibs/common/simcells.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 937512e7c..289673e82 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -465,7 +465,7 @@ endmodule
 //-
 //-     $_SR_NP_ (S, R, Q)
 //-
-//- A set-reset latch with negative polarity SET and positive polarioty RESET.
+//- A set-reset latch with negative polarity SET and positive polarity RESET.
 //-
 //- Truth table:    S R | Q
 //-                -----+---
@@ -489,7 +489,7 @@ endmodule
 //-
 //-     $_SR_PN_ (S, R, Q)
 //-
-//- A set-reset latch with positive polarity SET and negative polarioty RESET.
+//- A set-reset latch with positive polarity SET and negative polarity RESET.
 //-
 //- Truth table:    S R | Q
 //-                -----+---

From 9ef078848a5b121336b83043c565ce47433eb2d8 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 04:50:38 +0000
Subject: [PATCH 203/528] gate2lut: new techlib, for converting Yosys gates to
 FPGA LUTs.

---
 techlibs/common/Makefile.inc |  1 +
 techlibs/common/gate2lut.v   | 87 ++++++++++++++++++++++++++++++++++++
 tests/lut/.gitignore         |  1 +
 tests/lut/check_map.ys       | 13 ++++++
 tests/lut/map_and.v          |  5 +++
 tests/lut/map_mux.v          |  5 +++
 tests/lut/map_not.v          |  5 +++
 tests/lut/map_or.v           |  5 +++
 tests/lut/map_xor.v          |  5 +++
 tests/lut/run-test.sh        |  6 +++
 10 files changed, 133 insertions(+)
 create mode 100644 techlibs/common/gate2lut.v
 create mode 100644 tests/lut/.gitignore
 create mode 100644 tests/lut/check_map.ys
 create mode 100644 tests/lut/map_and.v
 create mode 100644 tests/lut/map_mux.v
 create mode 100644 tests/lut/map_not.v
 create mode 100644 tests/lut/map_or.v
 create mode 100644 tests/lut/map_xor.v
 create mode 100644 tests/lut/run-test.sh

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index ab961ac0b..70074f653 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -25,5 +25,6 @@ $(eval $(call add_share_file,share,techlibs/common/techmap.v))
 $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
 $(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
 $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
+$(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
 
diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
new file mode 100644
index 000000000..99c123f4a
--- /dev/null
+++ b/techlibs/common/gate2lut.v
@@ -0,0 +1,87 @@
+(* techmap_celltype = "$_NOT_" *)
+module _90_lut_not (A, Y);
+    input A;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b01)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_OR_" *)
+module _90_lut_or (A, B, Y);
+    input A, B;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b1110)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_AND_" *)
+module _90_lut_and (A, B, Y);
+    input A, B;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b1000)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_XOR_" *)
+module _90_lut_xor (A, B, Y);
+    input A, B;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        .LUT(4'b0110)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
+
+(* techmap_celltype = "$_MUX_" *)
+module _90_lut_mux (A, B, S, Y);
+    input A, B, S;
+    output Y;
+
+    wire [`LUT_WIDTH-1:0] AA;
+    assign AA = {S, B, A};
+
+    \$lut #(
+        .WIDTH(`LUT_WIDTH),
+        //     A 1010 1010
+        //     B 1100 1100
+        //     S 1111 0000
+        .LUT(8'b_1100_1010)
+    ) lut (
+        .A(AA),
+        .Y(Y)
+    );
+endmodule
diff --git a/tests/lut/.gitignore b/tests/lut/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/lut/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
new file mode 100644
index 000000000..6d659891f
--- /dev/null
+++ b/tests/lut/check_map.ys
@@ -0,0 +1,13 @@
+design -save preopt
+
+simplemap
+techmap -map +/gate2lut.v -D LUT_WIDTH=4
+select -assert-count 1 t:$lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/lut/map_and.v b/tests/lut/map_and.v
new file mode 100644
index 000000000..68ae33fd6
--- /dev/null
+++ b/tests/lut/map_and.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b;
+    output y;
+    assign y = a&b;
+endmodule
diff --git a/tests/lut/map_mux.v b/tests/lut/map_mux.v
new file mode 100644
index 000000000..ccecf3023
--- /dev/null
+++ b/tests/lut/map_mux.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b, s;
+    output y;
+    assign y = s?a:b;
+endmodule
diff --git a/tests/lut/map_not.v b/tests/lut/map_not.v
new file mode 100644
index 000000000..385997414
--- /dev/null
+++ b/tests/lut/map_not.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a;
+    output y;
+    assign y = ~a;
+endmodule
diff --git a/tests/lut/map_or.v b/tests/lut/map_or.v
new file mode 100644
index 000000000..8b8c55188
--- /dev/null
+++ b/tests/lut/map_or.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b;
+    output y;
+    assign y = a|b;
+endmodule
diff --git a/tests/lut/map_xor.v b/tests/lut/map_xor.v
new file mode 100644
index 000000000..708a05789
--- /dev/null
+++ b/tests/lut/map_xor.v
@@ -0,0 +1,5 @@
+module top(...);
+    input a, b;
+    output y;
+    assign y = a^b;
+endmodule
diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh
new file mode 100644
index 000000000..207417fa6
--- /dev/null
+++ b/tests/lut/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.v; do
+  echo "Running $x.."
+  ../../yosys -q -s check_map.ys -l ${x%.v}.log $x
+done

From d9fa4387c97745c558acdd8ea7f436917302796e Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 05:24:15 +0000
Subject: [PATCH 204/528] synth_ice40: add -noabc option, to use built-in LUT
 techmapping.

This should be combined with -relut to get sensible results.
---
 techlibs/ice40/synth_ice40.cc | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index cc4627cd3..931a190e7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
 		log("\n");
+		log("    -noabc\n");
+		log("        use built-in Yosys LUT techmapping instead of abc\n");
+		log("\n");
 		log("    -abc2\n");
 		log("        run two passes of 'abc' for slightly improved logic density\n");
 		log("\n");
@@ -93,7 +96,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool nocarry, nodffe, nobram, flatten, retime, relut, abc2, vpr;
+	bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass
 		flatten = true;
 		retime = false;
 		relut = false;
+		noabc = false;
 		abc2 = false;
 		vpr = false;
 	}
@@ -177,6 +181,10 @@ struct SynthIce40Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
+			if (args[argidx] == "-noabc") {
+				noabc = true;
+				continue;
+			}
 			if (args[argidx] == "-abc2") {
 				abc2 = true;
 				continue;
@@ -265,7 +273,13 @@ struct SynthIce40Pass : public ScriptPass
 				run("ice40_opt", "(only if -abc2)");
 			}
 			run("techmap -map +/ice40/latches_map.v");
-			run("abc -lut 4");
+			if (noabc || help_mode) {
+				run("simplemap", "                               (only if -noabc)");
+				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
+			}
+			if (!noabc) {
+				run("abc -lut 4", "(skip if -noabc)");
+			}
 			run("clean");
 			if (relut || help_mode) {
 				run("ice40_unlut", "                            (only if -relut)");

From 88217d0157a1dd11a8151542adaed5d0a1c90149 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 19:12:02 +0000
Subject: [PATCH 205/528] opt_lut: simplify type conversion. NFC.

---
 passes/opt/opt_lut.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index befe346a3..3c4cb95bb 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -58,7 +58,7 @@ struct OptLutWorker
 			}
 		}
 
-		return lut_table.extract(lut_index).as_int();
+		return lut_table.extract(lut_index).as_bool();
 	}
 
 	void show_stats_by_arity()

From d1f2cb01dcde4bd8972e28df9e600a4060b77344 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 19:27:48 +0000
Subject: [PATCH 206/528] lut2mux: handle 1-bit INIT constant in $lut cells.

This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
---
 passes/techmap/lut2mux.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index d32bbff14..a4ed79550 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -32,7 +32,7 @@ int lut2mux(Cell *cell)
 
 	if (GetSize(sig_a) == 1)
 	{
-		cell->module->addMuxGate(NEW_ID, lut[0], lut[1], sig_a, sig_y);
+		cell->module->addMuxGate(NEW_ID, lut.extract(0)[0], lut.extract(1)[0], sig_a, sig_y);
 	}
 	else
 	{

From a9baee4b24a2e2d854d96b9d38e53f3cc4e1262a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 20:34:53 +0000
Subject: [PATCH 207/528] rename: add -src, for inferring names from source
 locations.

---
 passes/cmds/rename.cc | 50 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index dce576fdf..4b4af0a40 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -52,6 +52,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 	log_cmd_error("Object `%s' not found!\n", from_name.c_str());
 }
 
+static std::string derive_name_from_src(const std::string &src, int counter)
+{
+	std::string src_base = src.substr(0, src.find('|'));
+	if (src_base.empty())
+		return stringf("$%d", counter);
+	else
+		return stringf("\\%s$%d", src_base.c_str(), counter);
+}
+
 struct RenamePass : public Pass {
 	RenamePass() : Pass("rename", "rename object in the design") { }
 	void help() YS_OVERRIDE
@@ -63,6 +72,10 @@ struct RenamePass : public Pass {
 		log("Rename the specified object. Note that selection patterns are not supported\n");
 		log("by this command.\n");
 		log("\n");
+		log("    rename -src [selection]\n");
+		log("\n");
+		log("Assign names auto-generated from the src attribute to all selected wires and\n");
+		log("cells with private names.\n");
 		log("\n");
 		log("    rename -enumerate [-pattern <pattern>] [selection]\n");
 		log("\n");
@@ -84,6 +97,7 @@ struct RenamePass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		std::string pattern_prefix = "_", pattern_suffix = "_";
+		bool flag_src = false;
 		bool flag_enumerate = false;
 		bool flag_hide = false;
 		bool flag_top = false;
@@ -93,6 +107,11 @@ struct RenamePass : public Pass {
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
 			std::string arg = args[argidx];
+			if (arg == "-src" && !got_mode) {
+				flag_src = true;
+				got_mode = true;
+				continue;
+			}
 			if (arg == "-enumerate" && !got_mode) {
 				flag_enumerate = true;
 				got_mode = true;
@@ -117,6 +136,37 @@ struct RenamePass : public Pass {
 			break;
 		}
 
+		if (flag_src)
+		{
+			extra_args(args, argidx, design);
+
+			for (auto &mod : design->modules_)
+			{
+				int counter = 0;
+
+				RTLIL::Module *module = mod.second;
+				if (!design->selected(module))
+					continue;
+
+				dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				for (auto &it : module->wires_) {
+					if (it.first[0] == '$' && design->selected(module, it.second))
+						it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++);
+					new_wires[it.second->name] = it.second;
+				}
+				module->wires_.swap(new_wires);
+				module->fixup_ports();
+
+				dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				for (auto &it : module->cells_) {
+					if (it.first[0] == '$' && design->selected(module, it.second))
+						it.second->name = derive_name_from_src(it.second->get_src_attribute(), counter++);
+					new_cells[it.second->name] = it.second;
+				}
+				module->cells_.swap(new_cells);
+			}
+		}
+		else
 		if (flag_enumerate)
 		{
 			extra_args(args, argidx, design);

From 910d94b21214b78d841cfb32a724c4f0ea8b365d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Dec 2018 07:21:50 +0100
Subject: [PATCH 208/528] Verific updates

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile                     |  2 +-
 frontends/verific/verific.cc | 53 ------------------------------------
 2 files changed, 1 insertion(+), 54 deletions(-)

diff --git a/Makefile b/Makefile
index 053796e9d..8da6315fb 100644
--- a/Makefile
+++ b/Makefile
@@ -357,7 +357,7 @@ endif
 
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
-VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree
+VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)
 LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-mac.a,$(VERIFIC_COMPONENTS)) -lz
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 971f0b24a..bc035c31a 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2094,42 +2094,6 @@ struct VerificPass : public Pass {
 
 			if (mode_all)
 			{
-#if 0
-				log("Running veri_file::ElaborateAll().\n");
-				if (!veri_file::ElaborateAll())
-					log_cmd_error("Elaboration of Verilog modules failed.\n");
-
-				log("Running vhdl_file::ElaborateAll().\n");
-				if (!vhdl_file::ElaborateAll())
-					log_cmd_error("Elaboration of VHDL modules failed.\n");
-
-				Library *lib = Netlist::PresentDesign()->Owner()->Owner();
-
-				if (argidx == GetSize(args))
-				{
-					MapIter iter;
-					char *iter_name;
-					Verific::Cell *iter_cell;
-
-					FOREACH_MAP_ITEM(lib->GetCells(), iter, &iter_name, &iter_cell) {
-						if (*iter_name != '$')
-							nl_todo.insert(iter_cell->GetFirstNetlist());
-					}
-				}
-				else
-				{
-					for (; argidx < GetSize(args); argidx++)
-					{
-						Verific::Cell *cell = lib->GetCell(args[argidx].c_str());
-
-						if (cell == nullptr)
-							log_cmd_error("Module not found: %s\n", args[argidx].c_str());
-
-						nl_todo.insert(cell->GetFirstNetlist());
-						cell->GetFirstNetlist()->SetPresentDesign();
-					}
-				}
-#else
 				log("Running hier_tree::ElaborateAll().\n");
 
 				VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
@@ -2146,28 +2110,12 @@ struct VerificPass : public Pass {
 				FOREACH_ARRAY_ITEM(netlists, i, nl)
 					nl_todo.insert(nl);
 				delete netlists;
-#endif
 			}
 			else
 			{
 				if (argidx == GetSize(args))
 					log_cmd_error("No top module specified.\n");
 
-#if 0
-				for (; argidx < GetSize(args); argidx++) {
-					if (veri_file::GetModule(args[argidx].c_str())) {
-						log("Running veri_file::Elaborate(\"%s\").\n", args[argidx].c_str());
-						if (!veri_file::Elaborate(args[argidx].c_str()))
-							log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
-						nl_todo.insert(Netlist::PresentDesign());
-					} else {
-						log("Running vhdl_file::Elaborate(\"%s\").\n", args[argidx].c_str());
-						if (!vhdl_file::Elaborate(args[argidx].c_str()))
-							log_cmd_error("Elaboration of top module `%s' failed.\n", args[argidx].c_str());
-						nl_todo.insert(Netlist::PresentDesign());
-					}
-				}
-#else
 				Array veri_modules, vhdl_units;
 				for (; argidx < GetSize(args); argidx++)
 				{
@@ -2199,7 +2147,6 @@ struct VerificPass : public Pass {
 				FOREACH_ARRAY_ITEM(netlists, i, nl)
 					nl_todo.insert(nl);
 				delete netlists;
-#endif
 			}
 
 			if (!verific_error_msg.empty())

From 643f858acffcb40cce4686a5a039dc80c18b933d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Dec 2018 07:29:21 +0100
Subject: [PATCH 209/528] Bugfix in opt_expr handling of a<0 and a>=0

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/opt_expr.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 0ba233c62..610edc5e9 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1406,7 +1406,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
 			{
 				if (sigConst.is_fully_zero()) {
-					RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
+					RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y")));
 					if (is_lt) {
 						log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
 								log_id(cell->type), log_id(cell));

From 7d1088afc453f57f0ecc0f55ac2c91fd72ad8f2e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 6 Dec 2018 07:29:37 +0100
Subject: [PATCH 210/528] Add missing .gitignore

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/svinterfaces/.gitignore | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 tests/svinterfaces/.gitignore

diff --git a/tests/svinterfaces/.gitignore b/tests/svinterfaces/.gitignore
new file mode 100644
index 000000000..a5b7927d1
--- /dev/null
+++ b/tests/svinterfaces/.gitignore
@@ -0,0 +1,8 @@
+/a.out
+/dut_result.txt
+/reference_result.txt
+/*.diff
+/*.log_stderr
+/*.log_stdout
+/*_ref_syn.v
+/*_syn.v

From 6e559ee3c78c0984e1f486ecedf61c3011aa0f0d Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Dec 2018 12:02:42 +0000
Subject: [PATCH 211/528] synth_ice40: split `map_gates` off `fine`.

---
 techlibs/ice40/synth_ice40.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 931a190e7..37b924dfd 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,6 +240,10 @@ struct SynthIce40Pass : public ScriptPass
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
+		}
+
+		if (check_label("map_gates"))
+		{
 			if (nocarry)
 				run("techmap");
 			else

From 1dfb2fecabae120e9c1ca1f214163857b524e718 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 4 Dec 2018 14:17:47 +0000
Subject: [PATCH 212/528] abc: Preserve naming through ABC using 'dress'
 command

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/techmap/abc.cc | 80 +++++++++++++++++++++++++++----------------
 1 file changed, 51 insertions(+), 29 deletions(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d2d15a4a9..d3bdd555b 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -329,6 +329,18 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 std::string remap_name(RTLIL::IdString abc_name)
 {
+	std::string abc_sname = abc_name.substr(1);
+	if (abc_sname.substr(0, 5) == "ys__n") {
+		int sid = std::stoi(abc_sname.substr(5));
+		bool inv = abc_sname.back() == 'v';
+		for (auto sig : signal_list) {
+			if (sig.id == sid) {
+				std::stringstream sstr;
+				sstr << "$abc$" << map_autoidx << "$" << log_signal(sig.bit) << (inv ? "_inv" : "");
+				return sstr.str();
+			}
+		}
+	}
 	std::stringstream sstr;
 	sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
 	return sstr.str();
@@ -353,12 +365,12 @@ void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std:
 	}
 
 	for (auto n : nodes)
-		fprintf(f, "  n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
+		fprintf(f, "  ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
 				n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
 
 	for (auto &e : edges)
 	for (auto n : e.second)
-		fprintf(f, "  n%d -> n%d;\n", e.first, n);
+		fprintf(f, "  ys__n%d -> ys__n%d;\n", e.first, n);
 
 	fprintf(f, "}\n");
 }
@@ -624,7 +636,7 @@ struct abc_output_filter
 void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 		std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
 		bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
+		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
 {
 	module = current_module;
 	map_autoidx = autoidx++;
@@ -728,7 +740,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 	for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
 		abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
-
+	if (abc_dress)
+		abc_script += "; dress";
 	abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
 	abc_script = add_echos_to_abc_cmd(abc_script);
 
@@ -784,7 +797,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	for (auto &si : signal_list) {
 		if (!si.is_port || si.type != G(NONE))
 			continue;
-		fprintf(f, " n%d", si.id);
+		fprintf(f, " ys__n%d", si.id);
 		pi_map[count_input++] = log_signal(si.bit);
 	}
 	if (count_input == 0)
@@ -796,17 +809,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	for (auto &si : signal_list) {
 		if (!si.is_port || si.type == G(NONE))
 			continue;
-		fprintf(f, " n%d", si.id);
+		fprintf(f, " ys__n%d", si.id);
 		po_map[count_output++] = log_signal(si.bit);
 	}
 	fprintf(f, "\n");
 
 	for (auto &si : signal_list)
-		fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
+		fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit));
 
 	for (auto &si : signal_list) {
 		if (si.bit.wire == NULL) {
-			fprintf(f, ".names n%d\n", si.id);
+			fprintf(f, ".names ys__n%d\n", si.id);
 			if (si.bit == RTLIL::State::S1)
 				fprintf(f, "1\n");
 		}
@@ -815,68 +828,68 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	int count_gates = 0;
 	for (auto &si : signal_list) {
 		if (si.type == G(BUF)) {
-			fprintf(f, ".names n%d n%d\n", si.in1, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
 			fprintf(f, "1 1\n");
 		} else if (si.type == G(NOT)) {
-			fprintf(f, ".names n%d n%d\n", si.in1, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
 			fprintf(f, "0 1\n");
 		} else if (si.type == G(AND)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "11 1\n");
 		} else if (si.type == G(NAND)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "0- 1\n");
 			fprintf(f, "-0 1\n");
 		} else if (si.type == G(OR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "-1 1\n");
 			fprintf(f, "1- 1\n");
 		} else if (si.type == G(NOR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "00 1\n");
 		} else if (si.type == G(XOR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "01 1\n");
 			fprintf(f, "10 1\n");
 		} else if (si.type == G(XNOR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "00 1\n");
 			fprintf(f, "11 1\n");
 		} else if (si.type == G(ANDNOT)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "10 1\n");
 		} else if (si.type == G(ORNOT)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "1- 1\n");
 			fprintf(f, "-0 1\n");
 		} else if (si.type == G(MUX)) {
-			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "1-0 1\n");
 			fprintf(f, "-11 1\n");
 		} else if (si.type == G(AOI3)) {
-			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "-00 1\n");
 			fprintf(f, "0-0 1\n");
 		} else if (si.type == G(OAI3)) {
-			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "00- 1\n");
 			fprintf(f, "--0 1\n");
 		} else if (si.type == G(AOI4)) {
-			fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
 			fprintf(f, "-0-0 1\n");
 			fprintf(f, "-00- 1\n");
 			fprintf(f, "0--0 1\n");
 			fprintf(f, "0-0- 1\n");
 		} else if (si.type == G(OAI4)) {
-			fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
 			fprintf(f, "00-- 1\n");
 			fprintf(f, "--00 1\n");
 		} else if (si.type == G(FF)) {
 			if (si.init == State::S0 || si.init == State::S1) {
-				fprintf(f, ".latch n%d n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
+				fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
 				recover_init = true;
 			} else
-				fprintf(f, ".latch n%d n%d 2\n", si.in1, si.id);
+				fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
 		} else if (si.type != G(NONE))
 			log_abort();
 		if (si.type != G(NONE))
@@ -889,7 +902,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
 			count_gates, GetSize(signal_list), count_input, count_output);
 	log_push();
-
 	if (count_output > 0)
 	{
 		log_header(design, "Executing ABC.\n");
@@ -1213,7 +1225,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		for (auto &si : signal_list)
 			if (si.is_port) {
 				char buffer[100];
-				snprintf(buffer, 100, "\\n%d", si.id);
+				snprintf(buffer, 100, "\\ys__n%d", si.id);
 				RTLIL::SigSig conn;
 				if (si.type != G(NONE)) {
 					conn.first = si.bit;
@@ -1407,6 +1419,11 @@ struct AbcPass : public Pass {
 		log("        this attribute is a unique integer for each ABC process started. This\n");
 		log("        is useful for debugging the partitioning of clock domains.\n");
 		log("\n");
+		log("    -dress\n");
+		log("        run the 'dress' command after all other ABC commands. This aims to\n");
+		log("        preserve naming by an equivalence check between the original and post-ABC\n");
+		log("        netlists (experimental).\n");
+		log("\n");
 		log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
 		log("\n");
@@ -1441,6 +1458,7 @@ struct AbcPass : public Pass {
 		std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false, sop_mode = false;
+		bool abc_dress = false;
 		vector<int> lut_costs;
 		markgroups = false;
 
@@ -1555,6 +1573,10 @@ struct AbcPass : public Pass {
 				map_mux16 = true;
 				continue;
 			}
+			if (arg == "-dress") {
+				abc_dress = true;
+				continue;
+			}
 			if (arg == "-g" && argidx+1 < args.size()) {
 				for (auto g : split_tokens(args[++argidx], ",")) {
 					vector<string> gate_list;
@@ -1704,7 +1726,7 @@ struct AbcPass : public Pass {
 
 			if (!dff_mode || !clk_str.empty()) {
 				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
+						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
 				continue;
 			}
 
@@ -1849,7 +1871,7 @@ struct AbcPass : public Pass {
 				en_polarity = std::get<2>(it.first);
 				en_sig = assign_map(std::get<3>(it.first));
 				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
+						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
 				assign_map.set(mod);
 			}
 		}

From 889297c62a6e99c41995bcb3606e8be4490a2c9c Mon Sep 17 00:00:00 2001
From: Olof Kindgren <olof.kindgren@gmail.com>
Date: Thu, 6 Dec 2018 21:45:59 +0100
Subject: [PATCH 213/528] Only use non-blocking assignments of SB_RAM40_4K for
 yosys

In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.

Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.

This patch will change to use non-blocking assignments only for yosys
---
 techlibs/ice40/cells_sim.v | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e0a07af32..a2a842275 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -409,6 +409,7 @@ module SB_RAM40_4K (
 
 	initial begin
 		for (i=0; i<16; i=i+1) begin
+`ifdef YOSYS
 			memory[ 0*16 + i] <= INIT_0[16*i +: 16];
 			memory[ 1*16 + i] <= INIT_1[16*i +: 16];
 			memory[ 2*16 + i] <= INIT_2[16*i +: 16];
@@ -425,6 +426,24 @@ module SB_RAM40_4K (
 			memory[13*16 + i] <= INIT_D[16*i +: 16];
 			memory[14*16 + i] <= INIT_E[16*i +: 16];
 			memory[15*16 + i] <= INIT_F[16*i +: 16];
+`else
+			memory[ 0*16 + i] = INIT_0[16*i +: 16];
+			memory[ 1*16 + i] = INIT_1[16*i +: 16];
+			memory[ 2*16 + i] = INIT_2[16*i +: 16];
+			memory[ 3*16 + i] = INIT_3[16*i +: 16];
+			memory[ 4*16 + i] = INIT_4[16*i +: 16];
+			memory[ 5*16 + i] = INIT_5[16*i +: 16];
+			memory[ 6*16 + i] = INIT_6[16*i +: 16];
+			memory[ 7*16 + i] = INIT_7[16*i +: 16];
+			memory[ 8*16 + i] = INIT_8[16*i +: 16];
+			memory[ 9*16 + i] = INIT_9[16*i +: 16];
+			memory[10*16 + i] = INIT_A[16*i +: 16];
+			memory[11*16 + i] = INIT_B[16*i +: 16];
+			memory[12*16 + i] = INIT_C[16*i +: 16];
+			memory[13*16 + i] = INIT_D[16*i +: 16];
+			memory[14*16 + i] = INIT_E[16*i +: 16];
+			memory[15*16 + i] = INIT_F[16*i +: 16];
+`endif
 		end
 	end
 

From a8ab7228240fb227f4178ca02037cdcf897ee19e Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 16:31:15 +0000
Subject: [PATCH 214/528] opt_lut: add -limit option, for debugging
 misoptimizations.

---
 passes/opt/opt_lut.cc | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index befe346a3..ee3943f9c 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -93,7 +93,7 @@ struct OptLutWorker
 		}
 	}
 
-	OptLutWorker(dict<IdString, dict<int, IdString>> &dlogic, RTLIL::Module *module) :
+	OptLutWorker(dict<IdString, dict<int, IdString>> &dlogic, RTLIL::Module *module, int limit) :
 		dlogic(dlogic), module(module), index(module), sigmap(module)
 	{
 		log("Discovering LUTs.\n");
@@ -192,6 +192,12 @@ struct OptLutWorker
 		pool<RTLIL::Cell*> worklist = luts;
 		while (worklist.size())
 		{
+			if (limit == 0)
+			{
+				log("Limit reached.\n");
+				break;
+			}
+
 			auto lutA = worklist.pop();
 			SigSpec lutA_input = sigmap(lutA->getPort("\\A"));
 			SigSpec lutA_output = sigmap(lutA->getPort("\\Y")[0]);
@@ -398,6 +404,8 @@ struct OptLutWorker
 					worklist.erase(lutR);
 
 					combined_count++;
+					if (limit > 0)
+						limit--;
 				}
 			}
 		}
@@ -431,17 +439,22 @@ struct OptLutPass : public Pass {
 		log("        the case where both LUT and dedicated logic input are connected to\n");
 		log("        the same constant.\n");
 		log("\n");
+		log("    -limit N\n");
+		log("        only perform the first N combines, then stop. useful for debugging.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing OPT_LUT pass (optimize LUTs).\n");
 
 		dict<IdString, dict<int, IdString>> dlogic;
+		int limit = -1;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			if (args[argidx] == "-dlogic" && argidx+1 < args.size()) {
+			if (args[argidx] == "-dlogic" && argidx+1 < args.size())
+			{
 				std::vector<std::string> tokens;
 				split(tokens, args[++argidx], ':');
 				if (tokens.size() < 2)
@@ -458,6 +471,11 @@ struct OptLutPass : public Pass {
 				}
 				continue;
 			}
+			if (args[argidx] == "-limit" && argidx + 1 < args.size())
+			{
+				limit = atoi(args[++argidx].c_str());
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -465,7 +483,7 @@ struct OptLutPass : public Pass {
 		int total_count = 0;
 		for (auto module : design->selected_modules())
 		{
-			OptLutWorker worker(dlogic, module);
+			OptLutWorker worker(dlogic, module, limit - total_count);
 			total_count += worker.combined_count;
 		}
 		if (total_count)

From 9eb03d458dcb2a3ba91a84739e764558b26e335c Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 17:04:41 +0000
Subject: [PATCH 215/528] opt_lut: show original truth table for both cells.

---
 passes/opt/opt_lut.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index ee3943f9c..4207fbdb9 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -388,8 +388,9 @@ struct OptLutWorker
 						lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
 					}
 
-					log("  Old truth table: %s.\n", lutM->getParam("\\LUT").as_string().c_str());
-					log("  New truth table: %s.\n", lutM_new_table.as_string().c_str());
+					log("  Cell A truth table: %s.\n", lutA->getParam("\\LUT").as_string().c_str());
+					log("  Cell B truth table: %s.\n", lutB->getParam("\\LUT").as_string().c_str());
+					log("  Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
 
 					lutM->setParam("\\LUT", lutM_new_table);
 					lutM->setPort("\\A", lutM_new_inputs);

From 7ec740b7ad4ee4bc02e2564671e0153cdd08152f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 17:13:52 +0000
Subject: [PATCH 216/528] opt_lut: leave intact LUTs with cascade feeding
 module outputs.

---
 passes/opt/opt_lut.cc     |  6 ++++++
 tests/opt/opt_lut_port.il | 18 ++++++++++++++++++
 tests/opt/opt_lut_port.ys |  2 ++
 3 files changed, 26 insertions(+)
 create mode 100644 tests/opt/opt_lut_port.il
 create mode 100644 tests/opt/opt_lut_port.ys

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 4207fbdb9..ba2cc6ee7 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -225,6 +225,12 @@ struct OptLutWorker
 
 					log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
 
+					if (index.query_is_output(lutA->getPort("\\Y")))
+					{
+						log("  Not combining LUTs (cascade connection feeds module output).\n");
+						continue;
+					}
+
 					pool<SigBit> lutA_inputs;
 					pool<SigBit> lutB_inputs;
 					for (auto &bit : lutA_input)
diff --git a/tests/opt/opt_lut_port.il b/tests/opt/opt_lut_port.il
new file mode 100644
index 000000000..7eb71890f
--- /dev/null
+++ b/tests/opt/opt_lut_port.il
@@ -0,0 +1,18 @@
+module $1
+  wire width 4 input 2 \_0_
+  wire output 4 \_1_
+  wire input 3 \_2_
+  wire output 1 \o
+  cell $lut \_3_
+    parameter \LUT 16'0011000000000011
+    parameter \WIDTH 4
+    connect \A { \_0_ [3] \o 2'00 }
+    connect \Y \_1_
+  end
+  cell $lut \_4_
+    parameter \LUT 4'0001
+    parameter \WIDTH 4
+    connect \A { 3'000 \_2_ }
+    connect \Y \o
+  end
+end
diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
new file mode 100644
index 000000000..51dfd988b
--- /dev/null
+++ b/tests/opt/opt_lut_port.ys
@@ -0,0 +1,2 @@
+read_ilang opt_lut_port.il
+select -assert-count 2 t:$lut

From c38ea9ae65b2a987d6a7ea790abf339944069f9a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 6 Dec 2018 14:28:20 +0000
Subject: [PATCH 217/528] equiv_opt: new command, for verifying optimization
 passes.

---
 passes/equiv/Makefile.inc |   2 +-
 passes/equiv/equiv_opt.cc | 165 ++++++++++++++++++++++++++++++++++++++
 tests/lut/check_map.ys    |  13 +--
 tests/opt/opt_lut.ys      |  13 +--
 4 files changed, 169 insertions(+), 24 deletions(-)
 create mode 100644 passes/equiv/equiv_opt.cc

diff --git a/passes/equiv/Makefile.inc b/passes/equiv/Makefile.inc
index dd7b3be02..27ea54b22 100644
--- a/passes/equiv/Makefile.inc
+++ b/passes/equiv/Makefile.inc
@@ -9,4 +9,4 @@ OBJS += passes/equiv/equiv_induct.o
 OBJS += passes/equiv/equiv_struct.o
 OBJS += passes/equiv/equiv_purge.o
 OBJS += passes/equiv/equiv_mark.o
-
+OBJS += passes/equiv/equiv_opt.o
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
new file mode 100644
index 000000000..68593d301
--- /dev/null
+++ b/passes/equiv/equiv_opt.cc
@@ -0,0 +1,165 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  whitequark <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct EquivOptPass : public ScriptPass
+{
+  EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
+
+  void help() YS_OVERRIDE
+  {
+    //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+    log("\n");
+    log("    equiv_opt [options] [command]\n");
+    log("\n");
+    log("This command checks circuit equivalence before and after an optimization pass.\n");
+    log("\n");
+    log("    -run <from_label>:<to_label>\n");
+    log("        only run the commands between the labels (see below). an empty\n");
+    log("        from label is synonymous to the start of the command list, and empty to\n");
+    log("        label is synonymous to the end of the command list.\n");
+    log("\n");
+    log("    -map <filename>\n");
+    log("        expand the modules in this file before proving equivalence. this is\n");
+    log("        useful for handling architecture-specific primitives.\n");
+    log("\n");
+    log("    -assert\n");
+    log("        produce an error if the circuits are not equivalent\n");
+    log("\n");
+    log("The following commands are executed by this verification command:\n");
+    help_script();
+    log("\n");
+  }
+
+  std::string command, techmap_opts;
+  bool assert;
+
+  void clear_flags() YS_OVERRIDE
+  {
+    command = "";
+    techmap_opts = "";
+    assert = false;
+  }
+
+  void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+  {
+    string run_from, run_to;
+    clear_flags();
+
+    size_t argidx;
+    for (argidx = 1; argidx < args.size(); argidx++)
+    {
+      if (args[argidx] == "-run" && argidx+1 < args.size()) {
+        size_t pos = args[argidx+1].find(':');
+        if (pos == std::string::npos)
+          break;
+        run_from = args[++argidx].substr(0, pos);
+        run_to = args[argidx].substr(pos+1);
+        continue;
+      }
+      if (args[argidx] == "-map" && argidx+1 < args.size()) {
+        techmap_opts += " -map " + args[++argidx];
+        continue;
+      }
+      if (args[argidx] == "-assert") {
+        assert = true;
+        continue;
+      }
+      break;
+    }
+
+    for (; argidx < args.size(); argidx++)
+    {
+      if (command.empty())
+      {
+        if (args[argidx].substr(0, 1) == "-")
+          cmd_error(args, argidx, "Unknown option.");
+      }
+      else
+      {
+        command += " ";
+      }
+      command += args[argidx];
+    }
+
+    if (command.empty())
+      log_cmd_error("No optimization pass specified!\n");
+
+    if (!design->full_selection())
+      log_cmd_error("This command only operates on fully selected designs!\n");
+
+    log_header(design, "Executing EQUIV_OPT pass.\n");
+    log_push();
+
+    run_script(design, run_from, run_to);
+
+    log_pop();
+  }
+
+  void script() YS_OVERRIDE
+  {
+    if (check_label("run_pass"))
+    {
+      run("hierarchy -auto-top");
+      run("design -save preopt");
+      if (help_mode)
+        run("[command]");
+      else
+        run(command);
+      run("design -stash postopt");
+    }
+
+    if (check_label("prepare"))
+    {
+      run("design -copy-from preopt  -as gold A:top");
+      run("design -copy-from postopt -as gate A:top");
+    }
+
+    if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)"))
+    {
+      if (help_mode)
+        run("techmap -autoproc -map <filename> ...");
+      else
+        run("techmap -autoproc" + techmap_opts);
+    }
+
+    if (check_label("prove"))
+    {
+      run("equiv_make gold gate equiv");
+      run("equiv_induct equiv");
+      if (help_mode)
+        run("equiv_status [-assert] equiv");
+      else if(assert)
+        run("equiv_status -assert equiv");
+      else
+        run("equiv_status equiv");
+    }
+
+    if (check_label("restore"))
+    {
+      run("design -load preopt");
+    }
+  }
+} EquivOptPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
index 6d659891f..dc0aaffc2 100644
--- a/tests/lut/check_map.ys
+++ b/tests/lut/check_map.ys
@@ -1,13 +1,4 @@
-design -save preopt
-
 simplemap
-techmap -map +/gate2lut.v -D LUT_WIDTH=4
+equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
+design -load postopt
 select -assert-count 1 t:$lut
-design -stash postopt
-
-design -copy-from preopt -as preopt top
-design -copy-from postopt -as postopt top
-equiv_make preopt postopt equiv
-prep -flatten -top equiv
-equiv_induct
-equiv_status -assert
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 86ad93bb3..f3c1e2822 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,15 +1,4 @@
 read_verilog opt_lut.v
 synth_ice40
 ice40_unlut
-design -save preopt
-
-opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
-design -stash postopt
-
-design -copy-from preopt -as preopt top
-design -copy-from postopt -as postopt top
-equiv_make preopt postopt equiv
-techmap -map ice40_carry.v
-prep -flatten -top equiv
-equiv_induct
-equiv_status -assert
+equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3

From 7ff5a9db2d17c384260c2220c9205a7b4891f001 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 16:58:33 +0000
Subject: [PATCH 218/528] equiv_opt: pass -D EQUIV when techmapping.

This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
---
 passes/equiv/equiv_opt.cc  | 6 ++++--
 techlibs/ice40/cells_sim.v | 2 ++
 tests/opt/ice40_carry.v    | 3 ---
 tests/opt/opt_lut.ys       | 2 +-
 4 files changed, 7 insertions(+), 6 deletions(-)
 delete mode 100644 tests/opt/ice40_carry.v

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 68593d301..408afd3e4 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -137,10 +137,12 @@ struct EquivOptPass : public ScriptPass
 
     if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)"))
     {
+      string opts;
       if (help_mode)
-        run("techmap -autoproc -map <filename> ...");
+        opts = " -map <filename> ...";
       else
-        run("techmap -autoproc" + techmap_opts);
+        opts = techmap_opts;
+      run("techmap -D EQUIV -autoproc" + opts);
     }
 
     if (check_label("prove"))
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index e0a07af32..c554c3f35 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -928,6 +928,7 @@ module SB_SPRAM256KA (
 	output reg [15:0] DATAOUT
 );
 `ifndef BLACKBOX
+`ifndef EQUIV
 	reg [15:0] mem [0:16383];
 	wire off = SLEEP || !POWEROFF;
 	integer i;
@@ -954,6 +955,7 @@ module SB_SPRAM256KA (
 		end
 	end
 `endif
+`endif
 endmodule
 
 (* blackbox *)
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
deleted file mode 100644
index ed938932a..000000000
--- a/tests/opt/ice40_carry.v
+++ /dev/null
@@ -1,3 +0,0 @@
-module SB_CARRY (output CO, input I0, I1, CI);
-    assign CO = (I0 && I1) || ((I0 || I1) && CI);
-endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index f3c1e2822..59b12c351 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -1,4 +1,4 @@
 read_verilog opt_lut.v
 synth_ice40
 ice40_unlut
-equiv_opt -map ice40_carry.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
+equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3

From 7fe770a441a129c509fd4da04b60ada942a28bc8 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 18:48:06 +0000
Subject: [PATCH 219/528] write_verilog: correctly map RTLIL `sync init`.

---
 backends/verilog/verilog_backend.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f920..922b4c44c 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1352,6 +1352,8 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 
 		if (sync->type == RTLIL::STa) {
 			f << stringf("%s" "always @* begin\n", indent.c_str());
+		} else if (sync->type == RTLIL::STi) {
+			f << stringf("%s" "initial begin\n", indent.c_str());
 		} else {
 			f << stringf("%s" "always @(", indent.c_str());
 			if (sync->type == RTLIL::STp || sync->type == RTLIL::ST1)

From ed3c57fad3616b981e54e2f209e7ee40ff87c8a7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Dec 2018 06:21:31 +0100
Subject: [PATCH 220/528] Fix btor init value handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/btor/btor.cc | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 58d2a8625..ab2702807 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -506,6 +506,18 @@ struct BtorWorker
 				}
 			}
 
+			Const initval;
+			for (int i = 0; i < GetSize(sig_q); i++)
+				if (initbits.count(sig_q[i]))
+					initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
+				else
+					initval.bits.push_back(State::Sx);
+
+			int nid_init_val = -1;
+
+			if (!initval.is_fully_undef())
+				nid_init_val = get_sig_nid(initval);
+
 			int sid = get_bv_sid(GetSize(sig_q));
 			int nid = next_nid++;
 
@@ -514,15 +526,7 @@ struct BtorWorker
 			else
 				btorf("%d state %d %s\n", nid, sid, log_id(symbol));
 
-			Const initval;
-			for (int i = 0; i < GetSize(sig_q); i++)
-				if (initbits.count(sig_q[i]))
-					initval.bits.push_back(initbits.at(sig_q[i]) ? State::S1 : State::S0);
-				else
-					initval.bits.push_back(State::Sx);
-
-			if (!initval.is_fully_undef()) {
-				int nid_init_val = get_sig_nid(initval);
+			if (nid_init_val >= 0) {
 				int nid_init = next_nid++;
 				if (verbose)
 					btorf("; initval = %s\n", log_signal(initval));

From 47a5dfdaa4bd7d400c6e3d58476de80904df460d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 8 Dec 2018 06:59:27 +0100
Subject: [PATCH 221/528] Add "yosys-smtbmc --btorwit" skeleton

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtbmc.py | 20 +++++++++++++++++++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index b944ee004..57b50ccb6 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -32,6 +32,8 @@ cexfile = None
 aimfile = None
 aiwfile = None
 aigheader = True
+btorfile = None
+witfile = None
 vlogtbfile = None
 vlogtbtop = None
 inconstr = list()
@@ -92,6 +94,10 @@ yosys-smtbmc [options] <yosys_smt2_output>
         the AIGER witness file does not include the status and
         properties lines.
 
+    --btorwit <prefix>
+    --btorwit <btor_filename>:<witness_filename>
+        read a BTOR file and a BTOR witness for that BTOR file.
+
     --noinfo
         only run the core proof, do not collect and print any
         additional information (e.g. which assert failed)
@@ -152,7 +158,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
 
 try:
     opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:igcm:", so.longopts +
-            ["final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "presat",
+            ["final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader", "btorwit=", "presat",
              "dump-vcd=", "dump-vlogtb=", "vlogtb-top=", "dump-smtc=", "dump-all", "noinfo", "append=",
              "smtc-init", "smtc-top=", "noinit"])
 except:
@@ -189,6 +195,12 @@ for o, a in opts:
             aiwfile = a + ".aiw"
     elif o == "--aig-noheader":
         aigheader = False
+    elif o == "--btorwit":
+        if ":" in a:
+            btorfile, witfile = a.split(":")
+        else:
+            btorfile = a + ".btor"
+            witfile = a + ".wit"
     elif o == "--dump-vcd":
         vcdfile = a
     elif o == "--dump-vlogtb":
@@ -575,6 +587,12 @@ if aimfile is not None:
                 num_steps = max(num_steps, step+1)
             step += 1
 
+if btorfile is not None:
+    print("The --btorwit feature is not implemented yet")
+    smt.write("(exit)")
+    smt.wait()
+    sys.exit(1)
+
 def write_vcd_trace(steps_start, steps_stop, index):
     filename = vcdfile.replace("%", index)
     print_msg("Writing trace to VCD file: %s" % (filename))

From add6ab9b2a8d94bee0e7949a4524cc673ec336b1 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Sat, 8 Dec 2018 22:46:28 +0100
Subject: [PATCH 222/528] ice40: Honor the "dont_touch" attribute in FFSSR pass

This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/ice40_ffssr.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/techlibs/ice40/ice40_ffssr.cc b/techlibs/ice40/ice40_ffssr.cc
index 668df09dd..a7649d7a0 100644
--- a/techlibs/ice40/ice40_ffssr.cc
+++ b/techlibs/ice40/ice40_ffssr.cc
@@ -81,6 +81,9 @@ struct Ice40FfssrPass : public Pass {
 
 			for (auto cell : ff_cells)
 			{
+				if (cell->get_bool_attribute("\\dont_touch"))
+					continue;
+
 				SigSpec sig_d = cell->getPort("\\D");
 
 				if (GetSize(sig_d) < 1)

From 0b9bb852c66ec2a6e9b4b510b3e2e32b8c6a6b16 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 10 Dec 2018 03:43:07 +0100
Subject: [PATCH 223/528] Add yosys-smtbmc support for btor witness

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtbmc.py | 115 ++++++++++++++++++++++++++++++++++------
 1 file changed, 100 insertions(+), 15 deletions(-)

diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 57b50ccb6..721a395e3 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -32,8 +32,7 @@ cexfile = None
 aimfile = None
 aiwfile = None
 aigheader = True
-btorfile = None
-witfile = None
+btorwitfile = None
 vlogtbfile = None
 vlogtbtop = None
 inconstr = list()
@@ -94,9 +93,8 @@ yosys-smtbmc [options] <yosys_smt2_output>
         the AIGER witness file does not include the status and
         properties lines.
 
-    --btorwit <prefix>
-    --btorwit <btor_filename>:<witness_filename>
-        read a BTOR file and a BTOR witness for that BTOR file.
+    --btorwit <btor_witness_filename>
+        read a BTOR witness.
 
     --noinfo
         only run the core proof, do not collect and print any
@@ -196,11 +194,7 @@ for o, a in opts:
     elif o == "--aig-noheader":
         aigheader = False
     elif o == "--btorwit":
-        if ":" in a:
-            btorfile, witfile = a.split(":")
-        else:
-            btorfile = a + ".btor"
-            witfile = a + ".wit"
+        btorwitfile = a
     elif o == "--dump-vcd":
         vcdfile = a
     elif o == "--dump-vlogtb":
@@ -587,11 +581,102 @@ if aimfile is not None:
                 num_steps = max(num_steps, step+1)
             step += 1
 
-if btorfile is not None:
-    print("The --btorwit feature is not implemented yet")
-    smt.write("(exit)")
-    smt.wait()
-    sys.exit(1)
+if btorwitfile is not None:
+    with open(btorwitfile, "r") as f:
+        step = None
+        suffix = None
+        altsuffix = None
+        header_okay = False
+
+        for line in f:
+            line = line.strip()
+
+            if line == "sat":
+                header_okay = True
+                continue
+
+            if not header_okay:
+                continue
+
+            if line == "" or line[0] == "b" or line[0] == "j":
+                continue
+
+            if line == ".":
+                break
+
+            if line[0] == '#' or line[0] == '@':
+                step = int(line[1:])
+                suffix = line
+                altsuffix = suffix
+                if suffix[0] == "@":
+                    altsuffix = "#" + suffix[1:]
+                else:
+                    altsuffix = "@" + suffix[1:]
+                continue
+
+            line = line.split()
+
+            if len(line) == 0:
+                continue
+
+            if line[-1].endswith(suffix):
+                line[-1] = line[-1][0:len(line[-1]) - len(suffix)]
+
+            if line[-1].endswith(altsuffix):
+                line[-1] = line[-1][0:len(line[-1]) - len(altsuffix)]
+
+            if line[-1][0] == "$":
+                continue
+
+            # BV assignments
+            if len(line) == 3 and line[1][0] != "[":
+                value = line[1]
+                name = line[2]
+
+                path = smt.get_path(topmod, name)
+
+                if not smt.net_exists(topmod, path):
+                    continue
+
+                width = smt.net_width(topmod, path)
+
+                if width == 1:
+                    assert value in ["0", "1"]
+                    value = "true" if value == "1" else "false"
+                else:
+                    value = "#b" + value
+
+                smtexpr = "(= [%s] %s)" % (name, value)
+                constr_assumes[step].append((btorwitfile, smtexpr))
+
+            # Array assignments
+            if len(line) == 4 and line[1][0] == "[":
+                index = line[1]
+                value = line[2]
+                name = line[3]
+
+                path = smt.get_path(topmod, name)
+
+                if not smt.mem_exists(topmod, path):
+                    continue
+
+                meminfo = smt.mem_info(topmod, path)
+
+                if meminfo[1] == 1:
+                    assert value in ["0", "1"]
+                    value = "true" if value == "1" else "false"
+                else:
+                    value = "#b" + value
+
+                assert index[0] == "["
+                assert index[-1] == "]"
+                index = "#b" + index[1:-1]
+
+                smtexpr = "(= (select [%s] %s) %s)" % (name, index, value)
+                constr_assumes[step].append((btorwitfile, smtexpr))
+
+        skip_steps = step
+        num_steps = step+1
 
 def write_vcd_trace(steps_start, steps_stop, index):
     filename = vcdfile.replace("%", index)

From 4fef9689abb81286af4d9c6bc420b78f61d89550 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sat, 8 Dec 2018 09:59:56 +0000
Subject: [PATCH 224/528] memory_bram: Fix initdata bit order after shuffling

In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.

This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).

This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
---
 passes/memory/memory_bram.cc | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index 8740042c4..cf4095d06 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -472,8 +472,12 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 		std::vector<SigSpec> new_wr_en(GetSize(old_wr_en));
 		std::vector<SigSpec> new_wr_data(GetSize(old_wr_data));
 		std::vector<SigSpec> new_rd_data(GetSize(old_rd_data));
+		std::vector<std::vector<State>> new_initdata;
 		std::vector<int> shuffle_map;
 
+		if (cell_init)
+			new_initdata.resize(mem_size);
+
 		for (auto &it : en_order)
 		{
 			auto &bits = bits_wr_en.at(it);
@@ -489,6 +493,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 				}
 				for (int j = 0; j < rd_ports; j++)
 					new_rd_data[j].append(old_rd_data[j][bits[i]]);
+				if (cell_init) {
+					for (int j = 0; j < mem_size; j++)
+						new_initdata[j].push_back(initdata[j][bits[i]]);
+				}
 				shuffle_map.push_back(bits[i]);
 			}
 
@@ -499,6 +507,10 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 				}
 				for (int j = 0; j < rd_ports; j++)
 					new_rd_data[j].append(State::Sx);
+				if (cell_init) {
+					for (int j = 0; j < mem_size; j++)
+						new_initdata[j].push_back(State::Sx);
+				}
 				shuffle_map.push_back(-1);
 			}
 		}
@@ -522,6 +534,11 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 
 		for (int i = 0; i < rd_ports; i++)
 			rd_data.replace(i*mem_width, new_rd_data[i]);
+
+		if (cell_init) {
+			for (int i = 0; i < mem_size; i++)
+				initdata[i] = Const(new_initdata[i]);
+		}
 	}
 
 	// assign write ports

From d3fe9465f3efc30daf54926d6b3d2743b5fb3e51 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 12 Dec 2018 16:50:46 +0000
Subject: [PATCH 225/528] deminout: Don't demote constant-driven inouts to
 inputs

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/techmap/deminout.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 9f0c7bf67..0cc3df2af 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -113,7 +113,8 @@ struct DeminoutPass : public Pass {
 						{
 							if (bits_numports[bit] > 1 || bits_inout.count(bit))
 								new_input = true, new_output = true;
-
+							if (bit == State::S0 || bit == State::S1)
+								new_output = true;
 							if (bits_written.count(bit)) {
 								new_output = true;
 								if (bits_tribuf.count(bit))

From 4c5944716834e42f5ff5ddaf9a4ef748f8cc2af7 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 12 Dec 2018 17:17:36 +0000
Subject: [PATCH 226/528] deminout: Consider $tribuf cells

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/techmap/deminout.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
index 0cc3df2af..47d0ff416 100644
--- a/passes/techmap/deminout.cc
+++ b/passes/techmap/deminout.cc
@@ -83,9 +83,9 @@ struct DeminoutPass : public Pass {
 						for (auto bit : sigmap(conn.second))
 							bits_used.insert(bit);
 
-					if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_"))
+					if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
 					{
-						bool tribuf = (cell->type == "$_TBUF_");
+						bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf");
 
 						if (!tribuf) {
 							for (auto &c : cell->connections()) {

From 58fb2ac818d07021b6929cb9ff14e13e993a231f Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Thu, 13 Dec 2018 18:47:05 +0100
Subject: [PATCH 227/528] verilog_parser: Properly handle recursion when
 processing attributes

Fixes #737

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 frontends/verilog/verilog_parser.y | 48 ++++++++++++++++++------------
 1 file changed, 29 insertions(+), 19 deletions(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 5ab1b62df..51e112ed3 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -35,6 +35,7 @@
 
 %{
 #include <list>
+#include <stack>
 #include <string.h>
 #include "frontends/verilog/verilog_frontend.h"
 #include "kernel/log.h"
@@ -47,7 +48,8 @@ YOSYS_NAMESPACE_BEGIN
 namespace VERILOG_FRONTEND {
 	int port_counter;
 	std::map<std::string, int> port_stubs;
-	std::map<std::string, AstNode*> attr_list, default_attr_list;
+	std::map<std::string, AstNode*> *attr_list, default_attr_list;
+	std::stack<std::map<std::string, AstNode*> *> attr_list_stack;
 	std::map<std::string, AstNode*> *albuf;
 	std::vector<AstNode*> ast_stack;
 	struct AstNode *astbuf1, *astbuf2, *astbuf3;
@@ -175,15 +177,18 @@ design:
 
 attr:
 	{
-		for (auto &it : attr_list)
-			delete it.second;
-		attr_list.clear();
+		if (attr_list != nullptr)
+			attr_list_stack.push(attr_list);
+		attr_list = new std::map<std::string, AstNode*>;
 		for (auto &it : default_attr_list)
-			attr_list[it.first] = it.second->clone();
+			(*attr_list)[it.first] = it.second->clone();
 	} attr_opt {
-		std::map<std::string, AstNode*> *al = new std::map<std::string, AstNode*>;
-		al->swap(attr_list);
-		$$ = al;
+		$$ = attr_list;
+		if (!attr_list_stack.empty()) {
+			attr_list = attr_list_stack.top();
+			attr_list_stack.pop();
+		} else
+			attr_list = nullptr;
 	};
 
 attr_opt:
@@ -192,15 +197,20 @@ attr_opt:
 
 defattr:
 	DEFATTR_BEGIN {
+		if (attr_list != nullptr)
+			attr_list_stack.push(attr_list);
+		attr_list = new std::map<std::string, AstNode*>;
 		for (auto &it : default_attr_list)
 			delete it.second;
 		default_attr_list.clear();
-		for (auto &it : attr_list)
-			delete it.second;
-		attr_list.clear();
 	} opt_attr_list {
-		default_attr_list = attr_list;
-		attr_list.clear();
+		attr_list->swap(default_attr_list);
+		delete attr_list;
+		if (!attr_list_stack.empty()) {
+			attr_list = attr_list_stack.top();
+			attr_list_stack.pop();
+		} else
+			attr_list = nullptr;
 	} DEFATTR_END;
 
 opt_attr_list:
@@ -212,15 +222,15 @@ attr_list:
 
 attr_assign:
 	hierarchical_id {
-		if (attr_list.count(*$1) != 0)
-			delete attr_list[*$1];
-		attr_list[*$1] = AstNode::mkconst_int(1, false);
+		if (attr_list->count(*$1) != 0)
+			delete (*attr_list)[*$1];
+		(*attr_list)[*$1] = AstNode::mkconst_int(1, false);
 		delete $1;
 	} |
 	hierarchical_id '=' expr {
-		if (attr_list.count(*$1) != 0)
-			delete attr_list[*$1];
-		attr_list[*$1] = $3;
+		if (attr_list->count(*$1) != 0)
+			delete (*attr_list)[*$1];
+		(*attr_list)[*$1] = $3;
 		delete $1;
 	};
 

From f53e19cc718f2b8b8f48f8de988f980af5474d25 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Dec 2018 15:57:28 +0100
Subject: [PATCH 228/528] Fix equiv_opt indenting

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/equiv/equiv_opt.cc | 236 ++++++++++++++++++--------------------
 1 file changed, 113 insertions(+), 123 deletions(-)

diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc
index 408afd3e4..86550a69b 100644
--- a/passes/equiv/equiv_opt.cc
+++ b/passes/equiv/equiv_opt.cc
@@ -22,146 +22,136 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct EquivOptPass : public ScriptPass
+struct EquivOptPass:public ScriptPass
 {
-  EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
+	EquivOptPass() : ScriptPass("equiv_opt", "prove equivalence for optimized circuit") { }
 
-  void help() YS_OVERRIDE
-  {
-    //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-    log("\n");
-    log("    equiv_opt [options] [command]\n");
-    log("\n");
-    log("This command checks circuit equivalence before and after an optimization pass.\n");
-    log("\n");
-    log("    -run <from_label>:<to_label>\n");
-    log("        only run the commands between the labels (see below). an empty\n");
-    log("        from label is synonymous to the start of the command list, and empty to\n");
-    log("        label is synonymous to the end of the command list.\n");
-    log("\n");
-    log("    -map <filename>\n");
-    log("        expand the modules in this file before proving equivalence. this is\n");
-    log("        useful for handling architecture-specific primitives.\n");
-    log("\n");
-    log("    -assert\n");
-    log("        produce an error if the circuits are not equivalent\n");
-    log("\n");
-    log("The following commands are executed by this verification command:\n");
-    help_script();
-    log("\n");
-  }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    equiv_opt [options] [command]\n");
+		log("\n");
+		log("This command checks circuit equivalence before and after an optimization pass.\n");
+		log("\n");
+		log("    -run <from_label>:<to_label>\n");
+		log("        only run the commands between the labels (see below). an empty\n");
+		log("        from label is synonymous to the start of the command list, and empty to\n");
+		log("        label is synonymous to the end of the command list.\n");
+		log("\n");
+		log("    -map <filename>\n");
+		log("        expand the modules in this file before proving equivalence. this is\n");
+		log("        useful for handling architecture-specific primitives.\n");
+		log("\n");
+		log("    -assert\n");
+		log("        produce an error if the circuits are not equivalent\n");
+		log("\n");
+		log("The following commands are executed by this verification command:\n");
+		help_script();
+		log("\n");
+	}
 
-  std::string command, techmap_opts;
-  bool assert;
+	std::string command, techmap_opts;
+	bool assert;
 
-  void clear_flags() YS_OVERRIDE
-  {
-    command = "";
-    techmap_opts = "";
-    assert = false;
-  }
+	void clear_flags() YS_OVERRIDE
+	{
+		command = "";
+		techmap_opts = "";
+		assert = false;
+	}
 
-  void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-  {
-    string run_from, run_to;
-    clear_flags();
+	void execute(std::vector < std::string > args, RTLIL::Design * design) YS_OVERRIDE
+	{
+		string run_from, run_to;
+		clear_flags();
 
-    size_t argidx;
-    for (argidx = 1; argidx < args.size(); argidx++)
-    {
-      if (args[argidx] == "-run" && argidx+1 < args.size()) {
-        size_t pos = args[argidx+1].find(':');
-        if (pos == std::string::npos)
-          break;
-        run_from = args[++argidx].substr(0, pos);
-        run_to = args[argidx].substr(pos+1);
-        continue;
-      }
-      if (args[argidx] == "-map" && argidx+1 < args.size()) {
-        techmap_opts += " -map " + args[++argidx];
-        continue;
-      }
-      if (args[argidx] == "-assert") {
-        assert = true;
-        continue;
-      }
-      break;
-    }
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-run" && argidx + 1 < args.size()) {
+				size_t pos = args[argidx + 1].find(':');
+				if (pos == std::string::npos)
+					break;
+				run_from = args[++argidx].substr(0, pos);
+				run_to = args[argidx].substr(pos + 1);
+				continue;
+			}
+			if (args[argidx] == "-map" && argidx + 1 < args.size()) {
+				techmap_opts += " -map " + args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-assert") {
+				assert = true;
+				continue;
+			}
+			break;
+		}
 
-    for (; argidx < args.size(); argidx++)
-    {
-      if (command.empty())
-      {
-        if (args[argidx].substr(0, 1) == "-")
-          cmd_error(args, argidx, "Unknown option.");
-      }
-      else
-      {
-        command += " ";
-      }
-      command += args[argidx];
-    }
+		for (; argidx < args.size(); argidx++) {
+			if (command.empty()) {
+				if (args[argidx].substr(0, 1) == "-")
+					cmd_error(args, argidx, "Unknown option.");
+			} else {
+				command += " ";
+			}
+			command += args[argidx];
+		}
 
-    if (command.empty())
-      log_cmd_error("No optimization pass specified!\n");
+		if (command.empty())
+			log_cmd_error("No optimization pass specified!\n");
 
-    if (!design->full_selection())
-      log_cmd_error("This command only operates on fully selected designs!\n");
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
-    log_header(design, "Executing EQUIV_OPT pass.\n");
-    log_push();
+		log_header(design, "Executing EQUIV_OPT pass.\n");
+		log_push();
 
-    run_script(design, run_from, run_to);
+		run_script(design, run_from, run_to);
 
-    log_pop();
-  }
+		log_pop();
+	}
 
-  void script() YS_OVERRIDE
-  {
-    if (check_label("run_pass"))
-    {
-      run("hierarchy -auto-top");
-      run("design -save preopt");
-      if (help_mode)
-        run("[command]");
-      else
-        run(command);
-      run("design -stash postopt");
-    }
+	void script() YS_OVERRIDE
+	{
+		if (check_label("run_pass")) {
+			run("hierarchy -auto-top");
+			run("design -save preopt");
+			if (help_mode)
+				run("[command]");
+			else
+				run(command);
+			run("design -stash postopt");
+		}
 
-    if (check_label("prepare"))
-    {
-      run("design -copy-from preopt  -as gold A:top");
-      run("design -copy-from postopt -as gate A:top");
-    }
+		if (check_label("prepare")) {
+			run("design -copy-from preopt  -as gold A:top");
+			run("design -copy-from postopt -as gate A:top");
+		}
 
-    if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)"))
-    {
-      string opts;
-      if (help_mode)
-        opts = " -map <filename> ...";
-      else
-        opts = techmap_opts;
-      run("techmap -D EQUIV -autoproc" + opts);
-    }
+		if ((!techmap_opts.empty() || help_mode) && check_label("techmap", "(only with -map)")) {
+			string opts;
+			if (help_mode)
+				opts = " -map <filename> ...";
+			else
+				opts = techmap_opts;
+			run("techmap -D EQUIV -autoproc" + opts);
+		}
 
-    if (check_label("prove"))
-    {
-      run("equiv_make gold gate equiv");
-      run("equiv_induct equiv");
-      if (help_mode)
-        run("equiv_status [-assert] equiv");
-      else if(assert)
-        run("equiv_status -assert equiv");
-      else
-        run("equiv_status equiv");
-    }
+		if (check_label("prove")) {
+			run("equiv_make gold gate equiv");
+			run("equiv_induct equiv");
+			if (help_mode)
+				run("equiv_status [-assert] equiv");
+			else if (assert)
+				run("equiv_status -assert equiv");
+			else
+				run("equiv_status equiv");
+		}
 
-    if (check_label("restore"))
-    {
-      run("design -load preopt");
-    }
-  }
+		if (check_label("restore")) {
+			run("design -load preopt");
+		}
+	}
 } EquivOptPass;
 
 PRIVATE_NAMESPACE_END

From 8f359cf1ff52c9e039b9d0465d70c63dc564455f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 14:57:43 +0000
Subject: [PATCH 229/528] Add .editorconfig file.

See https://editorconfig.org/ for details.
---
 .editorconfig | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 .editorconfig

diff --git a/.editorconfig b/.editorconfig
new file mode 100644
index 000000000..4d6f5ef7a
--- /dev/null
+++ b/.editorconfig
@@ -0,0 +1,7 @@
+root = true
+
+[*]
+indent_style = tab
+indent_size = tab
+trim_trailing_whitespace = true
+insert_final_newline = true

From fccaa25ec1b053259a377991d8deba0f71021956 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 13 Dec 2018 04:36:02 +0000
Subject: [PATCH 230/528] write_verilog: add a missing newline.

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index dde03f920..850abfad7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1419,7 +1419,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
-				"processes to logic networks and registers.", log_id(module));
+				"processes to logic networks and registers.\n", log_id(module));
 
 	f << stringf("\n");
 	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)

From 5fa5dbbddab03af89e00426e21df9f30d020a94e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Dec 2018 16:36:19 +0100
Subject: [PATCH 231/528] Rename "fine:" label to "map:" in "synth_ice40"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 37b924dfd..c2aed873b 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -235,7 +235,7 @@ struct SynthIce40Pass : public ScriptPass
 			run("techmap -map +/ice40/brams_map.v");
 		}
 
-		if (check_label("fine"))
+		if (check_label("map"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");

From f6412d71099ff31fe899e0e982df99c3c8bc98aa Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 13 Dec 2018 04:31:58 +0000
Subject: [PATCH 232/528] select: print selection if a -assert-* flag causes an
 error.

---
 passes/cmds/select.cc | 58 +++++++++++++++++++++++++++++++++++++------
 1 file changed, 50 insertions(+), 8 deletions(-)

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index d97aa2b37..ba407ea8c 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -896,6 +896,29 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 	select_filter_active_mod(design, work_stack.back());
 }
 
+static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel)
+{
+	std::string desc = "Selection contains:\n";
+	for (auto mod_it : design->modules_)
+	{
+		if (sel->selected_module(mod_it.first)) {
+			for (auto &it : mod_it.second->wires_)
+				if (sel->selected_member(mod_it.first, it.first))
+					desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+			for (auto &it : mod_it.second->memories)
+				if (sel->selected_member(mod_it.first, it.first))
+					desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+			for (auto &it : mod_it.second->cells_)
+				if (sel->selected_member(mod_it.first, it.first))
+					desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+			for (auto &it : mod_it.second->processes)
+				if (sel->selected_member(mod_it.first, it.first))
+					desc += stringf("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+		}
+	}
+	return desc;
+}
+
 PRIVATE_NAMESPACE_END
 YOSYS_NAMESPACE_BEGIN
 
@@ -1394,7 +1417,12 @@ struct SelectPass : public Pass {
 				log_cmd_error("No selection to check.\n");
 			work_stack.back().optimize(design);
 			if (!work_stack.back().empty())
-				log_error("Assertion failed: selection is not empty:%s\n", sel_str.c_str());
+			{
+				RTLIL::Selection *sel = &work_stack.back();
+				sel->optimize(design);
+				std::string desc = describe_selection_for_assert(design, sel);
+				log_error("Assertion failed: selection is not empty:%s\n%s", sel_str.c_str(), desc.c_str());
+			}
 			return;
 		}
 
@@ -1404,7 +1432,12 @@ struct SelectPass : public Pass {
 				log_cmd_error("No selection to check.\n");
 			work_stack.back().optimize(design);
 			if (work_stack.back().empty())
-				log_error("Assertion failed: selection is empty:%s\n", sel_str.c_str());
+			{
+				RTLIL::Selection *sel = &work_stack.back();
+				sel->optimize(design);
+				std::string desc = describe_selection_for_assert(design, sel);
+				log_error("Assertion failed: selection is empty:%s\n%s", sel_str.c_str(), desc.c_str());
+			}
 			return;
 		}
 
@@ -1431,14 +1464,23 @@ struct SelectPass : public Pass {
 							total_count++;
 				}
 			if (assert_count >= 0 && assert_count != total_count)
-				log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n",
-						total_count, assert_count, sel_str.c_str());
+			{
+				std::string desc = describe_selection_for_assert(design, sel);
+				log_error("Assertion failed: selection contains %d elements instead of the asserted %d:%s\n%s",
+						total_count, assert_count, sel_str.c_str(), desc.c_str());
+			}
 			if (assert_max >= 0 && assert_max < total_count)
-				log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n",
-						total_count, assert_max, sel_str.c_str());
+			{
+				std::string desc = describe_selection_for_assert(design, sel);
+				log_error("Assertion failed: selection contains %d elements, more than the maximum number %d:%s\n%s",
+						total_count, assert_max, sel_str.c_str(), desc.c_str());
+			}
 			if (assert_min >= 0 && assert_min > total_count)
-				log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n",
-						total_count, assert_min, sel_str.c_str());
+			{
+				std::string desc = describe_selection_for_assert(design, sel);
+				log_error("Assertion failed: selection contains %d elements, less than the minimum number %d:%s\n%s",
+						total_count, assert_min, sel_str.c_str(), desc.c_str());
+			}
 			return;
 		}
 

From 4effb38e6d318e2e233bdfa9f2e0bb67e4998bf0 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 17:50:36 +0000
Subject: [PATCH 233/528] read_ilang: allow slicing sigspecs.

---
 frontends/ilang/ilang_parser.y | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index bfc062fec..b957ecd96 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -387,17 +387,13 @@ sigspec:
 		$$ = new RTLIL::SigSpec(current_module->wires_[$1]);
 		free($1);
 	} |
-	TOK_ID '[' TOK_INT ']' {
-		if (current_module->wires_.count($1) == 0)
-			rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-		$$ = new RTLIL::SigSpec(current_module->wires_[$1], $3);
-		free($1);
+	sigspec '[' TOK_INT ']' {
+		$$ = new RTLIL::SigSpec($1->extract($3));
+		delete $1;
 	} |
-	TOK_ID '[' TOK_INT ':' TOK_INT ']' {
-		if (current_module->wires_.count($1) == 0)
-			rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
-		$$ = new RTLIL::SigSpec(current_module->wires_[$1], $5, $3 - $5 + 1);
-		free($1);
+	sigspec '[' TOK_INT ':' TOK_INT ']' {
+		$$ = new RTLIL::SigSpec($1->extract($5, $3 - $5 + 1));
+		delete $1;
 	} |
 	'{' sigspec_list '}' {
 		$$ = $2;

From 9f5c7017ff89ad914b6b9be0620996d77e24f71b Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 18:25:53 +0000
Subject: [PATCH 234/528] Update CHANGELOG.

---
 CHANGELOG | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/CHANGELOG b/CHANGELOG
index a00c2adf8..42e01645e 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -9,6 +9,13 @@ Yosys 0.8 .. Yosys 0.8-dev
  * Various
     - Added $changed support to read_verilog
     - Added "write_edif -attrprop"
+    - Added "ice40_unlut" pass
+    - Added "opt_lut" pass
+    - Added "synth_ice40 -relut"
+    - Added "synth_ice40 -noabc"
+    - Added "gate2lut.v" techmap rule
+    - Added "rename -src"
+    - Added "equiv_opt" pass
 
 
 Yosys 0.7 .. Yosys 0.8

From ca866d384e666f27e2cd7bb80950d0a1dd7c0ebd Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 16 Dec 2018 18:46:32 +0000
Subject: [PATCH 235/528] write_verilog: handle the $shift cell.

The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:

    module \\$shift (A, B, Y);

    parameter A_SIGNED = 0;
    parameter B_SIGNED = 0;
    parameter A_WIDTH = 0;
    parameter B_WIDTH = 0;
    parameter Y_WIDTH = 0;

    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] Y;

    generate
        if (B_SIGNED) begin:BLOCK1
            assign Y = $signed(B) < 0 ? A << -B : A >> B;
        end else begin:BLOCK2
            assign Y = A >> B;
        end
    endgenerate

    endmodule
---
 backends/verilog/verilog_backend.cc | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 3a47b478f..71db25f98 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -678,6 +678,35 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 #undef HANDLE_UNIOP
 #undef HANDLE_BINOP
 
+	if (cell->type == "$shift")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		if (cell->getParam("\\B_SIGNED").as_bool())
+		{
+			f << stringf("$signed(");
+			dump_sigspec(f, cell->getPort("\\B"));
+			f << stringf(")");
+			f << stringf(" < 0 ? ");
+			dump_sigspec(f, cell->getPort("\\A"));
+			f << stringf(" << - ");
+			dump_sigspec(f, cell->getPort("\\B"));
+			f << stringf(" : ");
+			dump_sigspec(f, cell->getPort("\\A"));
+			f << stringf(" >> ");
+			dump_sigspec(f, cell->getPort("\\B"));
+		}
+		else
+		{
+			dump_sigspec(f, cell->getPort("\\A"));
+			f << stringf(" >> ");
+			dump_sigspec(f, cell->getPort("\\B"));
+		}
+		f << stringf(";\n");
+		return true;
+	}
+
 	if (cell->type == "$shiftx")
 	{
 		f << stringf("%s" "assign ", indent.c_str());

From 2641a3089bf042b6681727c25ad1a5d08dcc89a2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Dec 2018 21:27:31 +0100
Subject: [PATCH 236/528] Revert "Proof-of-concept: preserve naming through ABC
 using dress"

---
 passes/techmap/abc.cc | 80 ++++++++++++++++---------------------------
 1 file changed, 29 insertions(+), 51 deletions(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d3bdd555b..d2d15a4a9 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -329,18 +329,6 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 std::string remap_name(RTLIL::IdString abc_name)
 {
-	std::string abc_sname = abc_name.substr(1);
-	if (abc_sname.substr(0, 5) == "ys__n") {
-		int sid = std::stoi(abc_sname.substr(5));
-		bool inv = abc_sname.back() == 'v';
-		for (auto sig : signal_list) {
-			if (sig.id == sid) {
-				std::stringstream sstr;
-				sstr << "$abc$" << map_autoidx << "$" << log_signal(sig.bit) << (inv ? "_inv" : "");
-				return sstr.str();
-			}
-		}
-	}
 	std::stringstream sstr;
 	sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
 	return sstr.str();
@@ -365,12 +353,12 @@ void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std:
 	}
 
 	for (auto n : nodes)
-		fprintf(f, "  ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
+		fprintf(f, "  n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
 				n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
 
 	for (auto &e : edges)
 	for (auto n : e.second)
-		fprintf(f, "  ys__n%d -> ys__n%d;\n", e.first, n);
+		fprintf(f, "  n%d -> n%d;\n", e.first, n);
 
 	fprintf(f, "}\n");
 }
@@ -636,7 +624,7 @@ struct abc_output_filter
 void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 		std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
 		bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
+		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
 {
 	module = current_module;
 	map_autoidx = autoidx++;
@@ -740,8 +728,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 	for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
 		abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
-	if (abc_dress)
-		abc_script += "; dress";
+
 	abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
 	abc_script = add_echos_to_abc_cmd(abc_script);
 
@@ -797,7 +784,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	for (auto &si : signal_list) {
 		if (!si.is_port || si.type != G(NONE))
 			continue;
-		fprintf(f, " ys__n%d", si.id);
+		fprintf(f, " n%d", si.id);
 		pi_map[count_input++] = log_signal(si.bit);
 	}
 	if (count_input == 0)
@@ -809,17 +796,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	for (auto &si : signal_list) {
 		if (!si.is_port || si.type == G(NONE))
 			continue;
-		fprintf(f, " ys__n%d", si.id);
+		fprintf(f, " n%d", si.id);
 		po_map[count_output++] = log_signal(si.bit);
 	}
 	fprintf(f, "\n");
 
 	for (auto &si : signal_list)
-		fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit));
+		fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
 
 	for (auto &si : signal_list) {
 		if (si.bit.wire == NULL) {
-			fprintf(f, ".names ys__n%d\n", si.id);
+			fprintf(f, ".names n%d\n", si.id);
 			if (si.bit == RTLIL::State::S1)
 				fprintf(f, "1\n");
 		}
@@ -828,68 +815,68 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	int count_gates = 0;
 	for (auto &si : signal_list) {
 		if (si.type == G(BUF)) {
-			fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
+			fprintf(f, ".names n%d n%d\n", si.in1, si.id);
 			fprintf(f, "1 1\n");
 		} else if (si.type == G(NOT)) {
-			fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
+			fprintf(f, ".names n%d n%d\n", si.in1, si.id);
 			fprintf(f, "0 1\n");
 		} else if (si.type == G(AND)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "11 1\n");
 		} else if (si.type == G(NAND)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "0- 1\n");
 			fprintf(f, "-0 1\n");
 		} else if (si.type == G(OR)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "-1 1\n");
 			fprintf(f, "1- 1\n");
 		} else if (si.type == G(NOR)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "00 1\n");
 		} else if (si.type == G(XOR)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "01 1\n");
 			fprintf(f, "10 1\n");
 		} else if (si.type == G(XNOR)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "00 1\n");
 			fprintf(f, "11 1\n");
 		} else if (si.type == G(ANDNOT)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "10 1\n");
 		} else if (si.type == G(ORNOT)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "1- 1\n");
 			fprintf(f, "-0 1\n");
 		} else if (si.type == G(MUX)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "1-0 1\n");
 			fprintf(f, "-11 1\n");
 		} else if (si.type == G(AOI3)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "-00 1\n");
 			fprintf(f, "0-0 1\n");
 		} else if (si.type == G(OAI3)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "00- 1\n");
 			fprintf(f, "--0 1\n");
 		} else if (si.type == G(AOI4)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
+			fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
 			fprintf(f, "-0-0 1\n");
 			fprintf(f, "-00- 1\n");
 			fprintf(f, "0--0 1\n");
 			fprintf(f, "0-0- 1\n");
 		} else if (si.type == G(OAI4)) {
-			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
+			fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
 			fprintf(f, "00-- 1\n");
 			fprintf(f, "--00 1\n");
 		} else if (si.type == G(FF)) {
 			if (si.init == State::S0 || si.init == State::S1) {
-				fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
+				fprintf(f, ".latch n%d n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
 				recover_init = true;
 			} else
-				fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
+				fprintf(f, ".latch n%d n%d 2\n", si.in1, si.id);
 		} else if (si.type != G(NONE))
 			log_abort();
 		if (si.type != G(NONE))
@@ -902,6 +889,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
 			count_gates, GetSize(signal_list), count_input, count_output);
 	log_push();
+
 	if (count_output > 0)
 	{
 		log_header(design, "Executing ABC.\n");
@@ -1225,7 +1213,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		for (auto &si : signal_list)
 			if (si.is_port) {
 				char buffer[100];
-				snprintf(buffer, 100, "\\ys__n%d", si.id);
+				snprintf(buffer, 100, "\\n%d", si.id);
 				RTLIL::SigSig conn;
 				if (si.type != G(NONE)) {
 					conn.first = si.bit;
@@ -1419,11 +1407,6 @@ struct AbcPass : public Pass {
 		log("        this attribute is a unique integer for each ABC process started. This\n");
 		log("        is useful for debugging the partitioning of clock domains.\n");
 		log("\n");
-		log("    -dress\n");
-		log("        run the 'dress' command after all other ABC commands. This aims to\n");
-		log("        preserve naming by an equivalence check between the original and post-ABC\n");
-		log("        netlists (experimental).\n");
-		log("\n");
 		log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
 		log("\n");
@@ -1458,7 +1441,6 @@ struct AbcPass : public Pass {
 		std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false, sop_mode = false;
-		bool abc_dress = false;
 		vector<int> lut_costs;
 		markgroups = false;
 
@@ -1573,10 +1555,6 @@ struct AbcPass : public Pass {
 				map_mux16 = true;
 				continue;
 			}
-			if (arg == "-dress") {
-				abc_dress = true;
-				continue;
-			}
 			if (arg == "-g" && argidx+1 < args.size()) {
 				for (auto g : split_tokens(args[++argidx], ",")) {
 					vector<string> gate_list;
@@ -1726,7 +1704,7 @@ struct AbcPass : public Pass {
 
 			if (!dff_mode || !clk_str.empty()) {
 				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
+						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
 				continue;
 			}
 
@@ -1871,7 +1849,7 @@ struct AbcPass : public Pass {
 				en_polarity = std::get<2>(it.first);
 				en_sig = assign_map(std::get<3>(it.first));
 				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
+						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
 				assign_map.set(mod);
 			}
 		}

From 634d7d1c1424c69d983c008cfd800c0d7db43379 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 14 Dec 2018 16:46:01 +0800
Subject: [PATCH 237/528] Revert "Leave only real black box cells"

This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7.

For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/eagle_bb.v | 312 ++++++++++++++++++++++++++++++++++++
 1 file changed, 312 insertions(+)

diff --git a/techlibs/anlogic/eagle_bb.v b/techlibs/anlogic/eagle_bb.v
index 48442db2f..7cbec331a 100644
--- a/techlibs/anlogic/eagle_bb.v
+++ b/techlibs/anlogic/eagle_bb.v
@@ -1,6 +1,274 @@
 // Anlogic Eagle - Blackbox cells
 // FIXME: Create sim models
 
+(* blackbox *)
+module EG_LOGIC_BUF(
+  output o,
+  input i
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BUFG(
+  output o,
+  input i
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BUFIO(
+  input clki,
+  input rst,
+  input coe,
+  output clko,
+  output clkdiv1,
+  output clkdivx
+);
+  parameter GSR = "DISABLE";
+  parameter DIV = 2;
+  parameter STOPCLK = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_BUFGMUX(
+  output o,
+  input i0,
+  input i1,
+  input s
+);
+  parameter INIT_OUT = "0";
+  parameter PRESELECT_I0 = "TRUE";
+  parameter PRESELECT_I1 = "FALSE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_MBOOT(
+  input rebootn,
+  input [7:0] dynamic_addr  
+);
+  parameter ADDR_SOURCE_SEL = "STATIC";
+  parameter STATIC_ADDR = 8'b00000000;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_DNA(
+  output dout,
+  input  clk,
+  input  din,
+  input  shift_en
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_GCTRL(
+  output done,
+  output highz
+);
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_GSRN(
+  input gsrn,
+  input sync_clk
+);
+  parameter GSRN_SYNC_SEL = "DISABLE";
+  parameter USR_GSRN_EN = "DISABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_CCLK(
+  output cclk,
+  input  en
+);
+  parameter FREQ = "4.5";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_IDELAY(
+  output o,
+  input i
+);
+  parameter INDEL = 0;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_IDDR(
+  output q1,
+  output q0,
+  input clk,
+  input d,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+  parameter PIPEMODE = "PIPED";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODDR(
+  output q,
+  input clk,
+  input d1,
+  input d0,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_IDDRx2(
+  output q3,
+  output q2,
+  output q1,
+  output q0,
+  input pclk,
+  input sclk,
+  input d,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODELAY(
+  output o,
+  input i
+);
+  parameter OUTDEL = 0;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODDRx2(
+  output q,
+  input pclk,
+  input sclk,
+  input d3,
+  input d2,
+  input d1,
+  input d0,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_ODDRx2l(
+  output q,
+  input sclk,
+  input d3,
+  input d2,
+  input d1,
+  input d0,
+  input rst
+);
+  parameter ASYNCRST = "ENABLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_FIFO(
+  input rst,
+  input [DATA_WIDTH_W-1:0] di,
+  output [DATA_WIDTH_R-1:0] do,
+  input clkw,
+  input we,
+  input clkr,
+  input re,
+  input ore,
+  input [2:0] csw,
+  input [2:0] csr,
+  output empty_flag,
+  output aempty_flag,
+  output full_flag,
+  output afull_flag
+);
+  parameter DATA_WIDTH_W = 9;
+  parameter DATA_WIDTH_R = DATA_WIDTH_W;
+  parameter DATA_DEPTH_W = 1024;
+  parameter DATA_DEPTH_R = DATA_WIDTH_W * DATA_DEPTH_W / DATA_WIDTH_R;
+  parameter MODE = "FIFO8K";
+  parameter REGMODE_W = "NOREG";
+  parameter REGMODE_R = "NOREG";
+  parameter E = 0;
+  parameter AE = 6;
+  parameter AF = DATA_DEPTH_W - 6;
+  parameter F = DATA_DEPTH_W;
+  parameter GSR = "DISABLE";
+  parameter RESETMODE = "ASYNC";
+  parameter ASYNC_RESET_RELEASE = "SYNC";
+  parameter ENDIAN = "LITTLE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_DRAM(
+  input [DATA_WIDTH_W-1:0] di,
+  input [ADDR_WIDTH_W-1:0] waddr,
+  input wclk,
+  input we,
+  output [DATA_WIDTH_R-1:0] do,
+  input [ADDR_WIDTH_R-1:0] raddr
+);
+  parameter DATA_WIDTH_W = 9;
+  parameter ADDR_WIDTH_W = 10;
+  parameter DATA_DEPTH_W = 2 ** ADDR_WIDTH_W;
+  parameter DATA_WIDTH_R = 9;
+  parameter ADDR_WIDTH_R = 10;
+  parameter DATA_DEPTH_R = 2 ** ADDR_WIDTH_R;
+  parameter INIT_FILE = "NONE";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_DRAM16X4(
+  input [3:0] di,
+  input [3:0] waddr,
+  input wclk,
+  input we,
+  input [3:0]raddr,
+  output [3:0]do
+);
+  parameter INIT_D0=16'h0000;
+  parameter INIT_D1=16'h0000;
+  parameter INIT_D2=16'h0000;
+  parameter INIT_D3=16'h0000;
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_MULT(
+  output [OUTPUT_WIDTH-1:0] p,
+  input [INPUT_WIDTH_A-1:0] a,
+  input [INPUT_WIDTH_B-1:0] b,
+  input cea,
+  input ceb,
+  input cepd,
+  input clk,
+  input rstan,
+  input rstbn,
+  input rstpdn
+); 
+  parameter INPUT_WIDTH_A = 18;
+  parameter INPUT_WIDTH_B = 18;
+  parameter OUTPUT_WIDTH = 36;
+  parameter INPUTFORMAT = "SIGNED";
+  parameter INPUTREGA = "ENABLE";
+  parameter INPUTREGB = "ENABLE";
+  parameter OUTPUTREG = "ENABLE";
+  parameter SRMODE = "ASYNC";
+  parameter IMPLEMENT = "AUTO";
+endmodule
+
+(* blackbox *)
+module EG_LOGIC_SEQ_DIV(
+  input clk,
+  input rst,
+  input start,
+  input [NUMER_WIDTH-1:0] numer,
+  input [DENOM_WIDTH-1:0] denom,
+  output [NUMER_WIDTH-1:0] quotient,
+  output [DENOM_WIDTH-1:0] remain,
+  output done
+);
+	parameter NUMER_WIDTH = 16;
+  parameter DENOM_WIDTH = 16;
+endmodule
+
 (* blackbox *)
 module EG_PHY_BRAM(
   output [8:0] doa,
@@ -695,6 +963,50 @@ module EG_PHY_PLL(
   parameter GEN_BASIC_CLOCK = "DISABLE";
 endmodule
 
+(* blackbox *)
+module EG_LOGIC_BRAM(
+  output [DATA_WIDTH_A-1:0] doa,
+  output [DATA_WIDTH_B-1:0] dob,
+  input [DATA_WIDTH_A-1:0] dia,
+  input [DATA_WIDTH_B-1:0] dib,
+  input cea,
+  input ocea,
+  input clka,
+  input wea,
+  input rsta,
+  input ceb,
+  input oceb,
+  input clkb,
+  input web,
+  input rstb,
+  input [BYTE_A - 1 : 0] bea,
+  input [BYTE_B - 1 : 0] beb,
+  input [ADDR_WIDTH_A-1:0] addra,
+  input [ADDR_WIDTH_B-1:0] addrb
+);
+  parameter DATA_WIDTH_A = 9;
+  parameter DATA_WIDTH_B = DATA_WIDTH_A;
+  parameter ADDR_WIDTH_A = 10;
+  parameter ADDR_WIDTH_B = ADDR_WIDTH_A;
+  parameter DATA_DEPTH_A = 2 ** ADDR_WIDTH_A;
+  parameter DATA_DEPTH_B = 2 ** ADDR_WIDTH_B;
+  parameter BYTE_ENABLE = 0;
+  parameter BYTE_A = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_A / BYTE_ENABLE;
+  parameter BYTE_B = BYTE_ENABLE == 0 ? 1 : DATA_WIDTH_B / BYTE_ENABLE;  
+  parameter MODE = "DP";
+  parameter REGMODE_A = "NOREG";
+  parameter REGMODE_B = "NOREG";
+  parameter WRITEMODE_A = "NORMAL";
+  parameter WRITEMODE_B = "NORMAL";
+  parameter RESETMODE = "SYNC";
+  parameter DEBUGGABLE = "NO";
+  parameter PACKABLE = "NO";
+  parameter FORCE_KEEP = "OFF";
+  parameter INIT_FILE = "NONE";
+  parameter FILL_ALL = "NONE";
+  parameter IMPLEMENT = "9K";
+endmodule     
+
 (* blackbox *)
 module EG_PHY_ADC(
   input clk,

From d53a2bd1d3ae3cfbc9ead0fc12999fe269628179 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Fri, 14 Dec 2018 16:50:37 +0800
Subject: [PATCH 238/528] anlogic: add support for Eagle Distributed RAM

The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.

Enable to synthesis to DRAM.

As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/Makefile.inc     |  3 ++-
 techlibs/anlogic/drams.txt        | 16 ++++++++++++++++
 techlibs/anlogic/drams_map.v      | 19 +++++++++++++++++++
 techlibs/anlogic/synth_anlogic.cc |  6 ++++++
 4 files changed, 43 insertions(+), 1 deletion(-)
 create mode 100644 techlibs/anlogic/drams.txt
 create mode 100644 techlibs/anlogic/drams_map.v

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 750dced31..59be83fd0 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -5,4 +5,5 @@ OBJS += techlibs/anlogic/anlogic_eqn.o
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
-$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
new file mode 100644
index 000000000..2bff14a03
--- /dev/null
+++ b/techlibs/anlogic/drams.txt
@@ -0,0 +1,16 @@
+bram $__ANLOGIC_DRAM16X4
+  init 0
+  abits 4
+  dbits 2
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 0 1
+  transp 0 0
+  clocks 0 1
+  clkpol 0 1
+endbram
+
+match $__ANLOGIC_DRAM16X4
+  make_outreg
+endmatch
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v
new file mode 100644
index 000000000..87cbb6a45
--- /dev/null
+++ b/techlibs/anlogic/drams_map.v
@@ -0,0 +1,19 @@
+module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	input CLK1;
+
+	input [3:0] A1ADDR;
+	output [3:0] A1DATA;
+
+	input [3:0] B1ADDR;
+	input [3:0] B1DATA;
+	input B1EN;
+
+	EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
+		.di(B1DATA),
+		.waddr(B1ADDR),
+		.wclk(CLK1),
+		.we(B1EN),
+		.raddr(A1ADDR),
+		.do(A1DATA)
+	);
+endmodule
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index f4ef88770..a4eafeddf 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -150,6 +150,12 @@ struct SynthAnlogicPass : public ScriptPass
 			run("synth -run coarse");
 		}
 
+		if (check_label("dram"))
+		{
+			run("memory_bram -rules +/anlogic/drams.txt");
+			run("techmap -map +/anlogic/drams_map.v");
+		}
+
 		if (check_label("fine"))
 		{
 			run("opt -fast -mux_undef -undriven -fine");

From abf5930a3325b8ae89f8cbb89a0f963e316c0889 Mon Sep 17 00:00:00 2001
From: makaimann <makaim@stanford.edu>
Date: Mon, 5 Nov 2018 11:49:31 -0800
Subject: [PATCH 239/528] Add btor ops for $mul, $div, $mod and $concat

---
 backends/btor/btor.cc       | 40 +++++++++++++++++++++++++++++++++++--
 backends/btor/test_cells.sh |  0
 2 files changed, 38 insertions(+), 2 deletions(-)
 mode change 100644 => 100755 backends/btor/test_cells.sh

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index ab2702807..d3fb9b858 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -133,12 +133,13 @@ struct BtorWorker
 		cell_recursion_guard.insert(cell);
 		btorf_push(log_id(cell));
 
-		if (cell->type.in("$add", "$sub", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
-				"$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
+		if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
+                      "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
 		{
 			string btor_op;
 			if (cell->type == "$add") btor_op = "add";
 			if (cell->type == "$sub") btor_op = "sub";
+			if (cell->type == "$mul") btor_op = "mul";
 			if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
 			if (cell->type == "$shr") btor_op = "srl";
 			if (cell->type == "$sshr") btor_op = "sra";
@@ -146,6 +147,7 @@ struct BtorWorker
 			if (cell->type.in("$and", "$_AND_")) btor_op = "and";
 			if (cell->type.in("$or", "$_OR_")) btor_op = "or";
 			if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
+			if (cell->type == "$concat") btor_op = "concat";
 			if (cell->type == "$_NAND_") btor_op = "nand";
 			if (cell->type == "$_NOR_") btor_op = "nor";
 			if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
@@ -214,6 +216,40 @@ struct BtorWorker
 			goto okay;
 		}
 
+		if (cell->type.in("$div", "$mod"))
+		{
+			string btor_op;
+			if (cell->type == "$div") btor_op = "div";
+			if (cell->type == "$mod") btor_op = "rem";
+			log_assert(!btor_op.empty());
+
+			int width = GetSize(cell->getPort("\\Y"));
+			width = std::max(width, GetSize(cell->getPort("\\A")));
+			width = std::max(width, GetSize(cell->getPort("\\B")));
+
+			bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
+			bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
+
+			int nid_a = get_sig_nid(cell->getPort("\\A"), width, a_signed);
+			int nid_b = get_sig_nid(cell->getPort("\\B"), width, b_signed);
+
+			int sid = get_bv_sid(width);
+			int nid = next_nid++;
+			btorf("%d %c%s %d %d %d\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b);
+
+			SigSpec sig = sigmap(cell->getPort("\\Y"));
+
+			if (GetSize(sig) < width) {
+				int sid = get_bv_sid(GetSize(sig));
+				int nid2 = next_nid++;
+				btorf("%d slice %d %d %d 0\n", nid2, sid, nid, GetSize(sig)-1);
+				nid = nid2;
+			}
+
+			add_nid_sig(nid, sig);
+			goto okay;
+		}
+
 		if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
 		{
 			int sid = get_bv_sid(1);
diff --git a/backends/btor/test_cells.sh b/backends/btor/test_cells.sh
old mode 100644
new mode 100755

From 7854d5ba217788bb66881237feac8ba2748758b9 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Tue, 18 Dec 2018 14:38:44 +0800
Subject: [PATCH 240/528] anlogic: fix dbits of Anlogic Eagle DRAM16X4

The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.

Fix the dbits number in the RAM configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/drams.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
index 2bff14a03..eb94775ae 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/drams.txt
@@ -1,7 +1,7 @@
 bram $__ANLOGIC_DRAM16X4
   init 0
   abits 4
-  dbits 2
+  dbits 4
   groups 2
   ports  1 1
   wrmode 0 1

From fec8b3c81ffcf1f8a27e79250c05b6ea91571bbe Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Tue, 18 Dec 2018 15:37:43 +0800
Subject: [PATCH 241/528] Add "dffinit -strinit high low"

On some platforms the string to initialize DFF might not be "high" and
"low", e.g. with Anlogic TD it's "SET" and "RESET".

Add a "-strinit" parameter for dffinit to allow specify the strings used
for high and low.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 passes/techmap/dffinit.cc | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index a8eecc970..4fa15a35b 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -43,6 +43,11 @@ struct DffinitPass : public Pass {
 		log("        initial value of 1 or 0. (multi-bit values are not supported in this\n");
 		log("        mode.)\n");
 		log("\n");
+		log("    -strinit <string for high> <string for low> \n");
+		log("        use string values in the command line to represent a single-bit\n");
+		log("        initial value of 1 or 0. (multi-bit values are not supported in this\n");
+		log("        mode.)\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -50,11 +55,20 @@ struct DffinitPass : public Pass {
 
 		dict<IdString, dict<IdString, IdString>> ff_types;
 		bool highlow_mode = false;
+		std::string high_string, low_string;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			if (args[argidx] == "-highlow") {
 				highlow_mode = true;
+				high_string = "high";
+				low_string = "low";
+				continue;
+			}
+			if (args[argidx] == "-strinit" && argidx+2 < args.size()) {
+				highlow_mode = true;
+				high_string = args[++argidx];
+				low_string = args[++argidx];
 				continue;
 			}
 			if (args[argidx] == "-ff" && argidx+3 < args.size()) {
@@ -121,9 +135,9 @@ struct DffinitPass : public Pass {
 							log_error("Multi-bit init value for %s.%s.%s is incompatible with -highlow mode.\n",
 									log_id(module), log_id(cell), log_id(it.second));
 						if (value[0] == State::S1)
-							value = Const("high");
+							value = Const(high_string);
 						else
-							value = Const("low");
+							value = Const(low_string);
 					}
 
 					log("Setting %s.%s.%s (port=%s, net=%s) to %s.\n", log_id(module), log_id(cell), log_id(it.second),

From 3d671630e2bf78cd53ef1b678a1bbb63338cbcd2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Dec 2018 16:01:22 +0100
Subject: [PATCH 242/528] Improve src tagging (using names and attrs) of cells
 and wires in verific front-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 258 +++++++++++++++++++++--------------
 frontends/verific/verific.h  |   1 +
 2 files changed, 160 insertions(+), 99 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index bc035c31a..61d9d593c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -130,6 +130,15 @@ bool is_blackbox(Netlist *nl)
 	return false;
 }
 
+RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
+{
+	std::string s = stringf("$verific$%s", obj->Name());
+	if (obj->Linefile())
+		s += stringf("$%s:%d", Verific::LineFile::GetFileName(obj->Linefile()), Verific::LineFile::GetLineNo(obj->Linefile()));
+	s += stringf("$%d", autoidx++);
+	return s;
+}
+
 void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
 {
 	MapIter mi;
@@ -215,7 +224,7 @@ RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*,
 			dummy_wire = NULL;
 		} else {
 			if (dummy_wire == NULL)
-				dummy_wire = module->addWire(NEW_ID);
+				dummy_wire = module->addWire(new_verific_id(inst));
 			else
 				dummy_wire->width++;
 			sig.append(RTLIL::SigSpec(dummy_wire, dummy_wire->width - 1));
@@ -231,8 +240,8 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 	}
 
 	if (inst->Type() == PRIM_NAND) {
-		RTLIL::SigSpec tmp = module->addWire(NEW_ID);
-		module->addAndGate(NEW_ID, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
+		RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
+		module->addAndGate(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
 		module->addNotGate(inst_name, tmp, net_map_at(inst->GetOutput()));
 		return true;
 	}
@@ -243,8 +252,8 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 	}
 
 	if (inst->Type() == PRIM_NOR) {
-		RTLIL::SigSpec tmp = module->addWire(NEW_ID);
-		module->addOrGate(NEW_ID, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
+		RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
+		module->addOrGate(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
 		module->addNotGate(inst_name, tmp, net_map_at(inst->GetOutput()));
 		return true;
 	}
@@ -284,16 +293,16 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 	if (inst->Type() == PRIM_FADD)
 	{
 		RTLIL::SigSpec a = net_map_at(inst->GetInput1()), b = net_map_at(inst->GetInput2()), c = net_map_at(inst->GetCin());
-		RTLIL::SigSpec x = inst->GetCout() ? net_map_at(inst->GetCout()) : module->addWire(NEW_ID);
-		RTLIL::SigSpec y = inst->GetOutput() ? net_map_at(inst->GetOutput()) : module->addWire(NEW_ID);
-		RTLIL::SigSpec tmp1 = module->addWire(NEW_ID);
-		RTLIL::SigSpec tmp2 = module->addWire(NEW_ID);
-		RTLIL::SigSpec tmp3 = module->addWire(NEW_ID);
-		module->addXorGate(NEW_ID, a, b, tmp1);
+		RTLIL::SigSpec x = inst->GetCout() ? net_map_at(inst->GetCout()) : module->addWire(new_verific_id(inst));
+		RTLIL::SigSpec y = inst->GetOutput() ? net_map_at(inst->GetOutput()) : module->addWire(new_verific_id(inst));
+		RTLIL::SigSpec tmp1 = module->addWire(new_verific_id(inst));
+		RTLIL::SigSpec tmp2 = module->addWire(new_verific_id(inst));
+		RTLIL::SigSpec tmp3 = module->addWire(new_verific_id(inst));
+		module->addXorGate(new_verific_id(inst), a, b, tmp1);
 		module->addXorGate(inst_name, tmp1, c, y);
-		module->addAndGate(NEW_ID, tmp1, c, tmp2);
-		module->addAndGate(NEW_ID, a, b, tmp3);
-		module->addOrGate(NEW_ID, tmp2, tmp3, x);
+		module->addAndGate(new_verific_id(inst), tmp1, c, tmp2);
+		module->addAndGate(new_verific_id(inst), a, b, tmp3);
+		module->addOrGate(new_verific_id(inst), tmp2, tmp3, x);
 		return true;
 	}
 
@@ -320,63 +329,78 @@ bool VerificImporter::import_netlist_instance_gates(Instance *inst, RTLIL::IdStr
 
 bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdString inst_name)
 {
+	RTLIL::Cell *cell = nullptr;
+
 	if (inst->Type() == PRIM_AND) {
-		module->addAnd(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		cell = module->addAnd(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_NAND) {
-		RTLIL::SigSpec tmp = module->addWire(NEW_ID);
-		module->addAnd(NEW_ID, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
-		module->addNot(inst_name, tmp, net_map_at(inst->GetOutput()));
+		RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
+		cell = module->addAnd(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
+		import_attributes(cell->attributes, inst);
+		cell = module->addNot(inst_name, tmp, net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_OR) {
-		module->addOr(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		cell = module->addOr(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_NOR) {
-		RTLIL::SigSpec tmp = module->addWire(NEW_ID);
-		module->addOr(NEW_ID, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
-		module->addNot(inst_name, tmp, net_map_at(inst->GetOutput()));
+		RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst));
+		cell = module->addOr(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), tmp);
+		import_attributes(cell->attributes, inst);
+		cell = module->addNot(inst_name, tmp, net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_XOR) {
-		module->addXor(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		cell = module->addXor(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_XNOR) {
-		module->addXnor(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		cell = module->addXnor(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_INV) {
-		module->addNot(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		cell = module->addNot(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_MUX) {
-		module->addMux(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
+		cell = module->addMux(inst_name, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_TRI) {
-		module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
+		cell = module->addMux(inst_name, RTLIL::State::Sz, net_map_at(inst->GetInput()), net_map_at(inst->GetControl()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_FADD)
 	{
-		RTLIL::SigSpec a_plus_b = module->addWire(NEW_ID, 2);
-		RTLIL::SigSpec y = inst->GetOutput() ? net_map_at(inst->GetOutput()) : module->addWire(NEW_ID);
+		RTLIL::SigSpec a_plus_b = module->addWire(new_verific_id(inst), 2);
+		RTLIL::SigSpec y = inst->GetOutput() ? net_map_at(inst->GetOutput()) : module->addWire(new_verific_id(inst));
 		if (inst->GetCout())
 			y.append(net_map_at(inst->GetCout()));
-		module->addAdd(NEW_ID, net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), a_plus_b);
-		module->addAdd(inst_name, a_plus_b, net_map_at(inst->GetCin()), y);
+		cell = module->addAdd(new_verific_id(inst), net_map_at(inst->GetInput1()), net_map_at(inst->GetInput2()), a_plus_b);
+		import_attributes(cell->attributes, inst);
+		cell = module->addAdd(inst_name, a_plus_b, net_map_at(inst->GetCin()), y);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -387,24 +411,26 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		log_assert(clocking.body_net == nullptr);
 
 		if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
-			clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+			cell = clocking.addDff(inst_name, net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
 		else if (inst->GetSet()->IsGnd())
-			clocking.addAdff(inst_name, net_map_at(inst->GetReset()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S0);
+			cell = clocking.addAdff(inst_name, net_map_at(inst->GetReset()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S0);
 		else if (inst->GetReset()->IsGnd())
-			clocking.addAdff(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S1);
+			cell = clocking.addAdff(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()), RTLIL::State::S1);
 		else
-			clocking.addDffsr(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
+			cell = clocking.addDffsr(inst_name, net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
 					net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == PRIM_DLATCHRS)
 	{
 		if (inst->GetSet()->IsGnd() && inst->GetReset()->IsGnd())
-			module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+			cell = module->addDlatch(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
 		else
-			module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
+			cell = module->addDlatchsr(inst_name, net_map_at(inst->GetControl()), net_map_at(inst->GetSet()), net_map_at(inst->GetReset()),
 					net_map_at(inst->GetInput()), net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -420,37 +446,45 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		if (inst->GetCout() != NULL)
 			out.append(net_map_at(inst->GetCout()));
 		if (inst->GetCin()->IsGnd()) {
-			module->addAdd(inst_name, IN1, IN2, out, SIGNED);
+			cell = module->addAdd(inst_name, IN1, IN2, out, SIGNED);
+			import_attributes(cell->attributes, inst);
 		} else {
-			RTLIL::SigSpec tmp = module->addWire(NEW_ID, GetSize(out));
-			module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED);
-			module->addAdd(inst_name, tmp, net_map_at(inst->GetCin()), out, false);
+			RTLIL::SigSpec tmp = module->addWire(new_verific_id(inst), GetSize(out));
+			cell = module->addAdd(new_verific_id(inst), IN1, IN2, tmp, SIGNED);
+			import_attributes(cell->attributes, inst);
+			cell = module->addAdd(inst_name, tmp, net_map_at(inst->GetCin()), out, false);
+			import_attributes(cell->attributes, inst);
 		}
 		return true;
 	}
 
 	if (inst->Type() == OPER_MULTIPLIER) {
-		module->addMul(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addMul(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_DIVIDER) {
-		module->addDiv(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addDiv(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_MODULO) {
-		module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_REMAINDER) {
-		module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addMod(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_SHIFT_LEFT) {
-		module->addShl(inst_name, IN1, IN2, OUT, false);
+		cell = module->addShl(inst_name, IN1, IN2, OUT, false);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -460,7 +494,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		for (unsigned i = 1; i < inst->OutputSize(); i++) {
 			vec.append(RTLIL::State::S0);
 		}
-		module->addShl(inst_name, vec, IN, OUT, false);
+		cell = module->addShl(inst_name, vec, IN, OUT, false);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -470,7 +505,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		for (unsigned i = 1; i < inst->OutputSize(); i++) {
 			vec.append(RTLIL::State::S0);
 		}
-		module->addShl(inst_name, vec, IN, OUT, false);
+		cell = module->addShl(inst_name, vec, IN, OUT, false);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -478,108 +514,127 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		Net *net_cin = inst->GetCin();
 		Net *net_a_msb = inst->GetInput1Bit(0);
 		if (net_cin->IsGnd())
-			module->addShr(inst_name, IN1, IN2, OUT, false);
+			cell = module->addShr(inst_name, IN1, IN2, OUT, false);
 		else if (net_cin == net_a_msb)
-			module->addSshr(inst_name, IN1, IN2, OUT, true);
+			cell = module->addSshr(inst_name, IN1, IN2, OUT, true);
 		else
 			log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst->Name());
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_REDUCE_AND) {
-		module->addReduceAnd(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		cell = module->addReduceAnd(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_REDUCE_OR) {
-		module->addReduceOr(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		cell = module->addReduceOr(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_REDUCE_XOR) {
-		module->addReduceXor(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		cell = module->addReduceXor(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_REDUCE_XNOR) {
-		module->addReduceXnor(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		cell = module->addReduceXnor(inst_name, IN, net_map_at(inst->GetOutput()), SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_REDUCE_NOR) {
-		SigSpec t = module->ReduceOr(NEW_ID, IN, SIGNED);
-		module->addNot(inst_name, t, net_map_at(inst->GetOutput()));
+		SigSpec t = module->ReduceOr(new_verific_id(inst), IN, SIGNED);
+		cell = module->addNot(inst_name, t, net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_LESSTHAN) {
 		Net *net_cin = inst->GetCin();
 		if (net_cin->IsGnd())
-			module->addLt(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
+			cell = module->addLt(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
 		else if (net_cin->IsPwr())
-			module->addLe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
+			cell = module->addLe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
 		else
 			log_error("Can't import Verific OPER_LESSTHAN instance %s: carry_in is neither 0 nor 1\n", inst->Name());
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_AND) {
-		module->addAnd(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addAnd(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_OR) {
-		module->addOr(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addOr(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_XOR) {
-		module->addXor(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addXor(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_XNOR) {
-		module->addXnor(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addXnor(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_BUF) {
-		module->addPos(inst_name, IN, FILTERED_OUT, SIGNED);
+		cell = module->addPos(inst_name, IN, FILTERED_OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_INV) {
-		module->addNot(inst_name, IN, OUT, SIGNED);
+		cell = module->addNot(inst_name, IN, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_MINUS) {
-		module->addSub(inst_name, IN1, IN2, OUT, SIGNED);
+		cell = module->addSub(inst_name, IN1, IN2, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_UMINUS) {
-		module->addNeg(inst_name, IN, OUT, SIGNED);
+		cell = module->addNeg(inst_name, IN, OUT, SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_EQUAL) {
-		module->addEq(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
+		cell = module->addEq(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_NEQUAL) {
-		module->addNe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
+		cell = module->addNe(inst_name, IN1, IN2, net_map_at(inst->GetOutput()), SIGNED);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_MUX) {
-		module->addMux(inst_name, IN1, IN2, net_map_at(inst->GetControl()), OUT);
+		cell = module->addMux(inst_name, IN1, IN2, net_map_at(inst->GetControl()), OUT);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_NTO1MUX) {
-		module->addShr(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
+		cell = module->addShr(inst_name, IN2, IN1, net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -599,25 +654,29 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 			padded_data.append(d);
 		}
 
-		module->addShr(inst_name, padded_data, sel, out);
+		cell = module->addShr(inst_name, padded_data, sel, out);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_SELECTOR)
 	{
-		module->addPmux(inst_name, State::S0, IN2, IN1, net_map_at(inst->GetOutput()));
+		cell = module->addPmux(inst_name, State::S0, IN2, IN1, net_map_at(inst->GetOutput()));
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_SELECTOR)
 	{
 		SigSpec out = OUT;
-		module->addPmux(inst_name, SigSpec(State::S0, GetSize(out)), IN2, IN1, out);
+		cell = module->addPmux(inst_name, SigSpec(State::S0, GetSize(out)), IN2, IN1, out);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
 	if (inst->Type() == OPER_WIDE_TRI) {
-		module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT);
+		cell = module->addMux(inst_name, RTLIL::SigSpec(RTLIL::State::Sz, inst->OutputSize()), IN, net_map_at(inst->GetControl()), OUT);
+		import_attributes(cell->attributes, inst);
 		return true;
 	}
 
@@ -631,9 +690,10 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 		RTLIL::SigSpec sig_reset = operatorInport(inst, "reset");
 
 		if (sig_set.is_fully_const() && !sig_set.as_bool() && sig_reset.is_fully_const() && !sig_reset.as_bool())
-			clocking.addDff(inst_name, IN, OUT);
+			cell = clocking.addDff(inst_name, IN, OUT);
 		else
-			clocking.addDffsr(inst_name, sig_set, sig_reset, IN, OUT);
+			cell = clocking.addDffsr(inst_name, sig_set, sig_reset, IN, OUT);
+		import_attributes(cell->attributes, inst);
 
 		return true;
 	}
@@ -862,7 +922,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 						ascii_initdata++;
 					}
 					if (initval_valid) {
-						RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit");
+						RTLIL::Cell *cell = module->addCell(new_verific_id(net), "$meminit");
 						cell->parameters["\\WORDS"] = 1;
 						if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound())
 							cell->setPort("\\ADDR", word_idx);
@@ -925,7 +985,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		if (net->Bus())
 			continue;
 
-		RTLIL::IdString wire_name = module->uniquify(mode_names || net->IsUserDeclared() ? RTLIL::escape_id(net->Name()) : NEW_ID);
+		RTLIL::IdString wire_name = module->uniquify(mode_names || net->IsUserDeclared() ? RTLIL::escape_id(net->Name()) : new_verific_id(net));
 
 		if (verific_verbose)
 			log("  importing net %s as %s.\n", net->Name(), log_id(wire_name));
@@ -949,7 +1009,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 		if (found_new_net)
 		{
-			RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(netbus->Name()) : NEW_ID);
+			RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(netbus->Name()) : new_verific_id(netbus));
 
 			if (verific_verbose)
 				log("  importing netbus %s as %s.\n", netbus->Name(), log_id(wire_name));
@@ -1025,16 +1085,16 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		}
 
 		if (GetSize(anyconst_sig))
-			module->connect(anyconst_sig, module->Anyconst(NEW_ID, GetSize(anyconst_sig)));
+			module->connect(anyconst_sig, module->Anyconst(new_verific_id(netbus), GetSize(anyconst_sig)));
 
 		if (GetSize(anyseq_sig))
-			module->connect(anyseq_sig, module->Anyseq(NEW_ID, GetSize(anyseq_sig)));
+			module->connect(anyseq_sig, module->Anyseq(new_verific_id(netbus), GetSize(anyseq_sig)));
 
 		if (GetSize(allconst_sig))
-			module->connect(allconst_sig, module->Allconst(NEW_ID, GetSize(allconst_sig)));
+			module->connect(allconst_sig, module->Allconst(new_verific_id(netbus), GetSize(allconst_sig)));
 
 		if (GetSize(allseq_sig))
-			module->connect(allseq_sig, module->Allseq(NEW_ID, GetSize(allseq_sig)));
+			module->connect(allseq_sig, module->Allseq(new_verific_id(netbus), GetSize(allseq_sig)));
 	}
 
 	for (auto it : init_nets)
@@ -1058,10 +1118,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 	}
 
 	for (auto net : anyconst_nets)
-		module->connect(net_map_at(net), module->Anyconst(NEW_ID));
+		module->connect(net_map_at(net), module->Anyconst(new_verific_id(net)));
 
 	for (auto net : anyseq_nets)
-		module->connect(net_map_at(net), module->Anyseq(NEW_ID));
+		module->connect(net_map_at(net), module->Anyseq(new_verific_id(net)));
 
 	pool<Instance*, hash_ptr_ops> sva_asserts;
 	pool<Instance*, hash_ptr_ops> sva_assumes;
@@ -1072,7 +1132,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 	FOREACH_INSTANCE_OF_NETLIST(nl, mi, inst)
 	{
-		RTLIL::IdString inst_name = module->uniquify(mode_names || inst->IsUserDeclared() ? RTLIL::escape_id(inst->Name()) : NEW_ID);
+		RTLIL::IdString inst_name = module->uniquify(mode_names || inst->IsUserDeclared() ? RTLIL::escape_id(inst->Name()) : new_verific_id(inst));
 
 		if (verific_verbose)
 			log("  importing cell %s (%s) as %s.\n", inst->Name(), inst->View()->Owner()->Name(), log_id(inst_name));
@@ -1196,7 +1256,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			log_assert(inst->Input1Size() == inst->OutputSize());
 
 			SigSpec sig_d, sig_q, sig_o;
-			sig_q = module->addWire(NEW_ID, inst->Input1Size());
+			sig_q = module->addWire(new_verific_id(inst), inst->Input1Size());
 
 			for (int i = int(inst->Input1Size())-1; i >= 0; i--){
 				sig_d.append(net_map_at(inst->GetInput1Bit(i)));
@@ -1210,8 +1270,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 						log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
 			}
 
-			clocking.addDff(NEW_ID, sig_d, sig_q);
-			module->addXnor(NEW_ID, sig_d, sig_q, sig_o);
+			clocking.addDff(new_verific_id(inst), sig_d, sig_q);
+			module->addXnor(new_verific_id(inst), sig_d, sig_q, sig_o);
 
 			if (!mode_keep)
 				continue;
@@ -1225,7 +1285,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 			SigSpec sig_d = net_map_at(inst->GetInput1());
 			SigSpec sig_o = net_map_at(inst->GetOutput());
-			SigSpec sig_q = module->addWire(NEW_ID);
+			SigSpec sig_q = module->addWire(new_verific_id(inst));
 
 			if (verific_verbose) {
 				log("    %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
@@ -1234,8 +1294,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 						log_signal(sig_d), log_signal(sig_q), log_signal(sig_o));
 			}
 
-			clocking.addDff(NEW_ID, sig_d, sig_q);
-			module->addXnor(NEW_ID, sig_d, sig_q, sig_o);
+			clocking.addDff(new_verific_id(inst), sig_d, sig_q);
+			module->addXnor(new_verific_id(inst), sig_d, sig_q, sig_o);
 
 			if (!mode_keep)
 				continue;
@@ -1254,7 +1314,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 				log("    %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
 						log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
 
-			past_ffs.insert(clocking.addDff(NEW_ID, sig_d, sig_q));
+			past_ffs.insert(clocking.addDff(new_verific_id(inst), sig_d, sig_q));
 
 			if (!mode_keep)
 				continue;
@@ -1268,14 +1328,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 			SigBit sig_d = net_map_at(inst->GetInput1());
 			SigBit sig_o = net_map_at(inst->GetOutput());
-			SigBit sig_q = module->addWire(NEW_ID);
+			SigBit sig_q = module->addWire(new_verific_id(inst));
 
 			if (verific_verbose)
 				log("    %sedge FF with D=%s, Q=%s, C=%s.\n", clocking.posedge ? "pos" : "neg",
 						log_signal(sig_d), log_signal(sig_q), log_signal(clocking.clock_sig));
 
-			clocking.addDff(NEW_ID, sig_d, sig_q);
-			module->addEq(NEW_ID, {sig_q, sig_d}, Const(inst->Type() == PRIM_SVA_ROSE ? 1 : 2, 2), sig_o);
+			clocking.addDff(new_verific_id(inst), sig_d, sig_q);
+			module->addEq(new_verific_id(inst), {sig_q, sig_d}, Const(inst->Type() == PRIM_SVA_ROSE ? 1 : 2, 2), sig_o);
 
 			if (!mode_keep)
 				continue;
@@ -1298,9 +1358,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 
 			Cell *cell = nullptr;
 			if (assume_attr != nullptr && !strcmp(assume_attr, "1"))
-				cell = module->addAssume(NEW_ID, cond, State::S1);
+				cell = module->addAssume(new_verific_id(inst), cond, State::S1);
 			else
-				cell = module->addAssert(NEW_ID, cond, State::S1);
+				cell = module->addAssert(new_verific_id(inst), cond, State::S1);
 
 			import_attributes(cell->attributes, inst);
 			continue;
@@ -1342,7 +1402,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 			IdString port_name_id = RTLIL::escape_id(port_name);
 			auto &sigvec = cell_port_conns[port_name_id];
 			if (GetSize(sigvec) <= port_offset) {
-				SigSpec zwires = module->addWire(NEW_ID, port_offset+1-GetSize(sigvec));
+				SigSpec zwires = module->addWire(new_verific_id(inst), port_offset+1-GetSize(sigvec));
 				for (auto bit : zwires)
 					sigvec.push_back(bit);
 			}
diff --git a/frontends/verific/verific.h b/frontends/verific/verific.h
index 334a436af..b331dd4b9 100644
--- a/frontends/verific/verific.h
+++ b/frontends/verific/verific.h
@@ -78,6 +78,7 @@ struct VerificImporter
 
 	RTLIL::SigBit net_map_at(Verific::Net *net);
 
+	RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
 	void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj);
 
 	RTLIL::SigSpec operatorInput(Verific::Instance *inst);

From 256fb8c95c3b974fb636f515297191a6fc70b356 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Tue, 18 Dec 2018 23:10:40 +0800
Subject: [PATCH 243/528] Add "dffinit -noreinit" parameter

Sometimes the FF cell might be initialized during the map process, e.g.
some FPGA platforms (Anlogic Eagle and Lattice ECP5 for example) has
only a "SR" pin for a FF for async reset, that resets the FF to the
initial value, which means the async reset value should be set as the
initial value. In this case the DFFINIT pass shouldn't reinitialize it
to a different value, which will lead to error.

Add a "-noreinit" parameter for the safeguard. If a FF is not
technically initialized before DFFINIT pass, the default value should be
set to x.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 passes/techmap/dffinit.cc | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index 4fa15a35b..48390488e 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -48,13 +48,18 @@ struct DffinitPass : public Pass {
 		log("        initial value of 1 or 0. (multi-bit values are not supported in this\n");
 		log("        mode.)\n");
 		log("\n");
+		log("    -noreinit\n");
+		log("        fail if the FF cell has already a defined initial value set in other\n");
+		log("        passes and the initial value of the net it drives is not equal to\n");
+		log("        the already defined initial value.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
 
 		dict<IdString, dict<IdString, IdString>> ff_types;
-		bool highlow_mode = false;
+		bool highlow_mode = false, noreinit = false;
 		std::string high_string, low_string;
 
 		size_t argidx;
@@ -78,6 +83,10 @@ struct DffinitPass : public Pass {
 				ff_types[cell_name][output_port] = init_param;
 				continue;
 			}
+			if (args[argidx] == "-noreinit") {
+				noreinit = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -126,6 +135,10 @@ struct DffinitPass : public Pass {
 							continue;
 						while (GetSize(value.bits) <= i)
 							value.bits.push_back(State::S0);
+						if (noreinit && value.bits[i] != State::Sx && value.bits[i] != init_bits.at(sig[i]))
+							log_error("Trying to assign a different init value for %s.%s.%s which technically "
+									"have a conflicted init value.\n",
+									log_id(module), log_id(cell), log_id(it.second));
 						value.bits[i] = init_bits.at(sig[i]);
 						cleanup_bits.insert(sig[i]);
 					}

From 4bf8ac728cbebabf2333f2a15b9e52c6af8b806a Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Tue, 18 Dec 2018 15:39:02 +0800
Subject: [PATCH 244/528] anlogic: set the init value of DFFs

As dffinit has already supported for different initialization strings
for DFFs and check for re-initialization, initialization of Anlogic
DFFs are now ready to go.

Support for set the init values of Anlogic DFFs.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/cells_map.v      | 28 ++++++++++++++--------------
 techlibs/anlogic/synth_anlogic.cc |  1 +
 2 files changed, 15 insertions(+), 14 deletions(-)

diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index 36b920ef0..98b8d46ef 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -1,19 +1,19 @@
-module  \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
-module  \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(1'b0)); endmodule
+module  \$_DFF_N_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(1'b0)); endmodule
+module  \$_DFF_P_ (input D, C, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(1'b0)); endmodule
 
-module  \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module  \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
-module  \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_NN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_NP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_PN_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'bx), .SRMUX("SR"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(E), .sr(1'b0)); endmodule
 
-module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(~C), .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C) , .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("INV"), .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b0), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET(1'b1), .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
 
 `ifndef NO_LUT
 module \$lut (A, Y);
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index a4eafeddf..492a830b9 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -170,6 +170,7 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("dffsr2dff");
 			run("techmap -D NO_LUT -map +/anlogic/cells_map.v");
+			run("dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit");
 			run("opt_expr -mux_undef");
 			run("simplemap");
 		}

From fdf7c421810e8718f7ee312ddd3cfdbfb65aa2ce Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Dec 2018 17:49:38 +0100
Subject: [PATCH 245/528] Fix segfault in AST simplify

(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 55abe165f..83714f897 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1810,6 +1810,11 @@ skip_dynamic_range_lvalue_expansion:;
 
 				log_assert(block != nullptr);
 
+				if (num_steps == 0) {
+					newNode = children[0]->clone();
+					goto apply_newNode;
+				}
+
 				int myidx = autoidx++;
 				AstNode *outreg = nullptr;
 

From 2b16d4ed3d4dc5776253fcb3736e3b54c8e4916e Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 18 Dec 2018 17:40:01 +0000
Subject: [PATCH 246/528] memory_dff: Fix typo when checking init value

Signed-off-by: David Shah <davey1576@gmail.com>
---
 passes/memory/memory_dff.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 32df19174..220d29295 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -41,7 +41,7 @@ struct MemoryDffWorker
 			if (wire->attributes.count("\\init") == 0)
 				continue;
 			SigSpec sig = sigmap(wire);
-			Const initval = wire->attributes.count("\\init");
+			Const initval = wire->attributes.at("\\init");
 			for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
 				if (initval[i] == State::S0 || initval[i] == State::S1)
 					init_bits.insert(sig[i]);

From 23bb77867f56e966195d99d1d89b45d510d0b92d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 18 Dec 2018 20:02:39 +0100
Subject: [PATCH 247/528] Minor style fixes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/btor/btor.cc       | 2 +-
 backends/btor/test_cells.sh | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 mode change 100755 => 100644 backends/btor/test_cells.sh

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index d3fb9b858..53359bd7b 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -134,7 +134,7 @@ struct BtorWorker
 		btorf_push(log_id(cell));
 
 		if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
-                      "$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
+				"$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
 		{
 			string btor_op;
 			if (cell->type == "$add") btor_op = "add";
diff --git a/backends/btor/test_cells.sh b/backends/btor/test_cells.sh
old mode 100755
new mode 100644

From c9513c695a76124ef1155343e3c058767c418051 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 19 Dec 2018 09:36:53 +0800
Subject: [PATCH 248/528] Anlogic: let LUT5/6 have more cost than LUT4-

According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.

So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.

Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/synth_anlogic.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index a4eafeddf..9c44599ea 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -176,7 +176,7 @@ struct SynthAnlogicPass : public ScriptPass
 
 		if (check_label("map_luts"))
 		{
-			run("abc -lut 6");
+			run("abc -lut 4:6");
 			run("clean");
 		}
 

From 3993ba71f7eb663fba73c0da4e35183b076168dd Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 19 Dec 2018 10:23:58 +0800
Subject: [PATCH 249/528] anlogic: fix Makefile.inc

During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.

Fix this issue.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/Makefile.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index 59be83fd0..f37b5e7e9 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -5,5 +5,6 @@ OBJS += techlibs/anlogic/anlogic_eqn.o
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))

From 90d00182cfe358438d777f2ca7abacb4c6a2733c Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Wed, 19 Dec 2018 10:18:47 +0800
Subject: [PATCH 250/528] anlogic: implement DRAM initialization

As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.

Now add the support by add a new pass to determine unknown values in the
initial value.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/Makefile.inc              |  2 +
 techlibs/anlogic/anlogic_determine_init.cc | 72 ++++++++++++++++++++++
 techlibs/anlogic/dram_init_16x4.vh         | 16 +++++
 techlibs/anlogic/drams.txt                 |  2 +-
 techlibs/anlogic/drams_map.v               |  5 +-
 techlibs/anlogic/synth_anlogic.cc          |  1 +
 6 files changed, 96 insertions(+), 2 deletions(-)
 create mode 100644 techlibs/anlogic/anlogic_determine_init.cc
 create mode 100644 techlibs/anlogic/dram_init_16x4.vh

diff --git a/techlibs/anlogic/Makefile.inc b/techlibs/anlogic/Makefile.inc
index f37b5e7e9..67cf9cf10 100644
--- a/techlibs/anlogic/Makefile.inc
+++ b/techlibs/anlogic/Makefile.inc
@@ -1,6 +1,7 @@
 
 OBJS += techlibs/anlogic/synth_anlogic.o
 OBJS += techlibs/anlogic/anlogic_eqn.o
+OBJS += techlibs/anlogic/anlogic_determine_init.o
 
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_map.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/arith_map.v))
@@ -8,3 +9,4 @@ $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/cells_sim.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/eagle_bb.v))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams.txt))
 $(eval $(call add_share_file,share/anlogic,techlibs/anlogic/drams_map.v))
+$(eval $(call add_share_file,share/anlogic,techlibs/anlogic/dram_init_16x4.vh))
diff --git a/techlibs/anlogic/anlogic_determine_init.cc b/techlibs/anlogic/anlogic_determine_init.cc
new file mode 100644
index 000000000..34b1d4f8a
--- /dev/null
+++ b/techlibs/anlogic/anlogic_determine_init.cc
@@ -0,0 +1,72 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018 Icenowy Zheng <icenowy@aosc.io>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct AnlogicDetermineInitPass : public Pass {
+	AnlogicDetermineInitPass() : Pass("anlogic_determine_init", "Anlogic: Determine the init value of cells") { }
+	void help() YS_OVERRIDE
+	{
+		log("\n");
+		log("    anlogic_determine_init [selection]\n");
+		log("\n");
+		log("Determine the init value of cells that doesn't allow unknown init value.\n");
+		log("\n");
+	}
+
+	Const determine_init(Const init)
+	{
+		for (int i = 0; i < GetSize(init); i++) {
+			if (init[i] != State::S0 && init[i] != State::S1)
+				init[i] = State::S0;
+		}
+
+		return init;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ANLOGIC_DETERMINE_INIT pass (determine init value for cells).\n");
+
+		extra_args(args, args.size(), design);
+
+		size_t cnt = 0;
+		for (auto module : design->selected_modules())
+		{
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type == "\\EG_LOGIC_DRAM16X4")
+				{
+					cell->setParam("\\INIT_D0", determine_init(cell->getParam("\\INIT_D0")));
+					cell->setParam("\\INIT_D1", determine_init(cell->getParam("\\INIT_D1")));
+					cell->setParam("\\INIT_D2", determine_init(cell->getParam("\\INIT_D2")));
+					cell->setParam("\\INIT_D3", determine_init(cell->getParam("\\INIT_D3")));
+					cnt++;
+				}
+			}
+		}
+		log_header(design, "Updated %lu cells with determined init value.\n", cnt);
+	}
+} AnlogicDetermineInitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/anlogic/dram_init_16x4.vh b/techlibs/anlogic/dram_init_16x4.vh
new file mode 100644
index 000000000..32fb1578c
--- /dev/null
+++ b/techlibs/anlogic/dram_init_16x4.vh
@@ -0,0 +1,16 @@
+.INIT_D0({INIT[15*4+0], INIT[14*4+0], INIT[13*4+0], INIT[12*4+0],
+	  INIT[11*4+0], INIT[10*4+0], INIT[9*4+0], INIT[8*4+0],
+	  INIT[7*4+0], INIT[6*4+0], INIT[5*4+0], INIT[4*4+0],
+	  INIT[3*4+0], INIT[2*4+0], INIT[1*4+0], INIT[0*4+0]}),
+.INIT_D1({INIT[15*4+1], INIT[14*4+1], INIT[13*4+1], INIT[12*4+1],
+	  INIT[11*4+1], INIT[10*4+1], INIT[9*4+1], INIT[8*4+1],
+	  INIT[7*4+1], INIT[6*4+1], INIT[5*4+1], INIT[4*4+1],
+	  INIT[3*4+1], INIT[2*4+1], INIT[1*4+1], INIT[0*4+1]}),
+.INIT_D2({INIT[15*4+2], INIT[14*4+2], INIT[13*4+2], INIT[12*4+2],
+	  INIT[11*4+2], INIT[10*4+2], INIT[9*4+2], INIT[8*4+2],
+	  INIT[7*4+2], INIT[6*4+2], INIT[5*4+2], INIT[4*4+2],
+	  INIT[3*4+2], INIT[2*4+2], INIT[1*4+2], INIT[0*4+2]}),
+.INIT_D3({INIT[15*4+3], INIT[14*4+3], INIT[13*4+3], INIT[12*4+3],
+	  INIT[11*4+3], INIT[10*4+3], INIT[9*4+3], INIT[8*4+3],
+	  INIT[7*4+3], INIT[6*4+3], INIT[5*4+3], INIT[4*4+3],
+	  INIT[3*4+3], INIT[2*4+3], INIT[1*4+3], INIT[0*4+3]})
diff --git a/techlibs/anlogic/drams.txt b/techlibs/anlogic/drams.txt
index eb94775ae..4e903c0a2 100644
--- a/techlibs/anlogic/drams.txt
+++ b/techlibs/anlogic/drams.txt
@@ -1,5 +1,5 @@
 bram $__ANLOGIC_DRAM16X4
-  init 0
+  init 1
   abits 4
   dbits 4
   groups 2
diff --git a/techlibs/anlogic/drams_map.v b/techlibs/anlogic/drams_map.v
index 87cbb6a45..084e2a25f 100644
--- a/techlibs/anlogic/drams_map.v
+++ b/techlibs/anlogic/drams_map.v
@@ -1,4 +1,5 @@
 module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
+	parameter [63:0]INIT = 64'bx;
 	input CLK1;
 
 	input [3:0] A1ADDR;
@@ -8,7 +9,9 @@ module \$__ANLOGIC_DRAM16X4 (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 	input [3:0] B1DATA;
 	input B1EN;
 
-	EG_LOGIC_DRAM16X4 _TECHMAP_REPLACE_ (
+	EG_LOGIC_DRAM16X4 #(
+		`include "dram_init_16x4.vh"
+	) _TECHMAP_REPLACE_ (
 		.di(B1DATA),
 		.waddr(B1ADDR),
 		.wclk(CLK1),
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 9c44599ea..b34f4788f 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -154,6 +154,7 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("memory_bram -rules +/anlogic/drams.txt");
 			run("techmap -map +/anlogic/drams_map.v");
+			run("anlogic_determine_init");
 		}
 
 		if (check_label("fine"))

From a9ff81dd82d347b5ed867f142e61271aa40d85ee Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 20 Dec 2018 04:37:28 +0000
Subject: [PATCH 251/528] manual: document $meminit cell and memory_* passes.

---
 manual/CHAPTER_CellLib.tex  | 27 +++++++++++++++++++++------
 manual/CHAPTER_Overview.tex |  4 ++--
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 277e89328..6589bb2e7 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -211,14 +211,15 @@ Add information about {\tt \$sr} cells (set-reset flip-flops) and d-type latches
 \subsection{Memories}
 \label{sec:memcells}
 
-Memories are either represented using RTLIL::Memory objects and {\tt \$memrd} and {\tt \$memwr} cells
-or simply by using {\tt \$mem} cells.
+Memories are either represented using RTLIL::Memory objects, {\tt \$memrd}, {\tt \$memwr}, and {\tt \$meminit}
+cells, or by {\tt \$mem} cells alone.
 
 In the first alternative the RTLIL::Memory objects hold the general metadata for the memory (bit width,
 size in number of words, etc.) and for each port a {\tt \$memrd} (read port) or {\tt \$memwr} (write port)
 cell is created. Having individual cells for read and write ports has the advantage that they can be
 consolidated using resource sharing passes. In some cases this drastically reduces the number of required
-ports on the memory cell.
+ports on the memory cell. In this alternative, memory initialization data is represented by {\tt \$meminit} cells,
+which allow delaying constant folding for initialization addresses and data until after the frontend finishes.
 
 The {\tt \$memrd} cells have a clock input \B{CLK}, an enable input \B{EN}, an
 address input \B{ADDR}, and a data output \B{DATA}. They also have the
@@ -273,6 +274,15 @@ edge if this parameter is {\tt 1'b0}.
 The cell with the higher integer value in this parameter wins a write conflict.
 \end{itemize}
 
+The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}. Both of the inputs
+must resolve to a constant for synthesis to succeed. If two {\tt \$meminit} cells have the same
+\B{MEMID} parameter and \B{ADDR} input, the contents of that memory at that address is undefined.
+
+\begin{itemize}
+\item \B{MEMID} \\
+The name of the RTLIL::Memory object that is associated with this initialization cell.
+\end{itemize}
+
 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous
 {\tt \$memrd} and {\tt \$memwr} cells. The {\tt memory} pass (i.e.~its various sub-passes) migrates
 {\tt \$dff} cells into the {\tt \$memrd} and {\tt \$memwr} cells making them synchronous, then
@@ -295,6 +305,9 @@ The number of address bits.
 \item \B{WIDTH} \\
 The number of data bits per word.
 
+\item \B{INIT} \\
+The initial memory contents.
+
 \item \B{RD\_PORTS} \\
 The number of read ports on this memory cell.
 
@@ -345,9 +358,11 @@ This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals
 This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all data signals for the write ports.
 \end{itemize}
 
-The {\tt techmap} pass can be used to manually map {\tt \$mem} cells to
-specialized memory cells on the target architecture, such as block ram resources
-on an FPGA.
+The {\tt memory\_collect} pass can be used to convert discrete {\tt \$memrd}, {\tt \$memwr}, and {\tt \$meminit} cells
+belonging to the same memory to a single {\tt \$mem} cell, whereas the {\tt memory\_unpack} pass performs the inverse operation.
+The {\tt memory\_dff} pass can combine asynchronous memory ports that are fed by or feeding registers into synchronous memory ports.
+The {\tt memory\_bram} pass can be used to recognize {\tt \$mem} cells that can be implemented with a block RAM resource on an FPGA.
+The {\tt memory\_map} pass can be used to implement {\tt \$mem} cells as basic logic: word-wide DFFs and address decoders.
 
 \subsection{Finite State Machines}
 
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex
index 964875d57..2feb0f1cb 100644
--- a/manual/CHAPTER_Overview.tex
+++ b/manual/CHAPTER_Overview.tex
@@ -428,8 +428,8 @@ memory object has the following properties:
 
 All read accesses to the memory are transformed to {\tt \$memrd} cells and all write accesses to
 {\tt \$memwr} cells by the language frontend. These cells consist of independent read- and write-ports
-to the memory. The \B{MEMID} parameter on these cells is used to link them together and to the
-RTLIL::Memory object they belong to.
+to the memory. Memory initialization is transformed to {\tt \$meminit} cells by the language frontend.
+The \B{MEMID} parameter on these cells is used to link them together and to the RTLIL::Memory object they belong to.
 
 The rationale behind using separate cells for the individual ports versus
 creating a large multiport memory cell right in the language frontend is that

From 2ca237e08665e4307da5bf40b7f3e17ca3e640db Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 20 Dec 2018 07:29:46 +0000
Subject: [PATCH 252/528] tcl: add support for passing arguments to scripts.

---
 kernel/yosys.cc | 25 ++++++++++++++++++-------
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index f002955ad..6884305d9 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -166,7 +166,7 @@ std::string vstringf(const char *fmt, va_list ap)
 	std::string string;
 	char *str = NULL;
 
-#if defined(_WIN32 )|| defined(__CYGWIN__) 
+#if defined(_WIN32 )|| defined(__CYGWIN__)
 	int sz = 64, rc;
 	while (1) {
 		va_list apc;
@@ -637,8 +637,9 @@ extern Tcl_Interp *yosys_get_tcl_interp()
 struct TclPass : public Pass {
 	TclPass() : Pass("tcl", "execute a TCL script file") { }
 	void help() YS_OVERRIDE {
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    tcl <filename>\n");
+		log("    tcl <filename> [args]\n");
 		log("\n");
 		log("This command executes the tcl commands in the specified file.\n");
 		log("Use 'yosys cmd' to run the yosys command 'cmd' from tcl.\n");
@@ -648,14 +649,24 @@ struct TclPass : public Pass {
 		log("'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'\n");
 		log("in order to avoid a name collision with the built in commands.\n");
 		log("\n");
+		log("If any arguments are specified, these arguments are provided to the script via\n");
+		log("the standard $argc and $argv variables.\n");
+		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE {
+	void execute(std::vector<std::string> args, RTLIL::Design *) YS_OVERRIDE {
 		if (args.size() < 2)
 			log_cmd_error("Missing script file.\n");
-		if (args.size() > 2)
-			extra_args(args, 1, design, false);
-		if (Tcl_EvalFile(yosys_get_tcl_interp(), args[1].c_str()) != TCL_OK)
-			log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(yosys_get_tcl_interp()));
+
+		std::vector<Tcl_Obj*> script_args;
+		for (auto it = args.begin() + 2; it != args.end(); ++it)
+			script_args.push_back(Tcl_NewStringObj((*it).c_str(), (*it).size()));
+
+		Tcl_Interp *interp = yosys_get_tcl_interp();
+		Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argc", 4), NULL, Tcl_NewIntObj(script_args.size()), 0);
+		Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv", 4), NULL, Tcl_NewListObj(script_args.size(), script_args.data()), 0);
+		Tcl_ObjSetVar2(interp, Tcl_NewStringObj("argv0", 5), NULL, Tcl_NewStringObj(args[1].c_str(), args[1].size()), 0);
+		if (Tcl_EvalFile(interp, args[1].c_str()) != TCL_OK)
+			log_cmd_error("TCL interpreter returned an error: %s\n", Tcl_GetStringResult(interp));
 	}
 } TclPass;
 #endif

From c04908c99740e616cae454aa6a5d7a3dd13af2fa Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Thu, 20 Dec 2018 07:59:40 +0000
Subject: [PATCH 253/528] manual: fix typos.

---
 manual/CHAPTER_CellLib.tex | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 6589bb2e7..65a79020f 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -254,7 +254,7 @@ enable bit for each data bit), an address input \B{ADDR} and a data input
 
 \begin{itemize}
 \item \B{MEMID} \\
-The name of the RTLIL::Memory object that is associated with this read port.
+The name of the RTLIL::Memory object that is associated with this write port.
 
 \item \B{ABITS} \\
 The number of address bits (width of the \B{ADDR} input port).
@@ -263,7 +263,7 @@ The number of address bits (width of the \B{ADDR} input port).
 The number of data bits (width of the \B{DATA} output port).
 
 \item \B{CLK\_ENABLE} \\
-When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and
+When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and
 the \B{CLK} input is not used.
 
 \item \B{CLK\_POLARITY} \\

From 0c318e7db513bed1844f594ae780f854ed08e18f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 21 Dec 2018 02:01:27 +0000
Subject: [PATCH 254/528] memory_collect: do not truncate 'x from \INIT.

The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
---
 passes/memory/memory_collect.cc | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 70d98713c..369fcc84e 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -184,9 +184,6 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
 	mem->parameters["\\OFFSET"] = Const(memory->start_offset);
 	mem->parameters["\\SIZE"] = Const(memory->size);
 	mem->parameters["\\ABITS"] = Const(addr_bits);
-
-	while (GetSize(init_data) > 1 && init_data.bits.back() == State::Sx && init_data.bits[GetSize(init_data)-2] == State::Sx)
-		init_data.bits.pop_back();
 	mem->parameters["\\INIT"] = init_data;
 
 	log_assert(sig_wr_clk.size() == wr_ports);

From 182d84ad54cff315e7afb07f5353a477e4c410f4 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 21 Dec 2018 01:26:08 +0000
Subject: [PATCH 255/528] manual: make description of $meminit ports match
 reality.

---
 manual/CHAPTER_CellLib.tex | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 65a79020f..d40a600ed 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -274,13 +274,25 @@ edge if this parameter is {\tt 1'b0}.
 The cell with the higher integer value in this parameter wins a write conflict.
 \end{itemize}
 
-The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}. Both of the inputs
-must resolve to a constant for synthesis to succeed. If two {\tt \$meminit} cells have the same
-\B{MEMID} parameter and \B{ADDR} input, the contents of that memory at that address is undefined.
+The {\tt \$meminit} cells have an address input \B{ADDR} and a data input \B{DATA}, with the width
+of the \B{DATA} port equal to \B{WIDTH} parameter times \B{WORDS} parameter. Both of the inputs
+must resolve to a constant for synthesis to succeed.
 
 \begin{itemize}
 \item \B{MEMID} \\
 The name of the RTLIL::Memory object that is associated with this initialization cell.
+
+\item \B{ABITS} \\
+The number of address bits (width of the \B{ADDR} input port).
+
+\item \B{WIDTH} \\
+The number of data bits per memory location.
+
+\item \B{WORDS} \\
+The number of consecutive memory locations initialized by this cell.
+
+\item \B{PRIORITY} \\
+The cell with the higher integer value in this parameter wins an initialization conflict.
 \end{itemize}
 
 The HDL frontend models a memory using RTLIL::Memory objects and asynchronous

From b784440857d6b71f46ae8784cc3767962e4edcaa Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sat, 22 Dec 2018 08:58:37 +0000
Subject: [PATCH 256/528] proc_clean: remove any empty cases at the end of the
 switch.

Previously, only completely empty switches were removed.
---
 passes/proc/proc_clean.cc | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index b9e43d1db..477d1ac60 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -77,18 +77,14 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 	}
 	else
 	{
-		bool all_cases_are_empty = true;
 		for (auto cs : sw->cases) {
-			if (cs->actions.size() != 0 || cs->switches.size() != 0)
-				all_cases_are_empty = false;
 			if (max_depth != 0)
 				proc_clean_case(cs, did_something, count, max_depth-1);
 		}
-		if (all_cases_are_empty) {
+		while (!sw->cases.empty() && (sw->cases.back()->actions.empty() && sw->cases.back()->switches.empty())) {
 			did_something = true;
-			for (auto cs : sw->cases)
-				delete cs;
-			sw->cases.clear();
+			delete sw->cases.back();
+			sw->cases.pop_back();
 		}
 	}
 }

From 18291c20d2b17689729d9c36b08967e928e4e32a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 23 Dec 2018 09:04:23 +0000
Subject: [PATCH 257/528] proc_clean: remove any empty cases if all cases use
 all-def compare.

---
 kernel/rtlil.cc           | 10 ++++++++++
 kernel/rtlil.h            |  4 ++++
 passes/proc/proc_clean.cc | 34 ++++++++++++++++++++++++++++------
 3 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 14259f8ed..8404db5e9 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3793,6 +3793,11 @@ RTLIL::CaseRule::~CaseRule()
 		delete *it;
 }
 
+bool RTLIL::CaseRule::empty() const
+{
+	return actions.empty() && switches.empty();
+}
+
 RTLIL::CaseRule *RTLIL::CaseRule::clone() const
 {
 	RTLIL::CaseRule *new_caserule = new RTLIL::CaseRule;
@@ -3809,6 +3814,11 @@ RTLIL::SwitchRule::~SwitchRule()
 		delete *it;
 }
 
+bool RTLIL::SwitchRule::empty() const
+{
+	return cases.empty();
+}
+
 RTLIL::SwitchRule *RTLIL::SwitchRule::clone() const
 {
 	RTLIL::SwitchRule *new_switchrule = new RTLIL::SwitchRule;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 276540aa1..f877622aa 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1227,6 +1227,8 @@ struct RTLIL::CaseRule
 	~CaseRule();
 	void optimize();
 
+	bool empty() const;
+
 	template<typename T> void rewrite_sigspecs(T &functor);
 	RTLIL::CaseRule *clone() const;
 };
@@ -1238,6 +1240,8 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
 
 	~SwitchRule();
 
+	bool empty() const;
+
 	template<typename T> void rewrite_sigspecs(T &functor);
 	RTLIL::SwitchRule *clone() const;
 };
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 477d1ac60..3919e4b9c 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -77,14 +77,36 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 	}
 	else
 	{
-		for (auto cs : sw->cases) {
+		bool all_fully_def = true;
+		for (auto cs : sw->cases)
+		{
 			if (max_depth != 0)
 				proc_clean_case(cs, did_something, count, max_depth-1);
+			for (auto cmp : cs->compare)
+				if (!cmp.is_fully_def())
+					all_fully_def = false;
 		}
-		while (!sw->cases.empty() && (sw->cases.back()->actions.empty() && sw->cases.back()->switches.empty())) {
-			did_something = true;
-			delete sw->cases.back();
-			sw->cases.pop_back();
+		if (all_fully_def)
+		{
+			for (auto cs = sw->cases.begin(); cs != sw->cases.end();)
+			{
+				if ((*cs)->empty())
+				{
+					did_something = true;
+					delete *cs;
+					cs = sw->cases.erase(cs);
+				}
+				else ++cs;
+			}
+		}
+		else
+		{
+			while (!sw->cases.empty() && sw->cases.back()->empty())
+			{
+				did_something = true;
+				delete sw->cases.back();
+				sw->cases.pop_back();
+			}
 		}
 	}
 }
@@ -102,7 +124,7 @@ void proc_clean_case(RTLIL::CaseRule *cs, bool &did_something, int &count, int m
 	}
 	for (size_t i = 0; i < cs->switches.size(); i++) {
 		RTLIL::SwitchRule *sw = cs->switches[i];
-		if (sw->cases.size() == 0) {
+		if (sw->empty()) {
 			cs->switches.erase(cs->switches.begin() + (i--));
 			did_something = true;
 			delete sw;

From 6dad1913779f729222f65e1098a4facb36c5837a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 23 Dec 2018 15:45:09 +0100
Subject: [PATCH 258/528] Add "read_ilang -[no]overwrite"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ilang/ilang_frontend.cc | 30 +++++++++++++++++++++++++++++-
 frontends/ilang/ilang_frontend.h  |  2 ++
 frontends/ilang/ilang_parser.y    | 26 +++++++++++++++++++++++---
 3 files changed, 54 insertions(+), 4 deletions(-)

diff --git a/frontends/ilang/ilang_frontend.cc b/frontends/ilang/ilang_frontend.cc
index d8783ac1d..6b302a796 100644
--- a/frontends/ilang/ilang_frontend.cc
+++ b/frontends/ilang/ilang_frontend.cc
@@ -44,11 +44,39 @@ struct IlangFrontend : public Frontend {
 		log("Load modules from an ilang file to the current design. (ilang is a text\n");
 		log("representation of a design in yosys's internal format.)\n");
 		log("\n");
+		log("    -nooverwrite\n");
+		log("        ignore re-definitions of modules. (the default behavior is to\n");
+		log("        create an error message if the existing module is not a blackbox\n");
+		log("        module, and overwrite the existing module if it is  a blackbox module.)\n");
+		log("\n");
+		log("    -overwrite\n");
+		log("        overwrite existing modules with the same name\n");
+		log("\n");
 	}
 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
+		ILANG_FRONTEND::flag_nooverwrite = false;
+		ILANG_FRONTEND::flag_overwrite = false;
+
 		log_header(design, "Executing ILANG frontend.\n");
-		extra_args(f, filename, args, 1);
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-nooverwrite") {
+				ILANG_FRONTEND::flag_nooverwrite = true;
+				ILANG_FRONTEND::flag_overwrite = false;
+				continue;
+			}
+			if (arg == "-overwrite") {
+				ILANG_FRONTEND::flag_nooverwrite = false;
+				ILANG_FRONTEND::flag_overwrite = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(f, filename, args, argidx);
+
 		log("Input filename: %s\n", filename.c_str());
 
 		ILANG_FRONTEND::lexin = f;
diff --git a/frontends/ilang/ilang_frontend.h b/frontends/ilang/ilang_frontend.h
index ad3ffec90..052dd4cb2 100644
--- a/frontends/ilang/ilang_frontend.h
+++ b/frontends/ilang/ilang_frontend.h
@@ -32,6 +32,8 @@ YOSYS_NAMESPACE_BEGIN
 namespace ILANG_FRONTEND {
 	extern std::istream *lexin;
 	extern RTLIL::Design *current_design;
+	extern bool flag_nooverwrite;
+	extern bool flag_overwrite;
 }
 
 YOSYS_NAMESPACE_END
diff --git a/frontends/ilang/ilang_parser.y b/frontends/ilang/ilang_parser.y
index b957ecd96..5bcc01f42 100644
--- a/frontends/ilang/ilang_parser.y
+++ b/frontends/ilang/ilang_parser.y
@@ -37,6 +37,8 @@ namespace ILANG_FRONTEND {
 	std::vector<std::vector<RTLIL::SwitchRule*>*> switch_stack;
 	std::vector<RTLIL::CaseRule*> case_stack;
 	dict<RTLIL::IdString, RTLIL::Const> attrbuf;
+	bool flag_nooverwrite, flag_overwrite;
+	bool delete_current_module;
 }
 using namespace ILANG_FRONTEND;
 YOSYS_NAMESPACE_END
@@ -93,18 +95,36 @@ design:
 
 module:
 	TOK_MODULE TOK_ID EOL {
-		if (current_design->has($2))
-			rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
+		delete_current_module = false;
+		if (current_design->has($2)) {
+			RTLIL::Module *existing_mod = current_design->module($2);
+			if (!flag_overwrite && attrbuf.count("\\blackbox") && attrbuf.at("\\blackbox").as_bool()) {
+				log("Ignoring blackbox re-definition of module %s.\n", $2);
+				delete_current_module = true;
+			} else if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) {
+				rtlil_frontend_ilang_yyerror(stringf("ilang error: redefinition of module %s.", $2).c_str());
+			} else if (flag_nooverwrite) {
+				log("Ignoring re-definition of module %s.\n", $2);
+				delete_current_module = true;
+			} else {
+				log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", $2);
+				current_design->remove(existing_mod);
+			}
+		}
 		current_module = new RTLIL::Module;
 		current_module->name = $2;
 		current_module->attributes = attrbuf;
-		current_design->add(current_module);
+		if (!delete_current_module)
+			current_design->add(current_module);
 		attrbuf.clear();
 		free($2);
 	} module_body TOK_END {
 		if (attrbuf.size() != 0)
 			rtlil_frontend_ilang_yyerror("dangling attribute");
 		current_module->fixup_ports();
+		if (delete_current_module)
+			delete current_module;
+		current_module = nullptr;
 	} EOL;
 
 module_body:

From 1b369442995ea3f83d0d0445bb34c8f8115c10a3 Mon Sep 17 00:00:00 2001
From: Icenowy Zheng <icenowy@aosc.io>
Date: Tue, 25 Dec 2018 22:47:46 +0800
Subject: [PATCH 259/528] anlogic: add latch cells

Add latch cells to Anlogic cells replacement library by copying other
FPGAs' latch code to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 techlibs/anlogic/cells_map.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/techlibs/anlogic/cells_map.v b/techlibs/anlogic/cells_map.v
index 36b920ef0..f54a81dcc 100644
--- a/techlibs/anlogic/cells_map.v
+++ b/techlibs/anlogic/cells_map.v
@@ -15,6 +15,18 @@ module  \$_DFF_PN1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REG
 module  \$_DFF_PP0_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("RESET"), .SRMUX("SR"),  .SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
 module  \$_DFF_PP1_ (input D, C, R, output Q); AL_MAP_SEQ #(.DFFMODE("FF"), .REGSET("SET"),   .SRMUX("SR"), . SRMODE("SYNC")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C),  .ce(1'b1), .sr(R)); endmodule
 
+module \$_DLATCH_N_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = !E ? D : Q;
+endmodule
+
+module \$_DLATCH_P_ (E, D, Q);
+  wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
+  input E, D;
+  output Q = E ? D : Q;
+endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
   parameter WIDTH = 0;

From 99706b3bf48de121e58b76d4341d601f0bcc26cd Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Fri, 28 Dec 2018 08:24:31 -0800
Subject: [PATCH 260/528] Squelch a little more trailing whitespace

---
 backends/simplec/test00_uut.v | 6 +++---
 tests/sva/basic01.sv          | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/backends/simplec/test00_uut.v b/backends/simplec/test00_uut.v
index 744dbe9e3..92329a6f9 100644
--- a/backends/simplec/test00_uut.v
+++ b/backends/simplec/test00_uut.v
@@ -3,12 +3,12 @@ module test(input [31:0] a, b, c, output [31:0] x, y, z, w);
   unit_y unit_y_inst (.a(a), .b(b), .c(c), .y(y));
   assign z = a ^ b ^ c, w = z;
 endmodule
-  
+
 module unit_x(input [31:0] a, b, c, output [31:0] x);
   assign x = (a & b) | c;
 endmodule
-  
+
 module unit_y(input [31:0] a, b, c, output [31:0] y);
   assign y = a & (b | c);
 endmodule
-  
+
diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv
index 74ab93430..d5ad497dd 100644
--- a/tests/sva/basic01.sv
+++ b/tests/sva/basic01.sv
@@ -6,7 +6,7 @@ module top (input logic clock, ctrl);
 		write <= ctrl;
 		ready <= write;
 	end
-	
+
 	a_rw: assert property ( @(posedge clock) !(read && write) );
 `ifdef FAIL
 	a_wr: assert property ( @(posedge clock) write |-> ready );

From ebe9351f82279f83ef16a24faac9853d40b3ece1 Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Fri, 28 Dec 2018 08:21:53 -0800
Subject: [PATCH 261/528] Fix 7 instances of add_share_file to
 add_gen_share_file

in techlibs/ecp5/Makefile.inc to permit out-of-tree builds
---
 techlibs/ecp5/Makefile.inc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index b23d5c70e..8df02be5f 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -34,11 +34,11 @@ techlibs/ecp5/bram_conn_4.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_9.vh: techlibs/ecp5/brams_connect.mk
 techlibs/ecp5/bram_conn_18.vh: techlibs/ecp5/brams_connect.mk
 
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_1_2_4.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_init_9_18_36.vh))
 
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_1.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_2.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_4.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_9.vh))
+$(eval $(call add_gen_share_file,share/ecp5,techlibs/ecp5/bram_conn_18.vh))

From 0a840dd88334c382314db3aafc2f1da2a1969df2 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 31 Dec 2018 16:34:27 +0100
Subject: [PATCH 262/528] Fix handling of (* keep *) wires in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/wreduce.cc | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 0164f58d6..8063b86a6 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -235,8 +235,11 @@ struct WreduceWorker
 		} else {
 			while (GetSize(sig) > 0)
 			{
-				auto info = mi.query(sig[GetSize(sig)-1]);
+				auto bit = sig[GetSize(sig)-1];
+				if (keep_bits.count(bit))
+					break;
 
+				auto info = mi.query(bit);
 				if (info->is_output || GetSize(info->ports) > 1)
 					break;
 

From 42c356c49c04a735fe27e672ff31452170f84b40 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 31 Dec 2018 23:53:23 +0000
Subject: [PATCH 263/528] opt_lut: eliminate LUTs evaluating to constants or
 inputs.

---
 passes/opt/opt_lut.cc     | 81 +++++++++++++++++++++++++++++++++++++++
 tests/opt/opt_lut_elim.il | 19 +++++++++
 tests/opt/opt_lut_elim.ys |  3 ++
 tests/opt/opt_lut_port.ys |  1 +
 4 files changed, 104 insertions(+)
 create mode 100644 tests/opt/opt_lut_elim.il
 create mode 100644 tests/opt/opt_lut_elim.ys

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index be050c713..261af538f 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -187,6 +187,87 @@ struct OptLutWorker
 		}
 		show_stats_by_arity();
 
+		log("\n");
+		log("Eliminating LUTs.\n");
+		for (auto lut : luts)
+		{
+			SigSpec lut_input = sigmap(lut->getPort("\\A"));
+			pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
+
+			vector<SigBit> lut_inputs;
+			for (auto &bit : lut_input)
+			{
+				if (bit.wire)
+					lut_inputs.push_back(sigmap(bit));
+			}
+
+			bool const0_match = true;
+			bool const1_match = true;
+			vector<bool> input_matches;
+			for (size_t i = 0; i < lut_inputs.size(); i++)
+				input_matches.push_back(true);
+
+			for (int eval = 0; eval < 1 << lut_inputs.size(); eval++)
+			{
+				dict<SigBit, bool> eval_inputs;
+				for (size_t i = 0; i < lut_inputs.size(); i++)
+					eval_inputs[lut_inputs[i]] = (eval >> i) & 1;
+				bool value = evaluate_lut(lut, eval_inputs);
+				if (value != 0)
+					const0_match = false;
+				if (value != 1)
+					const1_match = false;
+				for (size_t i = 0; i < lut_inputs.size(); i++)
+				{
+					if (value != eval_inputs[lut_inputs[i]])
+						input_matches[i] = false;
+				}
+			}
+
+			int input_match = -1;
+			for (size_t i = 0; i < lut_inputs.size(); i++)
+				if (input_matches[i])
+					input_match = i;
+
+			if (const0_match || const1_match || input_match != -1)
+			{
+				log("Found redundant cell %s.%s.\n", log_id(module), log_id(lut));
+
+				SigBit value;
+				if (const0_match)
+				{
+					log("  Cell evaluates constant 0.\n");
+					value = State::S0;
+				}
+				if (const1_match)
+				{
+					log("  Cell evaluates constant 1.\n");
+					value = State::S1;
+				}
+				if (input_match != -1) {
+					log("  Cell evaluates signal %s.\n", log_signal(lut_inputs[input_match]));
+					value = lut_inputs[input_match];
+				}
+
+				if (lut_dlogic_inputs.size())
+				{
+					log("  Not eliminating cell (connected to dedicated logic).\n");
+				}
+				else
+				{
+					SigSpec lut_output = lut->getPort("\\Y");
+					module->connect(lut_output, value);
+
+					module->remove(lut);
+					luts.erase(lut);
+					luts_arity.erase(lut);
+					luts_dlogics.erase(lut);
+					luts_dlogic_inputs.erase(lut);
+				}
+			}
+		}
+		show_stats_by_arity();
+
 		log("\n");
 		log("Combining LUTs.\n");
 		pool<RTLIL::Cell*> worklist = luts;
diff --git a/tests/opt/opt_lut_elim.il b/tests/opt/opt_lut_elim.il
new file mode 100644
index 000000000..75675d983
--- /dev/null
+++ b/tests/opt/opt_lut_elim.il
@@ -0,0 +1,19 @@
+module \test
+  wire input 1 \i
+
+  wire output 2 \o1
+  cell $lut $1
+    parameter \LUT 16'0110100110010110
+    parameter \WIDTH 4
+    connect \A { \i 3'000 }
+    connect \Y \o1
+  end
+
+  wire output 2 \o2
+  cell $lut $2
+    parameter \LUT 16'0110100010010110
+    parameter \WIDTH 4
+    connect \A { \i 3'000 }
+    connect \Y \o2
+  end
+end
diff --git a/tests/opt/opt_lut_elim.ys b/tests/opt/opt_lut_elim.ys
new file mode 100644
index 000000000..8e5e23aea
--- /dev/null
+++ b/tests/opt/opt_lut_elim.ys
@@ -0,0 +1,3 @@
+read_ilang opt_lut_elim.il
+opt_lut
+select -assert-count 0 t:$lut
diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
index 51dfd988b..3cb4ecb23 100644
--- a/tests/opt/opt_lut_port.ys
+++ b/tests/opt/opt_lut_port.ys
@@ -1,2 +1,3 @@
 read_ilang opt_lut_port.il
+opt_lut
 select -assert-count 2 t:$lut

From 8e53d2e0bf3584709cd320447ad5a89a80dcfd94 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 02:45:49 +0000
Subject: [PATCH 264/528] opt_expr: simplify any unsigned comparisons with
 all-0 and all-1.

Before this commit, only unsigned comparisons with all-0 would be
simplified. This commit also makes the code handling such comparisons
to be more rigorous and not abort on unexpected input.
---
 passes/opt/opt_expr.cc    | 86 +++++++++++++++++++++++++++++++--------
 tests/opt/opt_expr_cmp.v  | 11 +++++
 tests/opt/opt_expr_cmp.ys |  4 ++
 3 files changed, 84 insertions(+), 17 deletions(-)
 create mode 100644 tests/opt/opt_expr_cmp.v
 create mode 100644 tests/opt/opt_expr_cmp.ys

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 610edc5e9..87597ce57 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1344,6 +1344,75 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
+		// simplify comparisons
+		// currently, only replaces comparisons with an extreme of the signal range with a constant
+		// TODO: since, unlike the following optimization, this one does not assume that both inputs to the cell are constant,
+		// it is more robust; the following optimization should be folded into this one at some point
+		if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
+		{
+			IdString cmp_type = cell->type;
+			SigSpec var_sig = cell->getPort("\\A");
+			SigSpec const_sig = cell->getPort("\\B");
+			int var_width = cell->parameters["\\A_WIDTH"].as_int();
+			int const_width = cell->parameters["\\B_WIDTH"].as_int();
+			bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+
+			if (!const_sig.is_fully_const())
+			{
+				std::swap(var_sig, const_sig);
+				std::swap(var_width, const_width);
+				if (cmp_type == "$gt")
+					cmp_type = "$lt";
+				else if (cmp_type == "$lt")
+					cmp_type = "$gt";
+				else if (cmp_type == "$ge")
+					cmp_type = "$le";
+				else if (cmp_type == "$le")
+					cmp_type = "$ge";
+			}
+
+			if (const_sig.is_fully_def() && const_sig.is_fully_const())
+			{
+				const char *condition, *replacement;
+				SigSpec result_sig(State::S0, GetSize(cell->getPort("\\Y")));
+				result_sig[0] = State::Sx;
+
+				if (!is_signed)
+				{
+					if (const_sig.is_fully_zero() && cmp_type == "$lt") {
+						condition   = "unsigned X<0";
+						replacement = "constant 0";
+						result_sig[0] = State::S0;
+					}
+					if (const_sig.is_fully_zero() && cmp_type == "$ge") {
+						condition   = "unsigned X>=0";
+						replacement = "constant 1";
+						result_sig[0] = State::S1;
+					}
+					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$gt") {
+						condition   = "unsigned X>~0";
+						replacement = "constant 0";
+						result_sig[0] = State::S0;
+					}
+					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$le") {
+						condition   = "unsigned X<=~0";
+						replacement = "constant 1";
+						result_sig[0] = State::S1;
+					}
+				}
+
+				if (result_sig.is_fully_def())
+				{
+					log("Replacing %s cell `%s' (implementing %s) with %s.\n",
+							log_id(cell->type), log_id(cell), condition, replacement);
+					module->connect(cell->getPort("\\Y"), result_sig);
+					module->remove(cell);
+					did_something = true;
+					goto next_cell;
+				}
+			}
+		}
+
 		// replace a<0 or a>=0 with the top bit of a
 		if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
 		{
@@ -1405,23 +1474,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			} else
 			if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
 			{
-				if (sigConst.is_fully_zero()) {
-					RTLIL::SigSpec a_prime(RTLIL::State::S0, GetSize(cell->getPort("\\Y")));
-					if (is_lt) {
-						log("Replacing %s cell `%s' (implementing unsigned X<0) with constant false.\n",
-								log_id(cell->type), log_id(cell));
-						a_prime[0] = RTLIL::State::S0;
-					} else {
-						log("Replacing %s cell `%s' (implementing unsigned X>=0) with constant true.\n",
-								log_id(cell->type), log_id(cell));
-						a_prime[0] = RTLIL::State::S1;
-					}
-					module->connect(cell->getPort("\\Y"), a_prime);
-					module->remove(cell);
-					did_something = true;
-					goto next_cell;
-				}
-
 				int const_bit_set = get_onehot_bit_index(sigConst);
 				if (const_bit_set >= 0 && const_bit_set < width) {
 					int bit_set = const_bit_set;
diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
new file mode 100644
index 000000000..7eb65d531
--- /dev/null
+++ b/tests/opt/opt_expr_cmp.v
@@ -0,0 +1,11 @@
+module top(...);
+  input [3:0] a;
+  output o1 = 4'b0000 >  a;
+  output o2 = 4'b0000 <= a;
+  output o3 = 4'b1111 <  a;
+  output o4 = 4'b1111 >= a;
+  output o5 = a <  4'b0000;
+  output o6 = a >= 4'b0000;
+  output o7 = a >  4'b1111;
+  output o8 = a <= 4'b1111;
+endmodule
diff --git a/tests/opt/opt_expr_cmp.ys b/tests/opt/opt_expr_cmp.ys
new file mode 100644
index 000000000..214ce8b11
--- /dev/null
+++ b/tests/opt/opt_expr_cmp.ys
@@ -0,0 +1,4 @@
+read_verilog opt_expr_cmp.v
+equiv_opt -assert opt_expr -fine
+design -load postopt
+select -assert-count 0 t:$gt t:$ge t:$lt t:$le

From 9e9846a6ead700756fbd7a5e6c72ccb424006934 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 03:01:25 +0000
Subject: [PATCH 265/528] opt_expr: refactor simplification of signed X>=0 and
 X<0. NFCI.

---
 passes/opt/opt_expr.cc   | 50 +++++++++++++++++++++-------------------
 tests/opt/opt_expr_cmp.v | 22 +++++++++++-------
 2 files changed, 40 insertions(+), 32 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 87597ce57..989c949ce 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1373,38 +1373,59 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 
 			if (const_sig.is_fully_def() && const_sig.is_fully_const())
 			{
-				const char *condition, *replacement;
+				std::string condition, replacement;
 				SigSpec result_sig(State::S0, GetSize(cell->getPort("\\Y")));
-				result_sig[0] = State::Sx;
+				bool replace = false;
 
 				if (!is_signed)
-				{
+				{ /* unsigned */
 					if (const_sig.is_fully_zero() && cmp_type == "$lt") {
 						condition   = "unsigned X<0";
 						replacement = "constant 0";
 						result_sig[0] = State::S0;
+						replace = true;
 					}
 					if (const_sig.is_fully_zero() && cmp_type == "$ge") {
 						condition   = "unsigned X>=0";
 						replacement = "constant 1";
 						result_sig[0] = State::S1;
+						replace = true;
 					}
 					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$gt") {
 						condition   = "unsigned X>~0";
 						replacement = "constant 0";
 						result_sig[0] = State::S0;
+						replace = true;
 					}
 					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$le") {
 						condition   = "unsigned X<=~0";
 						replacement = "constant 1";
 						result_sig[0] = State::S1;
+						replace = true;
+					}
+				}
+				else
+				{ /* signed */
+					if (const_sig.is_fully_zero() && cmp_type == "$lt")
+					{
+						condition   = "signed X<0";
+						replacement = stringf("X[%d]", var_width - 1);
+						result_sig[0] = var_sig[var_width - 1];
+						replace = true;
+					}
+					if (const_sig.is_fully_zero() && cmp_type == "$ge")
+					{
+						condition   = "signed X>=0";
+						replacement = stringf("X[%d]", var_width - 1);
+						module->addNot(NEW_ID, var_sig[var_width - 1], result_sig);
+						replace = true;
 					}
 				}
 
-				if (result_sig.is_fully_def())
+				if (replace)
 				{
 					log("Replacing %s cell `%s' (implementing %s) with %s.\n",
-							log_id(cell->type), log_id(cell), condition, replacement);
+							log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
 					module->connect(cell->getPort("\\Y"), result_sig);
 					module->remove(cell);
 					did_something = true;
@@ -1453,25 +1474,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			} else
 				log_abort();
 
-			// replace a(signed) < 0 with the high bit of a
-			if (sigConst.is_fully_const() && sigConst.is_fully_zero() && var_signed == true)
-			{
-				RTLIL::SigSpec a_prime(RTLIL::State::S0, cell->parameters["\\Y_WIDTH"].as_int());
-				a_prime[0] = sigVar[width - 1];
-				if (is_lt) {
-					log("Replacing %s cell `%s' (implementing X<0) with X[%d]: %s\n",
-							log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
-					module->connect(cell->getPort("\\Y"), a_prime);
-					module->remove(cell);
-				} else {
-					log("Replacing %s cell `%s' (implementing X>=0) with ~X[%d]: %s\n",
-							log_id(cell->type), log_id(cell), width-1, log_signal(a_prime));
-					module->addNot(NEW_ID, a_prime, cell->getPort("\\Y"));
-					module->remove(cell);
-				}
-				did_something = true;
-				goto next_cell;
-			} else
 			if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
 			{
 				int const_bit_set = get_onehot_bit_index(sigConst);
diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
index 7eb65d531..72372bdf0 100644
--- a/tests/opt/opt_expr_cmp.v
+++ b/tests/opt/opt_expr_cmp.v
@@ -1,11 +1,17 @@
 module top(...);
   input [3:0] a;
-  output o1 = 4'b0000 >  a;
-  output o2 = 4'b0000 <= a;
-  output o3 = 4'b1111 <  a;
-  output o4 = 4'b1111 >= a;
-  output o5 = a <  4'b0000;
-  output o6 = a >= 4'b0000;
-  output o7 = a >  4'b1111;
-  output o8 = a <= 4'b1111;
+
+  output o1_1 = 4'b0000 >  a;
+  output o1_2 = 4'b0000 <= a;
+  output o1_3 = 4'b1111 <  a;
+  output o1_4 = 4'b1111 >= a;
+  output o1_5 = a <  4'b0000;
+  output o1_6 = a >= 4'b0000;
+  output o1_7 = a >  4'b1111;
+  output o1_8 = a <= 4'b1111;
+
+  output o2_1 = 4'sb0000 >  $signed(a);
+  output o2_2 = 4'sb0000 <= $signed(a);
+  output o2_3 = $signed(a) <  4'sb0000;
+  output o2_4 = $signed(a) >= 4'sb0000;
 endmodule

From 4fd458290c3da4c3f372f2e1fdd99829a9462a38 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 04:31:20 +0000
Subject: [PATCH 266/528] opt_expr: refactor simplification of unsigned
 X<onehot and X>=onehot. NFCI.

---
 passes/opt/opt_expr.cc   | 68 ++++++++++++++++++++++------------------
 tests/opt/opt_expr_cmp.v |  5 +++
 2 files changed, 42 insertions(+), 31 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 989c949ce..9abbdc6ac 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1374,35 +1374,60 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if (const_sig.is_fully_def() && const_sig.is_fully_const())
 			{
 				std::string condition, replacement;
-				SigSpec result_sig(State::S0, GetSize(cell->getPort("\\Y")));
+				SigSpec replace_sig(State::S0, GetSize(cell->getPort("\\Y")));
 				bool replace = false;
+				bool remove = false;
 
 				if (!is_signed)
 				{ /* unsigned */
 					if (const_sig.is_fully_zero() && cmp_type == "$lt") {
 						condition   = "unsigned X<0";
 						replacement = "constant 0";
-						result_sig[0] = State::S0;
+						replace_sig[0] = State::S0;
 						replace = true;
 					}
 					if (const_sig.is_fully_zero() && cmp_type == "$ge") {
 						condition   = "unsigned X>=0";
 						replacement = "constant 1";
-						result_sig[0] = State::S1;
+						replace_sig[0] = State::S1;
 						replace = true;
 					}
 					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$gt") {
 						condition   = "unsigned X>~0";
 						replacement = "constant 0";
-						result_sig[0] = State::S0;
+						replace_sig[0] = State::S0;
 						replace = true;
 					}
 					if (const_width == var_width && const_sig.is_fully_ones() && cmp_type == "$le") {
 						condition   = "unsigned X<=~0";
 						replacement = "constant 1";
-						result_sig[0] = State::S1;
+						replace_sig[0] = State::S1;
 						replace = true;
 					}
+
+					int const_bit_set = get_onehot_bit_index(const_sig);
+					if (const_bit_set >= 0 && const_bit_set < var_width)
+					{
+						RTLIL::SigSpec var_high_sig(RTLIL::State::S0, var_width - const_bit_set);
+						for (int i = const_bit_set; i < var_width; i++) {
+							var_high_sig[i - const_bit_set] = var_sig[i];
+						}
+
+						if (cmp_type == "$lt")
+						{
+							condition   = stringf("unsigned X<%s", log_signal(const_sig));
+							replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_set);
+							module->addLogicNot(NEW_ID, var_high_sig, cell->getPort("\\Y"));
+							remove = true;
+						}
+						if (cmp_type == "$ge")
+						{
+							condition   = stringf("unsigned X>=%s", log_signal(const_sig));
+							replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_set);
+							module->addReduceOr(NEW_ID, var_high_sig, cell->getPort("\\Y"));
+							remove = true;
+						}
+					}
 				}
 				else
 				{ /* signed */
@@ -1410,23 +1435,24 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					{
 						condition   = "signed X<0";
 						replacement = stringf("X[%d]", var_width - 1);
-						result_sig[0] = var_sig[var_width - 1];
+						replace_sig[0] = var_sig[var_width - 1];
 						replace = true;
 					}
 					if (const_sig.is_fully_zero() && cmp_type == "$ge")
 					{
 						condition   = "signed X>=0";
 						replacement = stringf("X[%d]", var_width - 1);
-						module->addNot(NEW_ID, var_sig[var_width - 1], result_sig);
-						replace = true;
+						module->addNot(NEW_ID, var_sig[var_width - 1], cell->getPort("\\Y"));
+						remove = true;
 					}
 				}
 
-				if (replace)
+				if (replace || remove)
 				{
 					log("Replacing %s cell `%s' (implementing %s) with %s.\n",
 							log_id(cell->type), log_id(cell), condition.c_str(), replacement.c_str());
-					module->connect(cell->getPort("\\Y"), result_sig);
+					if (replace)
+						module->connect(cell->getPort("\\Y"), replace_sig);
 					module->remove(cell);
 					did_something = true;
 					goto next_cell;
@@ -1477,26 +1503,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
 			{
 				int const_bit_set = get_onehot_bit_index(sigConst);
-				if (const_bit_set >= 0 && const_bit_set < width) {
-					int bit_set = const_bit_set;
-					RTLIL::SigSpec a_prime(RTLIL::State::S0, width - bit_set);
-					for (int i = bit_set; i < width; i++) {
-						a_prime[i - bit_set] = sigVar[i];
-					}
-					if (is_lt) {
-						log("Replacing %s cell `%s' (implementing unsigned X<%s) with !X[%d:%d]: %s.\n",
-								log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
-						module->addLogicNot(NEW_ID, a_prime, cell->getPort("\\Y"));
-					} else {
-						log("Replacing %s cell `%s' (implementing unsigned X>=%s) with |X[%d:%d]: %s.\n",
-								log_id(cell->type), log_id(cell), log_signal(sigConst), width - 1, bit_set, log_signal(a_prime));
-						module->addReduceOr(NEW_ID, a_prime, cell->getPort("\\Y"));
-					}
-					module->remove(cell);
-					did_something = true;
-					goto next_cell;
-				}
-				else if(const_bit_set >= width && const_bit_set >= 0){
+				if(const_bit_set >= width && const_bit_set >= 0){
 					RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
 					if(is_lt){
 						a_prime[0] = RTLIL::State::S1;
@@ -1509,7 +1516,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 					module->remove(cell);
 					did_something = true;
 					goto next_cell;
-
 				}
 			}
 		}
diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
index 72372bdf0..500b15f1b 100644
--- a/tests/opt/opt_expr_cmp.v
+++ b/tests/opt/opt_expr_cmp.v
@@ -14,4 +14,9 @@ module top(...);
   output o2_2 = 4'sb0000 <= $signed(a);
   output o2_3 = $signed(a) <  4'sb0000;
   output o2_4 = $signed(a) >= 4'sb0000;
+
+  output o3_1 = 4'b0100 >  a;
+  output o3_2 = 4'b0100 <= a;
+  output o3_3 = a <  4'b0100;
+  output o3_4 = a >= 4'b0100;
 endmodule

From a91892bba422bbe8de080a105a6fb4b44f96df1a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 07:53:31 +0000
Subject: [PATCH 267/528] cmp2lut: new techmap pass.

---
 techlibs/common/Makefile.inc |   2 +-
 techlibs/common/cmp2lut.v    | 105 +++++++++++++++++++++++++++++++++++
 tests/lut/check_map.ys       |   6 +-
 tests/lut/map_cmp.v          |  29 ++++++++++
 tests/lut/run-test.sh        |   0
 5 files changed, 139 insertions(+), 3 deletions(-)
 create mode 100644 techlibs/common/cmp2lut.v
 create mode 100644 tests/lut/map_cmp.v
 mode change 100644 => 100755 tests/lut/run-test.sh

diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc
index 70074f653..0e05620bc 100644
--- a/techlibs/common/Makefile.inc
+++ b/techlibs/common/Makefile.inc
@@ -26,5 +26,5 @@ $(eval $(call add_share_file,share,techlibs/common/pmux2mux.v))
 $(eval $(call add_share_file,share,techlibs/common/adff2dff.v))
 $(eval $(call add_share_file,share,techlibs/common/dff2ff.v))
 $(eval $(call add_share_file,share,techlibs/common/gate2lut.v))
+$(eval $(call add_share_file,share,techlibs/common/cmp2lut.v))
 $(eval $(call add_share_file,share,techlibs/common/cells.lib))
-
diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v
new file mode 100644
index 000000000..8aa1eb957
--- /dev/null
+++ b/techlibs/common/cmp2lut.v
@@ -0,0 +1,105 @@
+// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
+// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
+// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
+// cannot be optimized further.
+//
+// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
+// with n <= k inputs should be techmapped in this way, because this shortens the critical path
+// from n to 1 by avoiding carry chains.
+
+(* techmap_celltype = "$eq $ne $lt $le $gt $ge" *)
+module _90_lut_cmp_ (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+parameter _TECHMAP_CELLTYPE_ = "";
+
+parameter _TECHMAP_CONSTMSK_A_ = 0;
+parameter _TECHMAP_CONSTVAL_A_ = 0;
+parameter _TECHMAP_CONSTMSK_B_ = 0;
+parameter _TECHMAP_CONSTVAL_B_ = 0;
+
+function automatic integer gen_lut;
+	input integer width;
+	input integer operation;
+	input integer swap;
+	input integer sign;
+	input integer operand;
+	integer n, i_var, i_cst, lhs, rhs, o_bit;
+	begin
+		gen_lut = width'b0;
+		for (n = 0; n < (1 << width); n++) begin
+			if (sign)
+				i_var = n[width-1:0];
+			else
+				i_var = n;
+			i_cst = operand;
+			if (swap) begin
+				lhs = i_cst;
+				rhs = i_var;
+			end else begin
+				lhs = i_var;
+				rhs = i_cst;
+			end
+			if (operation == 0)
+				o_bit = (lhs <  rhs);
+			if (operation == 1)
+				o_bit = (lhs <= rhs);
+			if (operation == 2)
+				o_bit = (lhs >  rhs);
+			if (operation == 3)
+				o_bit = (lhs >= rhs);
+			if (operation == 4)
+				o_bit = (lhs == rhs);
+			if (operation == 5)
+				o_bit = (lhs != rhs);
+			gen_lut = gen_lut | (o_bit << n);
+		end
+	end
+endfunction
+
+generate
+	if (_TECHMAP_CELLTYPE_ == "$lt")
+		localparam operation = 0;
+	if (_TECHMAP_CELLTYPE_ == "$le")
+		localparam operation = 1;
+	if (_TECHMAP_CELLTYPE_ == "$gt")
+		localparam operation = 2;
+	if (_TECHMAP_CELLTYPE_ == "$ge")
+		localparam operation = 3;
+	if (_TECHMAP_CELLTYPE_ == "$eq")
+		localparam operation = 4;
+	if (_TECHMAP_CELLTYPE_ == "$ne")
+		localparam operation = 5;
+
+	if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
+		wire _TECHMAP_FAIL_ = 1;
+	else if (&_TECHMAP_CONSTMSK_B_)
+		\$lut #(
+			.WIDTH(A_WIDTH),
+			.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
+		) _TECHMAP_REPLACE_ (
+			.A(A),
+			.Y(Y)
+		);
+	else if (&_TECHMAP_CONSTMSK_A_)
+		\$lut #(
+			.WIDTH(B_WIDTH),
+			.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
+		) _TECHMAP_REPLACE_ (
+			.A(B),
+			.Y(Y)
+		);
+	else
+		wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule
diff --git a/tests/lut/check_map.ys b/tests/lut/check_map.ys
index dc0aaffc2..46854e82e 100644
--- a/tests/lut/check_map.ys
+++ b/tests/lut/check_map.ys
@@ -1,4 +1,6 @@
 simplemap
-equiv_opt -assert techmap -map +/gate2lut.v -D LUT_WIDTH=4
+equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/cmp2lut.v
 design -load postopt
-select -assert-count 1 t:$lut
+equiv_opt -assert techmap -D LUT_WIDTH=4 -map +/gate2lut.v
+design -load postopt
+select -assert-count 0 t:* t:$lut %d
diff --git a/tests/lut/map_cmp.v b/tests/lut/map_cmp.v
new file mode 100644
index 000000000..5e413f894
--- /dev/null
+++ b/tests/lut/map_cmp.v
@@ -0,0 +1,29 @@
+module top(...);
+	input [3:0] a;
+
+	output o1_1 = 4'b1010 <= a;
+	output o1_2 = 4'b1010 <  a;
+	output o1_3 = 4'b1010 >= a;
+	output o1_4 = 4'b1010 >  a;
+	output o1_5 = 4'b1010 == a;
+	output o1_6 = 4'b1010 != a;
+
+	output o2_1 = a <= 4'b1010;
+	output o2_2 = a <  4'b1010;
+	output o2_3 = a >= 4'b1010;
+	output o2_4 = a >  4'b1010;
+	output o2_5 = a == 4'b1010;
+	output o2_6 = a != 4'b1010;
+
+	output o3_1 = 4'sb0101 <= $signed(a);
+	output o3_2 = 4'sb0101 <  $signed(a);
+	output o3_3 = 4'sb0101 >= $signed(a);
+	output o3_4 = 4'sb0101 >  $signed(a);
+	output o3_5 = 4'sb0101 == $signed(a);
+	output o3_6 = 4'sb0101 != $signed(a);
+
+	output o4_1 = $signed(a) <= 4'sb0000;
+	output o4_2 = $signed(a) <  4'sb0000;
+	output o4_3 = $signed(a) >= 4'sb0000;
+	output o4_4 = $signed(a) >  4'sb0000;
+endmodule
diff --git a/tests/lut/run-test.sh b/tests/lut/run-test.sh
old mode 100644
new mode 100755

From fdff32dd731d92c854aef73ea9fad89635e82c0f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 08:05:44 +0000
Subject: [PATCH 268/528] synth: improve script documentation. NFC.

---
 techlibs/common/synth.cc | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index efb214759..5cadbba7a 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -186,19 +186,19 @@ struct SynthPass : public ScriptPass
 		{
 			run("proc");
 			if (help_mode || flatten)
-				run("flatten", "(if -flatten)");
+				run("flatten", "  (if -flatten)");
 			run("opt_expr");
 			run("opt_clean");
 			run("check");
 			run("opt");
 			run("wreduce");
 			if (!noalumacc)
-				run("alumacc");
+				run("alumacc", "  (unless -noalumacc)");
 			if (!noshare)
-				run("share");
+				run("share", "    (unless -noshare)");
 			run("opt");
 			if (!nofsm)
-				run("fsm" + fsm_opts);
+				run("fsm" + fsm_opts, "      (unless -nofsm)");
 			run("opt -fast");
 			run("memory -nomap" + memory_opts);
 			run("opt_clean");
@@ -214,8 +214,8 @@ struct SynthPass : public ScriptPass
 
 			if (!noabc) {
 		#ifdef YOSYS_ENABLE_ABC
-				run("abc -fast");
-				run("opt -fast");
+				run("abc -fast", "(unless -noabc)");
+				run("opt -fast", "(unless -noabc)");
 		#endif
 			}
 		}

From 18174202a957cb20137e13893ad002ac1b52b61b Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 08:25:03 +0000
Subject: [PATCH 269/528] synth: add k-LUT mode.

---
 techlibs/common/synth.cc | 38 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index 5cadbba7a..5ff813d18 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -51,6 +51,9 @@ struct SynthPass : public ScriptPass
 		log("    -encfile <file>\n");
 		log("        passed to 'fsm_recode' via 'fsm'\n");
 		log("\n");
+		log("    -lut <k>\n");
+		log("        perform synthesis for a k-LUT architecture.\n");
+		log("\n");
 		log("    -nofsm\n");
 		log("        do not run FSM optimization\n");
 		log("\n");
@@ -80,6 +83,7 @@ struct SynthPass : public ScriptPass
 
 	string top_module, fsm_opts, memory_opts;
 	bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
+	int lut;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -89,6 +93,7 @@ struct SynthPass : public ScriptPass
 
 		autotop = false;
 		flatten = false;
+		lut = 0;
 		noalumacc = false;
 		nofsm = false;
 		noabc = false;
@@ -130,6 +135,10 @@ struct SynthPass : public ScriptPass
 				flatten = true;
 				continue;
 			}
+			if (args[argidx] == "-lut") {
+				lut = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-nofsm") {
 				nofsm = true;
 				continue;
@@ -192,6 +201,10 @@ struct SynthPass : public ScriptPass
 			run("check");
 			run("opt");
 			run("wreduce");
+			if (help_mode)
+				run("techmap -map +/cmp2lut.v", " (if -lut)");
+			else
+				run(stringf("techmap -map +/cmp2lut.v -D LUT_WIDTH=%d", lut));
 			if (!noalumacc)
 				run("alumacc", "  (unless -noalumacc)");
 			if (!noshare)
@@ -210,12 +223,33 @@ struct SynthPass : public ScriptPass
 			run("memory_map");
 			run("opt -full");
 			run("techmap");
+			if (help_mode)
+			{
+				run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
+				run("clean; opt_lut", "           (if -noabc and -lut)");
+			}
+			else if (noabc && lut)
+			{
+				run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
+				run("clean; opt_lut");
+			}
 			run("opt -fast");
 
 			if (!noabc) {
 		#ifdef YOSYS_ENABLE_ABC
-				run("abc -fast", "(unless -noabc)");
-				run("opt -fast", "(unless -noabc)");
+				if (help_mode)
+				{
+					run("abc -fast", "       (unless -noabc, unless -lut)");
+					run("abc -fast -lut k", "(unless -noabc, if -lut)");
+				}
+				else
+				{
+					if (lut)
+						run(stringf("abc -fast -lut %d", lut));
+					else
+						run("abc -fast");
+				}
+				run("opt -fast", "       (unless -noabc)");
 		#endif
 			}
 		}

From 17b283135658b84a0dfeec8b35f7d2bfe782be19 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 08:25:55 +0000
Subject: [PATCH 270/528] synth_ice40: use 4-LUT coarse synthesis mode.

---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c2aed873b..4c4fdf7be 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -226,7 +226,7 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -run coarse");
+			run("synth -lut 4 -run coarse");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))

From f7363ac5086ccb8bdb97dcdbfed890c54e1ed153 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 08:40:01 +0000
Subject: [PATCH 271/528] opt_lut: count eliminated cells, and set
 opt.did_something for them.

---
 passes/opt/opt_lut.cc | 26 ++++++++++++++++++++------
 1 file changed, 20 insertions(+), 6 deletions(-)

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 261af538f..8c564b0ed 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -36,7 +36,7 @@ struct OptLutWorker
 	dict<RTLIL::Cell*, pool<RTLIL::Cell*>> luts_dlogics;
 	dict<RTLIL::Cell*, pool<int>> luts_dlogic_inputs;
 
-	int combined_count = 0;
+	int eliminated_count = 0, combined_count = 0;
 
 	bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
 	{
@@ -191,6 +191,12 @@ struct OptLutWorker
 		log("Eliminating LUTs.\n");
 		for (auto lut : luts)
 		{
+			if (limit == 0)
+			{
+				log("Limit reached.\n");
+				break;
+			}
+
 			SigSpec lut_input = sigmap(lut->getPort("\\A"));
 			pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
 
@@ -263,6 +269,10 @@ struct OptLutWorker
 					luts_arity.erase(lut);
 					luts_dlogics.erase(lut);
 					luts_dlogic_inputs.erase(lut);
+
+					eliminated_count++;
+					if (limit > 0)
+						limit--;
 				}
 			}
 		}
@@ -568,16 +578,20 @@ struct OptLutPass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		int total_count = 0;
+		int eliminated_count = 0, combined_count = 0;
 		for (auto module : design->selected_modules())
 		{
-			OptLutWorker worker(dlogic, module, limit - total_count);
-			total_count += worker.combined_count;
+			OptLutWorker worker(dlogic, module, limit - eliminated_count - combined_count);
+			eliminated_count += worker.eliminated_count;
+			combined_count   += worker.combined_count;
 		}
-		if (total_count)
+		if (eliminated_count)
+			design->scratchpad_set_bool("opt.did_something", true);
+		if (combined_count)
 			design->scratchpad_set_bool("opt.did_something", true);
 		log("\n");
-		log("Combined %d LUTs.\n", total_count);
+		log("Eliminated %d LUTs.\n", eliminated_count);
+		log("Combined %d LUTs.\n", combined_count);
 	}
 } OptLutPass;
 

From 06143ab33f4064677586be2a2b0d763f0818e856 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 09:36:32 +0000
Subject: [PATCH 272/528] opt_lut: use a worklist, and revisit cells affected
 by elimination.

---
 passes/opt/opt_lut.cc | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 8c564b0ed..a79a9a2da 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -189,7 +189,8 @@ struct OptLutWorker
 
 		log("\n");
 		log("Eliminating LUTs.\n");
-		for (auto lut : luts)
+		pool<RTLIL::Cell*> worklist = luts;
+		while (worklist.size())
 		{
 			if (limit == 0)
 			{
@@ -197,6 +198,7 @@ struct OptLutWorker
 				break;
 			}
 
+			auto lut = worklist.pop();
 			SigSpec lut_input = sigmap(lut->getPort("\\A"));
 			pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
 
@@ -262,8 +264,13 @@ struct OptLutWorker
 				else
 				{
 					SigSpec lut_output = lut->getPort("\\Y");
-					module->connect(lut_output, value);
+					for (auto &port : index.query_ports(lut_output))
+					{
+						if (port.cell != lut && luts.count(port.cell))
+							worklist.insert(port.cell);
+					}
 
+					module->connect(lut_output, value);
 					module->remove(lut);
 					luts.erase(lut);
 					luts_arity.erase(lut);
@@ -280,7 +287,7 @@ struct OptLutWorker
 
 		log("\n");
 		log("Combining LUTs.\n");
-		pool<RTLIL::Cell*> worklist = luts;
+		worklist = luts;
 		while (worklist.size())
 		{
 			if (limit == 0)

From c55dfb83693c6707ecb1d7dce7824a61e87eb44d Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 10:21:58 +0000
Subject: [PATCH 273/528] opt_lut: reflect changes in sigmap.

Otherwise, some LUTs will be missed during elimination.
---
 passes/opt/opt_lut.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index a79a9a2da..b9a1ce7a7 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -271,6 +271,8 @@ struct OptLutWorker
 					}
 
 					module->connect(lut_output, value);
+					sigmap.add(lut_output, value);
+
 					module->remove(lut);
 					luts.erase(lut);
 					luts_arity.erase(lut);

From efa278e232d20ea080743801bd91d55ec62955cf Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 7 Dec 2018 19:14:07 +0000
Subject: [PATCH 274/528] Fix typographical and grammatical errors and
 inconsistencies.

The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.

    DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
    DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
    codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint

More hits were found by looking through comments and strings manually.
---
 README.md                                  | 18 +++++++++---------
 backends/simplec/simplec.cc                |  2 +-
 backends/smt2/smtbmc.py                    |  8 ++++----
 backends/table/table.cc                    |  2 +-
 backends/verilog/verilog_backend.cc        |  2 +-
 frontends/ast/ast.cc                       |  4 ++--
 frontends/blif/blifparse.cc                |  2 +-
 frontends/liberty/liberty.cc               |  2 +-
 frontends/verific/verificsva.cc            |  8 ++++----
 frontends/verilog/verilog_parser.y         |  6 +++---
 kernel/log.h                               |  2 +-
 kernel/yosys.cc                            |  2 +-
 libs/ezsat/ezminisat.h                     |  2 +-
 libs/subcircuit/README                     |  6 +++---
 passes/cmds/chformal.cc                    |  4 ++--
 passes/cmds/connect.cc                     |  6 +++---
 passes/cmds/select.cc                      |  2 +-
 passes/cmds/setundef.cc                    |  2 +-
 passes/cmds/show.cc                        |  2 +-
 passes/cmds/tee.cc                         |  4 ++--
 passes/fsm/fsm_detect.cc                   |  8 ++++----
 passes/fsm/fsm_extract.cc                  |  4 ++--
 passes/hierarchy/hierarchy.cc              |  2 +-
 passes/opt/opt_expr.cc                     |  2 +-
 passes/opt/opt_lut.cc                      |  2 +-
 techlibs/achronix/speedster22i/cells_map.v | 16 ++++++++--------
 techlibs/achronix/synth_achronix.cc        |  2 +-
 techlibs/anlogic/synth_anlogic.cc          |  2 +-
 techlibs/common/prep.cc                    |  2 +-
 techlibs/common/synth.cc                   |  2 +-
 techlibs/coolrunner2/synth_coolrunner2.cc  |  2 +-
 techlibs/easic/synth_easic.cc              |  2 +-
 techlibs/ecp5/cells_bb.v                   |  2 +-
 techlibs/ecp5/synth_ecp5.cc                |  2 +-
 techlibs/gowin/synth_gowin.cc              |  2 +-
 techlibs/greenpak4/synth_greenpak4.cc      |  2 +-
 techlibs/ice40/synth_ice40.cc              |  2 +-
 techlibs/intel/cyclonev/cells_sim.v        |  2 +-
 techlibs/sf2/synth_sf2.cc                  |  2 +-
 techlibs/xilinx/synth_xilinx.cc            |  2 +-
 40 files changed, 74 insertions(+), 74 deletions(-)

diff --git a/README.md b/README.md
index 840f2c8b2..883f2b0a5 100644
--- a/README.md
+++ b/README.md
@@ -117,7 +117,7 @@ reading the design using the Verilog frontend:
 
 	yosys> read_verilog tests/simple/fiedler-cooley.v
 
-writing the design to the console in yosys's internal format:
+writing the design to the console in Yosys's internal format:
 
 	yosys> write_ilang
 
@@ -234,7 +234,7 @@ Unsupported Verilog-2005 Features
 =================================
 
 The following Verilog-2005 features are not supported by
-yosys and there are currently no plans to add support
+Yosys and there are currently no plans to add support
 for them:
 
 - Non-synthesizable language features as defined in
@@ -285,9 +285,9 @@ Verilog Attributes and non-standard features
   storage element. The register itself will always have all bits set
   to 'x' (undefined). The variable may only be used as blocking assigned
   temporary variable within an always block. This is mostly used internally
-  by yosys to synthesize Verilog functions and access arrays.
+  by Yosys to synthesize Verilog functions and access arrays.
 
-- The ``onehot`` attribute on wires mark them as onehot state register. This
+- The ``onehot`` attribute on wires mark them as one-hot state register. This
   is used for example for memory port sharing and set by the fsm_map pass.
 
 - The ``blackbox`` attribute on modules is used to mark empty stub modules
@@ -319,13 +319,13 @@ Verilog Attributes and non-standard features
   through the synthesis. When entities are combined, a new |-separated
   string is created that contains all the string from the original entities.
 
-- In addition to the ``(* ... *)`` attribute syntax, yosys supports
+- In addition to the ``(* ... *)`` attribute syntax, Yosys supports
   the non-standard ``{* ... *}`` attribute syntax to set default attributes
   for everything that comes after the ``{* ... *}`` statement. (Reset
   by adding an empty ``{* *}`` statement.)
 
 - In module parameter and port declarations, and cell port and parameter
-  lists, a trailing comma is ignored. This simplifies writing verilog code
+  lists, a trailing comma is ignored. This simplifies writing Verilog code
   generators a bit in some cases.
 
 - Modules can be declared with ``module mod_name(...);`` (with three dots
@@ -410,11 +410,11 @@ Non-standard or SystemVerilog features for formal verification
 
 - The system functions ``$allconst`` and ``$allseq`` can be used to construct
   formal exist-forall problems. Assumptions only hold if the trace satisfies
-  the assumtion for all ``$allconst/$allseq`` values. For assertions and cover
+  the assumption for all ``$allconst/$allseq`` values. For assertions and cover
   statements it is sufficient if just one ``$allconst/$allseq`` value triggers
   the property (similar to ``$anyconst/$anyseq``).
 
-- Wires/registers decalred using the ``anyconst/anyseq/allconst/allseq`` attribute
+- Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute
   (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven
   by a ``$anyconst/$anyseq/$allconst/$allseq`` function.
 
@@ -485,6 +485,6 @@ Then execute, from the root of the repository:
 
 Notes:
 
-- To run `make manual` you need to have installed yosys with `make install`,
+- To run `make manual` you need to have installed Yosys with `make install`,
   otherwise it will fail on finding `kernel/yosys.h` while building
   `PRESENTATION_Prog`.
diff --git a/backends/simplec/simplec.cc b/backends/simplec/simplec.cc
index 349bc5a6d..6f2ccbe20 100644
--- a/backends/simplec/simplec.cc
+++ b/backends/simplec/simplec.cc
@@ -748,7 +748,7 @@ struct SimplecBackend : public Backend {
 		log("\n");
 		log("    write_simplec [options] [filename]\n");
 		log("\n");
-		log("Write simple C code for simulating the design. The C code writen can be used to\n");
+		log("Write simple C code for simulating the design. The C code written can be used to\n");
 		log("simulate the design in a C environment, but the purpose of this command is to\n");
 		log("generate code that works well with C-based formal verification.\n");
 		log("\n");
diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 721a395e3..94a5e2da0 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -87,7 +87,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
 
     --aig <aim_filename>:<aiw_filename>
         like above, but for map files and witness files that do not
-        share a filename prefix (or use differen file extensions).
+        share a filename prefix (or use different file extensions).
 
     --aig-noheader
         the AIGER witness file does not include the status and
@@ -103,8 +103,8 @@ yosys-smtbmc [options] <yosys_smt2_output>
     --presat
         check if the design with assumptions but without assertions
         is SAT before checking if assertions are UNSAT. This will
-        detect if there are contradicting assumtions. In some cases
-        this will also help to "warmup" the solver, potentially
+        detect if there are contradicting assumptions. In some cases
+        this will also help to "warm up" the solver, potentially
         yielding a speedup.
 
     --final-only
@@ -149,7 +149,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
     --append <num_steps>
         add <num_steps> time steps at the end of the trace
         when creating a counter example (this additional time
-        steps will still be constrained by assumtions)
+        steps will still be constrained by assumptions)
 """ + so.helpmsg())
     sys.exit(1)
 
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 979273dd3..b75169ea4 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -109,7 +109,7 @@ struct TableBackend : public Backend {
 				else if (cell->output(conn.first))
 					*f << "out" << "\t";
 				else
-					*f << "unkown" << "\t";
+					*f << "unknown" << "\t";
 
 				*f << log_signal(sigmap(conn.second)) << "\n";
 			}
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 71db25f98..2537e18e5 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1447,7 +1447,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 		}
 
 	if (!module->processes.empty())
-		log_warning("Module %s contains unmapped RTLIL proccesses. RTLIL processes\n"
+		log_warning("Module %s contains unmapped RTLIL processes. RTLIL processes\n"
 				"can't always be mapped directly to Verilog always blocks. Unintended\n"
 				"changes in simulation behavior are possible! Use \"proc\" to convert\n"
 				"processes to logic networks and registers.\n", log_id(module));
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 2c1561552..5a1bae7a7 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -36,14 +36,14 @@ YOSYS_NAMESPACE_BEGIN
 using namespace AST;
 using namespace AST_INTERNAL;
 
-// instanciate global variables (public API)
+// instantiate global variables (public API)
 namespace AST {
 	std::string current_filename;
 	void (*set_line_num)(int) = NULL;
 	int (*get_line_num)() = NULL;
 }
 
-// instanciate global variables (private API)
+// instantiate global variables (private API)
 namespace AST_INTERNAL {
 	bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 034b3e70c..9116b257f 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -276,7 +276,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
 
 				if(lastcell == nullptr || module == nullptr)
 				{
-					err_reason = stringf("No primative object to attach .cname %s.", p);
+					err_reason = stringf("No primitive object to attach .cname %s.", p);
 					goto error_with_reason;
 				}
 
diff --git a/frontends/liberty/liberty.cc b/frontends/liberty/liberty.cc
index 4acfbf1cb..6e3cffaca 100644
--- a/frontends/liberty/liberty.cc
+++ b/frontends/liberty/liberty.cc
@@ -616,7 +616,7 @@ struct LibertyFrontend : public Frontend {
 					LibertyAst *bus_type_node = node->find("bus_type");
 
 					if (!bus_type_node || !type_map.count(bus_type_node->value))
-						log_error("Unkown or unsupported type for bus interface %s on cell %s.\n",
+						log_error("Unknown or unsupported type for bus interface %s on cell %s.\n",
 								node->args.at(0).c_str(), log_id(cell_name));
 
 					int bus_type_width = std::get<0>(type_map.at(bus_type_node->value));
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index cdc9ece8c..6681115df 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -827,9 +827,9 @@ struct SvaFsm
 
 			for (auto &it : nodes[i].edges) {
 				if (it.second != State::S1)
-					log("          egde %s -> %d\n", log_signal(it.second), it.first);
+					log("          edge %s -> %d\n", log_signal(it.second), it.first);
 				else
-					log("          egde -> %d\n", it.first);
+					log("          edge -> %d\n", it.first);
 			}
 
 			for (auto &it : nodes[i].links) {
@@ -856,9 +856,9 @@ struct SvaFsm
 
 			for (auto &it : unodes[i].edges) {
 				if (!it.second.empty())
-					log("          egde %s -> %d\n", log_signal(it.second), it.first);
+					log("          edge %s -> %d\n", log_signal(it.second), it.first);
 				else
-					log("          egde -> %d\n", it.first);
+					log("          edge -> %d\n", it.first);
 			}
 
 			for (auto &ctrl : unodes[i].accept) {
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 51e112ed3..a6718b020 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -794,7 +794,7 @@ more_path_inputs :
 list_of_path_outputs :
 	specify_output_terminal_descriptor |
 	list_of_path_outputs ',' specify_output_terminal_descriptor ;
-	
+
 opt_polarity_operator :
 	'+'
 	| '-'
@@ -819,7 +819,7 @@ system_timing_arg :
 system_timing_args :
 	system_timing_arg |
 	system_timing_args ',' system_timing_arg ;
- 
+
 /*
 t_path_delay_expression :
 	path_delay_expression;
@@ -881,7 +881,7 @@ constant_mintypmax_expression :
 // for the time being this is OK, but we may write our own expr here.
 // as I'm not sure it is legal to use a full expr here (probably not)
 // On the other hand, other rules requiring constant expressions also use 'expr'
-// (such as param assignment), so we may leave this as-is, perhaps assing runtime checks for constant-ness
+// (such as param assignment), so we may leave this as-is, perhaps adding runtime checks for constant-ness
 constant_expression:
 	expr ;
 
diff --git a/kernel/log.h b/kernel/log.h
index 0b4905c3a..e1f54a197 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -195,7 +195,7 @@ struct PerformanceTimer
 		t += 1000000000ULL * (int64_t) rusage.ru_stime.tv_sec + (int64_t) rusage.ru_stime.tv_usec * 1000ULL;
 		return t;
 #  else
-#    error Dont know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?).
+#    error "Don't know how to measure per-process CPU time. Need alternative method (times()/clocks()/gettimeofday()?)."
 #  endif
 	}
 
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6884305d9..2ed0f4db4 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -744,7 +744,7 @@ std::string proc_self_dirname()
 	return "/";
 }
 #else
-	#error Dont know how to determine process executable base path!
+	#error "Don't know how to determine process executable base path!"
 #endif
 
 #ifdef EMSCRIPTEN
diff --git a/libs/ezsat/ezminisat.h b/libs/ezsat/ezminisat.h
index 983e6fd0e..3a34c13c8 100644
--- a/libs/ezsat/ezminisat.h
+++ b/libs/ezsat/ezminisat.h
@@ -28,7 +28,7 @@
 #include <time.h>
 
 // minisat is using limit macros and format macros in their headers that
-// can be the source of some troubles when used from c++11. thefore we
+// can be the source of some troubles when used from c++11. therefore we
 // don't force ezSAT users to use minisat headers..
 namespace Minisat {
 	class Solver;
diff --git a/libs/subcircuit/README b/libs/subcircuit/README
index b1335681e..ecaa987db 100644
--- a/libs/subcircuit/README
+++ b/libs/subcircuit/README
@@ -109,7 +109,7 @@ look at the demo.cc example program in this directory.
 Setting up graphs
 -----------------
 
-Instanciate the SubCircuit::Graph class and use the methods of this class to
+Instantiate the SubCircuit::Graph class and use the methods of this class to
 set up the circuit.
 
 	SubCircuit::Graph myGraph;
@@ -152,7 +152,7 @@ rotate shift,
 
 The method createConstant() can be used to add a constant driver to a signal.
 The signal value is encoded as one char by bit, allowing for multi-valued
-logic matching. The follwoing command sets the lowest bit of cell6.A to a
+logic matching. The following command sets the lowest bit of cell6.A to a
 logic 1:
 
 	myGraph.createConnection("cell6", "A", 0, '1');
@@ -314,7 +314,7 @@ bool userCompareEdge(needleGraphId, needleFromNodeId, needleFromUserData, needle
 
 	Perform additional checks on a pair of a pair of adjacent nodes (one
 	adjacent pair from the needle and one adjacent pair from the haystack)
-	to determine wheter this edge from the needle is compatible with
+	to determine whether this edge from the needle is compatible with
 	that edge from the haystack. The default implementation always
 	returns true.
 
diff --git a/passes/cmds/chformal.cc b/passes/cmds/chformal.cc
index 522758eae..7e32da65f 100644
--- a/passes/cmds/chformal.cc
+++ b/passes/cmds/chformal.cc
@@ -32,7 +32,7 @@ struct ChformalPass : public Pass {
 		log("    chformal [types] [mode] [options] [selection]\n");
 		log("\n");
 		log("Make changes to the formal constraints of the design. The [types] options\n");
-		log("the type of constraint to operate on. If none of the folling options is given,\n");
+		log("the type of constraint to operate on. If none of the following options are given,\n");
 		log("the command will operate on all constraint types:\n");
 		log("\n");
 		log("    -assert       $assert cells, representing assert(...) constraints\n");
@@ -59,7 +59,7 @@ struct ChformalPass : public Pass {
 		log("    -assume2assert\n");
 		log("    -live2fair\n");
 		log("    -fair2live\n");
-		log("        change the roles of cells as indicated. this options can be combined\n");
+		log("        change the roles of cells as indicated. these options can be combined\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc
index d480b79ac..f93bada27 100644
--- a/passes/cmds/connect.cc
+++ b/passes/cmds/connect.cc
@@ -137,7 +137,7 @@ struct ConnectPass : public Pass {
 		if (!set_lhs.empty())
 		{
 			if (!unset_expr.empty() || !port_cell.empty())
-				log_cmd_error("Cant use -set together with -unset and/or -port.\n");
+				log_cmd_error("Can't use -set together with -unset and/or -port.\n");
 
 			RTLIL::SigSpec sig_lhs, sig_rhs;
 			if (!RTLIL::SigSpec::parse_sel(sig_lhs, design, module, set_lhs))
@@ -157,7 +157,7 @@ struct ConnectPass : public Pass {
 		if (!unset_expr.empty())
 		{
 			if (!port_cell.empty() || flag_nounset)
-				log_cmd_error("Cant use -unset together with -port and/or -nounset.\n");
+				log_cmd_error("Can't use -unset together with -port and/or -nounset.\n");
 
 			RTLIL::SigSpec sig;
 			if (!RTLIL::SigSpec::parse_sel(sig, design, module, unset_expr))
@@ -170,7 +170,7 @@ struct ConnectPass : public Pass {
 		if (!port_cell.empty())
 		{
 			if (flag_nounset)
-				log_cmd_error("Cant use -port together with -nounset.\n");
+				log_cmd_error("Can't use -port together with -nounset.\n");
 
 			if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0)
 				log_cmd_error("Can't find cell %s.\n", port_cell.c_str());
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index ba407ea8c..b5e8ef1af 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -987,7 +987,7 @@ struct SelectPass : public Pass {
 		log("list of selected objects.\n");
 		log("\n");
 		log("Note that many commands support an optional [selection] argument that can be\n");
-		log("used to YS_OVERRIDE the global selection for the command. The syntax of this\n");
+		log("used to override the global selection for the command. The syntax of this\n");
 		log("optional argument is identical to the syntax of the <selection> argument\n");
 		log("described here.\n");
 		log("\n");
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index a1dfa9b5c..56ef2d125 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -137,7 +137,7 @@ struct SetundefPass : public Pass {
 		log("        replace with $anyconst drivers (for formal)\n");
 		log("\n");
 		log("    -random <seed>\n");
-		log("        replace with random bits using the specified integer als seed\n");
+		log("        replace with random bits using the specified integer as seed\n");
 		log("        value for the random number generator.\n");
 		log("\n");
 		log("    -init\n");
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index a48873244..58acd302d 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -623,7 +623,7 @@ struct ShowPass : public Pass {
 		log("        assigned to each unique value of this attribute.\n");
 		log("\n");
 		log("    -width\n");
-		log("        annotate busses with a label indicating the width of the bus.\n");
+		log("        annotate buses with a label indicating the width of the bus.\n");
 		log("\n");
 		log("    -signed\n");
 		log("        mark ports (A, B) that are declared as signed (using the [AB]_SIGNED\n");
diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc
index ff80f3859..ee96ace86 100644
--- a/passes/cmds/tee.cc
+++ b/passes/cmds/tee.cc
@@ -37,7 +37,7 @@ struct TeePass : public Pass {
 		log("specified logfile(s).\n");
 		log("\n");
 		log("    -q\n");
-		log("        Do not print output to the normal destination (console and/or log file)\n");
+		log("        Do not print output to the normal destination (console and/or log file).\n");
 		log("\n");
 		log("    -o logfile\n");
 		log("        Write output to this file, truncate if exists.\n");
@@ -46,7 +46,7 @@ struct TeePass : public Pass {
 		log("        Write output to this file, append if exists.\n");
 		log("\n");
 		log("    +INT, -INT\n");
-		log("        Add/subract INT from the -v setting for this command.\n");
+		log("        Add/subtract INT from the -v setting for this command.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index fc504e98c..5ae991b28 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -196,13 +196,13 @@ static void detect_fsm(RTLIL::Wire *wire)
 		vector<string> warnings;
 
 		if (is_module_port)
-			warnings.push_back("Forcing fsm recoding on module port might result in larger circuit.\n");
+			warnings.push_back("Forcing FSM recoding on module port might result in larger circuit.\n");
 
 		if (!looks_like_good_state_reg)
-			warnings.push_back("Users of state reg look like fsm recoding might result in larger circuit.\n");
+			warnings.push_back("Users of state reg look like FSM recoding might result in larger circuit.\n");
 
 		if (has_init_attr)
-			warnings.push_back("Init value on fsm state registers are ignored. Possible simulation-synthesis mismatch!");
+			warnings.push_back("Initialization value on FSM state register is ignored. Possible simulation-synthesis mismatch!\n");
 
 		if (!looks_like_state_reg)
 			warnings.push_back("Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!\n");
@@ -236,7 +236,7 @@ static void detect_fsm(RTLIL::Wire *wire)
 			log("    Users of register don't seem to benefit from recoding.\n");
 
 		if (has_init_attr)
-			log("    Register has an initialization value.");
+			log("    Register has an initialization value.\n");
 
 		if (is_self_resetting)
 			log("    Circuit seems to be self-resetting.\n");
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 67551f673..6095eaf30 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -178,7 +178,7 @@ undef_bit_in_next_state:
 			log_state_in = fsm_data.state_table.at(state_in);
 
 		if (states.count(ce.values_map(ce.assign_map(dff_in)).as_const()) == 0) {
-			log("  transition: %10s %s -> INVALID_STATE(%s) %s  <ignored invalid transistion!>%s\n",
+			log("  transition: %10s %s -> INVALID_STATE(%s) %s  <ignored invalid transition!>%s\n",
 					log_signal(log_state_in), log_signal(tr.ctrl_in),
 					log_signal(ce.values_map(ce.assign_map(dff_in))), log_signal(tr.ctrl_out),
 					undef_bit_in_next_state_mode ? " SHORTENED" : "");
@@ -194,7 +194,7 @@ undef_bit_in_next_state:
 					log_signal(log_state_in), log_signal(tr.ctrl_in),
 					log_signal(fsm_data.state_table[tr.state_out]), log_signal(tr.ctrl_out));
 		} else {
-			log("  transition: %10s %s -> %10s %s  <ignored undef transistion!>\n",
+			log("  transition: %10s %s -> %10s %s  <ignored undef transition!>\n",
 					log_signal(log_state_in), log_signal(tr.ctrl_in),
 					log_signal(fsm_data.state_table[tr.state_out]), log_signal(tr.ctrl_out));
 		}
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 0c782b8ab..0e28dbca2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -543,7 +543,7 @@ struct HierarchyPass : public Pass {
 		log("        an unknown module is used as cell type.\n");
 		log("\n");
 		log("    -simcheck\n");
-		log("        like -check, but also thow an error if blackbox modules are\n");
+		log("        like -check, but also throw an error if blackbox modules are\n");
 		log("        instantiated, and throw an error if the design has no top module\n");
 		log("\n");
 		log("    -purge_lib\n");
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 610edc5e9..998c6507c 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -1477,7 +1477,7 @@ struct OptExprPass : public Pass {
 		log("    opt_expr [options] [selection]\n");
 		log("\n");
 		log("This pass performs const folding on internal cell types with constant inputs.\n");
-		log("It also performs some simple expression rewritring.\n");
+		log("It also performs some simple expression rewriting.\n");
 		log("\n");
 		log("    -mux_undef\n");
 		log("        remove 'undef' inputs from $mux, $pmux and $_MUX_ cells\n");
diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 261af538f..d1b8ab358 100644
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -133,7 +133,7 @@ struct OptLutWorker
 				// Second, make sure that the connection to dedicated logic is legal. If it is not legal,
 				// it means one of the two things:
 				//   * The connection is spurious. I.e. this is dedicated logic that will be packed
-				//     with some other LUT, and it just happens to be conected to this LUT as well.
+				//     with some other LUT, and it just happens to be connected to this LUT as well.
 				//   * The connection is illegal.
 				// In either of these cases, we don't need to concern ourselves with preserving the connection
 				// between this LUT and this dedicated logic cell.
diff --git a/techlibs/achronix/speedster22i/cells_map.v b/techlibs/achronix/speedster22i/cells_map.v
index 95f5d59c5..9f647cbef 100755
--- a/techlibs/achronix/speedster22i/cells_map.v
+++ b/techlibs/achronix/speedster22i/cells_map.v
@@ -32,7 +32,7 @@ endmodule
 // > end buffers <
 
 // > Look-Up table <
-// > VT: I still think Achronix folks would have choosen a better \
+// > VT: I still think Achronix folks would have chosen a better \
 // >     logic architecture.
 // LUT Map
 module \$lut (A, Y);
@@ -43,30 +43,30 @@ module \$lut (A, Y);
    generate
       if (WIDTH == 1) begin
 	   // VT: This is not consistent and ACE will complain: assign Y = ~A[0];
-         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+         LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
            (.dout(Y), .din0(A[0]), .din1(1'b0), .din2(1'b0), .din3(1'b0));
       end else
       if (WIDTH == 2) begin
-              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_ 
+              LUT4 #(.lut_function({4{LUT}})) _TECHMAP_REPLACE_
                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(1'b0), .din3(1'b0));
       end else
       if(WIDTH == 3) begin
-	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_ 
+	      LUT4 #(.lut_function({2{LUT}})) _TECHMAP_REPLACE_
                 (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(1'b0));
       end else
       if(WIDTH == 4) begin
-             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_ 
+             LUT4 #(.lut_function(LUT)) _TECHMAP_REPLACE_
                (.dout(Y), .din0(A[0]), .din1(A[1]), .din2(A[2]), .din3(A[3]));
       end else
 	   wire _TECHMAP_FAIL_ = 1;
    endgenerate
-endmodule 
+endmodule
 // > end LUT <
 
 // > Flops <
 // DFF flop
 module  \$_DFF_P_ (input D, C, output Q);
-   DFF _TECHMAP_REPLACE_ 
+   DFF _TECHMAP_REPLACE_
      (.q(Q), .d(D), .ck(C));
-endmodule 
+endmodule
 
diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 92b10781d..3642e3bd3 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -108,7 +108,7 @@ struct SynthAchronixPass : public ScriptPass {
     extra_args(args, argidx, design);
 
     if (!design->full_selection())
-      log_cmd_error("This comannd only operates on fully selected designs!\n");
+      log_cmd_error("This command only operates on fully selected designs!\n");
 
     log_header(design, "Executing SYNTH_ACHRONIX pass.\n");
     log_push();
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 9c44599ea..68f4399d4 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -119,7 +119,7 @@ struct SynthAnlogicPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ANLOGIC pass.\n");
 		log_push();
diff --git a/techlibs/common/prep.cc b/techlibs/common/prep.cc
index 897f37dbb..86fb4d6c6 100644
--- a/techlibs/common/prep.cc
+++ b/techlibs/common/prep.cc
@@ -153,7 +153,7 @@ struct PrepPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing PREP pass.\n");
 		log_push();
diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc
index efb214759..d9565131e 100644
--- a/techlibs/common/synth.cc
+++ b/techlibs/common/synth.cc
@@ -155,7 +155,7 @@ struct SynthPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH pass.\n");
 		log_push();
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index a5dac3566..810380d4a 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -111,7 +111,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_COOLRUNNER2 pass.\n");
 		log_push();
diff --git a/techlibs/easic/synth_easic.cc b/techlibs/easic/synth_easic.cc
index b5ed93be4..dd9e3dab7 100644
--- a/techlibs/easic/synth_easic.cc
+++ b/techlibs/easic/synth_easic.cc
@@ -117,7 +117,7 @@ struct SynthEasicPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_EASIC pass.\n");
 		log_push();
diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 057f9d737..425d62d24 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -484,7 +484,7 @@ module DCUA(
 	parameter D_XGE_MODE = "0b0";
 
 // These parameters don't do anything but are
-// needed for compatability with Diamond
+// needed for compatibility with Diamond
 	parameter D_TX_MAX_RATE = "2.5";
 	parameter D_RX_MAX_RATE = "2.5";
 	parameter CH0_TXAMPLITUDE = "0d1300";
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 825e131c4..2e9176a84 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -189,7 +189,7 @@ struct SynthEcp5Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ECP5 pass.\n");
 		log_push();
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index e3d924e26..9700b3898 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -109,7 +109,7 @@ struct SynthGowinPass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_GOWIN pass.\n");
 		log_push();
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index b91d5273a..eeb001b46 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -120,7 +120,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
 			log_cmd_error("Invalid part name: '%s'\n", part.c_str());
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index c2aed873b..626f6d381 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -198,7 +198,7 @@ struct SynthIce40Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_ICE40 pass.\n");
 		log_push();
diff --git a/techlibs/intel/cyclonev/cells_sim.v b/techlibs/intel/cyclonev/cells_sim.v
index 5ecdabcfc..fa27c2c8e 100644
--- a/techlibs/intel/cyclonev/cells_sim.v
+++ b/techlibs/intel/cyclonev/cells_sim.v
@@ -54,7 +54,7 @@ module cyclonev_lcell_comb
    // Internal variables
    // Sub mask for fragmented LUTs
    wire [15:0] mask_a, mask_b, mask_c, mask_d;
-   // Independant output for fragmented LUTs
+   // Independent output for fragmented LUTs
    wire        output_0, output_1, output_2, output_3;
    // Extended mode uses mux to define the output
    wire        mux_0, mux_1;
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 2676ea657..62b3cd0e2 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -118,7 +118,7 @@ struct SynthSf2Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		log_header(design, "Executing SYNTH_SF2 pass.\n");
 		log_push();
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index b27c08529..6c11d885d 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -178,7 +178,7 @@ struct SynthXilinxPass : public Pass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		bool active = run_from.empty();
 

From 50b09de03320843660636c663629c649ab242321 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Jan 2019 15:05:23 +0100
Subject: [PATCH 275/528] Fix VerificImporter asymmetric memories error message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 61d9d593c..5280a2b9c 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1201,7 +1201,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		{
 			RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
 			if (memory->width != int(inst->Input2Size()))
-				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
+				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
 
 			RTLIL::SigSpec addr = operatorInput1(inst);
 			RTLIL::SigSpec data = operatorInput2(inst);

From 1eb101a38a0e6ca99cb1dfbcc77f16a6bff79465 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 2 Jan 2019 15:33:43 +0100
Subject: [PATCH 276/528] Improve VerificImporter support for writes to
 asymmetric memories

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 53 ++++++++++++++++++++++--------------
 1 file changed, 33 insertions(+), 20 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 5280a2b9c..94138cdd6 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1200,27 +1200,34 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 		if (inst->Type() == OPER_WRITE_PORT || inst->Type() == OPER_CLOCKED_WRITE_PORT)
 		{
 			RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
-			if (memory->width != int(inst->Input2Size()))
+			int numchunks = int(inst->Input2Size()) / memory->width;
+			int chunksbits = ceil_log2(numchunks);
+
+			if ((numchunks * memory->width) != int(inst->Input2Size()) || (numchunks & (numchunks - 1)) != 0)
 				log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
 
-			RTLIL::SigSpec addr = operatorInput1(inst);
-			RTLIL::SigSpec data = operatorInput2(inst);
+			for (int i = 0; i < numchunks; i++)
+			{
+				RTLIL::SigSpec addr = {operatorInput1(inst), RTLIL::Const(i, chunksbits)};
+				RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
 
-			RTLIL::Cell *cell = module->addCell(inst_name, "$memwr");
-			cell->parameters["\\MEMID"] = memory->name.str();
-			cell->parameters["\\CLK_ENABLE"] = false;
-			cell->parameters["\\CLK_POLARITY"] = true;
-			cell->parameters["\\PRIORITY"] = 0;
-			cell->parameters["\\ABITS"] = GetSize(addr);
-			cell->parameters["\\WIDTH"] = GetSize(data);
-			cell->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
-			cell->setPort("\\CLK", RTLIL::State::S0);
-			cell->setPort("\\ADDR", addr);
-			cell->setPort("\\DATA", data);
+				RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
+						RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memwr");
+				cell->parameters["\\MEMID"] = memory->name.str();
+				cell->parameters["\\CLK_ENABLE"] = false;
+				cell->parameters["\\CLK_POLARITY"] = true;
+				cell->parameters["\\PRIORITY"] = 0;
+				cell->parameters["\\ABITS"] = GetSize(addr);
+				cell->parameters["\\WIDTH"] = GetSize(data);
+				cell->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
+				cell->setPort("\\CLK", RTLIL::State::S0);
+				cell->setPort("\\ADDR", addr);
+				cell->setPort("\\DATA", data);
 
-			if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
-				cell->parameters["\\CLK_ENABLE"] = true;
-				cell->setPort("\\CLK", net_map_at(inst->GetClock()));
+				if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
+					cell->parameters["\\CLK_ENABLE"] = true;
+					cell->setPort("\\CLK", net_map_at(inst->GetClock()));
+				}
 			}
 			continue;
 		}
@@ -1893,13 +1900,19 @@ struct VerificPass : public Pass {
 		{
 			Message::SetConsoleOutput(0);
 			Message::RegisterCallBackMsg(msg_func);
+
 			RuntimeFlags::SetVar("db_preserve_user_nets", 1);
 			RuntimeFlags::SetVar("db_allow_external_nets", 1);
-			RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
-			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
+			RuntimeFlags::SetVar("db_infer_wide_operators", 1);
+
 			RuntimeFlags::SetVar("veri_extract_dualport_rams", 0);
 			RuntimeFlags::SetVar("veri_extract_multiport_rams", 1);
-			RuntimeFlags::SetVar("db_infer_wide_operators", 1);
+
+			RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);
+			RuntimeFlags::SetVar("vhdl_extract_multiport_rams", 1);
+
+			RuntimeFlags::SetVar("vhdl_support_variable_slice", 1);
+			RuntimeFlags::SetVar("vhdl_ignore_assertion_statements", 0);
 
 			// Workaround for VIPER #13851
 			RuntimeFlags::SetVar("veri_create_name_for_unnamed_gen_block", 1);

From bf8db55ef36f6839827cd8bc69f673fd3fd43cca Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 05:04:28 +0000
Subject: [PATCH 277/528] opt_expr: improve simplification of comparisons with
 large constants.

The idea behind this simplification is that a N-bit signal X being
compared with an M-bit constant where M>N and the constant has Nth
or higher bit set, it either always succeeds or always fails.

However, the existing implementation only worked with one-hot signals
for some reason. It also printed incorrect messages.

This commit adjusts the simplification to have as much power as
possible, and fixes other bugs.
---
 passes/opt/opt_expr.cc   | 117 ++++++++++++++++-----------------------
 tests/opt/opt_expr_cmp.v |  18 ++++++
 2 files changed, 65 insertions(+), 70 deletions(-)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 9abbdc6ac..76bcfd44f 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -259,6 +259,22 @@ bool is_one_or_minus_one(const Const &value, bool is_signed, bool &is_negative)
 	return last_bit_one;
 }
 
+int get_highest_hot_index(RTLIL::SigSpec signal)
+{
+	for (int i = GetSize(signal) - 1; i >= 0; i--)
+	{
+		if (signal[i] == RTLIL::State::S0)
+			continue;
+
+		if (signal[i] == RTLIL::State::S1)
+			return i;
+
+		break;
+	}
+
+	return -1;
+}
+
 // if the signal has only one bit set, return the index of that bit.
 // otherwise return -1
 int get_onehot_bit_index(RTLIL::SigSpec signal)
@@ -1345,9 +1361,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 		}
 
 		// simplify comparisons
-		// currently, only replaces comparisons with an extreme of the signal range with a constant
-		// TODO: since, unlike the following optimization, this one does not assume that both inputs to the cell are constant,
-		// it is more robust; the following optimization should be folded into this one at some point
 		if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
 		{
 			IdString cmp_type = cell->type;
@@ -1405,29 +1418,53 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						replace = true;
 					}
 
-					int const_bit_set = get_onehot_bit_index(const_sig);
-					if (const_bit_set >= 0 && const_bit_set < var_width)
+					int const_bit_hot = get_onehot_bit_index(const_sig);
+					if (const_bit_hot >= 0 && const_bit_hot < var_width)
 					{
-						RTLIL::SigSpec var_high_sig(RTLIL::State::S0, var_width - const_bit_set);
-						for (int i = const_bit_set; i < var_width; i++) {
-							var_high_sig[i - const_bit_set] = var_sig[i];
+						RTLIL::SigSpec var_high_sig(RTLIL::State::S0, var_width - const_bit_hot);
+						for (int i = const_bit_hot; i < var_width; i++) {
+							var_high_sig[i - const_bit_hot] = var_sig[i];
 						}
 
 						if (cmp_type == "$lt")
 						{
 							condition   = stringf("unsigned X<%s", log_signal(const_sig));
-							replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_set);
+							replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
 							module->addLogicNot(NEW_ID, var_high_sig, cell->getPort("\\Y"));
 							remove = true;
 						}
 						if (cmp_type == "$ge")
 						{
 							condition   = stringf("unsigned X>=%s", log_signal(const_sig));
-							replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_set);
+							replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
 							module->addReduceOr(NEW_ID, var_high_sig, cell->getPort("\\Y"));
 							remove = true;
 						}
 					}
+
+					int const_bit_set = get_highest_hot_index(const_sig);
+					if(const_bit_set >= var_width)
+					{
+						string cmp_name;
+						if (cmp_type == "$lt" || cmp_type == "$le")
+						{
+							if (cmp_type == "$lt") cmp_name = "<";
+							if (cmp_type == "$le") cmp_name = "<=";
+							condition   = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
+							replacement = "constant 1";
+							replace_sig[0] = State::S1;
+							replace = true;
+						}
+						if (cmp_type == "$gt" || cmp_type == "$ge")
+						{
+							if (cmp_type == "$gt") cmp_name = ">";
+							if (cmp_type == "$ge") cmp_name = ">=";
+							condition   = stringf("unsigned X[%d:0]%s%s", var_width - 1, cmp_name.c_str(), log_signal(const_sig));
+							replacement = "constant 0";
+							replace_sig[0] = State::S0;
+							replace = true;
+						}
+					}
 				}
 				else
 				{ /* signed */
@@ -1460,66 +1497,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 			}
 		}
 
-		// replace a<0 or a>=0 with the top bit of a
-		if (do_fine && (cell->type == "$lt" || cell->type == "$ge" || cell->type == "$gt" || cell->type == "$le"))
-		{
-			//used to decide whether the signal needs to be negated
-			bool is_lt = false;
-
-			//references the variable signal in the comparison
-			RTLIL::SigSpec sigVar;
-
-			//references the constant signal in the comparison
-			RTLIL::SigSpec sigConst;
-
-			// note that this signal must be constant for the optimization
-			// to take place, but it is not checked beforehand.
-			// If new passes are added, this signal must be checked for const-ness
-
-			//width of the variable port
-			int width;
-			int const_width;
-
-			bool var_signed;
-
-			if (cell->type == "$lt" || cell->type == "$ge") {
-				is_lt = cell->type == "$lt" ? 1 : 0;
-				sigVar = cell->getPort("\\A");
-				sigConst = cell->getPort("\\B");
-				width = cell->parameters["\\A_WIDTH"].as_int();
-				const_width = cell->parameters["\\B_WIDTH"].as_int();
-				var_signed = cell->parameters["\\A_SIGNED"].as_bool();
-			} else
-			if (cell->type == "$gt" || cell->type == "$le") {
-				is_lt = cell->type == "$gt" ? 1 : 0;
-				sigVar = cell->getPort("\\B");
-				sigConst = cell->getPort("\\A");
-				width = cell->parameters["\\B_WIDTH"].as_int();
-				const_width = cell->parameters["\\A_WIDTH"].as_int();
-				var_signed = cell->parameters["\\B_SIGNED"].as_bool();
-			} else
-				log_abort();
-
-			if (sigConst.is_fully_const() && sigConst.is_fully_def() && var_signed == false)
-			{
-				int const_bit_set = get_onehot_bit_index(sigConst);
-				if(const_bit_set >= width && const_bit_set >= 0){
-					RTLIL::SigSpec a_prime(RTLIL::State::S0, 1);
-					if(is_lt){
-						a_prime[0] = RTLIL::State::S1;
-						log("Replacing %s cell `%s' (implementing unsigned X[%d:0] < %s[%d:0]) with constant 0.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
-					}
-					else{
-						log("Replacing %s cell `%s' (implementing unsigned X[%d:0]>= %s[%d:0]) with constant 1.\n", log_id(cell->type), log_id(cell), width-1, log_signal(sigConst),const_width-1);
-					}
-					module->connect(cell->getPort("\\Y"), a_prime);
-					module->remove(cell);
-					did_something = true;
-					goto next_cell;
-				}
-			}
-		}
-
 	next_cell:;
 #undef ACTION_DO
 #undef ACTION_DO_Y
diff --git a/tests/opt/opt_expr_cmp.v b/tests/opt/opt_expr_cmp.v
index 500b15f1b..5aff4b80f 100644
--- a/tests/opt/opt_expr_cmp.v
+++ b/tests/opt/opt_expr_cmp.v
@@ -19,4 +19,22 @@ module top(...);
   output o3_2 = 4'b0100 <= a;
   output o3_3 = a <  4'b0100;
   output o3_4 = a >= 4'b0100;
+
+  output o4_1 = 5'b10000 >  a;
+  output o4_2 = 5'b10000 >= a;
+  output o4_3 = 5'b10000 <  a;
+  output o4_4 = 5'b10000 <= a;
+  output o4_5 = a <  5'b10000;
+  output o4_6 = a <= 5'b10000;
+  output o4_7 = a >  5'b10000;
+  output o4_8 = a >= 5'b10000;
+
+  output o5_1 = 5'b10100 >  a;
+  output o5_2 = 5'b10100 >= a;
+  output o5_3 = 5'b10100 <  a;
+  output o5_4 = 5'b10100 <= a;
+  output o5_5 = a <  5'b10100;
+  output o5_6 = a <= 5'b10100;
+  output o5_7 = a >  5'b10100;
+  output o5_8 = a >= 5'b10100;
 endmodule

From 07af772a7279d656564fb23eee457e71cc0d657f Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 2 Jan 2019 14:09:53 +0000
Subject: [PATCH 278/528] flowmap: new techmap pass.

---
 passes/opt/Makefile.inc     |   2 +-
 passes/techmap/Makefile.inc |   1 +
 passes/techmap/flowmap.cc   | 873 ++++++++++++++++++++++++++++++++++++
 3 files changed, 875 insertions(+), 1 deletion(-)
 create mode 100644 passes/techmap/flowmap.cc

diff --git a/passes/opt/Makefile.inc b/passes/opt/Makefile.inc
index 0f596b1f4..c3e0a2a40 100644
--- a/passes/opt/Makefile.inc
+++ b/passes/opt/Makefile.inc
@@ -6,12 +6,12 @@ OBJS += passes/opt/opt_reduce.o
 OBJS += passes/opt/opt_rmdff.o
 OBJS += passes/opt/opt_clean.o
 OBJS += passes/opt/opt_expr.o
-OBJS += passes/opt/opt_lut.o
 
 ifneq ($(SMALL),1)
 OBJS += passes/opt/share.o
 OBJS += passes/opt/wreduce.o
 OBJS += passes/opt/opt_demorgan.o
 OBJS += passes/opt/rmports.o
+OBJS += passes/opt/opt_lut.o
 endif
 
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 4faa0ab00..cf9e198ad 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -36,6 +36,7 @@ OBJS += passes/techmap/attrmvcp.o
 OBJS += passes/techmap/attrmap.o
 OBJS += passes/techmap/zinit.o
 OBJS += passes/techmap/dff2dffs.o
+OBJS += passes/techmap/flowmap.o
 endif
 
 GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
new file mode 100644
index 000000000..cdca78db8
--- /dev/null
+++ b/passes/techmap/flowmap.cc
@@ -0,0 +1,873 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  whitequark <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// [[CITE]]
+// Jason Cong; Yuzheng Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,"
+// Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 13, no. 1, Jan 1994
+// doi: 10.1109/43.273754
+
+// Required reading material:
+//
+// Min-cut max-flow theorem:
+//   https://www.coursera.org/lecture/algorithms-part2/maxflow-mincut-theorem-beb9G
+// FlowMap paper:
+//   http://cadlab.cs.ucla.edu/~cong/papers/iccad92.pdf
+
+// Notes on implementation:
+//
+// 1. In the paper, the nodes are logic elements (analogous to Yosys cells) and edges are wires. However, in our implementation, we use
+// an inverted approach: the nodes are Yosys wire bits, and the edges are derived from (but aren't represented by) Yosys cells.
+// This may seem counterintuitive. Three observations may help understanding this. First, for a cell with a 1-bit Y output that is
+// the sole driver of its output net (which is the typical case), these representations are equivalent, because there is an exact
+// correspondence between cells and output wires. Second, in the paper, primary inputs (analogous to Yosys cell or module ports) are
+// nodes, and in Yosys, inputs are wires; our approach allows a direct mapping from both primary inputs and 1-output logic elements to
+// flow graph nodes. Third, Yosys cells may have multiple outputs or multi-bit outputs, and by using Yosys wire bits as flow graph nodes,
+// such cells are supported without any additional effort; any Yosys cell with n output wire bits ends up being split into n flow graph
+// nodes.
+//
+// 2. The paper introduces three networks: Nt, Nt', and Nt''. The network Nt is directly represented by a subgraph of RTLIL graph,
+// which is parsed into an equivalent but easier to traverse representation in FlowmapWorker. The network Nt' is built explicitly
+// from a subgraph of Nt, and uses a similar representation in FlowGraph. The network Nt'' is implicit in FlowGraph, which is possible
+// because of the following observation: each Nt' node corresponds to an Nt'' edge of capacity 1, and each Nt' edge corresponds to
+// an Nt'' edge of capacity ∞. Therefore, we only need to explicitly record flow for Nt' edges and through Nt' nodes.
+//
+// 3. The paper ambiguously states: "Moreover, we can find such a cut (X′′, X̅′′) by performing a depth first search starting at the source s,
+// and including in X′′ all the nodes which are reachable from s." This actually refers to a specific kind of search, mincut computation.
+// Mincut computation involves computing the set of nodes reachable from s by an undirected path with no full (i.e. zero capacity) forward
+// edges or empty (i.e. no flow) backward edges.
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/modtools.h"
+#include "kernel/consteval.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct GraphStyle
+{
+	string label;
+	string color;
+
+	GraphStyle(string label = "", string color = "black") :
+		label(label), color(color) {}
+};
+
+static string dot_escape(string value)
+{
+	std::string escaped;
+	for (char c : value) {
+		if (c == '\n')
+		{
+			escaped += "\\n";
+			continue;
+		}
+		if (c == '\\' || c == '"')
+			escaped += "\\";
+		escaped += c;
+	}
+	return escaped;
+}
+
+static void dump_dot_graph(string filename,
+                           pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges,
+                           pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs,
+                           std::function<GraphStyle(RTLIL::SigBit)> node_style =
+                           		[](RTLIL::SigBit) { return GraphStyle{}; },
+                           std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style =
+                           		[](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
+                           string name = "")
+{
+	FILE *f = fopen(filename.c_str(), "w");
+	fprintf(f, "digraph \"%s\" {\n", name.c_str());
+	fprintf(f, "  rankdir=\"TB\";\n");
+
+	dict<RTLIL::SigBit, int> ids;
+	for (auto node : nodes)
+	{
+		ids[node] = ids.size();
+
+		string shape = "ellipse";
+		if (inputs[node])
+			shape = "box";
+		if (outputs[node])
+			shape = "octagon";
+		auto prop = node_style(node);
+		string id;
+		if (node == SigBit())
+			id = "(source)";
+		else
+			id = log_signal(node);
+		fprintf(f, "  n%d [ shape=%s, fontname=\"Monospace\", label=\"%s%s\", color=\"%s\" ];\n",
+		        ids[node], shape.c_str(), dot_escape(id).c_str(), dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
+	}
+
+	fprintf(f, "  { rank=\"source\"; ");
+	for (auto input : inputs)
+		if (nodes[input])
+			fprintf(f, "n%d; ", ids[input]);
+	fprintf(f, "}\n");
+
+	fprintf(f, "  { rank=\"sink\"; ");
+	for (auto output : outputs)
+		if (nodes[output])
+			fprintf(f, "n%d; ", ids[output]);
+	fprintf(f, "}\n");
+
+	for (auto edge : edges)
+	{
+		auto source = edge.first;
+		for (auto sink : edge.second) {
+			if (nodes[source] && nodes[sink])
+			{
+				auto prop = edge_style(source, sink);
+				fprintf(f, "  n%d -> n%d [ label=\"%s\", color=\"%s\" ];\n",
+				        ids[source], ids[sink], dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
+			}
+		}
+	}
+
+	fprintf(f, "}\n");
+	fclose(f);
+}
+
+struct FlowGraph
+{
+	const RTLIL::SigBit source;
+	RTLIL::SigBit sink;
+	pool<RTLIL::SigBit> nodes = {source};
+	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
+
+	const int MAX_NODE_FLOW = 1;
+	dict<RTLIL::SigBit, int> node_flow;
+	dict<pair<RTLIL::SigBit, RTLIL::SigBit>, int> edge_flow;
+
+	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed;
+
+	void dump_dot_graph(string filename)
+	{
+		auto node_style = [&](RTLIL::SigBit node) {
+			string label;
+			for (auto collapsed_node : collapsed[node])
+				label += stringf(" %s", log_signal(collapsed_node));
+			int flow = node_flow[node];
+			if (node != source && node != sink)
+				label += stringf("\n%d/%d", flow, MAX_NODE_FLOW);
+			else
+				label += stringf("\n%d/∞", flow);
+			return GraphStyle{label, flow < MAX_NODE_FLOW ? "green" : "black"};
+		};
+		auto edge_style = [&](RTLIL::SigBit source, RTLIL::SigBit sink) {
+			int flow = edge_flow[{source, sink}];
+			return GraphStyle{stringf("%d/∞", flow), flow > 0 ? "blue" : "black"};
+		};
+		::dump_dot_graph(filename, nodes, edges_fw, {source}, {sink}, node_style, edge_style);
+	}
+
+	// Here, we are working on the Nt'' network, but our representation is the Nt' network.
+	// The difference between these is that where in Nt' we have a subgraph:
+	//
+	//   v1 -> v2 -> v3
+	//
+	// in Nt'' we have a corresponding subgraph:
+	//
+	//   v'1b -∞-> v'2t -f-> v'2b -∞-> v'3t
+	//
+	// To address this, we split each node v into two nodes, v't and v'b. This representation is virtual,
+	// in the sense that nodes v't and v'b are overlaid on top of the original node v, and only exist
+	// in paths and worklists.
+
+	struct NodePrime
+	{
+		RTLIL::SigBit node;
+		bool is_bottom;
+
+		NodePrime(RTLIL::SigBit node, bool is_bottom) :
+			node(node), is_bottom(is_bottom) {}
+
+		bool operator==(const NodePrime &other) const
+		{
+			return node == other.node && is_bottom == other.is_bottom;
+		}
+		bool operator!=(const NodePrime &other) const
+		{
+			return !(*this == other);
+		}
+		unsigned int hash() const
+		{
+			return hash_ops<pair<RTLIL::SigBit, int>>::hash({node, is_bottom});
+		}
+
+		static NodePrime top(RTLIL::SigBit node)
+		{
+			return NodePrime(node, /*is_bottom=*/false);
+		}
+
+		static NodePrime bottom(RTLIL::SigBit node)
+		{
+			return NodePrime(node, /*is_bottom=*/true);
+		}
+
+		NodePrime as_top() const
+		{
+			log_assert(is_bottom);
+			return top(node);
+		}
+
+		NodePrime as_bottom() const
+		{
+			log_assert(!is_bottom);
+			return bottom(node);
+		}
+	};
+
+	bool find_augmenting_path(bool commit)
+	{
+		NodePrime source_prime = {source, true};
+		NodePrime sink_prime = {sink, false};
+		vector<NodePrime> path = {source_prime};
+		pool<NodePrime> visited = {};
+		bool found;
+		do {
+			found = false;
+
+			auto node_prime = path.back();
+			visited.insert(node_prime);
+
+			if (!node_prime.is_bottom) // vt
+			{
+				if (!visited[node_prime.as_bottom()] && node_flow[node_prime.node] < MAX_NODE_FLOW)
+				{
+					path.push_back(node_prime.as_bottom());
+					found = true;
+				}
+				else
+				{
+					for (auto node_pred : edges_bw[node_prime.node])
+					{
+						if (!visited[NodePrime::bottom(node_pred)] && edge_flow[{node_pred, node_prime.node}] > 0)
+						{
+							path.push_back(NodePrime::bottom(node_pred));
+							found = true;
+							break;
+						}
+					}
+				}
+			}
+			else // vb
+			{
+				if (!visited[node_prime.as_top()] && node_flow[node_prime.node] > 0)
+				{
+					path.push_back(node_prime.as_top());
+					found = true;
+				}
+				else
+				{
+					for (auto node_succ : edges_fw[node_prime.node])
+					{
+						if (!visited[NodePrime::top(node_succ)] /* && edge_flow[...] < ∞ */)
+						{
+							path.push_back(NodePrime::top(node_succ));
+							found = true;
+							break;
+						}
+					}
+				}
+			}
+
+			if (!found && path.size() > 1)
+			{
+				path.pop_back();
+				found = true;
+			}
+		} while(path.back() != sink_prime && found);
+
+		if (commit && path.back() == sink_prime)
+		{
+			auto prev_prime = path.front();
+			for (auto node_prime : path)
+			{
+				if (node_prime == source_prime)
+					continue;
+
+				log_assert(prev_prime.is_bottom ^ node_prime.is_bottom);
+				if (prev_prime.node == node_prime.node)
+				{
+					auto node = node_prime.node;
+					if (!prev_prime.is_bottom && node_prime.is_bottom)
+					{
+						log_assert(node_flow[node] == 0);
+						node_flow[node]++;
+					}
+					else
+					{
+						log_assert(node_flow[node] != 0);
+						node_flow[node]--;
+					}
+				}
+				else
+				{
+					if (prev_prime.is_bottom && !node_prime.is_bottom)
+					{
+						log_assert(true /* edge_flow[...] < ∞ */);
+						edge_flow[{prev_prime.node, node_prime.node}]++;
+					}
+					else
+					{
+						log_assert((edge_flow[{node_prime.node, prev_prime.node}] > 0));
+						edge_flow[{node_prime.node, prev_prime.node}]--;
+					}
+				}
+				prev_prime = node_prime;
+			}
+
+			node_flow[source]++;
+			node_flow[sink]++;
+		}
+		return path.back() == sink_prime;
+	}
+
+	int maximum_flow(int order)
+	{
+		int flow = 0;
+		while (flow < order && find_augmenting_path(/*commit=*/true))
+			flow++;
+		return flow + find_augmenting_path(/*commit=*/false);
+	}
+
+	pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> edge_cut()
+	{
+		pool<RTLIL::SigBit> x, xi;
+
+		NodePrime source_prime = {source, true};
+		NodePrime sink_prime = {sink, false};
+		pool<NodePrime> worklist = {source_prime}, visited;
+		while (!worklist.empty())
+		{
+			auto node_prime = worklist.pop();
+			if (visited[node_prime])
+				continue;
+			visited.insert(node_prime);
+
+			if (!node_prime.is_bottom)
+				x.insert(node_prime.node);
+
+			// Mincut is constructed by traversing a graph in an undirected way along forward edges that aren't full, or backward edges
+			// that aren't empty.
+			if (!node_prime.is_bottom) // top
+			{
+				if (node_flow[node_prime.node] < MAX_NODE_FLOW)
+					worklist.insert(node_prime.as_bottom());
+				for (auto node_pred : edges_bw[node_prime.node])
+					if (edge_flow[{node_pred, node_prime.node}] > 0)
+						worklist.insert(NodePrime::bottom(node_pred));
+			}
+			else // bottom
+			{
+				if (node_flow[node_prime.node] > 0)
+					worklist.insert(node_prime.as_top());
+				for (auto node_succ : edges_fw[node_prime.node])
+					if (true /* edge_flow[...] < ∞ */)
+						worklist.insert(NodePrime::top(node_succ));
+			}
+		}
+
+		for (auto node : nodes)
+			if (!x[node])
+				xi.insert(node);
+
+		for (auto collapsed_node : collapsed[sink])
+			xi.insert(collapsed_node);
+
+		log_assert(!x[sink] && xi[sink]);
+		return {x, xi};
+	}
+};
+
+struct FlowmapWorker
+{
+	int order;
+	pool<IdString> cell_types;
+	bool debug;
+
+	RTLIL::Module *module;
+	SigMap sigmap;
+	ModIndex index;
+	pool<RTLIL::Cell*> cells;
+
+	pool<RTLIL::SigBit> nodes, inputs, outputs;
+	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
+	dict<RTLIL::SigBit, int> labels;
+
+	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates, lut_inputs;
+
+	dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
+	dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_fanout;
+
+	int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
+
+	void dump_dot_graph(string filename, pool<RTLIL::SigBit> subgraph = {}, pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {})
+	{
+		if (subgraph.empty())
+			subgraph = nodes;
+
+		auto node_style = [&](RTLIL::SigBit node) {
+			string label, color;
+			if (labels[node] == -1)
+				label = string("\n<unlabeled>");
+			else
+				label = stringf("\nl=%d", labels[node]);
+			color = "black";
+			if (cut.first[node])
+				color = "blue";
+			if (cut.second[node])
+				color = "red";
+			return GraphStyle{label, color};
+		};
+		auto edge_style = [&](RTLIL::SigBit, RTLIL::SigBit) {
+			return GraphStyle{};
+		};
+		::dump_dot_graph(filename, subgraph, edges_fw, inputs, outputs, node_style, edge_style, module->name.str());
+	}
+
+	pool<RTLIL::SigBit> find_subgraph(RTLIL::SigBit sink)
+	{
+		pool<RTLIL::SigBit> subgraph;
+		pool<RTLIL::SigBit> worklist = {sink};
+		while (!worklist.empty())
+		{
+			auto node = worklist.pop();
+			subgraph.insert(node);
+			for (auto source : edges_bw[node])
+			{
+				if (!subgraph[source])
+					worklist.insert(source);
+			}
+		}
+		return subgraph;
+	}
+
+	FlowGraph build_flow_graph(RTLIL::SigBit sink, int p)
+	{
+		FlowGraph flow_graph;
+		flow_graph.sink = sink;
+
+		pool<RTLIL::SigBit> worklist = {sink}, visited;
+		while (!worklist.empty())
+		{
+			auto node = worklist.pop();
+			visited.insert(node);
+
+			auto collapsed_node = labels[node] == p ? sink : node;
+			if (node != collapsed_node)
+				flow_graph.collapsed[collapsed_node].insert(node);
+			flow_graph.nodes.insert(collapsed_node);
+
+			for (auto node_pred : edges_bw[node])
+			{
+				auto collapsed_node_pred = labels[node_pred] == p ? sink : node_pred;
+				if (node_pred != collapsed_node_pred)
+					flow_graph.collapsed[collapsed_node_pred].insert(node_pred);
+				if (collapsed_node != collapsed_node_pred)
+				{
+					flow_graph.edges_bw[collapsed_node].insert(collapsed_node_pred);
+					flow_graph.edges_fw[collapsed_node_pred].insert(collapsed_node);
+				}
+				if (inputs[node_pred])
+				{
+					flow_graph.edges_bw[collapsed_node_pred].insert(flow_graph.source);
+					flow_graph.edges_fw[flow_graph.source].insert(collapsed_node_pred);
+				}
+
+				if (!visited[node_pred])
+					worklist.insert(node_pred);
+			}
+		}
+		return flow_graph;
+	}
+
+	FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
+		order(order), cell_types(cell_types), debug(debug), module(module), sigmap(module), index(module)
+	{
+		log("Labeling cells.\n");
+		for (auto cell : module->selected_cells())
+		{
+			if (cell_types[cell->type])
+			{
+				if (!cell->known())
+				{
+					log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
+				}
+				cells.insert(cell);
+
+				for (auto conn : cell->connections())
+				{
+					if (!cell->output(conn.first)) continue;
+					int offset = -1;
+					for (auto bit : conn.second)
+					{
+						offset++;
+						if (!bit.wire) continue;
+						auto mapped_bit = sigmap(bit);
+						if (nodes[mapped_bit])
+							log_error("Multiple drivers found for wire %s.\n", log_signal(mapped_bit));
+						nodes.insert(mapped_bit);
+						node_origins[mapped_bit] = ModIndex::PortInfo(cell, conn.first, offset);
+						cell_fanout[cell].insert(mapped_bit);
+					}
+				}
+
+				int fanin = 0;
+				for (auto conn : cell->connections())
+				{
+					if (!cell->input(conn.first)) continue;
+					for (auto bit : sigmap(conn.second))
+					{
+						if (!bit.wire) continue;
+						for (auto fanout_bit : cell_fanout[cell])
+						{
+							edges_fw[bit].insert(fanout_bit);
+							edges_bw[fanout_bit].insert(bit);
+						}
+						fanin++;
+					}
+				}
+
+				if (fanin > order)
+					log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
+					          cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
+			}
+		}
+
+		for (auto edge : edges_fw)
+		{
+			if (!nodes[edge.first])
+			{
+				inputs.insert(edge.first);
+				nodes.insert(edge.first);
+			}
+		}
+
+		for (auto node : nodes)
+		{
+			auto node_info = index.query(node);
+			if (node_info->is_output && !inputs[node])
+				outputs.insert(node);
+			for (auto port : node_info->ports)
+				if (!cell_types[port.cell->type] && !inputs[node])
+					outputs.insert(node);
+		}
+
+		for (auto node : nodes)
+			labels[node] = -1;
+		for (auto input : inputs)
+			labels[input] = 0;
+
+		if (debug)
+		{
+			dump_dot_graph("flowmap-init.dot");
+			log("Dumped complete combinatorial graph to `flowmap-init.dot`.\n");
+		}
+
+		pool<RTLIL::SigBit> worklist = nodes;
+		int debug_num = 0;
+		while (!worklist.empty())
+		{
+			auto sink = worklist.pop();
+			if (labels[sink] != -1)
+				continue;
+
+			bool inputs_have_labels = true;
+			for (auto sink_input : edges_bw[sink])
+			{
+				if (labels[sink_input] == -1)
+				{
+					inputs_have_labels = false;
+					break;
+				}
+			}
+			if (!inputs_have_labels)
+				continue;
+
+			if (debug)
+			{
+				debug_num++;
+				log("Examining subgraph %d rooted in %s.\n", debug_num, log_signal(sink));
+			}
+
+			pool<RTLIL::SigBit> subgraph = find_subgraph(sink);
+
+			int p = 1;
+			for (auto subgraph_node : subgraph)
+				p = max(p, labels[subgraph_node]);
+
+			FlowGraph flow_graph = build_flow_graph(sink, p);
+			int flow = flow_graph.maximum_flow(order);
+			pool<RTLIL::SigBit> x, xi;
+			if (flow <= order)
+			{
+				labels[sink] = p;
+				auto cut = flow_graph.edge_cut();
+				x = cut.first;
+				xi = cut.second;
+			}
+			else
+			{
+				labels[sink] = p + 1;
+				x = subgraph;
+				x.erase(sink);
+				xi.insert(sink);
+			}
+			lut_gates[sink] = xi;
+
+			pool<RTLIL::SigBit> k;
+			for (auto xi_node : xi)
+			{
+				for (auto xi_node_pred : edges_bw[xi_node])
+					if (x[xi_node_pred])
+						k.insert(xi_node_pred);
+			}
+			log_assert((int)k.size() <= order);
+			lut_inputs[sink] = k;
+
+			if (debug)
+			{
+				log("  Maximum flow: %d. Assigned label %d.\n", flow, labels[sink]);
+				dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {x, xi});
+				log("  Dumped subgraph to `flowmap-%d-sub.dot`.\n", debug_num);
+				flow_graph.dump_dot_graph(stringf("flowmap-%d-flow.dot", debug_num));
+				log("  Dumped flow graph to `flowmap-%d-flow.dot`.\n", debug_num);
+				log("    LUT packed:");
+				for (auto xi_node : xi)
+					log(" %s", log_signal(xi_node));
+				log(".\n");
+				log("    LUT inputs:");
+				for (auto k_node : k)
+					log(" %s", log_signal(k_node));
+				log(".\n");
+			}
+
+			for (auto sink_succ : edges_fw[sink])
+				worklist.insert(sink_succ);
+		}
+
+		if (debug)
+		{
+			dump_dot_graph("flowmap-done.dot");
+			log("Dumped complete combinatorial graph to `flowmap-done.dot`.\n");
+		}
+
+		int depth = 0;
+		for (auto label : labels)
+			depth = max(depth, label.second);
+		log("Maximum depth: %d levels.\n", depth);
+
+		ConstEval ce(module);
+		for (auto input_node : inputs)
+			ce.stop(input_node);
+
+		log("\n");
+		log("Mapping cells.\n");
+
+		pool<RTLIL::SigBit> mapped_nodes;
+		worklist = outputs;
+		while (!worklist.empty())
+		{
+			auto node = worklist.pop();
+			if (node_origins.count(node))
+			{
+				auto origin = node_origins[node];
+				if (origin.cell->getPort(origin.port).size() == 1)
+					log("Mapping %s.%s.%s (%s).\n",
+					    log_id(module), log_id(origin.cell), origin.port.c_str(), log_signal(node));
+				else
+					log("Mapping %s.%s.%s [%d] (%s).\n",
+					    log_id(module), log_id(origin.cell), origin.port.c_str(), origin.offset, log_signal(node));
+			}
+			else
+			{
+				log("Mapping %s.%s.\n", log_id(module), log_signal(node));
+			}
+
+			for (auto gate_node : lut_gates[node])
+			{
+				log_assert(node_origins.count(gate_node));
+
+				if (gate_node == node)
+					continue;
+
+				auto gate_origin = node_origins[gate_node];
+				if (gate_origin.cell->getPort(gate_origin.port).size() == 1)
+					log("  Packing %s.%s.%s (%s).\n",
+					    log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), log_signal(gate_node));
+				else
+					log("  Packing %s.%s.%s [%d] (%s).\n",
+					    log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
+			}
+
+			vector<RTLIL::SigBit> input_nodes(lut_inputs[node].begin(), lut_inputs[node].end());
+			RTLIL::Const lut_table(State::Sx, 1 << input_nodes.size());
+			for (unsigned i = 0; i < (1 << input_nodes.size()); i++)
+			{
+				ce.push();
+				for (size_t n = 0; n < input_nodes.size(); n++)
+					ce.set(input_nodes[n], ((i >> n) & 1) ? State::S1 : State::S0);
+
+				RTLIL::SigSpec value = node, undef;
+				if (!ce.eval(value, undef))
+				{
+					string env;
+					for (auto input_node : input_nodes)
+						env += stringf("  %s = %s\n", log_signal(input_node), log_signal(ce.values_map(input_node)));
+					log_error("Cannot evaluate %s because %s is not defined.\nEvaluation environment:\n%s",
+					          log_signal(node), log_signal(undef), env.c_str());
+				}
+
+				lut_table[i] = value.as_bool() ? State::S1 : State::S0;
+				ce.pop();
+			}
+
+			RTLIL::SigSpec lut_a, lut_y = node;
+			for (auto input_node : input_nodes)
+				lut_a.append_bit(input_node);
+
+			RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
+			mapped_count++;
+
+			for (auto gate_node : lut_gates[node])
+			{
+				auto gate_origin = node_origins[gate_node];
+				lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src"));
+				packed_count++;
+			}
+
+			log("  Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
+
+			mapped_nodes.insert(node);
+			for (auto input_node : input_nodes)
+			{
+				if (!mapped_nodes[input_node] && !inputs[input_node])
+					worklist.insert(input_node);
+			}
+		}
+
+		unique_packed_count += nodes.size();
+
+		for (auto node : mapped_nodes)
+		{
+			auto origin = node_origins[node];
+			RTLIL::SigSpec driver = origin.cell->getPort(origin.port);
+			driver[origin.offset] = module->addWire(NEW_ID);
+			origin.cell->setPort(origin.port, driver);
+		}
+	}
+};
+
+static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
+{
+	size_t start = 0, end = 0;
+	while ((end = text.find(sep, start)) != std::string::npos) {
+		tokens.push_back(text.substr(start, end - start));
+		start = end + 1;
+	}
+	tokens.push_back(text.substr(start));
+}
+
+struct FlowmapPass : public Pass {
+	FlowmapPass() : Pass("flowmap", "pack LUTs with FlowMap") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    flowmap [options] [selection]\n");
+		log("\n");
+		log("This pass uses the FlowMap technology mapping algorithm to pack logic gates\n");
+		log("into k-LUTs with optimal depth. It allows mapping any circuit elements that can\n");
+		log("be evaluated with the `eval` pass, including cells with multiple output ports\n");
+		log("and multi-bit input and output ports.\n");
+		log("\n");
+		log("    -maxlut <k>\n");
+		log("        perform technology mapping for a k-LUT architecture. if not specified,\n");
+		log("        defaults to 3.\n");
+		log("\n");
+		log("    -cells <cell>[,<cell>,...]\n");
+		log("        map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,\n");
+		log("        $_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.\n");
+		log("\n");
+		log("    -debug\n");
+		log("        dump intermediate graphs.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
+
+		int order = 3;
+		vector<string> cells;
+		bool debug = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-maxlut" && argidx + 1 < args.size())
+			{
+				order = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-cells" && argidx + 1 < args.size())
+			{
+				split(cells, args[++argidx], ',');
+				continue;
+			}
+			if (args[argidx] == "-debug")
+			{
+				debug = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		pool<IdString> cell_types;
+		if (!cells.empty())
+		{
+			for (auto &cell : cells)
+				cell_types.insert(cell);
+		}
+		else
+		{
+			cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"};
+		}
+
+		int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
+		for (auto module : design->selected_modules())
+		{
+			FlowmapWorker worker(order, cell_types, debug, module);
+			mapped_count += worker.mapped_count;
+			packed_count += worker.packed_count;
+			unique_packed_count += worker.unique_packed_count;
+		}
+
+		log("\n");
+		log("Mapped %d LUTs.\n", mapped_count);
+		log("Packed %d cells %d times.\n", unique_packed_count, packed_count);
+	}
+} FlowmapPass;
+
+PRIVATE_NAMESPACE_END

From 7850a0c28a2a2d7761d49e23e139a93e837a3cca Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 4 Jan 2019 02:33:10 +0000
Subject: [PATCH 279/528] flowmap: add link to longer version of paper. NFC.

---
 passes/techmap/flowmap.cc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index cdca78db8..adfb70a69 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -19,7 +19,7 @@
 
 // [[CITE]]
 // Jason Cong; Yuzheng Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,"
-// Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 13, no. 1, Jan 1994
+// Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 13, pp. 1-12, Jan. 1994.
 // doi: 10.1109/43.273754
 
 // Required reading material:
@@ -27,7 +27,8 @@
 // Min-cut max-flow theorem:
 //   https://www.coursera.org/lecture/algorithms-part2/maxflow-mincut-theorem-beb9G
 // FlowMap paper:
-//   http://cadlab.cs.ucla.edu/~cong/papers/iccad92.pdf
+//   http://cadlab.cs.ucla.edu/~cong/papers/iccad92.pdf   (short version)
+//   https://limsk.ece.gatech.edu/book/papers/flowmap.pdf (long version)
 
 // Notes on implementation:
 //

From fd21564deb73c6fe19c5985ae5c168f628f190d6 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 4 Jan 2019 02:46:27 +0000
Subject: [PATCH 280/528] flowmap: improve debug graph output. NFC.

---
 passes/techmap/flowmap.cc | 123 +++++++++++++++++++++++---------------
 1 file changed, 76 insertions(+), 47 deletions(-)

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index adfb70a69..5d6b8b645 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -64,10 +64,10 @@ PRIVATE_NAMESPACE_BEGIN
 struct GraphStyle
 {
 	string label;
-	string color;
+	string color, fillcolor;
 
-	GraphStyle(string label = "", string color = "black") :
-		label(label), color(color) {}
+	GraphStyle(string label = "", string color = "black", string fillcolor = "") :
+		label(label), color(color), fillcolor(fillcolor) {}
 };
 
 static string dot_escape(string value)
@@ -110,13 +110,11 @@ static void dump_dot_graph(string filename,
 		if (outputs[node])
 			shape = "octagon";
 		auto prop = node_style(node);
-		string id;
-		if (node == SigBit())
-			id = "(source)";
-		else
-			id = log_signal(node);
-		fprintf(f, "  n%d [ shape=%s, fontname=\"Monospace\", label=\"%s%s\", color=\"%s\" ];\n",
-		        ids[node], shape.c_str(), dot_escape(id).c_str(), dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
+		string style = "";
+		if (!prop.fillcolor.empty())
+			style = "filled";
+		fprintf(f, "  n%d [ shape=%s, fontname=\"Monospace\", label=\"%s\", color=\"%s\", fillcolor=\"%s\", style=\"%s\" ];\n",
+		        ids[node], shape.c_str(), dot_escape(prop.label.c_str()).c_str(), prop.color.c_str(), prop.fillcolor.c_str(), style.c_str());
 	}
 
 	fprintf(f, "  { rank=\"source\"; ");
@@ -138,8 +136,8 @@ static void dump_dot_graph(string filename,
 			if (nodes[source] && nodes[sink])
 			{
 				auto prop = edge_style(source, sink);
-				fprintf(f, "  n%d -> n%d [ label=\"%s\", color=\"%s\" ];\n",
-				        ids[source], ids[sink], dot_escape(prop.label.c_str()).c_str(), prop.color.c_str());
+				fprintf(f, "  n%d -> n%d [ label=\"%s\", color=\"%s\", fillcolor=\"%s\" ];\n",
+				        ids[source], ids[sink], dot_escape(prop.label.c_str()).c_str(), prop.color.c_str(), prop.fillcolor.c_str());
 			}
 		}
 	}
@@ -164,7 +162,7 @@ struct FlowGraph
 	void dump_dot_graph(string filename)
 	{
 		auto node_style = [&](RTLIL::SigBit node) {
-			string label;
+			string label = (node == source) ? "(source)" : log_signal(node);
 			for (auto collapsed_node : collapsed[node])
 				label += stringf(" %s", log_signal(collapsed_node));
 			int flow = node_flow[node];
@@ -423,28 +421,46 @@ struct FlowmapWorker
 
 	int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
 
-	void dump_dot_graph(string filename, pool<RTLIL::SigBit> subgraph = {}, pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {})
+	void dump_dot_graph(string filename,
+	                    pool<RTLIL::SigBit> subgraph_nodes = {}, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> subgraph_edges = {},
+	                    pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {},
+	                    dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed = {})
 	{
-		if (subgraph.empty())
-			subgraph = nodes;
+		if (subgraph_nodes.empty())
+			subgraph_nodes = nodes;
+		if (subgraph_edges.empty())
+			subgraph_edges = edges_fw;
 
 		auto node_style = [&](RTLIL::SigBit node) {
-			string label, color;
+			string label = log_signal(node);
+			for (auto collapsed_node : collapsed[node])
+				if (collapsed_node != node)
+					label += stringf(" %s", log_signal(collapsed_node));
 			if (labels[node] == -1)
-				label = string("\n<unlabeled>");
+				label += "\nl=?";
 			else
-				label = stringf("\nl=%d", labels[node]);
-			color = "black";
-			if (cut.first[node])
-				color = "blue";
-			if (cut.second[node])
-				color = "red";
-			return GraphStyle{label, color};
+				label += stringf("\nl=%d", labels[node]);
+			if (cut.first.empty() && cut.second.empty())
+			{
+				if (labels[node] == -1)
+					return GraphStyle{label};
+				string fillcolor = stringf("/set311/%d", 1 + labels[node] % 11);
+				return GraphStyle{label, "", fillcolor};
+			}
+			else
+			{
+				string color = "black";
+				if (cut.first[node])
+					color = "blue";
+				if (cut.second[node])
+					color = "red";
+				return GraphStyle{label, color};
+			}
 		};
 		auto edge_style = [&](RTLIL::SigBit, RTLIL::SigBit) {
 			return GraphStyle{};
 		};
-		::dump_dot_graph(filename, subgraph, edges_fw, inputs, outputs, node_style, edge_style, module->name.str());
+		::dump_dot_graph(filename, subgraph_nodes, subgraph_edges, inputs, outputs, node_style, edge_style, module->name.str());
 	}
 
 	pool<RTLIL::SigBit> find_subgraph(RTLIL::SigBit sink)
@@ -582,8 +598,8 @@ struct FlowmapWorker
 
 		if (debug)
 		{
-			dump_dot_graph("flowmap-init.dot");
-			log("Dumped complete combinatorial graph to `flowmap-init.dot`.\n");
+			dump_dot_graph("flowmap-initial.dot");
+			log("Dumped complete initial graph to `flowmap-initial.dot`.\n");
 		}
 
 		pool<RTLIL::SigBit> worklist = nodes;
@@ -650,7 +666,7 @@ struct FlowmapWorker
 			if (debug)
 			{
 				log("  Maximum flow: %d. Assigned label %d.\n", flow, labels[sink]);
-				dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {x, xi});
+				dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {}, {x, xi});
 				log("  Dumped subgraph to `flowmap-%d-sub.dot`.\n", debug_num);
 				flow_graph.dump_dot_graph(stringf("flowmap-%d-flow.dot", debug_num));
 				log("  Dumped flow graph to `flowmap-%d-flow.dot`.\n", debug_num);
@@ -668,17 +684,40 @@ struct FlowmapWorker
 				worklist.insert(sink_succ);
 		}
 
-		if (debug)
-		{
-			dump_dot_graph("flowmap-done.dot");
-			log("Dumped complete combinatorial graph to `flowmap-done.dot`.\n");
-		}
-
 		int depth = 0;
 		for (auto label : labels)
 			depth = max(depth, label.second);
 		log("Maximum depth: %d levels.\n", depth);
 
+		if (debug)
+		{
+			dump_dot_graph("flowmap-labeled.dot");
+			log("Dumped complete labeled graph to `flowmap-labeled.dot`.\n");
+		}
+
+		pool<RTLIL::SigBit> lut_nodes;
+		dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges;
+		worklist = outputs;
+		while (!worklist.empty())
+		{
+			auto lut_node = worklist.pop();
+			lut_nodes.insert(lut_node);
+			for (auto input_node : lut_inputs[lut_node])
+			{
+				lut_edges[input_node].insert(lut_node);
+				if (!lut_nodes[input_node] && !inputs[input_node])
+					worklist.insert(input_node);
+			}
+		}
+
+		if (debug)
+		{
+			pool<RTLIL::SigBit> lut_and_input_nodes = lut_nodes;
+			lut_and_input_nodes.insert(inputs.begin(), inputs.end());
+			dump_dot_graph("flowmap-packed.dot", lut_and_input_nodes, lut_edges, {}, lut_gates);
+			log("Dumped complete packed graph to `flowmap-packed.dot`.\n");
+		}
+
 		ConstEval ce(module);
 		for (auto input_node : inputs)
 			ce.stop(input_node);
@@ -687,10 +726,8 @@ struct FlowmapWorker
 		log("Mapping cells.\n");
 
 		pool<RTLIL::SigBit> mapped_nodes;
-		worklist = outputs;
-		while (!worklist.empty())
+		for (auto node : lut_nodes)
 		{
-			auto node = worklist.pop();
 			if (node_origins.count(node))
 			{
 				auto origin = node_origins[node];
@@ -750,22 +787,14 @@ struct FlowmapWorker
 
 			RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
 			mapped_count++;
-
+			mapped_nodes.insert(node);
 			for (auto gate_node : lut_gates[node])
 			{
 				auto gate_origin = node_origins[gate_node];
 				lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src"));
 				packed_count++;
 			}
-
 			log("  Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
-
-			mapped_nodes.insert(node);
-			for (auto input_node : input_nodes)
-			{
-				if (!mapped_nodes[input_node] && !inputs[input_node])
-					worklist.insert(input_node);
-			}
 		}
 
 		unique_packed_count += nodes.size();

From 3b17c9018acd9d8bee12e653745fb2f00105bd58 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Jan 2019 11:37:25 +0100
Subject: [PATCH 281/528] Unify usage of noflatten among architectures

---
 techlibs/achronix/synth_achronix.cc       |  4 ++--
 techlibs/coolrunner2/synth_coolrunner2.cc |  2 +-
 techlibs/gowin/synth_gowin.cc             | 14 +++++++++++---
 techlibs/intel/synth_intel.cc             |  4 ++--
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 3642e3bd3..626860d9c 100755
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -95,8 +95,8 @@ struct SynthAchronixPass : public ScriptPass {
           run_to = args[argidx].substr(pos+1);
           continue;
         }
-        if (args[argidx] == "-flatten") {
-          flatten = true;
+        if (args[argidx] == "-noflatten") {
+          flatten = false;
           continue;
         }
         if (args[argidx] == "-retime") {
diff --git a/techlibs/coolrunner2/synth_coolrunner2.cc b/techlibs/coolrunner2/synth_coolrunner2.cc
index 810380d4a..21bbcaef4 100644
--- a/techlibs/coolrunner2/synth_coolrunner2.cc
+++ b/techlibs/coolrunner2/synth_coolrunner2.cc
@@ -129,7 +129,7 @@ struct SynthCoolrunner2Pass : public ScriptPass
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (check_label("flatten", "(unless -noflatten)") && flatten)
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
 		{
 			run("proc");
 			run("flatten");
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 9700b3898..96128a680 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -52,6 +52,9 @@ struct SynthGowinPass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use BRAM cells in output netlist\n");
 		log("\n");
+		log("    -noflatten\n");
+		log("        do not flatten design before synthesis\n");
+		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
@@ -62,14 +65,15 @@ struct SynthGowinPass : public ScriptPass
 	}
 
 	string top_opt, vout_file;
-	bool retime, nobram;
+	bool retime, flatten, nobram;
 
 	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		vout_file = "";
 		retime = false;
-                nobram = true;
+		flatten = true;
+		nobram = true;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -104,6 +108,10 @@ struct SynthGowinPass : public ScriptPass
 				nobram = true;
 				continue;
 			}
+			if (args[argidx] == "-noflatten") {
+				flatten = false;
+				continue;
+			}			
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -127,7 +135,7 @@ struct SynthGowinPass : public ScriptPass
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
-		if (check_label("flatten") && check_label("flatten", "(unless -noflatten)"))
+		if (flatten && check_label("flatten", "(unless -noflatten)"))
 		{
 			run("proc");
 			run("flatten");
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index d74f295ec..0f1d7a7b5 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -131,8 +131,8 @@ struct SynthIntelPass : public ScriptPass {
           nobram = true;
           continue;
         }
-        if (args[argidx] == "-flatten") {
-          flatten = true;
+        if (args[argidx] == "-noflatten") {
+          flatten = false;
           continue;
         }
         if (args[argidx] == "-retime") {

From 9bc5cf08440188fa3dab1115f10a0859ee2c7252 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 4 Jan 2019 04:54:20 +0000
Subject: [PATCH 282/528] flowmap: cleanup for clarity. NFCI.

---
 passes/techmap/flowmap.cc    | 260 ++++++++++++++++++++---------------
 passes/tests/flowmap/flow.v  |  22 +++
 passes/tests/flowmap/flowp.v |  16 +++
 3 files changed, 185 insertions(+), 113 deletions(-)
 create mode 100644 passes/tests/flowmap/flow.v
 create mode 100644 passes/tests/flowmap/flowp.v

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index 5d6b8b645..1b53de4db 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -402,29 +402,34 @@ struct FlowGraph
 struct FlowmapWorker
 {
 	int order;
-	pool<IdString> cell_types;
 	bool debug;
 
 	RTLIL::Module *module;
 	SigMap sigmap;
 	ModIndex index;
-	pool<RTLIL::Cell*> cells;
+
+	dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
 
 	pool<RTLIL::SigBit> nodes, inputs, outputs;
 	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
 	dict<RTLIL::SigBit, int> labels;
 
-	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates, lut_inputs;
+	pool<RTLIL::SigBit> lut_nodes;
+	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates;
+	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges_fw, lut_edges_bw;
 
-	dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
-	dict<RTLIL::Cell*, pool<RTLIL::SigBit>> cell_fanout;
+	int gate_count = 0, lut_count = 0, packed_count = 0;
+	int gate_area = 0, lut_area = 0;
 
-	int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
+	enum class GraphMode {
+		Label,
+		Cut,
+	};
 
-	void dump_dot_graph(string filename,
+	void dump_dot_graph(string filename, GraphMode mode,
 	                    pool<RTLIL::SigBit> subgraph_nodes = {}, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> subgraph_edges = {},
-	                    pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {},
-	                    dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed = {})
+	                    dict<RTLIL::SigBit, pool<RTLIL::SigBit>> collapsed = {},
+	                    pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut = {})
 	{
 		if (subgraph_nodes.empty())
 			subgraph_nodes = nodes;
@@ -436,26 +441,29 @@ struct FlowmapWorker
 			for (auto collapsed_node : collapsed[node])
 				if (collapsed_node != node)
 					label += stringf(" %s", log_signal(collapsed_node));
-			if (labels[node] == -1)
-				label += "\nl=?";
-			else
-				label += stringf("\nl=%d", labels[node]);
-			if (cut.first.empty() && cut.second.empty())
+			switch (mode)
 			{
-				if (labels[node] == -1)
+				case GraphMode::Label:
+					if (labels[node] == -1)
+					{
+						label += "\nl=?";
+						return GraphStyle{label};
+					}
+					else
+					{
+						label += stringf("\nl=%d", labels[node]);
+						string fillcolor = stringf("/set311/%d", 1 + labels[node] % 11);
+						return GraphStyle{label, "", fillcolor};
+					}
+
+				case GraphMode::Cut:
+					if (cut.first[node])
+						return GraphStyle{label, "blue"};
+					if (cut.second[node])
+						return GraphStyle{label, "red"};
 					return GraphStyle{label};
-				string fillcolor = stringf("/set311/%d", 1 + labels[node] % 11);
-				return GraphStyle{label, "", fillcolor};
-			}
-			else
-			{
-				string color = "black";
-				if (cut.first[node])
-					color = "blue";
-				if (cut.second[node])
-					color = "red";
-				return GraphStyle{label, color};
 			}
+			return GraphStyle{label};
 		};
 		auto edge_style = [&](RTLIL::SigBit, RTLIL::SigBit) {
 			return GraphStyle{};
@@ -519,57 +527,56 @@ struct FlowmapWorker
 		return flow_graph;
 	}
 
-	FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
-		order(order), cell_types(cell_types), debug(debug), module(module), sigmap(module), index(module)
+	void discover_nodes(pool<IdString> cell_types)
 	{
-		log("Labeling cells.\n");
 		for (auto cell : module->selected_cells())
 		{
-			if (cell_types[cell->type])
+			if (!cell_types[cell->type])
+				continue;
+
+			if (!cell->known())
+				log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
+
+			pool<RTLIL::SigBit> fanout;
+			for (auto conn : cell->connections())
 			{
-				if (!cell->known())
+				if (!cell->output(conn.first)) continue;
+				int offset = -1;
+				for (auto bit : conn.second)
 				{
-					log_error("Cell %s (%s.%s) is unknown.\n", cell->type.c_str(), log_id(module), log_id(cell));
+					offset++;
+					if (!bit.wire) continue;
+					auto mapped_bit = sigmap(bit);
+					if (nodes[mapped_bit])
+						log_error("Multiple drivers found for wire %s.\n", log_signal(mapped_bit));
+					nodes.insert(mapped_bit);
+					node_origins[mapped_bit] = ModIndex::PortInfo(cell, conn.first, offset);
+					fanout.insert(mapped_bit);
 				}
-				cells.insert(cell);
-
-				for (auto conn : cell->connections())
-				{
-					if (!cell->output(conn.first)) continue;
-					int offset = -1;
-					for (auto bit : conn.second)
-					{
-						offset++;
-						if (!bit.wire) continue;
-						auto mapped_bit = sigmap(bit);
-						if (nodes[mapped_bit])
-							log_error("Multiple drivers found for wire %s.\n", log_signal(mapped_bit));
-						nodes.insert(mapped_bit);
-						node_origins[mapped_bit] = ModIndex::PortInfo(cell, conn.first, offset);
-						cell_fanout[cell].insert(mapped_bit);
-					}
-				}
-
-				int fanin = 0;
-				for (auto conn : cell->connections())
-				{
-					if (!cell->input(conn.first)) continue;
-					for (auto bit : sigmap(conn.second))
-					{
-						if (!bit.wire) continue;
-						for (auto fanout_bit : cell_fanout[cell])
-						{
-							edges_fw[bit].insert(fanout_bit);
-							edges_bw[fanout_bit].insert(bit);
-						}
-						fanin++;
-					}
-				}
-
-				if (fanin > order)
-					log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
-					          cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
 			}
+
+			int fanin = 0;
+			for (auto conn : cell->connections())
+			{
+				if (!cell->input(conn.first)) continue;
+				for (auto bit : sigmap(conn.second))
+				{
+					if (!bit.wire) continue;
+					for (auto fanout_bit : fanout)
+					{
+						edges_fw[bit].insert(fanout_bit);
+						edges_bw[fanout_bit].insert(bit);
+					}
+					fanin++;
+				}
+			}
+
+			if (fanin > order)
+				log_error("Cell %s (%s.%s) with fan-in %d cannot be mapped to a %d-LUT.\n",
+				          cell->type.c_str(), log_id(module), log_id(cell), fanin, order);
+
+			gate_count++;
+			gate_area += 1 << fanin;
 		}
 
 		for (auto edge : edges_fw)
@@ -591,15 +598,23 @@ struct FlowmapWorker
 					outputs.insert(node);
 		}
 
+		if (debug)
+		{
+			dump_dot_graph("flowmap-initial.dot", GraphMode::Label);
+			log("Dumped initial graph to `flowmap-initial.dot`.\n");
+		}
+	}
+
+	void label_nodes()
+	{
 		for (auto node : nodes)
 			labels[node] = -1;
 		for (auto input : inputs)
-			labels[input] = 0;
-
-		if (debug)
 		{
-			dump_dot_graph("flowmap-initial.dot");
-			log("Dumped complete initial graph to `flowmap-initial.dot`.\n");
+			if (input.wire->attributes.count("\\$flowmap_level"))
+				labels[input] = input.wire->attributes["\\$flowmap_level"].as_int();
+			else
+				labels[input] = 0;
 		}
 
 		pool<RTLIL::SigBit> worklist = nodes;
@@ -661,70 +676,73 @@ struct FlowmapWorker
 						k.insert(xi_node_pred);
 			}
 			log_assert((int)k.size() <= order);
-			lut_inputs[sink] = k;
+			lut_edges_bw[sink] = k;
+			for (auto k_node : k)
+				lut_edges_fw[k_node].insert(sink);
 
 			if (debug)
 			{
 				log("  Maximum flow: %d. Assigned label %d.\n", flow, labels[sink]);
-				dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), subgraph, {}, {x, xi});
+				dump_dot_graph(stringf("flowmap-%d-sub.dot", debug_num), GraphMode::Cut, subgraph, {}, {}, {x, xi});
 				log("  Dumped subgraph to `flowmap-%d-sub.dot`.\n", debug_num);
 				flow_graph.dump_dot_graph(stringf("flowmap-%d-flow.dot", debug_num));
 				log("  Dumped flow graph to `flowmap-%d-flow.dot`.\n", debug_num);
-				log("    LUT packed:");
-				for (auto xi_node : xi)
-					log(" %s", log_signal(xi_node));
-				log(".\n");
 				log("    LUT inputs:");
 				for (auto k_node : k)
 					log(" %s", log_signal(k_node));
 				log(".\n");
+				log("    LUT packed gates:");
+				for (auto xi_node : xi)
+					log(" %s", log_signal(xi_node));
+				log(".\n");
 			}
 
 			for (auto sink_succ : edges_fw[sink])
 				worklist.insert(sink_succ);
 		}
 
-		int depth = 0;
-		for (auto label : labels)
-			depth = max(depth, label.second);
-		log("Maximum depth: %d levels.\n", depth);
-
 		if (debug)
 		{
-			dump_dot_graph("flowmap-labeled.dot");
-			log("Dumped complete labeled graph to `flowmap-labeled.dot`.\n");
+			dump_dot_graph("flowmap-labeled.dot", GraphMode::Label);
+			log("Dumped labeled graph to `flowmap-labeled.dot`.\n");
 		}
+	}
 
-		pool<RTLIL::SigBit> lut_nodes;
-		dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges;
-		worklist = outputs;
+	int pack_luts()
+	{
+		pool<RTLIL::SigBit> worklist = outputs;
 		while (!worklist.empty())
 		{
 			auto lut_node = worklist.pop();
 			lut_nodes.insert(lut_node);
-			for (auto input_node : lut_inputs[lut_node])
-			{
-				lut_edges[input_node].insert(lut_node);
+			for (auto input_node : lut_edges_bw[lut_node])
 				if (!lut_nodes[input_node] && !inputs[input_node])
 					worklist.insert(input_node);
-			}
 		}
 
+		int depth = 0;
+		for (auto label : labels)
+			depth = max(depth, label.second);
+		log("Solved to %d LUTs in %d levels.\n", (int)lut_nodes.size(), depth);
+
 		if (debug)
 		{
-			pool<RTLIL::SigBit> lut_and_input_nodes = lut_nodes;
+			pool<RTLIL::SigBit> lut_and_input_nodes;
+			lut_and_input_nodes.insert(lut_nodes.begin(), lut_nodes.end());
 			lut_and_input_nodes.insert(inputs.begin(), inputs.end());
-			dump_dot_graph("flowmap-packed.dot", lut_and_input_nodes, lut_edges, {}, lut_gates);
-			log("Dumped complete packed graph to `flowmap-packed.dot`.\n");
+			dump_dot_graph("flowmap-packed.dot", GraphMode::Label, lut_and_input_nodes, lut_edges_fw, lut_gates);
+			log("Dumped packed graph to `flowmap-packed.dot`.\n");
 		}
 
+		return depth;
+	}
+
+	void map_cells()
+	{
 		ConstEval ce(module);
 		for (auto input_node : inputs)
 			ce.stop(input_node);
 
-		log("\n");
-		log("Mapping cells.\n");
-
 		pool<RTLIL::SigBit> mapped_nodes;
 		for (auto node : lut_nodes)
 		{
@@ -759,7 +777,7 @@ struct FlowmapWorker
 					    log_id(module), log_id(gate_origin.cell), gate_origin.port.c_str(), gate_origin.offset, log_signal(gate_node));
 			}
 
-			vector<RTLIL::SigBit> input_nodes(lut_inputs[node].begin(), lut_inputs[node].end());
+			vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
 			RTLIL::Const lut_table(State::Sx, 1 << input_nodes.size());
 			for (unsigned i = 0; i < (1 << input_nodes.size()); i++)
 			{
@@ -786,7 +804,6 @@ struct FlowmapWorker
 				lut_a.append_bit(input_node);
 
 			RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
-			mapped_count++;
 			mapped_nodes.insert(node);
 			for (auto gate_node : lut_gates[node])
 			{
@@ -794,11 +811,11 @@ struct FlowmapWorker
 				lut->add_strpool_attribute("\\src", gate_origin.cell->get_strpool_attribute("\\src"));
 				packed_count++;
 			}
+			lut_count++;
+			lut_area += 1 << input_nodes.size();
 			log("  Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
 		}
 
-		unique_packed_count += nodes.size();
-
 		for (auto node : mapped_nodes)
 		{
 			auto origin = node_origins[node];
@@ -807,6 +824,19 @@ struct FlowmapWorker
 			origin.cell->setPort(origin.port, driver);
 		}
 	}
+
+	FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
+		order(order), debug(debug), module(module), sigmap(module), index(module)
+	{
+		log("Labeling cells.\n");
+		discover_nodes(cell_types);
+		label_nodes();
+		pack_luts();
+
+		log("\n");
+		log("Mapping cells.\n");
+		map_cells();
+	}
 };
 
 static void split(std::vector<std::string> &tokens, const std::string &text, char sep)
@@ -832,7 +862,7 @@ struct FlowmapPass : public Pass {
 		log("be evaluated with the `eval` pass, including cells with multiple output ports\n");
 		log("and multi-bit input and output ports.\n");
 		log("\n");
-		log("    -maxlut <k>\n");
+		log("    -maxlut k\n");
 		log("        perform technology mapping for a k-LUT architecture. if not specified,\n");
 		log("        defaults to 3.\n");
 		log("\n");
@@ -846,8 +876,6 @@ struct FlowmapPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
-
 		int order = 3;
 		vector<string> cells;
 		bool debug = false;
@@ -885,18 +913,24 @@ struct FlowmapPass : public Pass {
 			cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"};
 		}
 
-		int mapped_count = 0, packed_count = 0, unique_packed_count = 0;
+		log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
+
+		int gate_count = 0, lut_count = 0, packed_count = 0;
+		int gate_area = 0, lut_area = 0;
 		for (auto module : design->selected_modules())
 		{
 			FlowmapWorker worker(order, cell_types, debug, module);
-			mapped_count += worker.mapped_count;
+			gate_count += worker.gate_count;
+			lut_count += worker.lut_count;
 			packed_count += worker.packed_count;
-			unique_packed_count += worker.unique_packed_count;
+			gate_area += worker.gate_area;
+			lut_area += worker.lut_area;
 		}
 
 		log("\n");
-		log("Mapped %d LUTs.\n", mapped_count);
-		log("Packed %d cells %d times.\n", unique_packed_count, packed_count);
+		log("Mapped %d LUTs.\n", lut_count);
+		log("Packed %d cells; duplicated %d cells.\n", packed_count, packed_count - gate_count);
+		log("Solution has %.1f%% area overhead.\n", (lut_area - gate_area) * 100.0 / gate_area);
 	}
 } FlowmapPass;
 
diff --git a/passes/tests/flowmap/flow.v b/passes/tests/flowmap/flow.v
new file mode 100644
index 000000000..297ef910e
--- /dev/null
+++ b/passes/tests/flowmap/flow.v
@@ -0,0 +1,22 @@
+// Exact reproduction of Figure 2(a) from 10.1109/43.273754.
+module top(...);
+	input a,b,c,d,e,f;
+	wire nA = b&c;
+	wire A = !nA;
+	wire nB = c|d;
+	wire B = !nB;
+	wire nC = e&f;
+	wire C = !nC;
+	wire D = A|B;
+	wire E = a&D;
+	wire nF = D&C;
+	wire F = !nF;
+	wire nG = F|B;
+	wire G = !nG;
+	wire H = a&F;
+	wire I = E|G;
+	wire J = G&C;
+	wire np = H&I;
+	output p = !np;
+	output q = A|J;
+endmodule
diff --git a/passes/tests/flowmap/flowp.v b/passes/tests/flowmap/flowp.v
new file mode 100644
index 000000000..2fb40ffa4
--- /dev/null
+++ b/passes/tests/flowmap/flowp.v
@@ -0,0 +1,16 @@
+// Like flow.v, but results in a network identical to Figure 2(b).
+module top(...);
+	input a,b,c,d,e,f;
+	wire A = b&c;
+	wire B = c|d;
+	wire C = e&f;
+	wire D = A|B;
+	wire E = a&D;
+	wire F = D&C;
+	wire G = F|B;
+	wire H = a&F;
+	wire I = E|G;
+	wire J = G&C;
+	output p = H&I;
+	output q = A|J;
+endmodule

From f5d23d4c7af33f73b1d9250e458b0932ff7a965b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 4 Jan 2019 14:44:35 +0100
Subject: [PATCH 283/528] Update Verific default path

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 128539f6a..d83a71256 100644
--- a/Makefile
+++ b/Makefile
@@ -357,7 +357,7 @@ endif
 endif
 
 ifeq ($(ENABLE_VERIFIC),1)
-VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
+VERIFIC_DIR ?= /usr/local/src/verific_lib
 VERIFIC_COMPONENTS ?= verilog vhdl database util containers hier_tree
 CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
 ifeq ($(OS), Darwin)

From 6d1e7e9403c81289492af889922df9aa3e3842b0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 4 Jan 2019 15:03:29 +0100
Subject: [PATCH 284/528] Remove -m32 Verific eval lib build instructions

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/README | 29 -----------------------------
 1 file changed, 29 deletions(-)

diff --git a/frontends/verific/README b/frontends/verific/README
index b4c436a3a..c76cdd637 100644
--- a/frontends/verific/README
+++ b/frontends/verific/README
@@ -4,35 +4,6 @@ This directory contains Verific bindings for Yosys.
 See http://www.verific.com/ for details.
 
 
-Building Yosys with the 32 bit Verific eval library on amd64:
-=============================================================
-
-1.) Use a Makefile.conf like the following one:
-
---snip--
-CONFIG := gcc
-ENABLE_TCL := 0
-ENABLE_PLUGINS := 0
-ENABLE_VERIFIC := 1
-CXXFLAGS += -m32
-LDFLAGS += -m32
-VERIFIC_DIR = /usr/local/src/verific_lib_eval
---snap--
-
-
-2.) Install the necessary multilib packages
-
-Hint: On debian/ubuntu the multilib packages have names such as
-libreadline-dev:i386 or lib32readline6-dev, depending on the
-exact version of debian/ubuntu you are working with.
-
-
-3.) Build and test
-
-make -j8
-./yosys -p 'verific -sv frontends/verific/example.sv; verific -import top'
-
-
 Verific Features that should be enabled in your Verific library
 ===============================================================
 

From 50ef4561d49a471162799fd1f2cd42af408c0b73 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Jan 2019 15:15:23 +0100
Subject: [PATCH 285/528] Fix cells_sim.v for Achronix FPGA

---
 techlibs/achronix/speedster22i/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index da23fed7e..a94dce9b1 100755
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -61,7 +61,7 @@ reg [1:0]   s1;
   end
 endfunction
 
-always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
+always @(dataa_w or datab_w or datac_w or datad_w) begin
    combout_rt = lut_data(lut_function, dataa_w, datab_w,
                          datac_w, datad_w);
 end

From 2fcc1ee72edc4f94b4065696def810b38e503656 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 4 Jan 2019 21:18:03 +0000
Subject: [PATCH 286/528] flowmap: add -minlut option, to allow postprocessing
 with opt_lut.

---
 passes/techmap/flowmap.cc | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index 1b53de4db..8c127cb65 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -737,7 +737,7 @@ struct FlowmapWorker
 		return depth;
 	}
 
-	void map_cells()
+	void map_cells(int minlut)
 	{
 		ConstEval ce(module);
 		for (auto input_node : inputs)
@@ -778,7 +778,7 @@ struct FlowmapWorker
 			}
 
 			vector<RTLIL::SigBit> input_nodes(lut_edges_bw[node].begin(), lut_edges_bw[node].end());
-			RTLIL::Const lut_table(State::Sx, 1 << input_nodes.size());
+			RTLIL::Const lut_table(State::Sx, max(1 << input_nodes.size(), 1 << minlut));
 			for (unsigned i = 0; i < (1 << input_nodes.size()); i++)
 			{
 				ce.push();
@@ -802,6 +802,7 @@ struct FlowmapWorker
 			RTLIL::SigSpec lut_a, lut_y = node;
 			for (auto input_node : input_nodes)
 				lut_a.append_bit(input_node);
+			lut_a.append(RTLIL::Const(State::Sx, minlut - input_nodes.size()));
 
 			RTLIL::Cell *lut = module->addLut(NEW_ID, lut_a, lut_y, lut_table);
 			mapped_nodes.insert(node);
@@ -812,8 +813,12 @@ struct FlowmapWorker
 				packed_count++;
 			}
 			lut_count++;
-			lut_area += 1 << input_nodes.size();
-			log("  Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
+			lut_area += lut_table.size();
+
+			if ((int)input_nodes.size() >= minlut)
+				log("  Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
+			else
+				log("  Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", (int)input_nodes.size(), log_id(module), log_id(lut), minlut);
 		}
 
 		for (auto node : mapped_nodes)
@@ -825,7 +830,7 @@ struct FlowmapWorker
 		}
 	}
 
-	FlowmapWorker(int order, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
+	FlowmapWorker(int order, int minlut, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
 		order(order), debug(debug), module(module), sigmap(module), index(module)
 	{
 		log("Labeling cells.\n");
@@ -835,7 +840,7 @@ struct FlowmapWorker
 
 		log("\n");
 		log("Mapping cells.\n");
-		map_cells();
+		map_cells(minlut);
 	}
 };
 
@@ -866,6 +871,9 @@ struct FlowmapPass : public Pass {
 		log("        perform technology mapping for a k-LUT architecture. if not specified,\n");
 		log("        defaults to 3.\n");
 		log("\n");
+		log("    -minlut n\n");
+		log("        only produce n-input or larger LUTs. if not specified, defaults to 1.\n");
+		log("\n");
 		log("    -cells <cell>[,<cell>,...]\n");
 		log("        map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,\n");
 		log("        $_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.\n");
@@ -877,6 +885,7 @@ struct FlowmapPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		int order = 3;
+		int minlut = 1;
 		vector<string> cells;
 		bool debug = false;
 
@@ -888,6 +897,11 @@ struct FlowmapPass : public Pass {
 				order = atoi(args[++argidx].c_str());
 				continue;
 			}
+			if (args[argidx] == "-minlut" && argidx + 1 < args.size())
+			{
+				minlut = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-cells" && argidx + 1 < args.size())
 			{
 				split(cells, args[++argidx], ',');
@@ -919,7 +933,7 @@ struct FlowmapPass : public Pass {
 		int gate_area = 0, lut_area = 0;
 		for (auto module : design->selected_modules())
 		{
-			FlowmapWorker worker(order, cell_types, debug, module);
+			FlowmapWorker worker(order, minlut, cell_types, debug, module);
 			gate_count += worker.gate_count;
 			lut_count += worker.lut_count;
 			packed_count += worker.packed_count;

From 17ceab92a93f5d2ef0eb26f3fd04df65e4393f9f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 5 Jan 2019 12:10:24 +0100
Subject: [PATCH 287/528] Bugfix in Verilog string handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index f9118e142..1b1873e24 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -274,7 +274,7 @@ YOSYS_NAMESPACE_END
 		yystr[j++] = yystr[i++];
 	}
 	yystr[j] = 0;
-	frontend_verilog_yylval.string = new std::string(yystr);
+	frontend_verilog_yylval.string = new std::string(yystr, j);
 	free(yystr);
 	return TOK_STRING;
 }

From f589ce86bac3169281a077248af328f6758ff0eb Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 5 Jan 2019 17:02:01 +0100
Subject: [PATCH 288/528] Add skeleton Yosys-Libero igloo2 example project

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore |  2 ++
 examples/igloo2/example.v  | 22 ++++++++++++++++++++++
 examples/igloo2/example.ys |  2 ++
 examples/igloo2/libero.sh  |  4 ++++
 examples/igloo2/libero.tcl | 14 ++++++++++++++
 5 files changed, 44 insertions(+)
 create mode 100644 examples/igloo2/.gitignore
 create mode 100644 examples/igloo2/example.v
 create mode 100644 examples/igloo2/example.ys
 create mode 100644 examples/igloo2/libero.sh
 create mode 100644 examples/igloo2/libero.tcl

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
new file mode 100644
index 000000000..ae86e69cc
--- /dev/null
+++ b/examples/igloo2/.gitignore
@@ -0,0 +1,2 @@
+/example.edn
+/work
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
new file mode 100644
index 000000000..3eb7007c5
--- /dev/null
+++ b/examples/igloo2/example.v
@@ -0,0 +1,22 @@
+module top (
+	input  clk,
+	output LED1,
+	output LED2,
+	output LED3,
+	output LED4,
+	output LED5
+);
+
+	localparam BITS = 5;
+	localparam LOG2DELAY = 22;
+
+	reg [BITS+LOG2DELAY-1:0] counter = 0;
+	reg [BITS-1:0] outcnt;
+
+	always @(posedge clk) begin
+		counter <= counter + 1;
+		outcnt <= counter >> LOG2DELAY;
+	end
+
+	assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+endmodule
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
new file mode 100644
index 000000000..75a305d86
--- /dev/null
+++ b/examples/igloo2/example.ys
@@ -0,0 +1,2 @@
+read_verilog example.v
+synth_sf2 -top top -edif example.edn
diff --git a/examples/igloo2/libero.sh b/examples/igloo2/libero.sh
new file mode 100644
index 000000000..582f6ccb9
--- /dev/null
+++ b/examples/igloo2/libero.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+set -ex
+rm -rf work
+LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
new file mode 100644
index 000000000..cc1ab2403
--- /dev/null
+++ b/examples/igloo2/libero.tcl
@@ -0,0 +1,14 @@
+# Run with "libero SCRIPT:libero.tcl"
+
+new_project \
+    -name top \
+    -location work \
+    -family IGLOO2 \
+    -die PA4MGL500 \
+    -package tq144 \
+    -speed -1 \
+    -hdl VERILOG
+
+import_files -edif {example.edn}
+run_tool –name {COMPILE}
+run_tool –name {PLACEROUTEN}

From 62c90c4e171493afe0543ae269811a9ad2848802 Mon Sep 17 00:00:00 2001
From: Scott Mansell <phiren@gmail.com>
Date: Sun, 6 Jan 2019 14:40:10 +1300
Subject: [PATCH 289/528] Rename cells based on the wires they drive.

---
 passes/cmds/rename.cc | 66 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 4b4af0a40..698ce7235 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -61,6 +61,42 @@ static std::string derive_name_from_src(const std::string &src, int counter)
 		return stringf("\\%s$%d", src_base.c_str(), counter);
 }
 
+static IdString derive_name_from_wire(const RTLIL::Cell &cell)
+{
+	// Find output
+	const SigSpec *output = nullptr;
+	int num_outputs = 0;
+	for (auto &connection : cell.connections()) {
+		if (cell.output(connection.first)) {
+			output = &connection.second;
+			num_outputs++;
+		}
+	}
+
+	if (num_outputs != 1) // Skip cells thad drive multiple outputs
+		return cell.name;
+
+	std::string name = "";
+	for (auto &chunk : output->chunks()) {
+		// Skip cells that drive privately named wires
+		if (!chunk.wire || chunk.wire->name.str()[0] == '$')
+			return cell.name;
+
+		if (name != "")
+			name += "$";
+
+		name += chunk.wire->name.str();
+		if (chunk.wire->width != chunk.width) {
+			name += "[";
+			if (chunk.width != 1)
+				name += std::to_string(chunk.offset + chunk.width) + ":";
+			name += std::to_string(chunk.offset) + "]";
+		}
+	}
+
+	return name + cell.type.str();
+}
+
 struct RenamePass : public Pass {
 	RenamePass() : Pass("rename", "rename object in the design") { }
 	void help() YS_OVERRIDE
@@ -77,6 +113,10 @@ struct RenamePass : public Pass {
 		log("Assign names auto-generated from the src attribute to all selected wires and\n");
 		log("cells with private names.\n");
 		log("\n");
+		log("    rename -wire [selection]\n");
+		log("Assign auto-generated names based on the wires they drive to all selected\n");
+		log("cells with private names. Ignores cells driving privatly named wires.\n");
+		log("\n");
 		log("    rename -enumerate [-pattern <pattern>] [selection]\n");
 		log("\n");
 		log("Assign short auto-generated names to all selected wires and cells with private\n");
@@ -98,6 +138,7 @@ struct RenamePass : public Pass {
 	{
 		std::string pattern_prefix = "_", pattern_suffix = "_";
 		bool flag_src = false;
+		bool flag_wire = false;
 		bool flag_enumerate = false;
 		bool flag_hide = false;
 		bool flag_top = false;
@@ -112,6 +153,11 @@ struct RenamePass : public Pass {
 				got_mode = true;
 				continue;
 			}
+			if (arg == "-wire" && !got_mode) {
+				flag_wire = true;
+				got_mode = true;
+				continue;
+			}
 			if (arg == "-enumerate" && !got_mode) {
 				flag_enumerate = true;
 				got_mode = true;
@@ -167,6 +213,26 @@ struct RenamePass : public Pass {
 			}
 		}
 		else
+		if (flag_wire)
+		{
+			extra_args(args, argidx, design);
+
+			for (auto &mod : design->modules_)
+			{
+				RTLIL::Module *module = mod.second;
+				if (!design->selected(module))
+					continue;
+
+				dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				for (auto &it : module->cells_) {
+					if (it.first[0] == '$' && design->selected(module, it.second))
+						it.second->name = derive_name_from_wire(*it.second);
+					new_cells[it.second->name] = it.second;
+				}
+				module->cells_.swap(new_cells);
+			}
+		}
+		else
 		if (flag_enumerate)
 		{
 			extra_args(args, argidx, design);

From 8b44198e2366d304880e810ceee5975263db6aca Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 6 Jan 2019 19:51:37 +0000
Subject: [PATCH 290/528] flowmap: construct a max-volume max-flow min-cut, not
 just any one.

---
 passes/techmap/flowmap.cc | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index 8c127cb65..be70b579b 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -51,7 +51,8 @@
 // 3. The paper ambiguously states: "Moreover, we can find such a cut (X′′, X̅′′) by performing a depth first search starting at the source s,
 // and including in X′′ all the nodes which are reachable from s." This actually refers to a specific kind of search, mincut computation.
 // Mincut computation involves computing the set of nodes reachable from s by an undirected path with no full (i.e. zero capacity) forward
-// edges or empty (i.e. no flow) backward edges.
+// edges or empty (i.e. no flow) backward edges. In addition, the depth first search is required to compute a max-volume max-flow min-cut
+// specifically, because a max-flow min-cut is not, in general, unique.
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
@@ -356,10 +357,12 @@ struct FlowGraph
 
 		NodePrime source_prime = {source, true};
 		NodePrime sink_prime = {sink, false};
-		pool<NodePrime> worklist = {source_prime}, visited;
+		pool<NodePrime> visited;
+		vector<NodePrime> worklist = {source_prime};
 		while (!worklist.empty())
 		{
-			auto node_prime = worklist.pop();
+			auto node_prime = worklist.back();
+			worklist.pop_back();
 			if (visited[node_prime])
 				continue;
 			visited.insert(node_prime);
@@ -372,18 +375,18 @@ struct FlowGraph
 			if (!node_prime.is_bottom) // top
 			{
 				if (node_flow[node_prime.node] < MAX_NODE_FLOW)
-					worklist.insert(node_prime.as_bottom());
+					worklist.push_back(node_prime.as_bottom());
 				for (auto node_pred : edges_bw[node_prime.node])
 					if (edge_flow[{node_pred, node_prime.node}] > 0)
-						worklist.insert(NodePrime::bottom(node_pred));
+						worklist.push_back(NodePrime::bottom(node_pred));
 			}
 			else // bottom
 			{
 				if (node_flow[node_prime.node] > 0)
-					worklist.insert(node_prime.as_top());
+					worklist.push_back(node_prime.as_top());
 				for (auto node_succ : edges_fw[node_prime.node])
 					if (true /* edge_flow[...] < ∞ */)
-						worklist.insert(NodePrime::top(node_succ));
+						worklist.push_back(NodePrime::top(node_succ));
 			}
 		}
 

From a342d6db49b812efa1457f39dc9713bcda3d54ce Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 7 Jan 2019 00:11:49 +0000
Subject: [PATCH 291/528] bugpoint: new pass.

A typical use of `bugpoint` would involve a script with a pass under
test, e.g.:

    flowmap -relax -optarea 100

and would be invoked as:

    bugpoint -yosys ./yosys -script flowmap.ys -clean -cells

This replaces the current design with the minimal design that still
crashes the `flowmap.ys` script.

`bugpoint` can also be used to perform generic design minimization
using `select`, e.g. the following script:

    select i:* %x t:$_MUX_ %i -assert-max 0

would remove all parts of the design except for an unbroken path from
an input to an output port that goes through exactly one $_MUX_ cell.
(The condition is inverted.)
---
 passes/cmds/Makefile.inc |   2 +-
 passes/cmds/bugpoint.cc  | 369 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 370 insertions(+), 1 deletion(-)
 create mode 100644 passes/cmds/bugpoint.cc

diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc
index 44a83b2b9..c8067a8be 100644
--- a/passes/cmds/Makefile.inc
+++ b/passes/cmds/Makefile.inc
@@ -29,4 +29,4 @@ OBJS += passes/cmds/chformal.o
 OBJS += passes/cmds/chtype.o
 OBJS += passes/cmds/blackbox.o
 OBJS += passes/cmds/ltp.o
-
+OBJS += passes/cmds/bugpoint.o
diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
new file mode 100644
index 000000000..736e94274
--- /dev/null
+++ b/passes/cmds/bugpoint.cc
@@ -0,0 +1,369 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2018  whitequark <whitequark@whitequark.org>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "backends/ilang/ilang_backend.h"
+
+USING_YOSYS_NAMESPACE
+using namespace ILANG_BACKEND;
+PRIVATE_NAMESPACE_BEGIN
+
+struct BugpointPass : public Pass {
+	BugpointPass() : Pass("bugpoint", "minimize testcases") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    bugpoint [options]\n");
+		log("\n");
+		log("This command minimizes testcases that crash Yosys. It removes an arbitrary part\n");
+		log("of the design and recursively invokes Yosys with a given script, repeating these\n");
+		log("steps while it can find a smaller design that still causes a crash. Once this\n");
+		log("command finishes, it replaces the current design with the smallest testcase it\n");
+		log("was able to produce.\n");
+		log("\n");
+		log("It is possible to specify the kinds of design part that will be removed. If none\n");
+		log("are specified, all parts of design will be removed.\n");
+		log("\n");
+		log("    -yosys <filename>\n");
+		log("        use this Yosys binary. if not specified, `yosys` is used.\n");
+		log("\n");
+		log("    -script <filename>\n");
+		log("        use this script to crash Yosys. required.\n");
+		log("\n");
+		log("    -grep <string>\n");
+		log("        only consider crashes that place this string in the log file.\n");
+		log("\n");
+		log("    -fast\n");
+		log("        run `clean -purge` after each minimization step. converges faster, but\n");
+		log("        produces larger testcases, and may fail to produce any testcase at all if\n");
+		log("        the crash is related to dangling wires.\n");
+		log("\n");
+		log("    -clean\n");
+		log("        run `clean -purge` before checking testcase and after finishing. produces\n");
+		log("        smaller and more useful testcases, but may fail to produce any testcase\n");
+		log("        at all if the crash is related to dangling wires.\n");
+		log("\n");
+		log("    -modules\n");
+		log("        try to remove modules.\n");
+		log("\n");
+		log("    -ports\n");
+		log("        try to remove module ports.\n");
+		log("\n");
+		log("    -cells\n");
+		log("        try to remove cells.\n");
+		log("\n");
+		log("    -connections\n");
+		log("        try to reconnect ports to 'x.\n");
+		log("\n");
+	}
+
+	bool run_yosys(RTLIL::Design *design, string yosys_cmd, string script)
+	{
+		design->sort();
+
+		std::ofstream f("bugpoint-case.il");
+		ILANG_BACKEND::dump_design(f, design, /*only_selected=*/false, /*flag_m=*/true, /*flag_n=*/false);
+		f.close();
+
+		string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log -s %s bugpoint-case.il", yosys_cmd.c_str(), script.c_str());
+		return system(yosys_cmdline.c_str()) == 0;
+	}
+
+	bool check_logfile(string grep)
+	{
+		if (grep.empty())
+			return true;
+
+		std::ifstream f("bugpoint-case.log");
+		while (!f.eof())
+		{
+			string line;
+			getline(f, line);
+			if (line.find(grep) != std::string::npos)
+				return true;
+		}
+		return false;
+	}
+
+	RTLIL::Design *clean_design(RTLIL::Design *design, bool do_clean = true, bool do_delete = false)
+	{
+		if (!do_clean)
+			return design;
+
+		RTLIL::Design *design_copy = new RTLIL::Design;
+		for (auto &it : design->modules_)
+			design_copy->add(it.second->clone());
+		Pass::call(design_copy, "clean -purge");
+
+		if (do_delete)
+			delete design;
+		return design_copy;
+	}
+
+	RTLIL::Design *simplify_something(RTLIL::Design *design, int &seed, bool stage2, bool modules, bool ports, bool cells, bool connections)
+	{
+		RTLIL::Design *design_copy = new RTLIL::Design;
+		for (auto &it : design->modules_)
+			design_copy->add(it.second->clone());
+
+		int index = 0;
+		if (modules)
+		{
+			for (auto &it : design_copy->modules_)
+			{
+				if (it.second->get_bool_attribute("\\blackbox"))
+					continue;
+
+				if (index++ == seed)
+				{
+					log("Trying to remove module %s.\n", it.first.c_str());
+					design_copy->remove(it.second);
+					return design_copy;
+				}
+			}
+		}
+		if (ports)
+		{
+			for (auto mod : design_copy->modules())
+			{
+				if (mod->get_bool_attribute("\\blackbox"))
+					continue;
+
+				for (auto wire : mod->wires())
+				{
+					if (!stage2 && wire->get_bool_attribute("$bugpoint"))
+						continue;
+
+					if (wire->port_input || wire->port_output)
+					{
+						if (index++ == seed)
+						{
+							log("Trying to remove module port %s.\n", log_signal(wire));
+							wire->port_input = wire->port_output = false;
+							mod->fixup_ports();
+							return design_copy;
+						}
+					}
+				}
+			}
+		}
+		if (cells)
+		{
+			for (auto mod : design_copy->modules())
+			{
+				if (mod->get_bool_attribute("\\blackbox"))
+					continue;
+
+				for (auto &it : mod->cells_)
+				{
+					if (index++ == seed)
+					{
+						log("Trying to remove cell %s.%s.\n", mod->name.c_str(), it.first.c_str());
+						mod->remove(it.second);
+						return design_copy;
+					}
+				}
+			}
+		}
+		if (connections)
+		{
+			for (auto mod : design_copy->modules())
+			{
+				if (mod->get_bool_attribute("\\blackbox"))
+					continue;
+
+				for (auto cell : mod->cells())
+				{
+					for (auto it : cell->connections_)
+					{
+						RTLIL::SigSpec port = cell->getPort(it.first);
+						bool is_undef = port.is_fully_undef();
+						bool is_port = port.is_wire() && (port.as_wire()->port_input || port.as_wire()->port_output);
+
+						if(is_undef || (!stage2 && is_port))
+							continue;
+
+						if (index++ == seed)
+						{
+							log("Trying to remove cell port %s.%s.%s.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
+							RTLIL::SigSpec port_x(State::Sx, port.size());
+							cell->unsetPort(it.first);
+							cell->setPort(it.first, port_x);
+							return design_copy;
+						}
+
+						if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
+						{
+							log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
+							RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
+							wire->set_bool_attribute("$bugpoint");
+							wire->port_input = cell->input(it.first);
+							wire->port_output = cell->output(it.first);
+							cell->unsetPort(it.first);
+							cell->setPort(it.first, wire);
+							mod->fixup_ports();
+							return design_copy;
+						}
+					}
+				}
+			}
+		}
+		return NULL;
+	}
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		string yosys_cmd = "yosys", script, grep;
+		bool fast = false, clean = false;
+		bool modules = false, ports = false, cells = false, connections = false, has_part = false;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-yosys" && argidx + 1 < args.size()) {
+				yosys_cmd = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-script" && argidx + 1 < args.size()) {
+				script = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-grep" && argidx + 1 < args.size()) {
+				grep = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-fast") {
+				fast = true;
+				continue;
+			}
+			if (args[argidx] == "-clean") {
+				clean = true;
+				continue;
+			}
+			if (args[argidx] == "-modules") {
+				modules = true;
+				has_part = true;
+				continue;
+			}
+			if (args[argidx] == "-ports") {
+				ports = true;
+				has_part = true;
+				continue;
+			}
+			if (args[argidx] == "-cells") {
+				cells = true;
+				has_part = true;
+				continue;
+			}
+			if (args[argidx] == "-connections") {
+				connections = true;
+				has_part = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (!has_part)
+		{
+			modules = true;
+			ports = true;
+			cells = true;
+			connections = true;
+		}
+
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
+		RTLIL::Design *crashing_design = clean_design(design, clean);
+		if (run_yosys(crashing_design, yosys_cmd, script))
+			log_cmd_error("The provided script file and Yosys binary do not crash on this design!\n");
+		if (!check_logfile(grep))
+			log_cmd_error("The provided grep string is not found in the log file!\n");
+
+		int seed = 0, crashing_seed = seed;
+		bool found_something = false, stage2 = false;
+		while (true)
+		{
+			if (RTLIL::Design *simplified = simplify_something(crashing_design, seed, stage2, modules, ports, cells, connections))
+			{
+				simplified = clean_design(simplified, fast, /*do_delete=*/true);
+
+				bool crashes;
+				if (clean)
+				{
+					RTLIL::Design *testcase = clean_design(simplified);
+					crashes = !run_yosys(testcase, yosys_cmd, script);
+					delete testcase;
+				}
+				else
+				{
+					crashes = !run_yosys(simplified, yosys_cmd, script);
+				}
+
+				if (crashes && check_logfile(grep))
+				{
+					log("Testcase crashes.\n");
+					if (crashing_design != design)
+						delete crashing_design;
+					crashing_design = simplified;
+					crashing_seed = seed;
+					found_something = true;
+				}
+				else
+				{
+					log("Testcase does not crash.\n");
+					delete simplified;
+					seed++;
+				}
+			}
+			else
+			{
+				seed = 0;
+				if (found_something)
+					found_something = false;
+				else
+				{
+					if (!stage2)
+					{
+						log("Demoting introduced module ports.\n");
+						stage2 = true;
+					}
+					else
+					{
+						log("Simplifications exhausted.\n");
+						break;
+					}
+				}
+			}
+		}
+
+		if (crashing_design != design)
+		{
+			Pass::call(design, "design -reset");
+			crashing_design = clean_design(crashing_design, clean, /*do_delete=*/true);
+			for (auto &it : crashing_design->modules_)
+				design->add(it.second->clone());
+			delete crashing_design;
+		}
+	}
+} BugpointPass;
+
+PRIVATE_NAMESPACE_END

From b5f6e786ea3affc6688ec9d229ae8642f2c9e151 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 7 Jan 2019 09:45:21 +0100
Subject: [PATCH 292/528] Switch "bugpoint" from system() to run_command()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/cmds/bugpoint.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/bugpoint.cc b/passes/cmds/bugpoint.cc
index 736e94274..606276e64 100644
--- a/passes/cmds/bugpoint.cc
+++ b/passes/cmds/bugpoint.cc
@@ -83,7 +83,7 @@ struct BugpointPass : public Pass {
 		f.close();
 
 		string yosys_cmdline = stringf("%s -qq -L bugpoint-case.log -s %s bugpoint-case.il", yosys_cmd.c_str(), script.c_str());
-		return system(yosys_cmdline.c_str()) == 0;
+		return run_command(yosys_cmdline) == 0;
 	}
 
 	bool check_logfile(string grep)

From 8a63fc51d31bca50c3d08130c3271a288af1cf4b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 7 Jan 2019 10:01:11 +0100
Subject: [PATCH 293/528] Bugfix in $memrd sharing

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/share.cc | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index b80280829..c85c27427 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -710,8 +710,12 @@ struct ShareWorker
 			RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
 			RTLIL::SigSpec addr1 = c1->getPort("\\ADDR");
 			RTLIL::SigSpec addr2 = c2->getPort("\\ADDR");
-			if (addr1 != addr2)
-				supercell->setPort("\\ADDR", module->Mux(NEW_ID, addr2, addr1, act));
+			if (GetSize(addr1) < GetSize(addr2))
+				addr1.extend_u0(GetSize(addr2));
+			else
+				addr2.extend_u0(GetSize(addr1));
+			supercell->setPort("\\ADDR", addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
+			supercell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr1));
 			supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort("\\DATA"), c2->getPort("\\DATA")));
 			supercell_aux.insert(supercell);
 			return supercell;

From f042559e9dbcc0738c6404903ac22da63cd27404 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 7 Jan 2019 10:07:28 +0100
Subject: [PATCH 294/528] Fix typo in manual

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 manual/CHAPTER_CellLib.tex | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index d40a600ed..e22664a82 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -437,7 +437,7 @@ otherwise.
 \begin{lstlisting}[mathescape,language=Verilog]
 	always @($ClkEdge$ C, $RstEdge$ R)
 		if (R == $RstLvl$)
-			Q <= $RstVa$l;
+			Q <= $RstVal$;
 		else
 			Q <= D;
 \end{lstlisting}

From 211c26a4c9b9010380bfab9f02b79a25ee10ee29 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 4 Jan 2019 13:06:51 +0000
Subject: [PATCH 295/528] flowmap: implement depth relaxation.

---
 passes/techmap/flowmap.cc     | 702 ++++++++++++++++++++++++++++++++--
 passes/tests/flowmap/pack1.v  |  11 +
 passes/tests/flowmap/pack1p.v |  11 +
 passes/tests/flowmap/pack2.v  |  15 +
 passes/tests/flowmap/pack2p.v |  15 +
 passes/tests/flowmap/pack3.v  |  15 +
 passes/tests/flowmap/pack3p.v |  15 +
 7 files changed, 762 insertions(+), 22 deletions(-)
 create mode 100644 passes/tests/flowmap/pack1.v
 create mode 100644 passes/tests/flowmap/pack1p.v
 create mode 100644 passes/tests/flowmap/pack2.v
 create mode 100644 passes/tests/flowmap/pack2p.v
 create mode 100644 passes/tests/flowmap/pack3.v
 create mode 100644 passes/tests/flowmap/pack3p.v

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index be70b579b..f938efeee 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -17,11 +17,16 @@
  *
  */
 
-// [[CITE]]
+// [[CITE]] FlowMap algorithm
 // Jason Cong; Yuzheng Ding, "An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs,"
 // Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, Vol. 13, pp. 1-12, Jan. 1994.
 // doi: 10.1109/43.273754
 
+// [[CITE]] FlowMap-r algorithm
+// Jason Cong; Yuzheng Ding, "On Area/Depth Tradeoff in LUT-Based FPGA Technology Mapping,"
+// Very Large Scale Integration Systems, IEEE Transactions on, Vol. 2, June 1994.
+// doi: 10.1109/92.28574
+
 // Required reading material:
 //
 // Min-cut max-flow theorem:
@@ -29,11 +34,14 @@
 // FlowMap paper:
 //   http://cadlab.cs.ucla.edu/~cong/papers/iccad92.pdf   (short version)
 //   https://limsk.ece.gatech.edu/book/papers/flowmap.pdf (long version)
+// FlowMap-r paper:
+//   http://cadlab.cs.ucla.edu/~cong/papers/dac93.pdf     (short version)
+//   https://sci-hub.tw/10.1109/92.285741                 (long version)
 
-// Notes on implementation:
+// Notes on correspondence between paper and implementation:
 //
-// 1. In the paper, the nodes are logic elements (analogous to Yosys cells) and edges are wires. However, in our implementation, we use
-// an inverted approach: the nodes are Yosys wire bits, and the edges are derived from (but aren't represented by) Yosys cells.
+// 1. In the FlowMap paper, the nodes are logic elements (analogous to Yosys cells) and edges are wires. However, in our implementation,
+// we use an inverted approach: the nodes are Yosys wire bits, and the edges are derived from (but aren't represented by) Yosys cells.
 // This may seem counterintuitive. Three observations may help understanding this. First, for a cell with a 1-bit Y output that is
 // the sole driver of its output net (which is the typical case), these representations are equivalent, because there is an exact
 // correspondence between cells and output wires. Second, in the paper, primary inputs (analogous to Yosys cell or module ports) are
@@ -42,17 +50,50 @@
 // such cells are supported without any additional effort; any Yosys cell with n output wire bits ends up being split into n flow graph
 // nodes.
 //
-// 2. The paper introduces three networks: Nt, Nt', and Nt''. The network Nt is directly represented by a subgraph of RTLIL graph,
+// 2. The FlowMap paper introduces three networks: Nt, Nt', and Nt''. The network Nt is directly represented by a subgraph of RTLIL graph,
 // which is parsed into an equivalent but easier to traverse representation in FlowmapWorker. The network Nt' is built explicitly
 // from a subgraph of Nt, and uses a similar representation in FlowGraph. The network Nt'' is implicit in FlowGraph, which is possible
 // because of the following observation: each Nt' node corresponds to an Nt'' edge of capacity 1, and each Nt' edge corresponds to
 // an Nt'' edge of capacity ∞. Therefore, we only need to explicitly record flow for Nt' edges and through Nt' nodes.
 //
-// 3. The paper ambiguously states: "Moreover, we can find such a cut (X′′, X̅′′) by performing a depth first search starting at the source s,
-// and including in X′′ all the nodes which are reachable from s." This actually refers to a specific kind of search, mincut computation.
-// Mincut computation involves computing the set of nodes reachable from s by an undirected path with no full (i.e. zero capacity) forward
-// edges or empty (i.e. no flow) backward edges. In addition, the depth first search is required to compute a max-volume max-flow min-cut
-// specifically, because a max-flow min-cut is not, in general, unique.
+// 3. The FlowMap paper ambiguously states: "Moreover, we can find such a cut (X′′, X̅′′) by performing a depth first search starting at
+// the source s, and including in X′′ all the nodes which are reachable from s." This actually refers to a specific kind of search,
+// min-cut computation. Min-cut computation involves computing the set of nodes reachable from s by an undirected path with no full
+// (i.e. zero capacity) forward edges or empty (i.e. no flow) backward edges. In addition, the depth first search is required to compute
+// a max-volume max-flow min-cut specifically, because a max-flow min-cut is not, in general, unique.
+
+// Notes on implementation:
+//
+// 1. To compute depth optimal packing, an intermediate representation is used, where each cell with n output bits is split into n graph
+// nodes. Each such graph node is represented directly with the wire bit (RTLIL::SigBit instance) that corresponds to the output bit
+// it is created from. Fan-in and fan-out are represented explicitly by edge lists derived from the RTLIL graph. This IR never changes
+// after it has been computed.
+//
+// In terms of data, this IR is comprised of `inputs`, `outputs`, `nodes`, `edges_fw` and `edges_bw` fields.
+//
+// We call this IR "gate IR".
+//
+// 2. To compute area optimal packing, another intermediate representation is used, which consists of some K-feasible cone for every node
+// that exists in the gate IR. Immediately after depth optimal packing with FlowMap, each such cone occupies the lowest possible depth,
+// but this is not true in general, and transformations of this IR may change the cones, although each transformation has to keep each
+// cone K-feasible. In this IR, LUT fan-in and fan-out are represented explicitly by edge lists; if a K-feasible cone chosen for node A
+// includes nodes B and C, there are edges between all predecessors of A, B and C in the gate IR and node A in this IR. Moreover, in
+// this IR, cones may be *realized* or *derealized*. Only realized cones will end up mapped to actual LUTs in the output of this pass.
+//
+// Intuitively, this IR contains (some, ideally but not necessarily optimal) LUT representation for each input cell. By starting at outputs
+// and traversing the graph of this IR backwards, each K-feasible cone is converted to an actual LUT at the end of the pass. This is
+// the same as iterating through each realized LUT.
+//
+// The following are the invariants of this IR:
+//   a) Each gate IR node corresponds to a K-feasible cut.
+//   b) Each realized LUT is reachable through backward edges from some output.
+//   c) The LUT fan-in is exactly the fan-in of its constituent gates minus the fan-out of its constituent gates.
+// The invariants are kept even for derealized LUTs, since the whole point of this IR is ease of packing, unpacking, and repacking LUTs.
+//
+// In terms of data, this IR is comprised of `lut_nodes` (the set of all realized LUTs), `lut_gates` (the map from a LUT to its
+// constituent gates), `lut_edges_fw` and `lut_edges_bw` fields. The `inputs` and `outputs` fields are shared with the gate IR.
+//
+// We call this IR "LUT IR".
 
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
@@ -405,7 +446,8 @@ struct FlowGraph
 struct FlowmapWorker
 {
 	int order;
-	bool debug;
+	int r_alpha, r_beta, r_gamma;
+	bool debug, debug_relax;
 
 	RTLIL::Module *module;
 	SigMap sigmap;
@@ -413,13 +455,16 @@ struct FlowmapWorker
 
 	dict<RTLIL::SigBit, ModIndex::PortInfo> node_origins;
 
+	// Gate IR
 	pool<RTLIL::SigBit> nodes, inputs, outputs;
 	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges_fw, edges_bw;
 	dict<RTLIL::SigBit, int> labels;
 
+	// LUT IR
 	pool<RTLIL::SigBit> lut_nodes;
 	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_gates;
 	dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_edges_fw, lut_edges_bw;
+	dict<RTLIL::SigBit, int> lut_depths, lut_altitudes, lut_slacks;
 
 	int gate_count = 0, lut_count = 0, packed_count = 0;
 	int gate_area = 0, lut_area = 0;
@@ -427,6 +472,7 @@ struct FlowmapWorker
 	enum class GraphMode {
 		Label,
 		Cut,
+		Slack,
 	};
 
 	void dump_dot_graph(string filename, GraphMode mode,
@@ -465,6 +511,10 @@ struct FlowmapWorker
 					if (cut.second[node])
 						return GraphStyle{label, "red"};
 					return GraphStyle{label};
+
+				case GraphMode::Slack:
+					label += stringf("\nd=%d a=%d\ns=%d", lut_depths[node], lut_altitudes[node], lut_slacks[node]);
+					return GraphStyle{label, lut_slacks[node] == 0 ? "red" : "black"};
 			}
 			return GraphStyle{label};
 		};
@@ -474,6 +524,14 @@ struct FlowmapWorker
 		::dump_dot_graph(filename, subgraph_nodes, subgraph_edges, inputs, outputs, node_style, edge_style, module->name.str());
 	}
 
+	void dump_dot_lut_graph(string filename, GraphMode mode)
+	{
+		pool<RTLIL::SigBit> lut_and_input_nodes;
+		lut_and_input_nodes.insert(lut_nodes.begin(), lut_nodes.end());
+		lut_and_input_nodes.insert(inputs.begin(), inputs.end());
+		dump_dot_graph(filename, mode, lut_and_input_nodes, lut_edges_fw, lut_gates);
+	}
+
 	pool<RTLIL::SigBit> find_subgraph(RTLIL::SigBit sink)
 	{
 		pool<RTLIL::SigBit> subgraph;
@@ -726,20 +784,560 @@ struct FlowmapWorker
 		int depth = 0;
 		for (auto label : labels)
 			depth = max(depth, label.second);
-		log("Solved to %d LUTs in %d levels.\n", (int)lut_nodes.size(), depth);
+		log("Solved to %d LUTs with maximum depth %d.\n", (int)lut_nodes.size(), depth);
 
 		if (debug)
 		{
-			pool<RTLIL::SigBit> lut_and_input_nodes;
-			lut_and_input_nodes.insert(lut_nodes.begin(), lut_nodes.end());
-			lut_and_input_nodes.insert(inputs.begin(), inputs.end());
-			dump_dot_graph("flowmap-packed.dot", GraphMode::Label, lut_and_input_nodes, lut_edges_fw, lut_gates);
+			dump_dot_lut_graph("flowmap-packed.dot", GraphMode::Label);
 			log("Dumped packed graph to `flowmap-packed.dot`.\n");
 		}
 
 		return depth;
 	}
 
+	void realize_derealize_lut(RTLIL::SigBit lut, pool<RTLIL::SigBit> *changed = nullptr)
+	{
+		pool<RTLIL::SigBit> worklist = {lut};
+		while (!worklist.empty())
+		{
+			auto lut = worklist.pop();
+			if (inputs[lut])
+				continue;
+
+			bool realized_successors = false;
+			for (auto lut_succ : lut_edges_fw[lut])
+				if (lut_nodes[lut_succ])
+					realized_successors = true;
+
+			if (realized_successors && !lut_nodes[lut])
+				lut_nodes.insert(lut);
+			else if (!realized_successors && lut_nodes[lut])
+				lut_nodes.erase(lut);
+			else
+				continue;
+
+			for (auto lut_pred : lut_edges_bw[lut])
+				worklist.insert(lut_pred);
+
+			if (changed)
+				changed->insert(lut);
+		}
+	}
+
+	void add_lut_edge(RTLIL::SigBit pred, RTLIL::SigBit succ, pool<RTLIL::SigBit> *changed = nullptr)
+	{
+		log_assert(!lut_edges_fw[pred][succ] && !lut_edges_bw[succ][pred]);
+		log_assert((int)lut_edges_bw[succ].size() < order);
+
+		lut_edges_fw[pred].insert(succ);
+		lut_edges_bw[succ].insert(pred);
+		realize_derealize_lut(pred, changed);
+
+		if (changed)
+		{
+			changed->insert(pred);
+			changed->insert(succ);
+		}
+	}
+
+	void remove_lut_edge(RTLIL::SigBit pred, RTLIL::SigBit succ, pool<RTLIL::SigBit> *changed = nullptr)
+	{
+		log_assert(lut_edges_fw[pred][succ] && lut_edges_bw[succ][pred]);
+
+		lut_edges_fw[pred].erase(succ);
+		lut_edges_bw[succ].erase(pred);
+		realize_derealize_lut(pred, changed);
+
+		if (changed)
+		{
+			if (lut_nodes[pred])
+				changed->insert(pred);
+			changed->insert(succ);
+		}
+	}
+
+	pair<pool<RTLIL::SigBit>, pool<RTLIL::SigBit>> cut_lut_at_gate(RTLIL::SigBit lut, RTLIL::SigBit lut_gate)
+	{
+		pool<RTLIL::SigBit> gate_inputs = lut_edges_bw[lut];
+		pool<RTLIL::SigBit> other_inputs;
+		pool<RTLIL::SigBit> worklist = {lut};
+		while (!worklist.empty())
+		{
+			auto node = worklist.pop();
+			for (auto node_pred : edges_bw[node])
+			{
+				if (node_pred == lut_gate)
+					continue;
+				if (lut_gates[lut][node_pred])
+					worklist.insert(node_pred);
+				else
+				{
+					gate_inputs.erase(node_pred);
+					other_inputs.insert(node_pred);
+				}
+			}
+		}
+		return {gate_inputs, other_inputs};
+	}
+
+	void compute_lut_distances(dict<RTLIL::SigBit, int> &lut_distances, bool forward,
+	                          pool<RTLIL::SigBit> initial = {}, pool<RTLIL::SigBit> *changed = nullptr)
+	{
+		pool<RTLIL::SigBit> terminals = forward ? inputs : outputs;
+		auto &lut_edges_next = forward ? lut_edges_fw : lut_edges_bw;
+		auto &lut_edges_prev = forward ? lut_edges_bw : lut_edges_fw;
+
+		if (initial.empty())
+			initial = terminals;
+		for (auto node : initial)
+			lut_distances.erase(node);
+
+		pool<RTLIL::SigBit> worklist = initial;
+		while (!worklist.empty())
+		{
+			auto lut = worklist.pop();
+			int lut_distance = 0;
+			if (forward && inputs[lut])
+				lut_distance = labels[lut]; // to support (* $flowmap_level=n *)
+			for (auto lut_prev : lut_edges_prev[lut])
+				if ((lut_nodes[lut_prev] || inputs[lut_prev]) && lut_distances.count(lut_prev))
+					lut_distance = max(lut_distance, lut_distances[lut_prev] + 1);
+			if (!lut_distances.count(lut) || lut_distances[lut] != lut_distance)
+			{
+				lut_distances[lut] = lut_distance;
+				if (changed != nullptr && !inputs[lut])
+					changed->insert(lut);
+				for (auto lut_next : lut_edges_next[lut])
+					if (lut_nodes[lut_next] || inputs[lut_next])
+						worklist.insert(lut_next);
+			}
+		}
+	}
+
+	void check_lut_distances(const dict<RTLIL::SigBit, int> &lut_distances, bool forward)
+	{
+		dict<RTLIL::SigBit, int> gold_lut_distances;
+		compute_lut_distances(gold_lut_distances, forward);
+		for (auto lut_distance : lut_distances)
+			if (lut_nodes[lut_distance.first])
+				log_assert(lut_distance.second == gold_lut_distances[lut_distance.first]);
+	}
+
+	// LUT depth is the length of the longest path from any input in LUT fan-in to LUT.
+	// LUT altitude (for lack of a better term) is the length of the longest path from LUT to any output in LUT fan-out.
+	void update_lut_depths_altitudes(pool<RTLIL::SigBit> worklist = {}, pool<RTLIL::SigBit> *changed = nullptr)
+	{
+		compute_lut_distances(lut_depths, /*forward=*/true, worklist, changed);
+		compute_lut_distances(lut_altitudes, /*forward=*/false, worklist, changed);
+		if (debug_relax && !worklist.empty()) {
+			check_lut_distances(lut_depths, /*forward=*/true);
+			check_lut_distances(lut_altitudes, /*forward=*/false);
+		}
+	}
+
+	// LUT critical output set is the set of outputs whose depth will increase (equivalently, slack will decrease) if the depth of
+	// the LUT increases. (This is referred to as RPOv for LUTv in the paper.)
+	void compute_lut_critical_outputs(dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs,
+	                                  pool<RTLIL::SigBit> worklist = {})
+	{
+		if (worklist.empty())
+			worklist = lut_nodes;
+
+		while (!worklist.empty())
+		{
+			bool updated_some = false;
+			for (auto lut : worklist)
+			{
+				if (outputs[lut])
+					lut_critical_outputs[lut] = {lut};
+				else
+				{
+					bool all_succ_computed = true;
+					lut_critical_outputs[lut] = {};
+					for (auto lut_succ : lut_edges_fw[lut])
+					{
+						if (lut_nodes[lut_succ] && lut_depths[lut_succ] == lut_depths[lut] + 1)
+						{
+							if (lut_critical_outputs.count(lut_succ))
+								lut_critical_outputs[lut].insert(lut_critical_outputs[lut_succ].begin(), lut_critical_outputs[lut_succ].end());
+							else
+							{
+								all_succ_computed = false;
+								break;
+							}
+						}
+					}
+					if (!all_succ_computed)
+					{
+						lut_critical_outputs.erase(lut);
+						continue;
+					}
+				}
+				worklist.erase(lut);
+				updated_some = true;
+			}
+			log_assert(updated_some);
+		}
+	}
+
+	// Invalidating LUT critical output sets is tricky, because increasing the depth of a LUT may take other, adjacent LUTs off the critical
+	// path to the output. Conservatively, if we increase depth of some LUT, every LUT in its input cone needs to have its critical output
+	// set invalidated, too.
+	pool<RTLIL::SigBit> invalidate_lut_critical_outputs(dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs,
+	                                                    pool<RTLIL::SigBit> worklist)
+	{
+		pool<RTLIL::SigBit> changed;
+		while (!worklist.empty())
+		{
+			auto lut = worklist.pop();
+			changed.insert(lut);
+			lut_critical_outputs.erase(lut);
+			for (auto lut_pred : lut_edges_bw[lut])
+			{
+				if (lut_nodes[lut_pred] && !changed[lut_pred])
+				{
+					changed.insert(lut_pred);
+					worklist.insert(lut_pred);
+				}
+			}
+		}
+		return changed;
+	}
+
+	void check_lut_critical_outputs(const dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
+	{
+		dict<RTLIL::SigBit, pool<RTLIL::SigBit>> gold_lut_critical_outputs;
+		compute_lut_critical_outputs(gold_lut_critical_outputs);
+		for (auto lut_critical_output : lut_critical_outputs)
+			if (lut_nodes[lut_critical_output.first])
+				log_assert(lut_critical_output.second == gold_lut_critical_outputs[lut_critical_output.first]);
+	}
+
+	void update_lut_critical_outputs(dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs,
+	                                 pool<RTLIL::SigBit> worklist = {})
+	{
+		if (!worklist.empty())
+		{
+			pool<RTLIL::SigBit> invalidated = invalidate_lut_critical_outputs(lut_critical_outputs, worklist);
+			compute_lut_critical_outputs(lut_critical_outputs, invalidated);
+			check_lut_critical_outputs(lut_critical_outputs);
+		}
+		else
+			compute_lut_critical_outputs(lut_critical_outputs);
+	}
+
+	void update_breaking_node_potentials(dict<RTLIL::SigBit, dict<RTLIL::SigBit, int>> &potentials,
+	                                     const dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
+	{
+		for (auto lut : lut_nodes)
+		{
+			if (potentials.count(lut))
+				continue;
+			if (lut_gates[lut].size() == 1 || lut_slacks[lut] == 0)
+				continue;
+
+			if (debug_relax)
+				log("  Computing potentials for LUT %s.\n", log_signal(lut));
+
+			for (auto lut_gate : lut_gates[lut])
+			{
+				if (lut == lut_gate)
+					continue;
+
+				if (debug_relax)
+					log("    Considering breaking node %s.\n", log_signal(lut_gate));
+
+				int r_ex, r_im, r_slk;
+
+				auto cut_inputs = cut_lut_at_gate(lut, lut_gate);
+				pool<RTLIL::SigBit> gate_inputs = cut_inputs.first, other_inputs = cut_inputs.second;
+				if (gate_inputs.empty() && (int)other_inputs.size() == order)
+				{
+					if (debug_relax)
+						log("      Breaking would result in a (k+1)-LUT.\n");
+					continue;
+				}
+
+				pool<RTLIL::SigBit> elim_fanin_luts;
+				for (auto gate_input : gate_inputs)
+				{
+					if (lut_edges_fw[gate_input].size() == 1)
+					{
+						log_assert(lut_edges_fw[gate_input][lut]);
+						elim_fanin_luts.insert(gate_input);
+					}
+				}
+				if (debug_relax)
+				{
+					if (!lut_nodes[lut_gate])
+						log("      Breaking requires a new LUT.\n");
+					if (!gate_inputs.empty())
+					{
+						log("      Breaking eliminates LUT inputs");
+						for (auto gate_input : gate_inputs)
+							log(" %s", log_signal(gate_input));
+						log(".\n");
+					}
+					if (!elim_fanin_luts.empty())
+					{
+						log("      Breaking eliminates fan-in LUTs");
+						for (auto elim_fanin_lut : elim_fanin_luts)
+							log(" %s", log_signal(elim_fanin_lut));
+						log(".\n");
+					}
+				}
+				r_ex = (lut_nodes[lut_gate] ? 0 : -1) + elim_fanin_luts.size();
+
+				pool<pair<RTLIL::SigBit, RTLIL::SigBit>> maybe_mergeable_luts;
+
+				// Try to merge LUTv with one of its successors.
+				RTLIL::SigBit last_lut_succ;
+				int fanout = 0;
+				for (auto lut_succ : lut_edges_fw[lut])
+				{
+					if (lut_nodes[lut_succ])
+					{
+						fanout++;
+						last_lut_succ = lut_succ;
+					}
+				}
+				if (fanout == 1)
+					maybe_mergeable_luts.insert({lut, last_lut_succ});
+
+				// Try to merge LUTv with one of its predecessors.
+				for (auto lut_pred : other_inputs)
+				{
+					int fanout = 0;
+					for (auto lut_pred_succ : lut_edges_fw[lut_pred])
+						if (lut_nodes[lut_pred_succ] || lut_pred_succ == lut_gate)
+							fanout++;
+					if (fanout == 1)
+						maybe_mergeable_luts.insert({lut_pred, lut});
+				}
+
+				// Try to merge LUTw with one of its predecessors.
+				for (auto lut_gate_pred : lut_edges_bw[lut_gate])
+				{
+					int fanout = 0;
+					for (auto lut_gate_pred_succ : lut_edges_fw[lut_gate_pred])
+						if (lut_nodes[lut_gate_pred_succ] || lut_gate_pred_succ == lut_gate)
+							fanout++;
+					if (fanout == 1)
+						maybe_mergeable_luts.insert({lut_gate_pred, lut_gate});
+				}
+
+				r_im = 0;
+				for (auto maybe_mergeable_pair : maybe_mergeable_luts)
+				{
+					log_assert(lut_edges_fw[maybe_mergeable_pair.first][maybe_mergeable_pair.second]);
+					pool<RTLIL::SigBit> unique_inputs;
+					for (auto fst_lut_pred : lut_edges_bw[maybe_mergeable_pair.first])
+						if (lut_nodes[fst_lut_pred])
+							unique_inputs.insert(fst_lut_pred);
+					for (auto snd_lut_pred : lut_edges_bw[maybe_mergeable_pair.second])
+						if (lut_nodes[snd_lut_pred])
+							unique_inputs.insert(snd_lut_pred);
+					unique_inputs.erase(maybe_mergeable_pair.first);
+					if ((int)unique_inputs.size() <= order)
+					{
+						if (debug_relax)
+							log("      Breaking may allow merging %s and %s.\n",
+							    log_signal(maybe_mergeable_pair.first), log_signal(maybe_mergeable_pair.second));
+						r_im++;
+					}
+				}
+
+				int lut_gate_depth;
+				if (lut_nodes[lut_gate])
+					lut_gate_depth = lut_depths[lut_gate];
+				else
+				{
+					lut_gate_depth = 0;
+					for (auto lut_gate_pred : lut_edges_bw[lut_gate])
+						lut_gate_depth = max(lut_gate_depth, lut_depths[lut_gate_pred] + 1);
+				}
+				if (lut_depths[lut] >= lut_gate_depth + 1)
+					r_slk = 0;
+				else
+				{
+					int depth_delta = lut_gate_depth + 1 - lut_depths[lut];
+					if (depth_delta > lut_slacks[lut])
+					{
+						if (debug_relax)
+							log("      Breaking would increase depth by %d, which is more than available slack.\n", depth_delta);
+						continue;
+					}
+
+					if (debug_relax)
+					{
+						log("      Breaking increases depth of LUT by %d.\n", depth_delta);
+						if (lut_critical_outputs.at(lut).size())
+						{
+							log("      Breaking decreases slack of outputs");
+							for (auto lut_critical_output : lut_critical_outputs.at(lut))
+							{
+								log(" %s", log_signal(lut_critical_output));
+								log_assert(lut_slacks[lut_critical_output] > 0);
+							}
+							log(".\n");
+						}
+					}
+					r_slk = lut_critical_outputs.at(lut).size() * depth_delta;
+				}
+
+				int p = 100 * (r_alpha * r_ex + r_beta * r_im + r_gamma) / (r_slk + 1);
+				if (debug_relax)
+					log("    Potential for breaking node %s: %d (Rex=%d, Rim=%d, Rslk=%d).\n",
+					    log_signal(lut_gate), p, r_ex, r_im, r_slk);
+				potentials[lut][lut_gate] = p;
+			}
+		}
+	}
+
+	bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
+	{
+		for (auto node : lut_nodes)
+		{
+			lut_slacks[node] = depth_bound - (lut_depths[node] + lut_altitudes[node]);
+			log_assert(lut_slacks[node] >= 0);
+		}
+		if (debug)
+		{
+			dump_dot_lut_graph(stringf("flowmap-relax-%d-initial.dot", depth_bound), GraphMode::Slack);
+			log("  Dumped initial slack graph to `flowmap-relax-%d-initial.dot`.\n", depth_bound);
+		}
+
+		dict<RTLIL::SigBit, dict<RTLIL::SigBit, int>> potentials;
+		for (int break_num = 1; ; break_num++)
+		{
+			update_breaking_node_potentials(potentials, lut_critical_outputs);
+
+			if (potentials.empty())
+			{
+				log("  Relaxed to %d LUTs.\n", (int)lut_nodes.size());
+				if (!first && break_num == 1)
+				{
+					log("  Design fully relaxed.\n");
+					return true;
+				}
+				else
+				{
+					log("  Slack exhausted.\n");
+					break;
+				}
+			}
+
+			RTLIL::SigBit breaking_lut, breaking_gate;
+			int best_potential = INT_MIN;
+			for (auto lut_gate_potentials : potentials)
+			{
+				for (auto gate_potential : lut_gate_potentials.second)
+				{
+					if (gate_potential.second > best_potential)
+					{
+						breaking_lut = lut_gate_potentials.first;
+						breaking_gate = gate_potential.first;
+						best_potential = gate_potential.second;
+					}
+				}
+			}
+			log("  Breaking LUT %s to %s LUT %s (potential %d).\n",
+			    log_signal(breaking_lut), lut_nodes[breaking_gate] ? "reuse" : "extract", log_signal(breaking_gate), best_potential);
+
+			if (debug_relax)
+				log("    Removing breaking gate %s from LUT.\n", log_signal(breaking_gate));
+			lut_gates[breaking_lut].erase(breaking_gate);
+
+			auto cut_inputs = cut_lut_at_gate(breaking_lut, breaking_gate);
+			pool<RTLIL::SigBit> gate_inputs = cut_inputs.first, other_inputs = cut_inputs.second;
+
+			pool<RTLIL::SigBit> worklist = lut_gates[breaking_lut];
+			pool<RTLIL::SigBit> elim_gates = gate_inputs;
+			while (!worklist.empty())
+			{
+				auto lut_gate = worklist.pop();
+				bool all_gate_preds_elim = true;
+				for (auto lut_gate_pred : edges_bw[lut_gate])
+					if (!elim_gates[lut_gate_pred])
+						all_gate_preds_elim = false;
+				if (all_gate_preds_elim)
+				{
+					if (debug_relax)
+						log("    Removing gate %s from LUT.\n", log_signal(lut_gate));
+					lut_gates[breaking_lut].erase(lut_gate);
+					for (auto lut_gate_succ : edges_fw[lut_gate])
+						worklist.insert(lut_gate_succ);
+				}
+			}
+			log_assert(!lut_gates[breaking_lut].empty());
+
+			pool<RTLIL::SigBit> directly_affected_nodes = {breaking_lut};
+			for (auto gate_input : gate_inputs)
+			{
+				if (debug_relax)
+					log("    Removing LUT edge %s -> %s.\n", log_signal(gate_input), log_signal(breaking_lut));
+				remove_lut_edge(gate_input, breaking_lut, &directly_affected_nodes);
+			}
+			if (debug_relax)
+				log("    Adding LUT edge %s -> %s.\n", log_signal(breaking_gate), log_signal(breaking_lut));
+			add_lut_edge(breaking_gate, breaking_lut, &directly_affected_nodes);
+
+			if (debug_relax)
+				log("  Updating slack and potentials.\n");
+
+			pool<RTLIL::SigBit> indirectly_affected_nodes = {};
+			update_lut_depths_altitudes(directly_affected_nodes, &indirectly_affected_nodes);
+			update_lut_critical_outputs(lut_critical_outputs, indirectly_affected_nodes);
+			for (auto node : indirectly_affected_nodes)
+			{
+				lut_slacks[node] = depth_bound - (lut_depths[node] + lut_altitudes[node]);
+				log_assert(lut_slacks[node] >= 0);
+				if (debug_relax)
+					log("    LUT %s now has depth %d and slack %d.\n", log_signal(node), lut_depths[node], lut_slacks[node]);
+			}
+
+			worklist = indirectly_affected_nodes;
+			pool<RTLIL::SigBit> visited;
+			while (!worklist.empty())
+			{
+				auto node = worklist.pop();
+				visited.insert(node);
+				potentials.erase(node);
+				// We are invalidating the entire output cone of the gate IR node, not just of the LUT IR node. This is done to also invalidate
+				// all LUTs that could contain one of the indirectly affected nodes as a *part* of them, as they may not be in the output cone
+				// of any of the LUT IR nodes, e.g. if we have a LUT IR node A and node B as predecessors of node C, where node B includes all
+				// gates from node A.
+				for (auto node_succ : edges_fw[node])
+					if (!visited[node_succ])
+						worklist.insert(node_succ);
+			}
+
+			if (debug)
+			{
+				dump_dot_lut_graph(stringf("flowmap-relax-%d-break-%d.dot", depth_bound, break_num), GraphMode::Slack);
+				log("  Dumped slack graph after break %d to `flowmap-relax-%d-break-%d.dot`.\n",  break_num, depth_bound, break_num);
+			}
+		}
+
+		return false;
+	}
+
+	void optimize_area(int depth, int optarea)
+	{
+		dict<RTLIL::SigBit, pool<RTLIL::SigBit>> lut_critical_outputs;
+		update_lut_depths_altitudes();
+		update_lut_critical_outputs(lut_critical_outputs);
+
+		for (int depth_bound = depth; depth_bound <= depth + optarea; depth_bound++)
+		{
+			log("Relaxing with depth bound %d.\n", depth_bound);
+			bool fully_relaxed = relax_depth_for_bound(depth_bound == depth, depth_bound, lut_critical_outputs);
+
+			if (fully_relaxed)
+				break;
+		}
+	}
+
 	void map_cells(int minlut)
 	{
 		ConstEval ce(module);
@@ -833,13 +1431,23 @@ struct FlowmapWorker
 		}
 	}
 
-	FlowmapWorker(int order, int minlut, pool<IdString> cell_types, bool debug, RTLIL::Module *module) :
-		order(order), debug(debug), module(module), sigmap(module), index(module)
+	FlowmapWorker(int order, int minlut, pool<IdString> cell_types, int r_alpha, int r_beta, int r_gamma,
+	              bool relax, int optarea, bool debug, bool debug_relax,
+	              RTLIL::Module *module) :
+		order(order), r_alpha(r_alpha), r_beta(r_beta), r_gamma(r_gamma), debug(debug), debug_relax(debug_relax),
+		module(module), sigmap(module), index(module)
 	{
 		log("Labeling cells.\n");
 		discover_nodes(cell_types);
 		label_nodes();
-		pack_luts();
+		int depth = pack_luts();
+
+		if (relax)
+		{
+			log("\n");
+			log("Optimizing area.\n");
+			optimize_area(depth, optarea);
+		}
 
 		log("\n");
 		log("Mapping cells.\n");
@@ -881,16 +1489,34 @@ struct FlowmapPass : public Pass {
 		log("        map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,\n");
 		log("        $_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.\n");
 		log("\n");
+		log("    -relax\n");
+		log("        perform depth relaxation and area minimization.\n");
+		log("\n");
+		log("    -r-alpha n, -r-beta n, -r-gamma n\n");
+		log("        parameters of depth relaxation heuristic potential function.\n");
+		log("        if not specified, alpha=8, beta=2, gamma=1.\n");
+		log("\n");
+		log("    -optarea n\n");
+		log("        optimize for area by trading off at most n logic levels for fewer LUTs.\n");
+		log("        n may be zero, to optimize for area without increasing depth.\n");
+		log("        implies -relax.\n");
+		log("\n");
 		log("    -debug\n");
 		log("        dump intermediate graphs.\n");
 		log("\n");
+		log("    -debug-relax\n");
+		log("        explain decisions performed during depth relaxation.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		int order = 3;
 		int minlut = 1;
 		vector<string> cells;
-		bool debug = false;
+		bool relax = false;
+		int r_alpha = 8, r_beta = 2, r_gamma = 1;
+		int optarea = 0;
+		bool debug = false, debug_relax = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -910,11 +1536,42 @@ struct FlowmapPass : public Pass {
 				split(cells, args[++argidx], ',');
 				continue;
 			}
+			if (args[argidx] == "-relax")
+			{
+				relax = true;
+				continue;
+			}
+			if (args[argidx] == "-r-alpha" && argidx + 1 < args.size())
+			{
+				r_alpha = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-r-beta" && argidx + 1 < args.size())
+			{
+				r_beta = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-r-gamma" && argidx + 1 < args.size())
+			{
+				r_gamma = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-optarea" && argidx + 1 < args.size())
+			{
+				relax = true;
+				optarea = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-debug")
 			{
 				debug = true;
 				continue;
 			}
+			if (args[argidx] == "-debug-relax")
+			{
+				debug = debug_relax = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -930,13 +1587,14 @@ struct FlowmapPass : public Pass {
 			cell_types = {"$_NOT_", "$_AND_", "$_OR_", "$_XOR_", "$_MUX_"};
 		}
 
-		log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap).\n");
+		const char *algo_r = relax ? "-r" : "";
+		log_header(design, "Executing FLOWMAP pass (pack LUTs with FlowMap%s).\n", algo_r);
 
 		int gate_count = 0, lut_count = 0, packed_count = 0;
 		int gate_area = 0, lut_area = 0;
 		for (auto module : design->selected_modules())
 		{
-			FlowmapWorker worker(order, minlut, cell_types, debug, module);
+			FlowmapWorker worker(order, minlut, cell_types, r_alpha, r_beta, r_gamma, relax, optarea, debug, debug_relax, module);
 			gate_count += worker.gate_count;
 			lut_count += worker.lut_count;
 			packed_count += worker.packed_count;
diff --git a/passes/tests/flowmap/pack1.v b/passes/tests/flowmap/pack1.v
new file mode 100644
index 000000000..9454edf3c
--- /dev/null
+++ b/passes/tests/flowmap/pack1.v
@@ -0,0 +1,11 @@
+// Exact reproduction of Figure 3(a) from 10.1109/92.285741.
+module top(...);
+	input a,b,c,d,e,f,g,h;
+	wire x = !(c|d);
+	wire y = !(e&f);
+	wire u = !(a&b);
+	wire v = !(x|y);
+	wire w = !(g&h);
+	output s = !(u|v);
+	output t = !(v|w);
+endmodule
diff --git a/passes/tests/flowmap/pack1p.v b/passes/tests/flowmap/pack1p.v
new file mode 100644
index 000000000..fdb278833
--- /dev/null
+++ b/passes/tests/flowmap/pack1p.v
@@ -0,0 +1,11 @@
+// Like pack1.v, but results in a simpler network.
+module top(...);
+	input a,b,c,d,e,f,g,h;
+	wire x = c|d;
+	wire y = e&f;
+	wire u = a&b;
+	wire v = x|y;
+	wire w = g&h;
+	output s = u|v;
+	output t = v|w;
+endmodule
diff --git a/passes/tests/flowmap/pack2.v b/passes/tests/flowmap/pack2.v
new file mode 100644
index 000000000..445e4afb0
--- /dev/null
+++ b/passes/tests/flowmap/pack2.v
@@ -0,0 +1,15 @@
+// Exact reproduction of Figure 4(a) from 10.1109/92.285741.
+module top(...);
+	(* $flowmap_level=1 *) input a;
+	(* $flowmap_level=1 *) input b;
+	(* $flowmap_level=2 *) input c;
+	(* $flowmap_level=1 *) input d;
+	(* $flowmap_level=3 *) input e;
+	(* $flowmap_level=1 *) input f;
+	wire u = !(a&b);
+	wire w = !(c|d);
+	wire v = !(u|w);
+	wire n0 = !(w&e);
+	wire n1 = !(n0|f);
+	output n2 = !(v&n1);
+endmodule
diff --git a/passes/tests/flowmap/pack2p.v b/passes/tests/flowmap/pack2p.v
new file mode 100644
index 000000000..d4b41733d
--- /dev/null
+++ b/passes/tests/flowmap/pack2p.v
@@ -0,0 +1,15 @@
+// Like pack2.v, but results in a simpler network.
+module top(...);
+	(* $flowmap_level=1 *) input a;
+	(* $flowmap_level=1 *) input b;
+	(* $flowmap_level=2 *) input c;
+	(* $flowmap_level=1 *) input d;
+	(* $flowmap_level=3 *) input e;
+	(* $flowmap_level=1 *) input f;
+	wire u = a&b;
+	wire w = c|d;
+	wire v = u|w;
+	wire n0 = w&e;
+	wire n1 = n0|f;
+	output n2 = v&n1;
+endmodule
diff --git a/passes/tests/flowmap/pack3.v b/passes/tests/flowmap/pack3.v
new file mode 100644
index 000000000..06147a1aa
--- /dev/null
+++ b/passes/tests/flowmap/pack3.v
@@ -0,0 +1,15 @@
+// Exact reproduction of Figure 5(a) (bottom) from 10.1109/92.285741.
+module top(...);
+	input a,b,c,d,e,f,g,h,i,j;
+	wire x = !(a&b);
+	wire y = !(c|d);
+	wire z = !(e|f);
+	wire n0 = !(g&h);
+	wire n1 = !(i|j);
+	wire w = !(x&y);
+	wire n2 = !(z&n0);
+	wire n3 = !(n0|n1);
+	wire n4 = !(n2|n3);
+	wire v = !(w|n5);
+	output u = !(w&v);
+endmodule
diff --git a/passes/tests/flowmap/pack3p.v b/passes/tests/flowmap/pack3p.v
new file mode 100644
index 000000000..bc6ac1757
--- /dev/null
+++ b/passes/tests/flowmap/pack3p.v
@@ -0,0 +1,15 @@
+// Like pack2.v, but results in a simpler network.
+module top(...);
+	input a,b,c,d,e,f,g,h,i,j;
+	wire x = a&b;
+	wire y = c|d;
+	wire z = e|f;
+	wire n0 = g&h;
+	wire n1 = i|j;
+	wire w = x&y;
+	wire n2 = z&n0;
+	wire n3 = n0|n1;
+	wire n4 = n2|n3;
+	wire v = w|n5;
+	output u = w&v;
+endmodule

From e792bd56b77066ee048057e5efdb5d0f517b043a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 8 Jan 2019 02:05:06 +0000
Subject: [PATCH 296/528] flowmap: clean up terminology.

  * "map": group gates into LUTs;
  * "pack": replace gates with LUTs.

This is important because we have FlowMap and DF-Map, and currently
our messages are ambiguous.

Also clean up some other log messages while we're at it.
---
 passes/techmap/flowmap.cc | 35 ++++++++++++++++++-----------------
 1 file changed, 18 insertions(+), 17 deletions(-)

diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index f938efeee..ddbd7bf5d 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -769,7 +769,7 @@ struct FlowmapWorker
 		}
 	}
 
-	int pack_luts()
+	int map_luts()
 	{
 		pool<RTLIL::SigBit> worklist = outputs;
 		while (!worklist.empty())
@@ -784,12 +784,12 @@ struct FlowmapWorker
 		int depth = 0;
 		for (auto label : labels)
 			depth = max(depth, label.second);
-		log("Solved to %d LUTs with maximum depth %d.\n", (int)lut_nodes.size(), depth);
+		log("Mapped to %zu LUTs with maximum depth %d.\n", lut_nodes.size(), depth);
 
 		if (debug)
 		{
-			dump_dot_lut_graph("flowmap-packed.dot", GraphMode::Label);
-			log("Dumped packed graph to `flowmap-packed.dot`.\n");
+			dump_dot_lut_graph("flowmap-mapped.dot", GraphMode::Label);
+			log("Dumped mapped graph to `flowmap-mapped.dot`.\n");
 		}
 
 		return depth;
@@ -1196,6 +1196,8 @@ struct FlowmapWorker
 
 	bool relax_depth_for_bound(bool first, int depth_bound, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> &lut_critical_outputs)
 	{
+		size_t initial_count = lut_nodes.size();
+
 		for (auto node : lut_nodes)
 		{
 			lut_slacks[node] = depth_bound - (lut_depths[node] + lut_altitudes[node]);
@@ -1214,7 +1216,7 @@ struct FlowmapWorker
 
 			if (potentials.empty())
 			{
-				log("  Relaxed to %d LUTs.\n", (int)lut_nodes.size());
+				log("  Relaxed to %zu (+%zu) LUTs.\n", lut_nodes.size(), lut_nodes.size() - initial_count);
 				if (!first && break_num == 1)
 				{
 					log("  Design fully relaxed.\n");
@@ -1338,7 +1340,7 @@ struct FlowmapWorker
 		}
 	}
 
-	void map_cells(int minlut)
+	void pack_cells(int minlut)
 	{
 		ConstEval ce(module);
 		for (auto input_node : inputs)
@@ -1351,15 +1353,15 @@ struct FlowmapWorker
 			{
 				auto origin = node_origins[node];
 				if (origin.cell->getPort(origin.port).size() == 1)
-					log("Mapping %s.%s.%s (%s).\n",
+					log("Packing %s.%s.%s (%s).\n",
 					    log_id(module), log_id(origin.cell), origin.port.c_str(), log_signal(node));
 				else
-					log("Mapping %s.%s.%s [%d] (%s).\n",
+					log("Packing %s.%s.%s [%d] (%s).\n",
 					    log_id(module), log_id(origin.cell), origin.port.c_str(), origin.offset, log_signal(node));
 			}
 			else
 			{
-				log("Mapping %s.%s.\n", log_id(module), log_signal(node));
+				log("Packing %s.%s.\n", log_id(module), log_signal(node));
 			}
 
 			for (auto gate_node : lut_gates[node])
@@ -1417,9 +1419,9 @@ struct FlowmapWorker
 			lut_area += lut_table.size();
 
 			if ((int)input_nodes.size() >= minlut)
-				log("  Packed into a %d-LUT %s.%s.\n", (int)input_nodes.size(), log_id(module), log_id(lut));
+				log("  Packed into a %zu-LUT %s.%s.\n", input_nodes.size(), log_id(module), log_id(lut));
 			else
-				log("  Packed into a %d-LUT %s.%s (implemented as %d-LUT).\n", (int)input_nodes.size(), log_id(module), log_id(lut), minlut);
+				log("  Packed into a %zu-LUT %s.%s (implemented as %d-LUT).\n", input_nodes.size(), log_id(module), log_id(lut), minlut);
 		}
 
 		for (auto node : mapped_nodes)
@@ -1440,7 +1442,7 @@ struct FlowmapWorker
 		log("Labeling cells.\n");
 		discover_nodes(cell_types);
 		label_nodes();
-		int depth = pack_luts();
+		int depth = map_luts();
 
 		if (relax)
 		{
@@ -1450,8 +1452,8 @@ struct FlowmapWorker
 		}
 
 		log("\n");
-		log("Mapping cells.\n");
-		map_cells(minlut);
+		log("Packing cells.\n");
+		pack_cells(minlut);
 	}
 };
 
@@ -1603,9 +1605,8 @@ struct FlowmapPass : public Pass {
 		}
 
 		log("\n");
-		log("Mapped %d LUTs.\n", lut_count);
-		log("Packed %d cells; duplicated %d cells.\n", packed_count, packed_count - gate_count);
-		log("Solution has %.1f%% area overhead.\n", (lut_area - gate_area) * 100.0 / gate_area);
+		log("Packed %d cells (%d of them duplicated) into %d LUTs.\n", packed_count, packed_count - gate_count, lut_count);
+		log("Solution takes %.1f%% of original gate area.\n", lut_area * 100.0 / gate_area);
 	}
 } FlowmapPass;
 

From 2a2e0a4722ded7628b71f436b94a06aebd57bb62 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 8 Jan 2019 20:16:36 +0100
Subject: [PATCH 297/528] Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore              |  3 ++-
 examples/igloo2/example.ys              |  3 ++-
 examples/igloo2/libero.tcl              | 27 ++++++++++++++++++++++---
 examples/igloo2/{libero.sh => runme.sh} |  1 +
 4 files changed, 29 insertions(+), 5 deletions(-)
 rename examples/igloo2/{libero.sh => runme.sh} (88%)

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
index ae86e69cc..fa3c3d7ed 100644
--- a/examples/igloo2/.gitignore
+++ b/examples/igloo2/.gitignore
@@ -1,2 +1,3 @@
-/example.edn
+/netlist.edn
+/netlist.v
 /work
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
index 75a305d86..872f97b99 100644
--- a/examples/igloo2/example.ys
+++ b/examples/igloo2/example.ys
@@ -1,2 +1,3 @@
 read_verilog example.v
-synth_sf2 -top top -edif example.edn
+synth_sf2 -top top -edif netlist.edn
+write_verilog netlist.v
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index cc1ab2403..9f6d3b792 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -9,6 +9,27 @@ new_project \
     -speed -1 \
     -hdl VERILOG
 
-import_files -edif {example.edn}
-run_tool –name {COMPILE}
-run_tool –name {PLACEROUTEN}
+# import_files -edif "[pwd]/netlist.edn"
+
+import_files -hdl_source "[pwd]/netlist.v"
+set_root top
+
+save_project
+
+puts "**> SYNTHESIZE"
+run_tool -name {SYNTHESIZE}
+puts "<** SYNTHESIZE"
+
+puts "**> COMPILE"
+run_tool -name {COMPILE}
+puts "<** COMPILE"
+
+puts "**> PLACEROUTE"
+run_tool -name {PLACEROUTE}
+puts "<** PLACEROUTE"
+
+# puts "**> export_bitstream"
+# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
+# puts "<** export_bitstream"
+
+exit 0
diff --git a/examples/igloo2/libero.sh b/examples/igloo2/runme.sh
similarity index 88%
rename from examples/igloo2/libero.sh
rename to examples/igloo2/runme.sh
index 582f6ccb9..4edfb5409 100644
--- a/examples/igloo2/libero.sh
+++ b/examples/igloo2/runme.sh
@@ -1,4 +1,5 @@
 #!/bin/bash
 set -ex
 rm -rf work
+yosys example.ys
 LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl

From 7a45122168d06a416f1341e1adf0760cc4c462b8 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 14 Jan 2019 16:08:58 +0000
Subject: [PATCH 298/528] manual: explain $tribuf cell.

---
 manual/CHAPTER_CellLib.tex | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index e22664a82..464f7d1a9 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -119,6 +119,12 @@ than one bit from \B{S} is set the output is undefined. Cells of this type are u
 ``parallel cases'' (defined by using the {\tt parallel\_case} attribute or detected by
 an optimization).
 
+The {\tt \$tribuf} cell is used to implement tristate logic. Cells of this type have a \B{WIDTH}
+parameter and inputs \B{A} and \B{EN} and an output \B{Y}. The \B{A} input and \B{Y} output are
+\B{WIDTH} bits wide, and the \B{EN} input is one bit wide. When \B{EN} is 0, the output \B{Y}
+is not driven. When \B{EN} is 1, the value from \B{A} input is sent to the \B{Y} output. Therefore,
+the {\tt \$tribuf} cell implements the function \lstinline[language=Verilog]; Y = EN ? A : 'bz;.
+
 Behavioural code with cascaded {\tt if-then-else}- and {\tt case}-statements
 usually results in trees of multiplexer cells. Many passes (from various
 optimizations to FSM extraction) heavily depend on these multiplexer trees to
@@ -476,6 +482,10 @@ Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dl
 Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
 \end{fixme}
 
+\begin{fixme}
+Add information about {\tt \$\_TBUF\_} cells.
+\end{fixme}
+
 \begin{fixme}
 Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_ORNOT\_},
 {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.

From fc2dd7ec8e433bf54fffdb85e9aa2556fe3e39a2 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Mon, 14 Jan 2019 16:17:25 +0000
Subject: [PATCH 299/528] manual: document some gates.

---
 manual/CHAPTER_CellLib.tex | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 464f7d1a9..e64919182 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -404,9 +404,15 @@ Verilog & Cell Type \\
 \hline
 \lstinline[language=Verilog]; Y = ~A;    & {\tt \$\_NOT\_} \\
 \lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\
+\lstinline[language=Verilog]; Y = ~(A & B); & {\tt \$\_NAND\_} \\
+\lstinline[language=Verilog]; Y = A & ~B; & {\tt \$\_ANDNOT\_} \\
 \lstinline[language=Verilog]; Y = A | B; & {\tt \$\_OR\_} \\
+\lstinline[language=Verilog]; Y = ~(A | B); & {\tt \$\_NOR\_} \\
+\lstinline[language=Verilog]; Y = A | ~B; & {\tt \$\_ORNOT\_} \\
 \lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\
+\lstinline[language=Verilog]; Y = ~(A ^ B); & {\tt \$\_XNOR\_} \\
 \lstinline[language=Verilog]; Y = S ? B : A; & {\tt \$\_MUX\_} \\
+\lstinline[language=Verilog]; Y = EN ? A : 'bz; & {\tt \$\_TBUF\_} \\
 \hline
 \lstinline[language=Verilog]; always @(negedge C) Q <= D; & {\tt \$\_DFF\_N\_} \\
 \lstinline[language=Verilog]; always @(posedge C) Q <= D; & {\tt \$\_DFF\_P\_} \\
@@ -429,9 +435,10 @@ $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\
 \end{table}
 
 Table~\ref{tab:CellLib_gates} lists all cell types used for gate level logic. The cell types
-{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_}
-are used to model combinatorial logic. The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_}
-represent d-type flip-flops.
+{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_NAND\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_OR\_}, {\tt \$\_NOR\_},
+{\tt \$\_ORNOT\_}, {\tt \$\_XOR\_}, {\tt \$\_XNOR\_} and {\tt \$\_MUX\_} are used to model combinatorial logic.
+The cell type {\tt \$\_TBUF\_} is used to model tristate logic.
+The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_} represent d-type flip-flops.
 
 The cell types {\tt \$\_DFF\_NN0\_}, {\tt \$\_DFF\_NN1\_}, {\tt \$\_DFF\_NP0\_}, {\tt \$\_DFF\_NP1\_},
 {\tt \$\_DFF\_PN0\_}, {\tt \$\_DFF\_PN1\_}, {\tt \$\_DFF\_PP0\_} and {\tt \$\_DFF\_PP1\_} implement
@@ -483,11 +490,6 @@ Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLA
 \end{fixme}
 
 \begin{fixme}
-Add information about {\tt \$\_TBUF\_} cells.
-\end{fixme}
-
-\begin{fixme}
-Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_ANDNOT\_}, {\tt \$\_ORNOT\_},
-{\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
+Add information about {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
 \end{fixme}
 

From 6c5049f016538e887476bb66d3f653155fa354ff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 15 Jan 2019 10:55:27 +0100
Subject: [PATCH 300/528] Fix handling of $shiftx in Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 2537e18e5..8da3c0627 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -709,11 +709,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->type == "$shiftx")
 	{
+		std::string temp_id = next_auto_id();
+		f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort("\\A"))-1, temp_id.c_str());
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(";\n");
+
 		f << stringf("%s" "assign ", indent.c_str());
 		dump_sigspec(f, cell->getPort("\\Y"));
-		f << stringf(" = ");
-		dump_sigspec(f, cell->getPort("\\A"));
-		f << stringf("[");
+		f << stringf(" = %s[", temp_id.c_str());
 		if (cell->getParam("\\B_SIGNED").as_bool())
 			f << stringf("$signed(");
 		dump_sigspec(f, cell->getPort("\\B"));

From e70ebe557cd02f52f32a297fa63008dba25e4f6a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 13 Jan 2019 17:00:58 +0100
Subject: [PATCH 301/528] Add optional nullstr argument to log_id()

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/log.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/kernel/log.h b/kernel/log.h
index e1f54a197..759939025 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -94,7 +94,9 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint = true);
 const char *log_const(const RTLIL::Const &value, bool autoint = true);
 const char *log_id(RTLIL::IdString id);
 
-template<typename T> static inline const char *log_id(T *obj) {
+template<typename T> static inline const char *log_id(T *obj, const char *nullstr = nullptr) {
+	if (nullstr && obj == nullptr)
+		return nullstr;
 	return log_id(obj->name);
 }
 

From ad69c668cedaab76f84c982411d7cddbd868cccf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 11 Jan 2019 14:02:16 +0100
Subject: [PATCH 302/528] Add mockup .pmg (pattern matcher generator) file

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.pmg | 75 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 passes/pmgen/ice40_dsp.pmg

diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
new file mode 100644
index 000000000..5a0af3e04
--- /dev/null
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -0,0 +1,75 @@
+state SigBit clock
+state bool clock_pol, clock_vld
+state SigSpec sigA, sigB, sigY
+
+match mul
+	select mul->type.in($mul)
+	select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
+	select GetSize(mul->getPort(\Y)) > 10
+endmatch
+
+match ffA
+	select ffA->type.in($dff)
+	filter port(ffA, \Q) === port(mul, \A)
+	optional
+endmatch
+
+code sigA clock clock_pol clock_vld
+	sigA = port(mul, \A);
+
+	if (ffA != nullptr) {
+		sigA = port(ffA, \D);
+
+		clock = port(ffA, \CLK).as_bit();
+		clock_pol = param(ffA, \CLK_POLARITY).as_bool();
+		clock_vld = true;
+	}
+endcode
+
+match ffB
+	select ffB->type.in($dff)
+	filter port(ffB, \Q) === port(mul, \B)
+	optional
+endmatch
+
+code sigB clock clok_pol clock_vld
+	sigB = port(mul, \B);
+
+	if (ffB != nullptr) {
+		sigB = port(ffB, \D);
+		SigBit c = port(ffB, \CLK).as_bit();
+		bool cp = param(ffB, \CLK_POLARITY).as_bool();
+
+		if (clock_vld && (c != clock || cp != clock_pol))
+			reject;
+
+		clock = c;
+		clock_pol = cp;
+		clock_vld = true;
+	}
+endcode
+
+match ffY
+	select ffY->type.in($dff)
+	filter port(ffY, \D) === port(mul, \Y)
+	optional
+endmatch
+
+code sigY clock clok_pol clock_vld
+	sigY = port(mul, \Y);
+
+	if (ffY != nullptr) {
+		sigY = port(ffY, \D);
+		SigBit c = port(ffY, \CLK).as_bit();
+		bool cp = param(ffY, \CLK_POLARITY).as_bool();
+
+		if (clock_vld && (c != clock || cp != clock_pol))
+			reject;
+
+		clock = c;
+		clock_pol = cp;
+		clock_vld = true;
+	}
+
+	accept;
+endcode

From b9545aa0e1260f3d7123ec63e9dcfb0e022e2ff3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 13 Jan 2019 10:57:11 +0100
Subject: [PATCH 303/528] Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/.gitignore    |   1 +
 passes/pmgen/Makefile.inc  |   8 ++
 passes/pmgen/ice40_dsp.cc  |  65 +++++++++
 passes/pmgen/ice40_dsp.pmg |  19 +--
 passes/pmgen/pmgen.py      | 262 +++++++++++++++++++++++++++++++++++++
 5 files changed, 347 insertions(+), 8 deletions(-)
 create mode 100644 passes/pmgen/.gitignore
 create mode 100644 passes/pmgen/Makefile.inc
 create mode 100644 passes/pmgen/ice40_dsp.cc
 create mode 100644 passes/pmgen/pmgen.py

diff --git a/passes/pmgen/.gitignore b/passes/pmgen/.gitignore
new file mode 100644
index 000000000..c9263057e
--- /dev/null
+++ b/passes/pmgen/.gitignore
@@ -0,0 +1 @@
+/ice40_dsp_pm.h
diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
new file mode 100644
index 000000000..33baaca30
--- /dev/null
+++ b/passes/pmgen/Makefile.inc
@@ -0,0 +1,8 @@
+OBJS += passes/pmgen/ice40_dsp.o
+
+passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
+EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
+.SECONDARY: passes/pmgen/ice40_dsp_pm.h
+
+passes/pmgen/ice40_dsp_pm.h: passes/pmgen/ice40_dsp.pmg passes/pmgen/pmgen.py
+	$(P) cd passes/pmgen && python3 pmgen.py ice40_dsp
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
new file mode 100644
index 000000000..0498f31b7
--- /dev/null
+++ b/passes/pmgen/ice40_dsp.cc
@@ -0,0 +1,65 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "passes/pmgen/ice40_dsp_pm.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+void ice40_dsp_accept(ice40_dsp_pm * /* pm */)
+{
+}
+
+struct Ice40DspPass : public Pass {
+	Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_dsp [options] [selection]\n");
+		log("\n");
+		log("Map multipliers and iCE40 DSP resources.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			ice40_dsp_pm pm(module);
+			pm.run(ice40_dsp_accept);
+		}
+	}
+} Ice40DspPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 5a0af3e04..2b9bb8783 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,6 +1,6 @@
-state SigBit clock
-state bool clock_pol, clock_vld
-state SigSpec sigA, sigB, sigY
+state <SigBit> clock
+state <bool> clock_pol clock_vld
+state <SigSpec> sigA sigB sigY
 
 match mul
 	select mul->type.in($mul)
@@ -10,7 +10,8 @@ endmatch
 
 match ffA
 	select ffA->type.in($dff)
-	filter port(ffA, \Q) === port(mul, \A)
+	select nusers(port(ffA, \Q)) == 2
+	filter <SigSpec> port(ffA, \Q) === port(mul, \A)
 	optional
 endmatch
 
@@ -28,11 +29,12 @@ endcode
 
 match ffB
 	select ffB->type.in($dff)
-	filter port(ffB, \Q) === port(mul, \B)
+	select nusers(port(ffA, \Q)) == 2
+	filter <SigSpec> port(ffB, \Q) === port(mul, \B)
 	optional
 endmatch
 
-code sigB clock clok_pol clock_vld
+code sigB clock clock_pol clock_vld
 	sigB = port(mul, \B);
 
 	if (ffB != nullptr) {
@@ -51,11 +53,12 @@ endcode
 
 match ffY
 	select ffY->type.in($dff)
-	filter port(ffY, \D) === port(mul, \Y)
+	select nusers(port(ffY, \D)) == 2
+	filter <SigSpec> port(ffY, \D) === port(mul, \Y)
 	optional
 endmatch
 
-code sigY clock clok_pol clock_vld
+code sigY clock clock_pol clock_vld
 	sigY = port(mul, \Y);
 
 	if (ffY != nullptr) {
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
new file mode 100644
index 000000000..bf70a6dbd
--- /dev/null
+++ b/passes/pmgen/pmgen.py
@@ -0,0 +1,262 @@
+#!/usr/bin/env python3
+
+import re
+import sys
+import pprint
+
+pp = pprint.PrettyPrinter(indent=4)
+
+prefix = sys.argv[1]
+
+state_types = dict()
+blocks = list()
+ids = dict()
+
+def rewrite_cpp(s):
+    t = list()
+    i = 0
+    while i < len(s):
+        if s[i] in ("'", '"') and i + 1 < len(s):
+            j = i + 1
+            while j + 1 < len(s) and s[j] != s[i]:
+                if s[j] == '\\' and j + 1 < len(s):
+                    j += 1
+                j += 1
+            t.append(s[i:j+1])
+            i = j + 1
+            continue
+
+        if s[i] in ('$', '\\') and i + 1 < len(s):
+            j = i + 1
+            while True:
+                if j == len(s):
+                    j -= 1
+                    break
+                if ord('a') <= ord(s[j]) <= ord('z'):
+                    j += 1
+                    continue
+                if ord('A') <= ord(s[j]) <= ord('Z'):
+                    j += 1
+                    continue
+                if ord('0') <= ord(s[j]) <= ord('9'):
+                    j += 1
+                    continue
+                if s[j] == '_':
+                    j += 1
+                    continue
+                j -= 1
+                break
+
+            n = s[i:j+1]
+            i = j + 1
+
+            if n[0] == '$':
+                v = "id_d_" + n[1:]
+            else:
+                v = "id_b_" + n[1:]
+
+            if v not in ids:
+                ids[v] = n
+            else:
+                assert ids[v] == n
+
+            t.append(v)
+            continue
+
+        if s[i] == "\t":
+            t.append("  ")
+        else:
+            t.append(s[i])
+
+        i += 1
+
+    return "".join(t)
+
+with open("%s.pmg" % prefix, "r") as f:
+    while True:
+        line = f.readline()
+        if line == "": break
+        line = line.strip()
+
+        cmd = line.split()
+        if len(cmd) == 0: continue
+        cmd = cmd[0]
+        
+        if cmd == "state":
+            m = re.match(r"^state\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line)
+            assert m
+            type_str = m.group(1)
+            states_str = m.group(2)
+            for s in re.split(r"\s+", states_str):
+                assert s not in state_types
+                state_types[s] = type_str
+            continue
+
+        if cmd == "match":
+            block = dict()
+            block["type"] = "match"
+
+            line = line.split()
+            assert len(line) == 2
+            assert line[1] not in state_types
+            block["cell"] = line[1]
+            state_types[line[1]] = "Cell*";
+
+            block["select"] = list()
+            block["filter"] = list()
+            block["optional"] = False
+
+            while True:
+                l = f.readline()
+                assert l != ""
+                a = l.split()
+                if len(a) == 0: continue
+                if a[0] == "endmatch": break
+
+                if a[0] == "select":
+                    b = l.lstrip()[6:]
+                    block["select"].append(rewrite_cpp(b.strip()))
+                    continue
+
+                if a[0] == "filter":
+                    m = re.match(r"^\s*filter\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l)
+                    assert m
+                    block["filter"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3))))
+                    continue
+
+                if a[0] == "optional":
+                    block["optional"] = True
+                    continue
+
+                assert False
+
+            blocks.append(block)
+
+        if cmd == "code":
+            block = dict()
+            block["type"] = "code"
+            block["code"] = list()
+            block["states"] = set()
+
+            for s in line.split()[1:]:
+                assert s in state_types
+                block["states"].add(s)
+
+            while True:
+                l = f.readline()
+                assert l != ""
+                a = l.split()
+                if len(a) == 0: continue
+                if a[0] == "endcode": break
+
+                block["code"].append(rewrite_cpp(l.rstrip()))
+
+            blocks.append(block)
+
+# pp.pprint(blocks)
+
+with open("%s_pm.h" % prefix, "w") as f:
+    print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f)
+    print("#include \"kernel/yosys.h\"", file=f)
+    print("#include \"kernel/sigtools.h\"", file=f)
+    print("YOSYS_NAMESPACE_BEGIN", file=f)
+    print("struct {}_pm {{".format(prefix), file=f)
+    print("  Module *module;", file=f)
+    print("  SigMap sigmap;", file=f)
+    print("  std::function<void(struct {}_pm*)> on_accept;".format(prefix), file=f)
+    print("", file=f)
+
+    for index in range(len(blocks)):
+        block = blocks[index]
+        if block["type"] == "match":
+            index_types = list()
+            for filt in block["filter"]:
+                index_types.append(filt[0])
+            print("  typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
+            print("  dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
+    print("  pool<Cell*> blacklist;", file=f)
+    print("", file=f)
+
+    print("  struct state_t {", file=f)
+    
+    for s, t in sorted(state_types.items()):
+        print("    {} {};".format(t, s), file=f)
+    print("  } st;", file=f)
+    print("", file=f)
+
+    for v, n in sorted(ids.items()):
+        if n[0] == "\\":
+            print("  IdString {}{{\"\\{}\"}};".format(v, n), file=f)
+        else:
+            print("  IdString {}{{\"{}\"}};".format(v, n), file=f)
+    print("", file=f)
+
+    print("  {}_pm(Module *module) :".format(prefix), file=f)
+    print("      module(module), sigmap(module) {", file=f)
+    print("  }", file=f)
+
+    print("", file=f)
+    print("  void run(std::function<void(struct {}_pm*)> on_accept_f) {{".format(prefix), file=f)
+    print("    on_accept = on_accept_f;", file=f)
+    if len(blocks):
+        print("    block_0();", file=f)
+    print("  }", file=f)
+
+    for index in range(len(blocks)):
+        block = blocks[index]
+
+        print("", file=f)
+        print("  void block_{}() {{".format(index), file=f)
+
+        const_st = set()
+        nonconst_st = set()
+        restore_st = set()
+
+        for i in range(index):
+            if blocks[i]["type"] == "code":
+                for s in blocks[i]["states"]:
+                    const_st.add(s)
+            elif blocks[i]["type"] == "match":
+                const_st.add(blocks[i]["cell"])
+            else:
+                assert False
+
+        if block["type"] == "code":
+            for s in block["states"]:
+                if s in const_st:
+                    const_st.remove(s)
+                    restore_st.add(s)
+                nonconst_st.add(s)
+        elif block["type"] == "match":
+            s = block["cell"]
+            assert s not in const_st
+            nonconst_st.add(s)
+        else:
+            assert False
+
+        for s in sorted(const_st):
+            t = state_types[s]
+            if t.endswith("*"):
+                print("    {} const &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f)
+            else:
+                print("    const {} &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f)
+
+        for s in sorted(nonconst_st):
+            t = state_types[s]
+            print("    {} &{} YS_ATTRIBUTE(unused) = st.{};".format(t, s, s), file=f)
+
+        if len(restore_st):
+            print("", file=f)
+            for s in sorted(restore_st):
+                t = state_types[s]
+                print("    {} backup_{} = st.{};".format(t, s, s), file=f)
+
+        if len(restore_st):
+            print("", file=f)
+            for s in sorted(restore_st):
+                t = state_types[s]
+                print("    st.{} = backup_{};".format(s, s), file=f)
+
+        print("  }", file=f)
+
+    print("};\nYOSYS_NAMESPACE_END", file=f)

From 1f8e76f993b602bb8b03af216615a248bbde3652 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 13 Jan 2019 12:53:13 +0100
Subject: [PATCH 304/528] Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.cc  |  11 ++-
 passes/pmgen/ice40_dsp.pmg |   6 +-
 passes/pmgen/pmgen.py      | 163 +++++++++++++++++++++++++++++++++----
 3 files changed, 158 insertions(+), 22 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 0498f31b7..049ef6c0e 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -24,8 +24,15 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-void ice40_dsp_accept(ice40_dsp_pm * /* pm */)
+void ice40_dsp_accept(ice40_dsp_pm *pm)
 {
+	log("\n");
+	log("mul: %s\n", pm->st.mul ? log_id(pm->st.mul) : "--");
+	log("ffA: %s\n", pm->st.ffA ? log_id(pm->st.ffA) : "--");
+	log("ffB: %s\n", pm->st.ffB ? log_id(pm->st.ffB) : "--");
+	log("ffY: %s\n", pm->st.ffY ? log_id(pm->st.ffY) : "--");
+
+	pm->blacklist(pm->st.mul);
 }
 
 struct Ice40DspPass : public Pass {
@@ -56,7 +63,7 @@ struct Ice40DspPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
-			ice40_dsp_pm pm(module);
+			ice40_dsp_pm pm(module, module->cells());
 			pm.run(ice40_dsp_accept);
 		}
 	}
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 2b9bb8783..a2937ddc6 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -10,7 +10,7 @@ endmatch
 
 match ffA
 	select ffA->type.in($dff)
-	select nusers(port(ffA, \Q)) == 2
+	// select nusers(port(ffA, \Q)) == 2
 	filter <SigSpec> port(ffA, \Q) === port(mul, \A)
 	optional
 endmatch
@@ -29,7 +29,7 @@ endcode
 
 match ffB
 	select ffB->type.in($dff)
-	select nusers(port(ffA, \Q)) == 2
+	// select nusers(port(ffB, \Q)) == 2
 	filter <SigSpec> port(ffB, \Q) === port(mul, \B)
 	optional
 endmatch
@@ -73,6 +73,4 @@ code sigY clock clock_pol clock_vld
 		clock_pol = cp;
 		clock_vld = true;
 	}
-
-	accept;
 endcode
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index bf70a6dbd..7d33c4fc9 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -79,7 +79,7 @@ with open("%s.pmg" % prefix, "r") as f:
         line = line.strip()
 
         cmd = line.split()
-        if len(cmd) == 0: continue
+        if len(cmd) == 0 or cmd[0].startswith("//"): continue
         cmd = cmd[0]
         
         if cmd == "state":
@@ -110,7 +110,7 @@ with open("%s.pmg" % prefix, "r") as f:
                 l = f.readline()
                 assert l != ""
                 a = l.split()
-                if len(a) == 0: continue
+                if len(a) == 0 or a[0].startswith("//"): continue
                 if a[0] == "endmatch": break
 
                 if a[0] == "select":
@@ -153,13 +153,17 @@ with open("%s.pmg" % prefix, "r") as f:
 
             blocks.append(block)
 
-# pp.pprint(blocks)
-
 with open("%s_pm.h" % prefix, "w") as f:
     print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f)
+    print("", file=f)
+
     print("#include \"kernel/yosys.h\"", file=f)
     print("#include \"kernel/sigtools.h\"", file=f)
+    print("", file=f)
+
     print("YOSYS_NAMESPACE_BEGIN", file=f)
+    print("", file=f)
+
     print("struct {}_pm {{".format(prefix), file=f)
     print("  Module *module;", file=f)
     print("  SigMap sigmap;", file=f)
@@ -174,7 +178,9 @@ with open("%s_pm.h" % prefix, "w") as f:
                 index_types.append(filt[0])
             print("  typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
             print("  dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
-    print("  pool<Cell*> blacklist;", file=f)
+    print("  dict<SigBit, pool<Cell*>> sigusers;", file=f)
+    print("  pool<Cell*> blacklist_cells;", file=f)
+    print("  int rollback;", file=f)
     print("", file=f)
 
     print("  struct state_t {", file=f)
@@ -191,21 +197,89 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("  IdString {}{{\"{}\"}};".format(v, n), file=f)
     print("", file=f)
 
-    print("  {}_pm(Module *module) :".format(prefix), file=f)
-    print("      module(module), sigmap(module) {", file=f)
+    print("  void add_siguser(const SigSpec &sig, Cell *cell) {", file=f)
+    print("    for (auto bit : sigmap(sig)) {", file=f)
+    print("      if (bit.wire == nullptr) continue;", file=f)
+    print("      if (sigusers.count(bit) == 0 && bit.wire->port_id)", file=f)
+    print("        sigusers[bit].insert(nullptr);", file=f)
+    print("      sigusers[bit].insert(cell);", file=f)
+    print("    }", file=f)
     print("  }", file=f)
-
     print("", file=f)
+
+    print("  void blacklist(Cell *cell) {", file=f)
+    print("    blacklist_cells.insert(cell);", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
+    print("  void check_blacklist() {", file=f)
+    for index in range(len(blocks)):
+        block = blocks[index]
+        if block["type"] == "match":
+            print("    if (st.{} != nullptr && blacklist_cells.count(st.{})) {{".format(block["cell"], block["cell"]), file=f)
+            print("      rollback = {};".format(index+1), file=f)
+            print("      return;", file=f)
+            print("    }", file=f)
+    print("    rollback = 0;", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
+    print("  SigSpec port(Cell *cell, IdString portname) {", file=f)
+    print("    return sigmap(cell->getPort(portname));", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
+    print("  Const param(Cell *cell, IdString paramname) {", file=f)
+    print("    return cell->getParam(paramname);", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
+    print("  int nusers(const SigSpec &sig) {", file=f)
+    print("    pool<Cell*> users;", file=f)
+    print("    for (auto bit : sigmap(sig))", file=f)
+    print("      for (auto user : sigusers[bit])", file=f)
+    print("        users.insert(user);", file=f)
+    print("    return GetSize(users);", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
+    print("  {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
+    print("      module(module), sigmap(module) {", file=f)
+    print("    for (auto cell : cells) {", file=f)
+    print("      for (auto &conn : cell->connections())", file=f)
+    print("        add_siguser(conn.second, cell);", file=f)
+
+    for index in range(len(blocks)):
+        block = blocks[index]
+        if block["type"] == "match":
+            print("      do {", file=f)
+            print("        Cell *{} = cell;".format(block["cell"]), file=f)
+            for expr in block["select"]:
+                print("        if (!({})) break;".format(expr), file=f)
+            print("        index_{}_key_type key;".format(index), file=f)
+            for field, filt in enumerate(block["filter"]):
+                print("        std::get<{}>(key) = {};".format(field, filt[1]), file=f)
+            print("        index_{}[key].push_back(cell);".format(index), file=f)
+            print("      } while (0);", file=f)
+
+    print("    }", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
     print("  void run(std::function<void(struct {}_pm*)> on_accept_f) {{".format(prefix), file=f)
     print("    on_accept = on_accept_f;", file=f)
-    if len(blocks):
-        print("    block_0();", file=f)
+    print("    rollback = 0;", file=f)
+    print("    block_0();", file=f)
     print("  }", file=f)
+    print("", file=f)
+
+    print("#define reject break", file=f)
+    print("#define accept do { on_accept(this); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
+    print("", file=f)
 
     for index in range(len(blocks)):
         block = blocks[index]
 
-        print("", file=f)
         print("  void block_{}() {{".format(index), file=f)
 
         const_st = set()
@@ -251,12 +325,69 @@ with open("%s_pm.h" % prefix, "w") as f:
                 t = state_types[s]
                 print("    {} backup_{} = st.{};".format(t, s, s), file=f)
 
-        if len(restore_st):
+        if block["type"] == "code":
             print("", file=f)
-            for s in sorted(restore_st):
-                t = state_types[s]
-                print("    st.{} = backup_{};".format(s, s), file=f)
+            print("    do {", file=f)
+            for line in block["code"]:
+                print("    " + line, file=f)
+
+            print("", file=f)
+            print("      block_{}();".format(index+1), file=f)
+            print("rollback_label: YS_ATTRIBUTE(unused);", file=f)
+            print("    } while (0);", file=f)
+
+            if len(restore_st):
+                print("", file=f)
+                for s in sorted(restore_st):
+                    t = state_types[s]
+                    print("    st.{} = backup_{};".format(s, s), file=f)
+
+        elif block["type"] == "match":
+            assert len(restore_st) == 0
+
+            print("", file=f)
+            print("    index_{}_key_type key;".format(index), file=f)
+            for field, filt in enumerate(block["filter"]):
+                print("    std::get<{}>(key) = {};".format(field, filt[2]), file=f)
+            print("    const vector<Cell*> &cells = index_{}[key];".format(index), file=f)
+
+            print("", file=f)
+            print("    for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
+            print("      {} = cells[idx];".format(block["cell"]), file=f)
+            print("      block_{}();".format(index+1), file=f)
+            print("      if (rollback) {", file=f)
+            print("        if (rollback != {}) {{".format(index+1), file=f)
+            print("          {} = nullptr;".format(block["cell"]), file=f)
+            print("          return;", file=f)
+            print("        }", file=f)
+            print("        rollback = 0;", file=f)
+            print("      }", file=f)
+            print("    }", file=f)
+
+            print("", file=f)
+            print("    {} = nullptr;".format(block["cell"]), file=f)
+
+            if block["optional"]:
+                print("    block_{}();".format(index+1), file=f)
+
+        else:
+            assert False
+
 
         print("  }", file=f)
+        print("", file=f)
 
-    print("};\nYOSYS_NAMESPACE_END", file=f)
+    print("#undef reject", file=f)
+    print("#undef accept", file=f)
+    print("", file=f)
+
+    print("  void block_{}() {{".format(len(blocks)), file=f)
+    print("    on_accept(this);", file=f)
+    print("    check_blacklist();", file=f)
+    print("  }", file=f)
+    print("};", file=f)
+
+    print("", file=f)
+    print("YOSYS_NAMESPACE_END", file=f)
+
+# pp.pprint(blocks)

From d45379936b82a26b713e40d92f3e73cf03bcf7cc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 13 Jan 2019 17:03:58 +0100
Subject: [PATCH 305/528] Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.cc  | 29 ++++++++-------
 passes/pmgen/ice40_dsp.pmg | 74 ++++++++++++++++++++++++++++++++++----
 passes/pmgen/pmgen.py      | 72 ++++++++++++++++++++++++++++---------
 3 files changed, 139 insertions(+), 36 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 049ef6c0e..a8f63ebfe 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -24,17 +24,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-void ice40_dsp_accept(ice40_dsp_pm *pm)
-{
-	log("\n");
-	log("mul: %s\n", pm->st.mul ? log_id(pm->st.mul) : "--");
-	log("ffA: %s\n", pm->st.ffA ? log_id(pm->st.ffA) : "--");
-	log("ffB: %s\n", pm->st.ffB ? log_id(pm->st.ffB) : "--");
-	log("ffY: %s\n", pm->st.ffY ? log_id(pm->st.ffY) : "--");
-
-	pm->blacklist(pm->st.mul);
-}
-
 struct Ice40DspPass : public Pass {
 	Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
 	void help() YS_OVERRIDE
@@ -64,7 +53,23 @@ struct Ice40DspPass : public Pass {
 		for (auto module : design->selected_modules())
 		{
 			ice40_dsp_pm pm(module, module->cells());
-			pm.run(ice40_dsp_accept);
+			pm.match([&]()
+			{
+				log("\n");
+				log("ffA:   %s\n", log_id(pm.st.ffA, "--"));
+				log("ffB:   %s\n", log_id(pm.st.ffB, "--"));
+				log("mul:   %s\n", log_id(pm.st.mul, "--"));
+				log("ffY:   %s\n", log_id(pm.st.ffY, "--"));
+				log("addAB: %s\n", log_id(pm.st.addAB, "--"));
+				log("muxAB: %s\n", log_id(pm.st.muxAB, "--"));
+				log("ffS:   %s\n", log_id(pm.st.ffS, "--"));
+
+				pm.blacklist(pm.st.mul);
+				pm.blacklist(pm.st.ffA);
+				pm.blacklist(pm.st.ffB);
+				pm.blacklist(pm.st.ffY);
+				pm.blacklist(pm.st.ffS);
+			});
 		}
 	}
 } Ice40DspPass;
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index a2937ddc6..1370cb66a 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -1,6 +1,7 @@
 state <SigBit> clock
 state <bool> clock_pol clock_vld
-state <SigSpec> sigA sigB sigY
+state <SigSpec> sigA sigB sigY sigS
+state <Cell*> addAB muxAB
 
 match mul
 	select mul->type.in($mul)
@@ -11,14 +12,14 @@ endmatch
 match ffA
 	select ffA->type.in($dff)
 	// select nusers(port(ffA, \Q)) == 2
-	filter <SigSpec> port(ffA, \Q) === port(mul, \A)
+	index <SigSpec> port(ffA, \Q) === port(mul, \A)
 	optional
 endmatch
 
 code sigA clock clock_pol clock_vld
 	sigA = port(mul, \A);
 
-	if (ffA != nullptr) {
+	if (ffA) {
 		sigA = port(ffA, \D);
 
 		clock = port(ffA, \CLK).as_bit();
@@ -30,14 +31,14 @@ endcode
 match ffB
 	select ffB->type.in($dff)
 	// select nusers(port(ffB, \Q)) == 2
-	filter <SigSpec> port(ffB, \Q) === port(mul, \B)
+	index <SigSpec> port(ffB, \Q) === port(mul, \B)
 	optional
 endmatch
 
 code sigB clock clock_pol clock_vld
 	sigB = port(mul, \B);
 
-	if (ffB != nullptr) {
+	if (ffB) {
 		sigB = port(ffB, \D);
 		SigBit c = port(ffB, \CLK).as_bit();
 		bool cp = param(ffB, \CLK_POLARITY).as_bool();
@@ -54,14 +55,14 @@ endcode
 match ffY
 	select ffY->type.in($dff)
 	select nusers(port(ffY, \D)) == 2
-	filter <SigSpec> port(ffY, \D) === port(mul, \Y)
+	index <SigSpec> port(ffY, \D) === port(mul, \Y)
 	optional
 endmatch
 
 code sigY clock clock_pol clock_vld
 	sigY = port(mul, \Y);
 
-	if (ffY != nullptr) {
+	if (ffY) {
 		sigY = port(ffY, \D);
 		SigBit c = port(ffY, \CLK).as_bit();
 		bool cp = param(ffY, \CLK_POLARITY).as_bool();
@@ -74,3 +75,62 @@ code sigY clock clock_pol clock_vld
 		clock_vld = true;
 	}
 endcode
+
+match addA
+	select addA->type.in($add, $sub)
+	select nusers(port(addA, \A)) == 2
+	index <SigSpec> port(addA, \A) === sigY
+	optional
+endmatch
+
+match addB
+	if !addA
+	select addB->type.in($add, $sub)
+	select nusers(port(addB, \B)) == 2
+	index <SigSpec> port(addB, \B) === sigY
+	optional
+endmatch
+
+code addAB sigS
+	if (addA) {
+		addAB = addA;
+		sigS = port(addA, \B);
+	}
+	if (addB) {
+		addAB = addB;
+		sigS = port(addB, \A);
+	}
+endcode
+
+match muxA
+	if addAB
+	select muxA->type.in($mux)
+	select nusers(port(muxA, \A)) == 2
+	index <SigSpec> port(muxA, \A) === port(addAB, \Y)
+	optional
+endmatch
+
+match muxB
+	if addAB
+	if !muxA
+	select muxB->type.in($mux)
+	select nusers(port(muxB, \B)) == 2
+	index <SigSpec> port(muxB, \B) === port(addAB, \Y)
+	optional
+endmatch
+
+code muxAB
+	muxAB = addAB;
+	if (muxA)
+		muxAB = muxA;
+	if (muxB)
+		muxAB = muxB;
+endcode
+
+match ffS
+	if muxAB
+	select ffS->type.in($dff)
+	select nusers(port(ffS, \D)) == 2
+	index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
+	index <SigSpec> port(ffS, \Q) === sigS
+endmatch
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 7d33c4fc9..88d60d298 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -102,7 +102,9 @@ with open("%s.pmg" % prefix, "r") as f:
             block["cell"] = line[1]
             state_types[line[1]] = "Cell*";
 
+            block["if"] = list()
             block["select"] = list()
+            block["index"] = list()
             block["filter"] = list()
             block["optional"] = False
 
@@ -113,15 +115,25 @@ with open("%s.pmg" % prefix, "r") as f:
                 if len(a) == 0 or a[0].startswith("//"): continue
                 if a[0] == "endmatch": break
 
+                if a[0] == "if":
+                    b = l.lstrip()[2:]
+                    block["if"].append(rewrite_cpp(b.strip()))
+                    continue
+
                 if a[0] == "select":
                     b = l.lstrip()[6:]
                     block["select"].append(rewrite_cpp(b.strip()))
                     continue
 
-                if a[0] == "filter":
-                    m = re.match(r"^\s*filter\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l)
+                if a[0] == "index":
+                    m = re.match(r"^\s*index\s+<(.*?)>\s+(.*?)\s*===\s*(.*?)\s*$", l)
                     assert m
-                    block["filter"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3))))
+                    block["index"].append((m.group(1), rewrite_cpp(m.group(2)), rewrite_cpp(m.group(3))))
+                    continue
+
+                if a[0] == "filter":
+                    b = l.lstrip()[6:]
+                    block["filter"].append(rewrite_cpp(b.strip()))
                     continue
 
                 if a[0] == "optional":
@@ -167,15 +179,15 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("struct {}_pm {{".format(prefix), file=f)
     print("  Module *module;", file=f)
     print("  SigMap sigmap;", file=f)
-    print("  std::function<void(struct {}_pm*)> on_accept;".format(prefix), file=f)
+    print("  std::function<void()> on_accept;".format(prefix), file=f)
     print("", file=f)
 
     for index in range(len(blocks)):
         block = blocks[index]
         if block["type"] == "match":
             index_types = list()
-            for filt in block["filter"]:
-                index_types.append(filt[0])
+            for entry in block["index"]:
+                index_types.append(entry[0])
             print("  typedef std::tuple<{}> index_{}_key_type;".format(", ".join(index_types), index), file=f)
             print("  dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
     print("  dict<SigBit, pool<Cell*>> sigusers;", file=f)
@@ -208,7 +220,8 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("", file=f)
 
     print("  void blacklist(Cell *cell) {", file=f)
-    print("    blacklist_cells.insert(cell);", file=f)
+    print("    if (cell != nullptr)", file=f)
+    print("      blacklist_cells.insert(cell);", file=f)
     print("  }", file=f)
     print("", file=f)
 
@@ -248,6 +261,8 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("    for (auto cell : cells) {", file=f)
     print("      for (auto &conn : cell->connections())", file=f)
     print("        add_siguser(conn.second, cell);", file=f)
+    print("    }", file=f)
+    print("    for (auto cell : cells) {", file=f)
 
     for index in range(len(blocks)):
         block = blocks[index]
@@ -257,8 +272,8 @@ with open("%s_pm.h" % prefix, "w") as f:
             for expr in block["select"]:
                 print("        if (!({})) break;".format(expr), file=f)
             print("        index_{}_key_type key;".format(index), file=f)
-            for field, filt in enumerate(block["filter"]):
-                print("        std::get<{}>(key) = {};".format(field, filt[1]), file=f)
+            for field, entry in enumerate(block["index"]):
+                print("        std::get<{}>(key) = {};".format(field, entry[1]), file=f)
             print("        index_{}[key].push_back(cell);".format(index), file=f)
             print("      } while (0);", file=f)
 
@@ -266,15 +281,20 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  void run(std::function<void(struct {}_pm*)> on_accept_f) {{".format(prefix), file=f)
+    print("  void match(std::function<void()> on_accept_f) {{".format(prefix), file=f)
     print("    on_accept = on_accept_f;", file=f)
     print("    rollback = 0;", file=f)
+    for s, t in sorted(state_types.items()):
+        if t.endswith("*"):
+            print("    st.{} = nullptr;".format(s), file=f)
+        else:
+            print("    st.{} = {}();".format(s, t), file=f)
     print("    block_0();", file=f)
     print("  }", file=f)
     print("", file=f)
 
     print("#define reject break", file=f)
-    print("#define accept do { on_accept(this); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
+    print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
     print("", file=f)
 
     for index in range(len(blocks)):
@@ -323,7 +343,7 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("", file=f)
             for s in sorted(restore_st):
                 t = state_types[s]
-                print("    {} backup_{} = st.{};".format(t, s, s), file=f)
+                print("    {} backup_{} = {};".format(t, s, s), file=f)
 
         if block["type"] == "code":
             print("", file=f)
@@ -336,24 +356,42 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("rollback_label: YS_ATTRIBUTE(unused);", file=f)
             print("    } while (0);", file=f)
 
-            if len(restore_st):
+            if len(restore_st) or len(nonconst_st):
                 print("", file=f)
                 for s in sorted(restore_st):
                     t = state_types[s]
-                    print("    st.{} = backup_{};".format(s, s), file=f)
+                    print("    {} = backup_{};".format(s, s), file=f)
+                for s in sorted(nonconst_st):
+                    if s not in restore_st:
+                        t = state_types[s]
+                        if t.endswith("*"):
+                            print("    {} = nullptr;".format(s), file=f)
+                        else:
+                            print("    {} = {}();".format(s, t), file=f)
 
         elif block["type"] == "match":
             assert len(restore_st) == 0
 
+            if len(block["if"]):
+                for expr in block["if"]:
+                    print("", file=f)
+                    print("    if (!({})) {{".format(expr), file=f)
+                    print("      {} = nullptr;".format(block["cell"]), file=f)
+                    print("      block_{}();".format(index+1), file=f)
+                    print("      return;", file=f)
+                    print("    }", file=f)
+
             print("", file=f)
             print("    index_{}_key_type key;".format(index), file=f)
-            for field, filt in enumerate(block["filter"]):
-                print("    std::get<{}>(key) = {};".format(field, filt[2]), file=f)
+            for field, entry in enumerate(block["index"]):
+                print("    std::get<{}>(key) = {};".format(field, entry[2]), file=f)
             print("    const vector<Cell*> &cells = index_{}[key];".format(index), file=f)
 
             print("", file=f)
             print("    for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
             print("      {} = cells[idx];".format(block["cell"]), file=f)
+            for expr in block["filter"]:
+                print("      if (!({})) continue;".format(expr), file=f)
             print("      block_{}();".format(index+1), file=f)
             print("      if (rollback) {", file=f)
             print("        if (rollback != {}) {{".format(index+1), file=f)
@@ -382,7 +420,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("", file=f)
 
     print("  void block_{}() {{".format(len(blocks)), file=f)
-    print("    on_accept(this);", file=f)
+    print("    on_accept();", file=f)
     print("    check_blacklist();", file=f)
     print("  }", file=f)
     print("};", file=f)

From 55ac03038270f4a70da5e579dd317487e20fe6cf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 13 Jan 2019 17:15:40 +0100
Subject: [PATCH 306/528] Fix pmgen "reject" statement

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/pmgen.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 88d60d298..6486278d4 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -293,7 +293,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("#define reject break", file=f)
+    print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f)
     print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
     print("", file=f)
 

From 5216735210f1b081f84c8ec110acb1cf9c3a0555 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 14 Jan 2019 13:29:27 +0100
Subject: [PATCH 307/528] Progress in pmgen, add pmgen README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/README.md    | 224 ++++++++++++++++++++++++++++++++++++++
 passes/pmgen/ice40_dsp.cc |   4 +-
 passes/pmgen/pmgen.py     |  46 ++++++--
 3 files changed, 260 insertions(+), 14 deletions(-)
 create mode 100644 passes/pmgen/README.md

diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
new file mode 100644
index 000000000..27e54b43e
--- /dev/null
+++ b/passes/pmgen/README.md
@@ -0,0 +1,224 @@
+Pattern Matcher Generator
+=========================
+
+The program `pmgen.py` reads a `.pmg` (Pattern Matcher Generator) file and
+writes a header-only C++ library that implements that pattern matcher.
+
+The "patterns" in this context are subgraphs in a Yosys RTLIL netlist.
+
+The algorithm used in the generated pattern matcher is a simple recursive
+search with backtracking. It is left to the author of the `.pmg` file to
+determine an efficient cell order for the search that allows for maximum
+use of indices and early backtracking.
+
+
+API of Generated Matcher
+========================
+
+When `pmgen.py` reads a `foobar.pmg` file, it writes `foobar_pm.h` containing
+a class `foobar_pm`. That class is instanciated with an RTLIL module and a
+list of cells from that module:
+
+    foobar_pm pm(module, module->selected_cells());
+
+The caller must make sure that none of the cells in the 2nd argument are
+deleted for as long as the patter matcher instance is used.
+
+At any time it is possible to disable cells, preventing them from showing
+up in any future matches:
+
+    pm.blacklist(some_cell);
+
+The `.run(callback_function)` method searches for all matches and calls the
+callback function for each found match:
+
+    pm.run([&](){
+        log("found matching 'foo' cell: %s\n", log_id(pm.st.foo));
+        log("          with 'bar' cell: %s\n", log_id(pm.st.bar));
+    });
+
+The `.pmg` file declares matcher state variables that are accessible via the
+`.st.<state_name>` members. (The `.st` member is of type `foobar_pm::state_t`.)
+
+Similarly the `.pmg` file declares user data variables that become members of
+`.ud`, a struct of type `foobar_pm::udata_t`.
+
+
+The .pmg File Format
+====================
+
+The `.pmg` file format is a simple line-based file format. For the most part
+lines consist of whitespace-separated tokens.
+
+Lines in `.pmg` files starting with `//` are comments.
+
+Declaring state variables
+-------------------------
+
+One or more state variables can be declared using the `state` statement,
+followed by a C++ type in angle brackets, followed by a whitespace separated
+list of variable names. For example:
+
+    state <bool> flag1 flag2 happy big
+    state <SigSpec> sigA sigB sigY
+
+State variables are automatically managed by the generated backtracking algorithm
+and saved and restored as needed.
+
+They are atomatically initialzed to the default constructed value of their type
+when `.run(callback_function)` is called.
+
+Declaring udata variables
+-------------------------
+
+Udata (user-data) variables can be used for example to configure the matcher or
+the callback function used to perform actions on found matches.
+
+There is no automatic management of udata variables. For this reason it is
+recommended that the user-supplied matcher code treats them as read-only
+variables.
+
+They are declared like state variables, just using the `udata` statement:
+
+    udata <int> min_data_width max_data_width
+    udata <IdString> data_port_name
+
+They are atomatically initialzed to the default constructed value of their type
+when ther pattern matcher object is constructed.
+
+Embedded C++ code
+-----------------
+
+Many statements in a `.pmg` file contain C++ code. However, there are some
+slight additions to regular C++/Yosys/RTLIL code that make it a bit easier to
+write matchers:
+
+- Identifiers starting with a dollar sign or backslash are automatically
+  converted to special IdString variables that are initialized when the
+  matcher object is constructed.
+
+- The `port(<cell>, <portname>)` function is a handy alias for
+  `sigmap(<cell>->getPort(<portname>))`.
+
+- Similarly `param(<cell>, <paramname>)` looks up a parameter on a cell.
+
+- The function `nusers(<sigspec>)` returns the number of different cells
+  connected to any of the given signal bits, plus one if any of the signal
+  bits is also a primary input or primary output.
+
+- In `code..endcode` blocks there exist `accept`, `reject`, and `branch`
+  statements.
+
+- In `index` statements there is a special `===` operator for the index
+  lookup.
+
+Matching cells
+--------------
+
+Cells are matched using `match..endmatch` blocks. For example:
+
+    match mul
+        if ff
+        select mul->type == $mul
+        select nusers(port(mul, \Y) == 2
+        index <SigSpec> port(mul, \Y) === port(ff, \D)
+        filter some_weird_function(mul) < other_weird_function(ff)
+        optional
+    endmatch
+
+A `match` block starts with `match <statevar>` and implicitly generates
+a state variable `<statevar>` of type `RTLIL::Cell*`.
+
+All statements in the match block are optional. (An empty match block
+would simply match each and every cell in the module.)
+
+The `if <expression>` statement makes the match block conditional. If
+`<expression>` evaluates to `false` then the match block will be ignored
+and the corresponding state variable is set to `nullptr`. In our example
+we only try to match the `mul` cell if the `ff` state variable points
+to a cell. (Presumably `ff` is provided by a prior `match` block.)
+
+The `select` lines are evaluated once for each cell when the matcher is
+initialized. A `match` block will only consider cells for which all `select`
+expressions evaluated to `true`. Note that the state variable corresponding to
+the match (in the example `mul`) is the only state variable that may be used
+`select` lines.
+
+Index lines are using the `index <type> expr1 === expr2` syntax.  `expr1` is
+evaluated during matcher initialization and the same restrictions apply as for
+`select` expressions. `expr2` is evaluated when the match is calulated. It is a
+function of any state variables assigned to by previous blocks. Both expression
+are converted to the given type and compared for equality. Only cells for which
+all `index` statements in the block pass are considered by the match.
+
+Note that `select` and `index` are fast operations. Thus `select` and `index`
+should be used whenever possible to create efficient matchers.
+
+Finally, `filter <expression>` narrows down the remaining list of cells. For
+performance reasons `filter` statements should only be used for things that
+can't be done using `select` and `index`.
+
+The `optional` statement marks optional matches. I.e. the matcher will also
+explore the case where `mul` is set to `nullptr`. Without the `optional`
+statement a match may only be assigned nullptr when one of the `if` expressions
+evaluates to `false`.
+
+Additional code
+---------------
+
+Interleaved with `match..endmatch` blocks there may be `code..endcode` blocks.
+Such a block starts with the keyword `code` followed by a list of state variables
+that the block may modify. For example:
+
+    code addAB sigS
+        if (addA) {
+            addAB = addA;
+            sigS = port(addA, \B);
+        }
+        if (addB) {
+            addAB = addB;
+            sigS = port(addB, \A);
+        }
+    endcode
+
+The special keyword `reject` can be used to reject the current state and
+backtrack. For example:
+
+    code
+        if (ffA && ffB) {
+            if (port(ffA, \CLK) != port(ffB, \CLK))
+                reject;
+            if (param(ffA, \CLK_POLARITY) != param(ffB, \CLK_POLARITY))
+                reject;
+        }
+    endcode
+
+Similarly, the special keyword `accept` can be used to accept the current
+state. (`accept` will not backtrack. This means it continues with the current
+branch and may accept a larger match later.)
+
+The special keyword `branch` can be used to explore different cases. Note that
+each code block has an implicit `branch` at the end. So most use-cases of the
+`branch` keyword need to end the block with `reject` to avoid the implicit
+branch at the end. For example:
+
+    state <int> mode
+
+    code mode
+        for (mode = 0; mode < 8; mode++)
+            branch;
+        reject;
+    endcode
+
+But in some cases it is more natural to utilize the implicit branch statement:
+
+    state <IdString> portAB
+
+    code portAB
+        portAB = \A;
+        branch;
+        portAB = \B;
+    endcode
+
+There is an implicit `code..endcode` block at the end of each `.pgm` file
+that just accepts everything that gets all the way there.
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index a8f63ebfe..78b5bad33 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -52,8 +52,8 @@ struct Ice40DspPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
-			ice40_dsp_pm pm(module, module->cells());
-			pm.match([&]()
+			ice40_dsp_pm pm(module, module->selected_cells());
+			pm.run([&]()
 			{
 				log("\n");
 				log("ffA:   %s\n", log_id(pm.st.ffA, "--"));
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 6486278d4..885f6db1c 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -9,6 +9,7 @@ pp = pprint.PrettyPrinter(indent=4)
 prefix = sys.argv[1]
 
 state_types = dict()
+udata_types = dict()
 blocks = list()
 ids = dict()
 
@@ -92,6 +93,16 @@ with open("%s.pmg" % prefix, "r") as f:
                 state_types[s] = type_str
             continue
 
+        if cmd == "udata":
+            m = re.match(r"^udata\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line)
+            assert m
+            type_str = m.group(1)
+            udatas_str = m.group(2)
+            for s in re.split(r"\s+", udatas_str):
+                assert s not in udata_types
+                udata_types[s] = type_str
+            continue
+
         if cmd == "match":
             block = dict()
             block["type"] = "match"
@@ -196,12 +207,17 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("", file=f)
 
     print("  struct state_t {", file=f)
-    
     for s, t in sorted(state_types.items()):
         print("    {} {};".format(t, s), file=f)
     print("  } st;", file=f)
     print("", file=f)
 
+    print("  struct udata_t {", file=f)
+    for s, t in sorted(udata_types.items()):
+        print("    {} {};".format(t, s), file=f)
+    print("  } ud;", file=f)
+    print("", file=f)
+
     for v, n in sorted(ids.items()):
         if n[0] == "\\":
             print("  IdString {}{{\"\\{}\"}};".format(v, n), file=f)
@@ -258,7 +274,12 @@ with open("%s_pm.h" % prefix, "w") as f:
 
     print("  {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
     print("      module(module), sigmap(module) {", file=f)
-    print("    for (auto cell : cells) {", file=f)
+    for s, t in sorted(udata_types.items()):
+        if t.endswith("*"):
+            print("    ud.{} = nullptr;".format(s), file=f)
+        else:
+            print("    ud.{} = {}();".format(s, t), file=f)
+    print("    for (auto cell : module->cells()) {", file=f)
     print("      for (auto &conn : cell->connections())", file=f)
     print("        add_siguser(conn.second, cell);", file=f)
     print("    }", file=f)
@@ -281,7 +302,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  void match(std::function<void()> on_accept_f) {{".format(prefix), file=f)
+    print("  void run(std::function<void()> on_accept_f) {{".format(prefix), file=f)
     print("    on_accept = on_accept_f;", file=f)
     print("    rollback = 0;", file=f)
     for s, t in sorted(state_types.items()):
@@ -293,10 +314,6 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f)
-    print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
-    print("", file=f)
-
     for index in range(len(blocks)):
         block = blocks[index]
 
@@ -348,13 +365,22 @@ with open("%s_pm.h" % prefix, "w") as f:
         if block["type"] == "code":
             print("", file=f)
             print("    do {", file=f)
+            print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f)
+            print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
+            print("#define branch do {{ block_{}(); }} while(0)".format(index+1), file=f)
+
             for line in block["code"]:
                 print("    " + line, file=f)
 
             print("", file=f)
             print("      block_{}();".format(index+1), file=f)
-            print("rollback_label: YS_ATTRIBUTE(unused);", file=f)
+            print("#undef reject", file=f)
+            print("#undef accept", file=f)
+            print("#undef branch", file=f)
             print("    } while (0);", file=f)
+            print("", file=f)
+            print("rollback_label:", file=f)
+            print("    YS_ATTRIBUTE(unused);", file=f)
 
             if len(restore_st) or len(nonconst_st):
                 print("", file=f)
@@ -415,10 +441,6 @@ with open("%s_pm.h" % prefix, "w") as f:
         print("  }", file=f)
         print("", file=f)
 
-    print("#undef reject", file=f)
-    print("#undef accept", file=f)
-    print("", file=f)
-
     print("  void block_{}() {{".format(len(blocks)), file=f)
     print("    on_accept();", file=f)
     print("    check_blacklist();", file=f)

From 8ddec5d882c6834cb6b3415e05a2a88d416cabff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 14 Jan 2019 13:42:42 +0100
Subject: [PATCH 308/528] Progress in pmgen

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/pmgen.py | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 885f6db1c..a59cf5a81 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -203,6 +203,7 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("  dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
     print("  dict<SigBit, pool<Cell*>> sigusers;", file=f)
     print("  pool<Cell*> blacklist_cells;", file=f)
+    print("  bool blacklist_dirty;", file=f)
     print("  int rollback;", file=f)
     print("", file=f)
 
@@ -236,12 +237,17 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("", file=f)
 
     print("  void blacklist(Cell *cell) {", file=f)
-    print("    if (cell != nullptr)", file=f)
-    print("      blacklist_cells.insert(cell);", file=f)
+    print("    if (cell != nullptr) {", file=f)
+    print("      if (blacklist_cells.insert(cell).second)", file=f)
+    print("        blacklist_dirty = true;", file=f)
+    print("    }", file=f)
     print("  }", file=f)
     print("", file=f)
 
     print("  void check_blacklist() {", file=f)
+    print("    if (!blacklist_dirty)", file=f)
+    print("      return;", file=f)
+    print("    blacklist_dirty = false;", file=f)
     for index in range(len(blocks)):
         block = blocks[index]
         if block["type"] == "match":
@@ -305,6 +311,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  void run(std::function<void()> on_accept_f) {{".format(prefix), file=f)
     print("    on_accept = on_accept_f;", file=f)
     print("    rollback = 0;", file=f)
+    print("    blacklist_dirty = false;", file=f)
     for s, t in sorted(state_types.items()):
         if t.endswith("*"):
             print("    st.{} = nullptr;".format(s), file=f)
@@ -367,7 +374,7 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("    do {", file=f)
             print("#define reject do { check_blacklist(); goto rollback_label; } while(0)", file=f)
             print("#define accept do { on_accept(); check_blacklist(); if (rollback) goto rollback_label; } while(0)", file=f)
-            print("#define branch do {{ block_{}(); }} while(0)".format(index+1), file=f)
+            print("#define branch do {{ block_{}(); if (rollback) goto rollback_label; }} while(0)".format(index+1), file=f)
 
             for line in block["code"]:
                 print("    " + line, file=f)
@@ -416,6 +423,7 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("", file=f)
             print("    for (int idx = 0; idx < GetSize(cells); idx++) {", file=f)
             print("      {} = cells[idx];".format(block["cell"]), file=f)
+            print("      if (blacklist_cells.count({})) continue;".format(block["cell"]), file=f)
             for expr in block["filter"]:
                 print("      if (!({})) continue;".format(expr), file=f)
             print("      block_{}();".format(index+1), file=f)

From 54dc33b90518d8962d949a8f8b25842f720ac670 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 13:33:11 +0100
Subject: [PATCH 309/528] Add "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/edif/edif.cc | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index d4e56a9eb..2d25f879d 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -106,6 +106,10 @@ struct EdifBackend : public Backend {
 		log("        if the design contains constant nets. use \"hilomap\" to map to custom\n");
 		log("        constant drivers first)\n");
 		log("\n");
+		log("    -gndvccy\n");
+		log("        create \"GND\" and \"VCC\" cells with \"Y\" outputs. (the default is \"G\"\n");
+		log("        for \"GND\" and \"P\" for \"VCC\".)\n");
+		log("\n");
 		log("    -attrprop\n");
 		log("        create EDIF properties for cell attributes\n");
 		log("\n");
@@ -126,7 +130,7 @@ struct EdifBackend : public Backend {
 		bool port_rename = false;
 		bool attr_properties = false;
 		std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
-		bool nogndvcc = false;
+		bool nogndvcc = false, gndvccy = true;
 		CellTypes ct(design);
 		EdifNames edif_names;
 
@@ -141,6 +145,10 @@ struct EdifBackend : public Backend {
 				nogndvcc = true;
 				continue;
 			}
+			if (args[argidx] == "-gndvccy") {
+				gndvccy = true;
+				continue;
+			}
 			if (args[argidx] == "-attrprop") {
 				attr_properties = true;
 				continue;
@@ -211,7 +219,7 @@ struct EdifBackend : public Backend {
 			*f << stringf("      (cellType GENERIC)\n");
 			*f << stringf("      (view VIEW_NETLIST\n");
 			*f << stringf("        (viewType NETLIST)\n");
-			*f << stringf("        (interface (port G (direction OUTPUT)))\n");
+			*f << stringf("        (interface (port %c (direction OUTPUT)))\n", gndvccy ? 'Y' : 'G');
 			*f << stringf("      )\n");
 			*f << stringf("    )\n");
 
@@ -219,7 +227,7 @@ struct EdifBackend : public Backend {
 			*f << stringf("      (cellType GENERIC)\n");
 			*f << stringf("      (view VIEW_NETLIST\n");
 			*f << stringf("        (viewType NETLIST)\n");
-			*f << stringf("        (interface (port P (direction OUTPUT)))\n");
+			*f << stringf("        (interface (port %c (direction OUTPUT)))\n", gndvccy ? 'Y' : 'P');
 			*f << stringf("      )\n");
 			*f << stringf("    )\n");
 		}
@@ -420,9 +428,9 @@ struct EdifBackend : public Backend {
 					if (nogndvcc)
 						log_error("Design contains constant nodes (map with \"hilomap\" first).\n");
 					if (sig == RTLIL::State::S0)
-						*f << stringf("            (portRef G (instanceRef GND))\n");
+						*f << stringf("            (portRef %c (instanceRef GND))\n", gndvccy ? 'Y' : 'G');
 					if (sig == RTLIL::State::S1)
-						*f << stringf("            (portRef P (instanceRef VCC))\n");
+						*f << stringf("            (portRef %c (instanceRef VCC))\n", gndvccy ? 'Y' : 'P');
 				}
 				*f << stringf("          ))\n");
 			}

From 841ca74c90872985ae4e128608260b4a38d04762 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 13:33:45 +0100
Subject: [PATCH 310/528] Add "synth_sf2 -vlog", fix "synth_sf2 -edif"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/sf2/synth_sf2.cc | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 62b3cd0e2..6828a4298 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -44,6 +44,10 @@ struct SynthSf2Pass : public ScriptPass
 		log("        write the design to the specified EDIF file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
 		log("\n");
+		log("    -vlog <file>\n");
+		log("        write the design to the specified Verilog file. writing of an output file\n");
+		log("        is omitted if this parameter is not specified.\n");
+		log("\n");
 		log("    -json <file>\n");
 		log("        write the design to the specified JSON file. writing of an output file\n");
 		log("        is omitted if this parameter is not specified.\n");
@@ -65,13 +69,14 @@ struct SynthSf2Pass : public ScriptPass
 		log("\n");
 	}
 
-	string top_opt, edif_file, json_file;
+	string top_opt, edif_file, vlog_file, json_file;
 	bool flatten, retime;
 
 	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		edif_file = "";
+		vlog_file = "";
 		json_file = "";
 		flatten = true;
 		retime = false;
@@ -93,6 +98,10 @@ struct SynthSf2Pass : public ScriptPass
 				edif_file = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-vlog" && argidx+1 < args.size()) {
+				vlog_file = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-json" && argidx+1 < args.size()) {
 				json_file = args[++argidx];
 				continue;
@@ -192,7 +201,13 @@ struct SynthSf2Pass : public ScriptPass
 		if (check_label("edif"))
 		{
 			if (!edif_file.empty() || help_mode)
-				run(stringf("write_edif %s", help_mode ? "<file-name>" : edif_file.c_str()));
+				run(stringf("write_edif -gndvccy %s", help_mode ? "<file-name>" : edif_file.c_str()));
+		}
+
+		if (check_label("vlog"))
+		{
+			if (!vlog_file.empty() || help_mode)
+				run(stringf("write_verilog %s", help_mode ? "<file-name>" : vlog_file.c_str()));
 		}
 
 		if (check_label("json"))

From 9b277fc21ea455a0e0ca9b7acde039e90ddb380d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 13:35:52 +0100
Subject: [PATCH 311/528] Improve Igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore     |  4 ++--
 examples/igloo2/example.fp.pdc |  0
 examples/igloo2/example.io.pdc |  0
 examples/igloo2/example.sdc    |  0
 examples/igloo2/example.v      |  2 +-
 examples/igloo2/example.ys     |  4 ++--
 examples/igloo2/libero.tcl     | 42 +++++++++++++++++++++++++---------
 examples/igloo2/runme.sh       |  3 +--
 8 files changed, 37 insertions(+), 18 deletions(-)
 create mode 100644 examples/igloo2/example.fp.pdc
 create mode 100644 examples/igloo2/example.io.pdc
 create mode 100644 examples/igloo2/example.sdc

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
index fa3c3d7ed..ea58efc9f 100644
--- a/examples/igloo2/.gitignore
+++ b/examples/igloo2/.gitignore
@@ -1,3 +1,3 @@
 /netlist.edn
-/netlist.v
-/work
+/netlist.vm
+/proj
diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 3eb7007c5..0e336e557 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,4 +1,4 @@
-module top (
+module example (
 	input  clk,
 	output LED1,
 	output LED2,
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
index 872f97b99..04ea02672 100644
--- a/examples/igloo2/example.ys
+++ b/examples/igloo2/example.ys
@@ -1,3 +1,3 @@
 read_verilog example.v
-synth_sf2 -top top -edif netlist.edn
-write_verilog netlist.v
+synth_sf2 -top example -edif netlist.edn
+write_verilog netlist.vm
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 9f6d3b792..b2090f402 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -1,24 +1,38 @@
 # Run with "libero SCRIPT:libero.tcl"
 
+file delete -force proj
+
 new_project \
-    -name top \
-    -location work \
+    -name example \
+    -location proj \
+    -block_mode 1 \
+    -hdl "VERILOG" \
     -family IGLOO2 \
     -die PA4MGL500 \
     -package tq144 \
-    -speed -1 \
-    -hdl VERILOG
+    -speed -1
 
-# import_files -edif "[pwd]/netlist.edn"
+import_files -hdl_source {netlist.vm}
+import_files -sdc {example.sdc}
+import_files -io_pdc {example.io.pdc}
+import_files -fp_pdc {example.fp.pdc}
+set_option -synth 0
 
-import_files -hdl_source "[pwd]/netlist.v"
-set_root top
+organize_tool_files -tool PLACEROUTE \
+    -file {proj/constraint/example.sdc} \
+    -file {proj/constraint/io/example.io.pdc} \
+    -file {proj/constraint/fp/example.fp.pdc} \
+    -input_type constraint
 
-save_project
+organize_tool_files -tool VERIFYTIMING \
+    -file {proj/constraint/example.sdc} \
+    -input_type constraint
 
-puts "**> SYNTHESIZE"
-run_tool -name {SYNTHESIZE}
-puts "<** SYNTHESIZE"
+configure_tool -name PLACEROUTE \
+    -params TDPR:true \
+    -params PDPR:false \
+    -params EFFORT_LEVEL:false \
+    -params REPAIR_MIN_DELAY:false
 
 puts "**> COMPILE"
 run_tool -name {COMPILE}
@@ -28,6 +42,12 @@ puts "**> PLACEROUTE"
 run_tool -name {PLACEROUTE}
 puts "<** PLACEROUTE"
 
+puts "**> VERIFYTIMING"
+run_tool -name {VERIFYTIMING}
+puts "<** VERIFYTIMING"
+
+save_project
+
 # puts "**> export_bitstream"
 # export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
 # puts "<** export_bitstream"
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 4edfb5409..54247759f 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,5 +1,4 @@
 #!/bin/bash
 set -ex
-rm -rf work
-yosys example.ys
+yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
 LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl

From db5765b443c26b5b2dc3ac56d5a448fc8b861d43 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 14:38:37 +0100
Subject: [PATCH 312/528] Add SF2 IO buffer insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.v  |   3 +-
 examples/igloo2/libero.tcl |   2 +-
 techlibs/sf2/Makefile.inc  |   1 +
 techlibs/sf2/cells_sim.v   |  21 ++++++
 techlibs/sf2/sf2_iobs.cc   | 130 +++++++++++++++++++++++++++++++++++++
 techlibs/sf2/synth_sf2.cc  |  17 ++++-
 6 files changed, 171 insertions(+), 3 deletions(-)
 create mode 100644 techlibs/sf2/sf2_iobs.cc

diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 0e336e557..1a1967d5a 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,5 +1,6 @@
 module example (
 	input  clk,
+	input  EN,
 	output LED1,
 	output LED2,
 	output LED3,
@@ -14,7 +15,7 @@ module example (
 	reg [BITS-1:0] outcnt;
 
 	always @(posedge clk) begin
-		counter <= counter + 1;
+		counter <= counter + EN;
 		outcnt <= counter >> LOG2DELAY;
 	end
 
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index b2090f402..952342a4c 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -5,7 +5,7 @@ file delete -force proj
 new_project \
     -name example \
     -location proj \
-    -block_mode 1 \
+    -block_mode 0 \
     -hdl "VERILOG" \
     -family IGLOO2 \
     -die PA4MGL500 \
diff --git a/techlibs/sf2/Makefile.inc b/techlibs/sf2/Makefile.inc
index cade49f37..cc3054ace 100644
--- a/techlibs/sf2/Makefile.inc
+++ b/techlibs/sf2/Makefile.inc
@@ -1,5 +1,6 @@
 
 OBJS += techlibs/sf2/synth_sf2.o
+OBJS += techlibs/sf2/sf2_iobs.o
 
 $(eval $(call add_share_file,share/sf2,techlibs/sf2/arith_map.v))
 $(eval $(call add_share_file,share/sf2,techlibs/sf2/cells_map.v))
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index b03b2c750..f967068af 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -73,3 +73,24 @@ module CFG4 (
 	parameter [15:0] INIT = 16'h0;
 	assign Y = INIT >> {D, C, B, A};
 endmodule
+
+module CLKBUF (
+	input PAD,
+	output Y
+);
+	assign Y = PAD;
+endmodule
+
+module INBUF (
+	input PAD,
+	output Y
+);
+	assign Y = PAD;
+endmodule
+
+module OUTBUF (
+	input D,
+	output PAD
+);
+	assign PAD = D;
+endmodule
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
new file mode 100644
index 000000000..27141430c
--- /dev/null
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -0,0 +1,130 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Sf2IobsPass : public Pass {
+	Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    sf2_iobs [options] [selection]\n");
+		log("\n");
+		log("Add SF2 I/O buffers to top module IOs as needed.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		Module *module = design->top_module();
+
+		if (module == nullptr)
+			log_cmd_error("No top module found.\n");
+
+		SigMap sigmap(module);
+
+		pool<SigBit> clk_bits;
+		pool<SigBit> handled_io_bits;
+		dict<SigBit, SigBit> rewrite_bits;
+		vector<pair<Cell*, SigBit>> pad_bits;
+
+		for (auto cell : module->cells())
+		{
+			if (cell->type == "\\SLE") {
+				for (auto bit : sigmap(cell->getPort("\\CLK")))
+					clk_bits.insert(bit);
+			}
+			if (cell->type.in("\\INBUF", "\\OUTBUF", "\\CLKBUF")) {
+				for (auto bit : sigmap(cell->getPort("\\PAD")))
+					handled_io_bits.insert(bit);
+			}
+		}
+
+		for (auto wire : vector<Wire*>(module->wires()))
+		{
+			if (!wire->port_input && !wire->port_output)
+				continue;
+
+			for (int index = 0; index < GetSize(wire); index++)
+			{
+				SigBit bit(wire, index);
+				SigBit canonical_bit = sigmap(bit);
+
+				if (handled_io_bits.count(canonical_bit))
+					continue;
+
+				if (wire->port_input && wire->port_output)
+					log_error("Failed to add buffer for inout port bit %s.\n", log_signal(bit));
+
+				IdString buf_type, buf_port;
+
+				if (wire->port_output) {
+					buf_type = "\\OUTBUF";
+					buf_port = "\\D";
+				} else if (clk_bits.count(canonical_bit)) {
+					buf_type = "\\CLKBUF";
+					buf_port = "\\Y";
+				} else {
+					buf_type = "\\INBUF";
+					buf_port = "\\Y";
+				}
+
+				Cell *c = module->addCell(NEW_ID, buf_type);
+				SigBit new_bit = module->addWire(NEW_ID);
+				c->setPort(buf_port, new_bit);
+				pad_bits.push_back(make_pair(c, bit));
+				rewrite_bits[canonical_bit] = new_bit;
+
+				log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
+			}
+		}
+
+		auto rewrite_function = [&](SigSpec &s) {
+			for (auto &bit : s) {
+				SigBit canonical_bit = sigmap(bit);
+				if (rewrite_bits.count(canonical_bit))
+					bit = rewrite_bits.at(canonical_bit);
+			}
+		};
+
+		module->rewrite_sigspecs(rewrite_function);
+
+		for (auto &it : pad_bits)
+			it.first->setPort("\\PAD", it.second);
+	}
+} Sf2IobsPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 6828a4298..bdc20456d 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -60,6 +60,9 @@ struct SynthSf2Pass : public ScriptPass
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis\n");
 		log("\n");
+		log("    -noiobs\n");
+		log("        run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
+		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
@@ -70,7 +73,7 @@ struct SynthSf2Pass : public ScriptPass
 	}
 
 	string top_opt, edif_file, vlog_file, json_file;
-	bool flatten, retime;
+	bool flatten, retime, iobs;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -80,6 +83,7 @@ struct SynthSf2Pass : public ScriptPass
 		json_file = "";
 		flatten = true;
 		retime = false;
+		iobs = true;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -122,6 +126,10 @@ struct SynthSf2Pass : public ScriptPass
 				retime = true;
 				continue;
 			}
+			if (args[argidx] == "-noiobs") {
+				iobs = false;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -191,6 +199,13 @@ struct SynthSf2Pass : public ScriptPass
 			run("clean");
 		}
 
+		if (check_label("map_iobs"))
+		{
+			if (iobs || help_mode)
+				run("sf2_iobs", "(unless -noiobs)");
+			run("clean");
+		}
+
 		if (check_label("check"))
 		{
 			run("hierarchy -check");

From f3556e9f7ac6947be440a51699af773655de4911 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 17 Jan 2019 14:54:04 +0100
Subject: [PATCH 313/528] Cleanups in igloo2 example design

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.fp.pdc | 0
 examples/igloo2/example.io.pdc | 0
 examples/igloo2/example.pdc    | 1 +
 examples/igloo2/example.sdc    | 1 +
 examples/igloo2/example.ys     | 3 ---
 examples/igloo2/libero.tcl     | 6 ++----
 6 files changed, 4 insertions(+), 7 deletions(-)
 delete mode 100644 examples/igloo2/example.fp.pdc
 delete mode 100644 examples/igloo2/example.io.pdc
 create mode 100644 examples/igloo2/example.pdc
 delete mode 100644 examples/igloo2/example.ys

diff --git a/examples/igloo2/example.fp.pdc b/examples/igloo2/example.fp.pdc
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/igloo2/example.io.pdc b/examples/igloo2/example.io.pdc
deleted file mode 100644
index e69de29bb..000000000
diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
new file mode 100644
index 000000000..e6ffd53db
--- /dev/null
+++ b/examples/igloo2/example.pdc
@@ -0,0 +1 @@
+# Add placement constraints here
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index e69de29bb..c6ff94161 100644
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -0,0 +1 @@
+# Add timing constraints here
diff --git a/examples/igloo2/example.ys b/examples/igloo2/example.ys
deleted file mode 100644
index 04ea02672..000000000
--- a/examples/igloo2/example.ys
+++ /dev/null
@@ -1,3 +0,0 @@
-read_verilog example.v
-synth_sf2 -top example -edif netlist.edn
-write_verilog netlist.vm
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 952342a4c..1f3476316 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -14,14 +14,12 @@ new_project \
 
 import_files -hdl_source {netlist.vm}
 import_files -sdc {example.sdc}
-import_files -io_pdc {example.io.pdc}
-import_files -fp_pdc {example.fp.pdc}
+import_files -io_pdc {example.pdc}
 set_option -synth 0
 
 organize_tool_files -tool PLACEROUTE \
     -file {proj/constraint/example.sdc} \
-    -file {proj/constraint/io/example.io.pdc} \
-    -file {proj/constraint/fp/example.fp.pdc} \
+    -file {proj/constraint/io/example.pdc} \
     -input_type constraint
 
 organize_tool_files -tool VERIFYTIMING \

From 95b6c3588222564b86cfa73f0601be44e3af5786 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Fri, 18 Jan 2019 23:22:02 +0000
Subject: [PATCH 314/528] proc_clean: fix fully def check to consider
 compare/signal length.

Fixes #790.
---
 passes/proc/proc_clean.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 3919e4b9c..0e2f95226 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -82,9 +82,15 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 		{
 			if (max_depth != 0)
 				proc_clean_case(cs, did_something, count, max_depth-1);
+			int size = 0;
 			for (auto cmp : cs->compare)
-				if (!cmp.is_fully_def())
+			{
+				size += cmp.size();
+				if (cmp.is_fully_def())
 					all_fully_def = false;
+			}
+			if (sw->signal.size() != size)
+				all_fully_def = false;
 		}
 		if (all_fully_def)
 		{

From 01ea72f53a9707d741a1178d0ac4c4f69d6b65db Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:33:47 +0000
Subject: [PATCH 315/528] ecp5: Increase threshold for ALU mapping

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/arith_map.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ecp5/arith_map.v b/techlibs/ecp5/arith_map.v
index 1094c5f8a..eb7947601 100644
--- a/techlibs/ecp5/arith_map.v
+++ b/techlibs/ecp5/arith_map.v
@@ -33,7 +33,7 @@ module _80_ecp5_alu (A, B, CI, BI, X, Y, CO);
 	input CI, BI;
 	output [Y_WIDTH-1:0] CO;
 
-	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 4;
 
 	wire [Y_WIDTH-1:0] A_buf, B_buf;
 	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));

From d8003e87d1c5962e660ce84150239444b7fb037d Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:34:34 +0000
Subject: [PATCH 316/528] ecp5: More blackboxes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 425d62d24..32fb5c1ef 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -156,6 +156,23 @@ module OSCG(
 parameter DIV = 128;
 endmodule
 
+(* blackbox *) (* keep *)
+module USRMCLK(
+	input USRMCLKI, USRMCLKTS,
+	output USRMCLKO
+);
+endmodule
+
+(* blackbox *) (* keep *)
+module JTAGG(
+	input TCK, TMS, TDI, JTDO2, JTDO1,
+	output TDO, JTDI, JTCK, JRTI2, JRTI1,
+	output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1
+);
+parameter ER1 = "ENABLED";
+parameter ER2 = "ENABLED";
+endmodule
+
 (* blackbox *)
 module IDDRX1F(
 	input D, SCLK, RST,

From ee8c9e854f0b5f6500d030d4c700b29f042fb57f Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 21 Jan 2019 12:35:22 +0000
Subject: [PATCH 317/528] ecp5: Add LSRMODE to flipflops for PRLD support

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_sim.v | 23 ++++++++++++++++-------
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb..ca5d020f3 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -203,13 +203,14 @@ endmodule
 
 // ---------------------------------------
 
-module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
+module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 	parameter GSR = "ENABLED";
 	parameter [127:0] CEMUX = "1";
 	parameter CLKMUX = "CLK";
 	parameter LSRMUX = "LSR";
 	parameter SRMODE = "LSR_OVER_CE";
 	parameter REGSET = "RESET";
+	parameter [127:0] LSRMODE = "LSR";
 
 	reg muxce;
 	always @(*)
@@ -222,8 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
-
-	localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	generate
+		if (LSRMODE == "PRLD")
+			wire srval = M;
+		else
+			localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+	endgenerate
 
 	initial Q = srval;
 
@@ -339,6 +344,8 @@ module TRELLIS_SLICE(
 	parameter REG1_SD = "0";
 	parameter REG0_REGSET = "RESET";
 	parameter REG1_REGSET = "RESET";
+	parameter REG0_LSRMODE = "LSR";
+	parameter REG1_LSRMODE = "LSR";
 	parameter [127:0] CCU2_INJECT1_0 = "NO";
 	parameter [127:0] CCU2_INJECT1_1 = "NO";
 	parameter WREMUX = "WRE";
@@ -428,10 +435,11 @@ module TRELLIS_SLICE(
 		.CLKMUX(CLKMUX),
 		.LSRMUX(LSRMUX),
 		.SRMODE(SRMODE),
-		.REGSET(REG0_REGSET)
+		.REGSET(REG0_REGSET),
+		.LSRMODE(REG0_LSRMODE)
 	) ff_0 (
 		.CLK(CLK), .LSR(LSR), .CE(CE),
-		.DI(muxdi0),
+		.DI(muxdi0), .M(M0),
 		.Q(Q0)
 	);
 	TRELLIS_FF #(
@@ -440,10 +448,11 @@ module TRELLIS_SLICE(
 		.CLKMUX(CLKMUX),
 		.LSRMUX(LSRMUX),
 		.SRMODE(SRMODE),
-		.REGSET(REG1_REGSET)
+		.REGSET(REG1_REGSET),
+		.LSRMODE(REG1_LSRMODE)
 	) ff_1 (
 		.CLK(CLK), .LSR(LSR), .CE(CE),
-		.DI(muxdi1),
+		.DI(muxdi1), .M(M1),
 		.Q(Q1)
 	);
 endmodule

From 549b8e74b2cef41a23e609bdb65c5b04b3141a61 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 30 Nov 2018 19:29:03 +0000
Subject: [PATCH 318/528] ecp5: Support for flipflop initialisation

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/Makefile.inc   |   2 +-
 techlibs/ecp5/ecp5_ffinit.cc | 198 +++++++++++++++++++++++++++++++++++
 techlibs/ecp5/synth_ecp5.cc  |   3 -
 3 files changed, 199 insertions(+), 4 deletions(-)
 create mode 100644 techlibs/ecp5/ecp5_ffinit.cc

diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc
index 8df02be5f..4db087e87 100644
--- a/techlibs/ecp5/Makefile.inc
+++ b/techlibs/ecp5/Makefile.inc
@@ -1,5 +1,5 @@
 
-OBJS += techlibs/ecp5/synth_ecp5.o
+OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_ffinit.o
 
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_sim.v))
diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
new file mode 100644
index 000000000..02945fff4
--- /dev/null
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -0,0 +1,198 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2018-19  David Shah <david@symbioticeda.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct Ecp5FfinitPass : public Pass {
+	Ecp5FfinitPass() : Pass("ecp5_ffinit", "ECP5: handle FF init values") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ecp5_ffinit [options] [selection]\n");
+		log("\n");
+		log("Remove init values for FF output signals when equal to reset value.\n");
+		log("If reset is not used, set the reset value to the init value, otherwise\n");
+		log("unmap out the reset (if not an async reset).\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ECP5_FFINIT pass (implement FF init values).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-singleton") {
+			// 	singleton_mode = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			log("Handling FF init values in %s.\n", log_id(module));
+
+			SigMap sigmap(module);
+			pool<Wire*> init_wires;
+			dict<SigBit, State> initbits;
+			dict<SigBit, SigBit> initbit_to_wire;
+			pool<SigBit> handled_initbits;
+
+			for (auto wire : module->selected_wires())
+			{
+				if (wire->attributes.count("\\init") == 0)
+					continue;
+
+				SigSpec wirebits = sigmap(wire);
+				Const initval = wire->attributes.at("\\init");
+				init_wires.insert(wire);
+
+				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
+				{
+					SigBit bit = wirebits[i];
+					State val = initval[i];
+
+					if (val != State::S0 && val != State::S1)
+						continue;
+
+					if (initbits.count(bit)) {
+						if (initbits.at(bit) != val)
+							log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+									log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
+									log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+						continue;
+					}
+
+					initbits[bit] = val;
+					initbit_to_wire[bit] = SigBit(wire, i);
+				}
+			}
+			for (auto cell : module->selected_cells())
+			{
+				if (cell->type != "\\TRELLIS_FF")
+					continue;
+				SigSpec sig_d = cell->getPort("\\DI");
+				SigSpec sig_q = cell->getPort("\\Q");
+				SigSpec sig_lsr = cell->getPort("\\LSR");
+
+				if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
+					continue;
+
+				SigBit bit_d = sigmap(sig_d[0]);
+				SigBit bit_q = sigmap(sig_q[0]);
+
+				std::string regset = "RESET";
+				if (cell->hasParam("\\REGSET"))
+					regset = cell->getParam("\\REGSET").decode_string();
+				State resetState;
+				if (regset == "SET")
+					resetState = State::S1;
+				else if (regset == "RESET")
+					resetState = State::S0;
+				else
+					log_error("FF cell %s has illegal REGSET value %s.\n",
+						log_id(cell), regset.c_str());
+
+				if (!initbits.count(bit_q))
+					continue;
+
+				State val = initbits.at(bit_q);
+
+				log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
+						log_signal(bit_q), val != State::S0 ? '1' : '0');
+				// Initval is the same as the reset state. Matches hardware, nowt more to do
+				if (val == resetState) {
+					handled_initbits.insert(bit_q);
+					continue;
+				}
+
+				if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
+					std::string srmode = "LSR_OVER_CE";
+					if (cell->hasParam("\\SRMODE"))
+						srmode = cell->getParam("\\SRMODE").decode_string();
+					if (srmode == "ASYNC") {
+						log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
+							resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
+					} else {
+						SigBit bit_lsr = sigmap(sig_lsr[0]);
+						Wire *new_bit_d = module->addWire(NEW_ID);
+						if (resetState == State::S0) {
+							module->addAndnotGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
+						} else {
+							module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
+						}
+
+						cell->setPort("\\DI", new_bit_d);
+						cell->setPort("\\LSR", State::S0);
+
+						if(cell->hasPort("\\CE")) {
+							std::string cemux = "CE";
+							if (cell->hasParam("\\CEMUX"))
+								cemux = cell->getParam("\\CEMUX").decode_string();
+							SigSpec sig_ce = cell->getPort("\\CE");
+							if (GetSize(sig_ce) >= 1) {
+								SigBit bit_ce = sigmap(sig_ce[0]);
+								Wire *new_bit_ce = module->addWire(NEW_ID);
+								if (cemux == "INV")
+									module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
+								else
+									module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
+								cell->setPort("\\CE", new_bit_ce);
+							}
+						}
+						cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+						handled_initbits.insert(bit_q);
+					}
+				} else {
+					cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
+					handled_initbits.insert(bit_q);
+				}
+			}
+
+			for (auto wire : init_wires)
+			{
+				if (wire->attributes.count("\\init") == 0)
+					continue;
+
+				SigSpec wirebits = sigmap(wire);
+				Const &initval = wire->attributes.at("\\init");
+				bool remove_attribute = true;
+
+				for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
+					if (handled_initbits.count(wirebits[i]))
+						initval[i] = State::Sx;
+					else if (initval[i] != State::Sx)
+						remove_attribute = false;
+				}
+
+				if (remove_attribute)
+					wire->attributes.erase("\\init");
+			}
+		}
+	}
+} Ecp5FfinitPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 2e9176a84..835f10d8c 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -255,10 +255,7 @@ struct SynthEcp5Pass : public ScriptPass
 			run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
 			run("opt_expr -mux_undef");
 			run("simplemap");
-			// TODO
-#if 0
 			run("ecp5_ffinit");
-#endif
 		}
 
 		if (check_label("map_luts"))

From 58d059ccb7f32f4d061fe3d7caf57483fbf01516 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 23 Jan 2019 22:08:38 +0000
Subject: [PATCH 319/528] proc_clean: fix critical typo.

---
 passes/proc/proc_clean.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 0e2f95226..52141a8ec 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -86,7 +86,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
 			for (auto cmp : cs->compare)
 			{
 				size += cmp.size();
-				if (cmp.is_fully_def())
+				if (!cmp.is_fully_def())
 					all_fully_def = false;
 			}
 			if (sw->signal.size() != size)

From 0de328da8ffea4902c52b286d7b38d67a714c742 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 25 Jan 2019 19:25:25 +0100
Subject: [PATCH 320/528] Fixed Anlogic simulation model

---
 techlibs/anlogic/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/anlogic/cells_sim.v b/techlibs/anlogic/cells_sim.v
index 60a367928..058e76605 100644
--- a/techlibs/anlogic/cells_sim.v
+++ b/techlibs/anlogic/cells_sim.v
@@ -17,7 +17,7 @@ module AL_MAP_LUT1 (
 );
 	parameter [1:0] INIT = 2'h0;
 	parameter EQN = "(A)";
-	assign Y = INIT >> A;
+	assign o = INIT >> a;
 endmodule
 
 module AL_MAP_LUT2 (

From 42c47a83dab873290040367455c48f619d83e2a3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sat, 26 Jan 2019 23:55:46 +0000
Subject: [PATCH 321/528] write_verilog: escape names that match SystemVerilog
 keywords.

---
 backends/verilog/verilog_backend.cc | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 8da3c0627..fc38afbda 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -126,6 +126,33 @@ std::string id(RTLIL::IdString internal_id, bool may_rename = true)
 		break;
 	}
 
+	const pool<string> keywords = {
+		// IEEE 1800-2017 Annex B
+		"accept_on", "alias", "always", "always_comb", "always_ff", "always_latch", "and", "assert", "assign", "assume", "automatic", "before",
+		"begin", "bind", "bins", "binsof", "bit", "break", "buf", "bufif0", "bufif1", "byte", "case", "casex", "casez", "cell", "chandle",
+		"checker", "class", "clocking", "cmos", "config", "const", "constraint", "context", "continue", "cover", "covergroup", "coverpoint",
+		"cross", "deassign", "default", "defparam", "design", "disable", "dist", "do", "edge", "else", "end", "endcase", "endchecker",
+		"endclass", "endclocking", "endconfig", "endfunction", "endgenerate", "endgroup", "endinterface", "endmodule", "endpackage",
+		"endprimitive", "endprogram", "endproperty", "endsequence", "endspecify", "endtable", "endtask", "enum", "event", "eventually",
+		"expect", "export", "extends", "extern", "final", "first_match", "for", "force", "foreach", "forever", "fork", "forkjoin", "function",
+		"generate", "genvar", "global", "highz0", "highz1", "if", "iff", "ifnone", "ignore_bins", "illegal_bins", "implements", "implies",
+		"import", "incdir", "include", "initial", "inout", "input", "inside", "instance", "int", "integer", "interconnect", "interface",
+		"intersect", "join", "join_any", "join_none", "large", "let", "liblist", "library", "local", "localparam", "logic", "longint",
+		"macromodule", "matches", "medium", "modport", "module", "nand", "negedge", "nettype", "new", "nexttime", "nmos", "nor",
+		"noshowcancelled", "not", "notif0", "notif1", "null", "or", "output", "package", "packed", "parameter", "pmos", "posedge", "primitive",
+		"priority", "program", "property", "protected", "pull0", "pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent",
+		"pure", "rand", "randc", "randcase", "randsequence", "rcmos", "real", "realtime", "ref", "reg", "reject_on", "release", "repeat",
+		"restrict", "return", "rnmos", "rpmos", "rtran", "rtranif0", "rtranif1", "s_always", "s_eventually", "s_nexttime", "s_until",
+		"s_until_with", "scalared", "sequence", "shortint", "shortreal", "showcancelled", "signed", "small", "soft", "solve", "specify",
+		"specparam", "static", "string", "strong", "strong0", "strong1", "struct", "super", "supply0", "supply1", "sync_accept_on",
+		"sync_reject_on", "table", "tagged", "task", "this", "throughout", "time", "timeprecision", "timeunit", "tran", "tranif0", "tranif1",
+		"tri", "tri0", "tri1", "triand", "trior", "trireg", "type", "typedef", "union", "unique", "unique0", "unsigned", "until", "until_with",
+		"untyped", "use", "uwire", "var", "vectored", "virtual", "void", "wait", "wait_order", "wand", "weak", "weak0", "weak1", "while",
+		"wildcard", "wire", "with", "within", "wor", "xnor", "xor",
+	};
+	if (keywords.count(str))
+		do_escape = true;
+
 	if (do_escape)
 		return "\\" + std::string(str) + " ";
 	return std::string(str);

From 3d7925ad9f7840d5269b84d053ae808f36ccf762 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Sun, 27 Jan 2019 00:21:31 +0000
Subject: [PATCH 322/528] write_verilog: write $tribuf cell as ternary.

---
 backends/verilog/verilog_backend.cc | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 8da3c0627..54281e32e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -789,6 +789,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
+	if (cell->type == "$tribuf")
+	{
+		f << stringf("%s" "assign ", indent.c_str());
+		dump_sigspec(f, cell->getPort("\\Y"));
+		f << stringf(" = ");
+		dump_sigspec(f, cell->getPort("\\EN"));
+		f << stringf(" ? ");
+		dump_sigspec(f, cell->getPort("\\A"));
+		f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int());
+		return true;
+	}
+
 	if (cell->type == "$slice")
 	{
 		f << stringf("%s" "assign ", indent.c_str());

From 9666cca9ddba2e6d242006e80d66277b8b4df0fd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 27 Jan 2019 09:17:02 +0100
Subject: [PATCH 323/528] Remove asicworld tests for (unsupported) switch-level
 modelling

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/asicworld/code_hdl_models_misc1.v       | 22 -------------------
 .../asicworld/code_hdl_models_mux21_switch.v  | 22 -------------------
 tests/asicworld/code_hdl_models_nand_switch.v | 14 ------------
 .../asicworld/code_hdl_models_t_gate_switch.v | 11 ----------
 4 files changed, 69 deletions(-)
 delete mode 100644 tests/asicworld/code_hdl_models_misc1.v
 delete mode 100644 tests/asicworld/code_hdl_models_mux21_switch.v
 delete mode 100644 tests/asicworld/code_hdl_models_nand_switch.v
 delete mode 100644 tests/asicworld/code_hdl_models_t_gate_switch.v

diff --git a/tests/asicworld/code_hdl_models_misc1.v b/tests/asicworld/code_hdl_models_misc1.v
deleted file mode 100644
index e3d9d5d64..000000000
--- a/tests/asicworld/code_hdl_models_misc1.v
+++ /dev/null
@@ -1,22 +0,0 @@
-module misc1 (a,b,c,d,y);
-input a, b,c,d;
-output y;
-
-wire net1,net2,net3;
-
-supply1 vdd;
-supply0 vss;
-
-// y = !((a+b+c).d)
-
-pmos p1 (vdd,net1,a);
-pmos p2 (net1,net2,b);
-pmos p3 (net2,y,c);
-pmos p4 (vdd,y,d);
-
-nmos n1 (vss,net3,a);
-nmos n2 (vss,net3,b);
-nmos n3 (vss,net3,c);
-nmos n4 (net3,y,d);
-
-endmodule
diff --git a/tests/asicworld/code_hdl_models_mux21_switch.v b/tests/asicworld/code_hdl_models_mux21_switch.v
deleted file mode 100644
index 519c07fc5..000000000
--- a/tests/asicworld/code_hdl_models_mux21_switch.v
+++ /dev/null
@@ -1,22 +0,0 @@
-//-----------------------------------------------------
-// Design Name : mux21_switch
-// File Name   : mux21_switch.v
-// Function    : 2:1 Mux using Switch Primitives
-// Coder       : Deepak Kumar Tala
-//-----------------------------------------------------
-module mux21_switch (out, ctrl, in1, in2);
-   
-   output out;                    
-   input  ctrl, in1, in2;         
-   wire          w;            
-
-   supply1 power;             
-   supply0 ground;      
-   
-   pmos N1 (w, power, ctrl);     
-   nmos N2 (w, ground, ctrl);   
-   
-   cmos C1 (out, in1, w, ctrl);   
-   cmos C2 (out, in2, ctrl, w);
-   
-endmodule
diff --git a/tests/asicworld/code_hdl_models_nand_switch.v b/tests/asicworld/code_hdl_models_nand_switch.v
deleted file mode 100644
index 1ccdd3a7c..000000000
--- a/tests/asicworld/code_hdl_models_nand_switch.v
+++ /dev/null
@@ -1,14 +0,0 @@
-module nand_switch(a,b,out);
-input a,b;
-output out;
-
-supply0 vss;
-supply1 vdd;
-wire net1;
-
-pmos p1 (vdd,out,a);
-pmos p2 (vdd,out,b);
-nmos n1 (vss,net1,a);
-nmos n2 (net1,out,b);
-
-endmodule
\ No newline at end of file
diff --git a/tests/asicworld/code_hdl_models_t_gate_switch.v b/tests/asicworld/code_hdl_models_t_gate_switch.v
deleted file mode 100644
index 5a7e0eaff..000000000
--- a/tests/asicworld/code_hdl_models_t_gate_switch.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module t_gate_switch (L,R,nC,C);
- inout L;
- inout R;
- input nC;
- input C;
-
- //Syntax: keyword unique_name (drain. source, gate);
- pmos p1 (L,R,nC);
- nmos p2 (L,R,C);
-
-endmodule

From da65e1e8d9552f64e1e03c08108ca0532719bbfe Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Tue, 29 Jan 2019 02:24:00 +0000
Subject: [PATCH 324/528] write_verilog: correctly emit asynchronous
 transparent ports.

This commit fixes two related issues:
  * For asynchronous ports, clock is no longer added to domain list.
    (This would lead to absurd constructs like `always @(posedge 0)`.
  * The logic to distinguish synchronous and asynchronous ports is
    changed to correctly use or avoid clock in all cases.

Before this commit, the following RTLIL snippet (after memory_collect)

    cell $memrd $2
      parameter \MEMID "\\mem"
      parameter \ABITS 2
      parameter \WIDTH 4
      parameter \CLK_ENABLE 0
      parameter \CLK_POLARITY 1
      parameter \TRANSPARENT 1
      connect \CLK 1'0
      connect \EN 1'1
      connect \ADDR \mem_r_addr
      connect \DATA \mem_r_data
    end

would lead to invalid Verilog:

    reg [1:0] _0_;
    always @(posedge 1'h0) begin
      _0_ <= mem_r_addr;
    end
    assign mem_r_data = mem[_0_];

Note that there are two potential pitfalls remaining after this
change:
  * For asynchronous ports, the \EN input and \TRANSPARENT parameter
    are silently ignored. (Per discussion in #760 this is the correct
    behavior.)
  * For synchronous transparent ports, the \EN input is ignored. This
    matches the behavior of the $mem simulation cell. Again, see #760.
---
 backends/verilog/verilog_backend.cc | 79 +++++++++++++++--------------
 1 file changed, 41 insertions(+), 38 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a7f329ef8..60668f1f0 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1065,43 +1065,46 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool();
 			rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool();
 			rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool();
+			if (use_rd_clk)
 			{
-				std::ostringstream os;
-				dump_sigspec(os, sig_rd_clk);
-				clk_domain_str = stringf("%sedge %s", rd_clk_posedge ? "pos" : "neg", os.str().c_str());
-				if( clk_to_lof_body.count(clk_domain_str) == 0 )
-					clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
-			}
-			if (use_rd_clk && !rd_transparent)
-			{
-				// for clocked read ports make something like:
-				//   reg [..] temp_id;
-				//   always @(posedge clk)
-				//      if (rd_en) temp_id <= array_reg[r_addr];
-				//   assign r_data = temp_id;
-				std::string temp_id = next_auto_id();
-				lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", sig_rd_data.size() - 1, temp_id.c_str()) );
 				{
 					std::ostringstream os;
-					if (sig_rd_en != RTLIL::SigBit(true))
+					dump_sigspec(os, sig_rd_clk);
+					clk_domain_str = stringf("%sedge %s", rd_clk_posedge ? "pos" : "neg", os.str().c_str());
+					if( clk_to_lof_body.count(clk_domain_str) == 0 )
+						clk_to_lof_body[clk_domain_str] = std::vector<std::string>();
+				}
+				if (!rd_transparent)
+				{
+					// for clocked read ports make something like:
+					//   reg [..] temp_id;
+					//   always @(posedge clk)
+					//      if (rd_en) temp_id <= array_reg[r_addr];
+					//   assign r_data = temp_id;
+					std::string temp_id = next_auto_id();
+					lof_reg_declarations.push_back( stringf("reg [%d:0] %s;\n", sig_rd_data.size() - 1, temp_id.c_str()) );
 					{
-						os << stringf("if (");
-						dump_sigspec(os, sig_rd_en);
-						os << stringf(") ");
+						std::ostringstream os;
+						if (sig_rd_en != RTLIL::SigBit(true))
+						{
+							os << stringf("if (");
+							dump_sigspec(os, sig_rd_en);
+							os << stringf(") ");
+						}
+						os << stringf("%s <= %s[", temp_id.c_str(), mem_id.c_str());
+						dump_sigspec(os, sig_rd_addr);
+						os << stringf("];\n");
+						clk_to_lof_body[clk_domain_str].push_back(os.str());
+					}
+					{
+						std::ostringstream os;
+						dump_sigspec(os, sig_rd_data);
+						std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
+						clk_to_lof_body[""].push_back(line);
 					}
-					os << stringf("%s <= %s[", temp_id.c_str(), mem_id.c_str());
-					dump_sigspec(os, sig_rd_addr);
-					os << stringf("];\n");
-					clk_to_lof_body[clk_domain_str].push_back(os.str());
 				}
+				else
 				{
-					std::ostringstream os;
-					dump_sigspec(os, sig_rd_data);
-					std::string line = stringf("assign %s = %s;\n", os.str().c_str(), temp_id.c_str());
-					clk_to_lof_body[""].push_back(line);
-				}
-			} else {
-				if (rd_transparent) {
 					// for rd-transparent read-ports make something like:
 					//   reg [..] temp_id;
 					//   always @(posedge clk)
@@ -1121,15 +1124,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 						std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), temp_id.c_str());
 						clk_to_lof_body[""].push_back(line);
 					}
-				} else {
-					// for non-clocked read-ports make something like:
-					//   assign r_data = array_reg[r_addr];
-					std::ostringstream os, os2;
-					dump_sigspec(os, sig_rd_data);
-					dump_sigspec(os2, sig_rd_addr);
-					std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
-					clk_to_lof_body[""].push_back(line);
 				}
+			} else {
+				// for non-clocked read-ports make something like:
+				//   assign r_data = array_reg[r_addr];
+				std::ostringstream os, os2;
+				dump_sigspec(os, sig_rd_data);
+				dump_sigspec(os2, sig_rd_addr);
+				std::string line = stringf("assign %s = %s[%s];\n", os.str().c_str(), mem_id.c_str(), os2.str().c_str());
+				clk_to_lof_body[""].push_back(line);
 			}
 		}
 

From 3f0bb441f8a3014bf6b3a656b673fc07663bda76 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 4 Feb 2019 16:46:24 -0800
Subject: [PATCH 325/528] Add tests

---
 tests/aig/and.aag       |  5 +++++
 tests/aig/buffer.aag    |  3 +++
 tests/aig/cnt1.aag      |  3 +++
 tests/aig/cnt1e.aag     |  8 ++++++++
 tests/aig/empty.aag     |  1 +
 tests/aig/false.aag     |  2 ++
 tests/aig/halfadder.aag | 14 ++++++++++++++
 tests/aig/inverter.aag  |  3 +++
 tests/aig/notcnt1.aag   |  4 ++++
 tests/aig/notcnt1e.aag  |  8 ++++++++
 tests/aig/or.aag        |  5 +++++
 tests/aig/run-test.sh   | 20 ++++++++++++++++++++
 tests/aig/toggle-re.aag | 14 ++++++++++++++
 tests/aig/toggle.aag    |  4 ++++
 tests/aig/true.aag      |  2 ++
 tests/tools/autotest.sh | 21 +++++++++++++--------
 16 files changed, 109 insertions(+), 8 deletions(-)
 create mode 100644 tests/aig/and.aag
 create mode 100644 tests/aig/buffer.aag
 create mode 100644 tests/aig/cnt1.aag
 create mode 100644 tests/aig/cnt1e.aag
 create mode 100644 tests/aig/empty.aag
 create mode 100644 tests/aig/false.aag
 create mode 100644 tests/aig/halfadder.aag
 create mode 100644 tests/aig/inverter.aag
 create mode 100644 tests/aig/notcnt1.aag
 create mode 100644 tests/aig/notcnt1e.aag
 create mode 100644 tests/aig/or.aag
 create mode 100755 tests/aig/run-test.sh
 create mode 100644 tests/aig/toggle-re.aag
 create mode 100644 tests/aig/toggle.aag
 create mode 100644 tests/aig/true.aag

diff --git a/tests/aig/and.aag b/tests/aig/and.aag
new file mode 100644
index 000000000..d1ef2c5a5
--- /dev/null
+++ b/tests/aig/and.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+6
+6 2 4
diff --git a/tests/aig/buffer.aag b/tests/aig/buffer.aag
new file mode 100644
index 000000000..94a6fb1ed
--- /dev/null
+++ b/tests/aig/buffer.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+2
diff --git a/tests/aig/cnt1.aag b/tests/aig/cnt1.aag
new file mode 100644
index 000000000..ce4f28fcb
--- /dev/null
+++ b/tests/aig/cnt1.aag
@@ -0,0 +1,3 @@
+aag 1 0 1 0 0 1
+2 3
+2
diff --git a/tests/aig/cnt1e.aag b/tests/aig/cnt1e.aag
new file mode 100644
index 000000000..6db3f0ffd
--- /dev/null
+++ b/tests/aig/cnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+4
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aig/empty.aag b/tests/aig/empty.aag
new file mode 100644
index 000000000..40c0f00cb
--- /dev/null
+++ b/tests/aig/empty.aag
@@ -0,0 +1 @@
+aag 0 0 0 0 0
diff --git a/tests/aig/false.aag b/tests/aig/false.aag
new file mode 100644
index 000000000..421e64a91
--- /dev/null
+++ b/tests/aig/false.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+0
diff --git a/tests/aig/halfadder.aag b/tests/aig/halfadder.aag
new file mode 100644
index 000000000..5bf54d38d
--- /dev/null
+++ b/tests/aig/halfadder.aag
@@ -0,0 +1,14 @@
+aag 7 2 0 2 3
+2
+4
+6
+12
+6 13 15
+12 2 4
+14 3 5
+i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder
diff --git a/tests/aig/inverter.aag b/tests/aig/inverter.aag
new file mode 100644
index 000000000..ff7c28542
--- /dev/null
+++ b/tests/aig/inverter.aag
@@ -0,0 +1,3 @@
+aag 1 1 0 1 0
+2
+3
diff --git a/tests/aig/notcnt1.aag b/tests/aig/notcnt1.aag
new file mode 100644
index 000000000..e92815f23
--- /dev/null
+++ b/tests/aig/notcnt1.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 0 0 1
+2 3
+3
+b0 AIGER_NEVER
diff --git a/tests/aig/notcnt1e.aag b/tests/aig/notcnt1e.aag
new file mode 100644
index 000000000..141c864f7
--- /dev/null
+++ b/tests/aig/notcnt1e.aag
@@ -0,0 +1,8 @@
+aag 5 1 1 0 3 1
+2
+4 10
+5
+6 5 3
+8 4 2
+10 9 7
+b0 AIGER_NEVER
diff --git a/tests/aig/or.aag b/tests/aig/or.aag
new file mode 100644
index 000000000..f780e339f
--- /dev/null
+++ b/tests/aig/or.aag
@@ -0,0 +1,5 @@
+aag 3 2 0 1 1
+2
+4
+7
+6 3 5
diff --git a/tests/aig/run-test.sh b/tests/aig/run-test.sh
new file mode 100755
index 000000000..308578f01
--- /dev/null
+++ b/tests/aig/run-test.sh
@@ -0,0 +1,20 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
diff --git a/tests/aig/toggle-re.aag b/tests/aig/toggle-re.aag
new file mode 100644
index 000000000..b662bb386
--- /dev/null
+++ b/tests/aig/toggle-re.aag
@@ -0,0 +1,14 @@
+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7
+i0 enable
+i1 reset
+o0 Q
+o1 !Q
diff --git a/tests/aig/toggle.aag b/tests/aig/toggle.aag
new file mode 100644
index 000000000..09651012d
--- /dev/null
+++ b/tests/aig/toggle.aag
@@ -0,0 +1,4 @@
+aag 1 0 1 2 0
+2 3
+2
+3
diff --git a/tests/aig/true.aag b/tests/aig/true.aag
new file mode 100644
index 000000000..366893648
--- /dev/null
+++ b/tests/aig/true.aag
@@ -0,0 +1,2 @@
+aag 0 0 0 1 0
+1
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..c01ce5611 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -86,8 +86,9 @@ shift $((OPTIND - 1))
 
 for fn
 do
-	bn=${fn%.v}
-	if [ "$bn" == "$fn" ]; then
+	bn=${fn%.*}
+	ext=${fn##*.}
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
@@ -109,10 +110,14 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
-		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
+		if [[ "$ext" == "v" ]]; then
+			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
+		else
+			cp ../$fn ${bn}_ref.${ext}
+		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
+			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${ext}
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi
@@ -138,16 +143,16 @@ do
 		fi
 
 		if [ -n "$scriptfiles" ]; then
-			test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
+			test_passes -f "$frontend $include_opts" ${bn}_ref.${ext} $scriptfiles
 		elif [ -n "$scriptopt" ]; then
-			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${ext}
 		elif [ "$frontend" = "verific" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
 		elif [ "$frontend" = "verific_gates" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
 		else
-			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
-			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${ext}
+			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${ext}
 		fi
 		touch ../${bn}.log
 	}

From e112d2fbf5a31f00ef19e6d05f28fecc1e9c56b9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Feb 2019 16:35:59 +0100
Subject: [PATCH 326/528] Add missing blackslash-to-slash convertion to
 smtio.py (matching Smt2Worker::get_id() behavior)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtio.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py
index 68783e744..ab20a4af2 100644
--- a/backends/smt2/smtio.py
+++ b/backends/smt2/smtio.py
@@ -784,7 +784,7 @@ class SmtIo:
 
     def get_path(self, mod, path):
         assert mod in self.modinfo
-        path = path.split(".")
+        path = path.replace("\\", "/").split(".")
 
         for i in range(len(path)-1):
             first = ".".join(path[0:i+1])

From cc0b723484d27424a65336662b7e8c19e21589c2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 12:19:48 -0800
Subject: [PATCH 327/528] WIP

---
 frontends/aiger/Makefile.inc  |   3 +
 frontends/aiger/aigerparse.cc | 213 ++++++++++++++++++++++++++++++++++
 frontends/aiger/aigerparse.h  |  31 +++++
 3 files changed, 247 insertions(+)
 create mode 100644 frontends/aiger/Makefile.inc
 create mode 100644 frontends/aiger/aigerparse.cc
 create mode 100644 frontends/aiger/aigerparse.h

diff --git a/frontends/aiger/Makefile.inc b/frontends/aiger/Makefile.inc
new file mode 100644
index 000000000..bc1112452
--- /dev/null
+++ b/frontends/aiger/Makefile.inc
@@ -0,0 +1,3 @@
+
+OBJS += frontends/aiger/aigerparse.o
+
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
new file mode 100644
index 000000000..c7a9aecb9
--- /dev/null
+++ b/frontends/aiger/aigerparse.cc
@@ -0,0 +1,213 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                      Eddie Hung <eddie@fpgeh.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// [[CITE]] The AIGER And-Inverter Graph (AIG) Format Version 20071012
+// Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
+// http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "aigerparse.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+#define log_debug log
+
+void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
+{
+    std::string header;
+    f >> header;
+    if (header != "aag") {
+        log_error("Unsupported AIGER file!\n");
+        return;
+    }
+
+    int M, I, L, O, A;
+    int B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
+    if (!(f >> M >> I >> L >> O >> A)) {
+        log_error("Invalid AIGER header\n");
+        return;
+    }
+    for (auto &i : std::array<std::reference_wrapper<int>,4>{B, C, J, F}) {
+        if (f.peek() != ' ') break;
+        if (!(f >> i)) {
+            log_error("Invalid AIGER header\n");
+            return;
+        }
+    }
+
+    std::string line;
+    std::getline(f, line); // Ignore up to start of next ine, as standard
+                           // says anything that follows could be used for
+                           // optional sections
+    
+    log_debug("M=%d I=%d L=%d O=%d A=%d B=%d C=%d J=%d F=%d\n", M, I, L, O, A, B, C, J, F);
+
+    int line_count = 1;
+    std::stringstream ss;
+
+    auto module = new RTLIL::Module;
+    module->name = RTLIL::escape_id("aig"); // TODO: Name?
+    if (design->module(module->name))
+        log_error("Duplicate definition of module %s in line %d!\n", log_id(module->name), line_count);
+    design->add(module);
+
+    auto createWireIfNotExists = [module](int literal) {
+        const int variable = literal >> 1;
+        const bool invert = literal & 1;
+        RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
+        RTLIL::Wire *wire = module->wire(wire_name);
+        if (wire) return wire;
+        log_debug("Creating %s\n", wire_name.c_str());
+        wire = module->addWire(wire_name);
+        if (!invert) return wire;
+        RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
+        RTLIL::Wire *wire_inv = module->wire(wire_inv_name); 
+        if (wire_inv) {
+            if (module->cell(wire_inv_name)) return wire;
+        } 
+        else {
+            log_debug("Creating %s\n", wire_inv_name.c_str());
+            wire_inv = module->addWire(wire_inv_name);
+        }
+
+        log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
+        RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
+        inv->setPort("\\A", wire_inv);
+        inv->setPort("\\Y", wire);
+
+        return wire;
+    };
+
+    int l1, l2, l3;
+
+    // Parse inputs
+    for (int i = 0; i < I; ++i, ++line_count) {
+        if (!(f >> l1)) {
+            log_error("Line %d cannot be interpreted as an input!\n", line_count);
+            return;
+        }
+        log_debug("%d is an input\n", l1);
+        log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
+        RTLIL::Wire *wire = createWireIfNotExists(l1);
+        wire->port_input = true;
+    }
+
+    // Parse latches
+    for (int i = 0; i < L; ++i, ++line_count) {
+        if (!(f >> l1 >> l2)) {
+            log_error("Line %d cannot be interpreted as a latch!\n", line_count);
+            return;
+        }
+        log_debug("%d %d is a latch\n", l1, l2);
+        log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
+        RTLIL::Wire *q_wire = createWireIfNotExists(l1);
+        RTLIL::Wire *d_wire = createWireIfNotExists(l2);
+        RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
+        RTLIL::Wire *clk_wire = module->wire(clk_id);
+        if (!clk_wire) {
+            log_debug("Creating %s\n", clk_id.c_str());
+            clk_wire = module->addWire(clk_id);
+            clk_wire->port_input = true;
+        }
+
+        module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+        // AIGER latches are assumed to be initialized to zero
+        q_wire->attributes["\\init"] = RTLIL::Const(0);
+    }
+
+    // Parse outputs
+    for (int i = 0; i < O; ++i, ++line_count) {
+        if (!(f >> l1)) {
+            log_error("Line %d cannot be interpreted as an output!\n", line_count);
+            return;
+        }
+
+        log_debug("%d is an output\n", l1);
+        RTLIL::Wire *wire = createWireIfNotExists(l1);
+        wire->port_output = true;
+    }
+    std::getline(f, line); // Ignore up to start of next line
+    
+    // TODO: Parse bad state properties
+    for (int i = 0; i < B; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse invariant constraints
+    for (int i = 0; i < C; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse justice properties
+    for (int i = 0; i < J; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse fairness constraints
+    for (int i = 0; i < F; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // Parse AND
+    for (int i = 0; i < A; ++i, ++line_count) {
+        if (!(f >> l1 >> l2 >> l3)) {
+            log_error("Line %d cannot be interpreted as an AND!\n", line_count);
+            return;
+        }
+
+        log_debug("%d %d %d is an AND\n", l1, l2, l3);
+        log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
+        RTLIL::Wire *o_wire = createWireIfNotExists(l1);
+        RTLIL::Wire *i1_wire = createWireIfNotExists(l2);
+        RTLIL::Wire *i2_wire = createWireIfNotExists(l3);
+
+		RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
+		and_cell->setPort("\\A", i1_wire);
+		and_cell->setPort("\\B", i2_wire);
+		and_cell->setPort("\\Y", o_wire);
+    }
+
+    module->fixup_ports();
+}
+
+struct AigerFrontend : public Frontend {
+	AigerFrontend() : Frontend("aiger", "read AIGER file") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    read_aiger [options] [filename]\n");
+		log("\n");
+		log("Load modules from an AIGER file into the current design.\n");
+		log("\n");
+	}
+	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing AIGER frontend.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			break;
+		}
+		extra_args(f, filename, args, argidx);
+
+		parse_aiger(design, *f);
+	}
+} AigerFrontend;
+
+YOSYS_NAMESPACE_END
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
new file mode 100644
index 000000000..6a250aa67
--- /dev/null
+++ b/frontends/aiger/aigerparse.h
@@ -0,0 +1,31 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef ABC_AIGERPARSE
+#define ABC_AIGERPARSE
+
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+extern void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
+
+YOSYS_NAMESPACE_END
+
+#endif

From fdd55d064b16f9334c86bb15b1c32cfb45294802 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 12:20:36 -0800
Subject: [PATCH 328/528] Rename ASCII tests

---
 tests/{aig => aiger}/and.aag       | 0
 tests/{aig => aiger}/buffer.aag    | 0
 tests/{aig => aiger}/cnt1.aag      | 0
 tests/{aig => aiger}/cnt1e.aag     | 0
 tests/{aig => aiger}/empty.aag     | 0
 tests/{aig => aiger}/false.aag     | 0
 tests/{aig => aiger}/halfadder.aag | 0
 tests/{aig => aiger}/inverter.aag  | 0
 tests/{aig => aiger}/notcnt1.aag   | 0
 tests/{aig => aiger}/notcnt1e.aag  | 0
 tests/{aig => aiger}/or.aag        | 0
 tests/{aig => aiger}/run-test.sh   | 0
 tests/{aig => aiger}/toggle-re.aag | 0
 tests/{aig => aiger}/toggle.aag    | 0
 tests/{aig => aiger}/true.aag      | 0
 15 files changed, 0 insertions(+), 0 deletions(-)
 rename tests/{aig => aiger}/and.aag (100%)
 rename tests/{aig => aiger}/buffer.aag (100%)
 rename tests/{aig => aiger}/cnt1.aag (100%)
 rename tests/{aig => aiger}/cnt1e.aag (100%)
 rename tests/{aig => aiger}/empty.aag (100%)
 rename tests/{aig => aiger}/false.aag (100%)
 rename tests/{aig => aiger}/halfadder.aag (100%)
 rename tests/{aig => aiger}/inverter.aag (100%)
 rename tests/{aig => aiger}/notcnt1.aag (100%)
 rename tests/{aig => aiger}/notcnt1e.aag (100%)
 rename tests/{aig => aiger}/or.aag (100%)
 rename tests/{aig => aiger}/run-test.sh (100%)
 rename tests/{aig => aiger}/toggle-re.aag (100%)
 rename tests/{aig => aiger}/toggle.aag (100%)
 rename tests/{aig => aiger}/true.aag (100%)

diff --git a/tests/aig/and.aag b/tests/aiger/and.aag
similarity index 100%
rename from tests/aig/and.aag
rename to tests/aiger/and.aag
diff --git a/tests/aig/buffer.aag b/tests/aiger/buffer.aag
similarity index 100%
rename from tests/aig/buffer.aag
rename to tests/aiger/buffer.aag
diff --git a/tests/aig/cnt1.aag b/tests/aiger/cnt1.aag
similarity index 100%
rename from tests/aig/cnt1.aag
rename to tests/aiger/cnt1.aag
diff --git a/tests/aig/cnt1e.aag b/tests/aiger/cnt1e.aag
similarity index 100%
rename from tests/aig/cnt1e.aag
rename to tests/aiger/cnt1e.aag
diff --git a/tests/aig/empty.aag b/tests/aiger/empty.aag
similarity index 100%
rename from tests/aig/empty.aag
rename to tests/aiger/empty.aag
diff --git a/tests/aig/false.aag b/tests/aiger/false.aag
similarity index 100%
rename from tests/aig/false.aag
rename to tests/aiger/false.aag
diff --git a/tests/aig/halfadder.aag b/tests/aiger/halfadder.aag
similarity index 100%
rename from tests/aig/halfadder.aag
rename to tests/aiger/halfadder.aag
diff --git a/tests/aig/inverter.aag b/tests/aiger/inverter.aag
similarity index 100%
rename from tests/aig/inverter.aag
rename to tests/aiger/inverter.aag
diff --git a/tests/aig/notcnt1.aag b/tests/aiger/notcnt1.aag
similarity index 100%
rename from tests/aig/notcnt1.aag
rename to tests/aiger/notcnt1.aag
diff --git a/tests/aig/notcnt1e.aag b/tests/aiger/notcnt1e.aag
similarity index 100%
rename from tests/aig/notcnt1e.aag
rename to tests/aiger/notcnt1e.aag
diff --git a/tests/aig/or.aag b/tests/aiger/or.aag
similarity index 100%
rename from tests/aig/or.aag
rename to tests/aiger/or.aag
diff --git a/tests/aig/run-test.sh b/tests/aiger/run-test.sh
similarity index 100%
rename from tests/aig/run-test.sh
rename to tests/aiger/run-test.sh
diff --git a/tests/aig/toggle-re.aag b/tests/aiger/toggle-re.aag
similarity index 100%
rename from tests/aig/toggle-re.aag
rename to tests/aiger/toggle-re.aag
diff --git a/tests/aig/toggle.aag b/tests/aiger/toggle.aag
similarity index 100%
rename from tests/aig/toggle.aag
rename to tests/aiger/toggle.aag
diff --git a/tests/aig/true.aag b/tests/aiger/true.aag
similarity index 100%
rename from tests/aig/true.aag
rename to tests/aiger/true.aag

From a9674bd2eca5efac6e4f7b2871a01cbba80f64ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 12:49:30 -0800
Subject: [PATCH 329/528] Add testcase

---
 tests/simple/dff_init.v | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/simple/dff_init.v

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
new file mode 100644
index 000000000..aad378346
--- /dev/null
+++ b/tests/simple/dff_init.v
@@ -0,0 +1,10 @@
+module dff_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *)
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule

From 8524a479b15ff89db48872c57103c60be77142af Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 4 Dec 2018 14:17:47 +0000
Subject: [PATCH 330/528] abc: Preserve naming through ABC using 'dress'
 command

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/techmap/abc.cc | 80 +++++++++++++++++++++++++++----------------
 1 file changed, 51 insertions(+), 29 deletions(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d2d15a4a9..d3bdd555b 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -329,6 +329,18 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 
 std::string remap_name(RTLIL::IdString abc_name)
 {
+	std::string abc_sname = abc_name.substr(1);
+	if (abc_sname.substr(0, 5) == "ys__n") {
+		int sid = std::stoi(abc_sname.substr(5));
+		bool inv = abc_sname.back() == 'v';
+		for (auto sig : signal_list) {
+			if (sig.id == sid) {
+				std::stringstream sstr;
+				sstr << "$abc$" << map_autoidx << "$" << log_signal(sig.bit) << (inv ? "_inv" : "");
+				return sstr.str();
+			}
+		}
+	}
 	std::stringstream sstr;
 	sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
 	return sstr.str();
@@ -353,12 +365,12 @@ void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std:
 	}
 
 	for (auto n : nodes)
-		fprintf(f, "  n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
+		fprintf(f, "  ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
 				n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
 
 	for (auto &e : edges)
 	for (auto n : e.second)
-		fprintf(f, "  n%d -> n%d;\n", e.first, n);
+		fprintf(f, "  ys__n%d -> ys__n%d;\n", e.first, n);
 
 	fprintf(f, "}\n");
 }
@@ -624,7 +636,7 @@ struct abc_output_filter
 void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 		std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
 		bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
-		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
+		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
 {
 	module = current_module;
 	map_autoidx = autoidx++;
@@ -728,7 +740,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 	for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
 		abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
-
+	if (abc_dress)
+		abc_script += "; dress";
 	abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
 	abc_script = add_echos_to_abc_cmd(abc_script);
 
@@ -784,7 +797,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	for (auto &si : signal_list) {
 		if (!si.is_port || si.type != G(NONE))
 			continue;
-		fprintf(f, " n%d", si.id);
+		fprintf(f, " ys__n%d", si.id);
 		pi_map[count_input++] = log_signal(si.bit);
 	}
 	if (count_input == 0)
@@ -796,17 +809,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	for (auto &si : signal_list) {
 		if (!si.is_port || si.type == G(NONE))
 			continue;
-		fprintf(f, " n%d", si.id);
+		fprintf(f, " ys__n%d", si.id);
 		po_map[count_output++] = log_signal(si.bit);
 	}
 	fprintf(f, "\n");
 
 	for (auto &si : signal_list)
-		fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
+		fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit));
 
 	for (auto &si : signal_list) {
 		if (si.bit.wire == NULL) {
-			fprintf(f, ".names n%d\n", si.id);
+			fprintf(f, ".names ys__n%d\n", si.id);
 			if (si.bit == RTLIL::State::S1)
 				fprintf(f, "1\n");
 		}
@@ -815,68 +828,68 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	int count_gates = 0;
 	for (auto &si : signal_list) {
 		if (si.type == G(BUF)) {
-			fprintf(f, ".names n%d n%d\n", si.in1, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
 			fprintf(f, "1 1\n");
 		} else if (si.type == G(NOT)) {
-			fprintf(f, ".names n%d n%d\n", si.in1, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
 			fprintf(f, "0 1\n");
 		} else if (si.type == G(AND)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "11 1\n");
 		} else if (si.type == G(NAND)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "0- 1\n");
 			fprintf(f, "-0 1\n");
 		} else if (si.type == G(OR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "-1 1\n");
 			fprintf(f, "1- 1\n");
 		} else if (si.type == G(NOR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "00 1\n");
 		} else if (si.type == G(XOR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "01 1\n");
 			fprintf(f, "10 1\n");
 		} else if (si.type == G(XNOR)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "00 1\n");
 			fprintf(f, "11 1\n");
 		} else if (si.type == G(ANDNOT)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "10 1\n");
 		} else if (si.type == G(ORNOT)) {
-			fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
 			fprintf(f, "1- 1\n");
 			fprintf(f, "-0 1\n");
 		} else if (si.type == G(MUX)) {
-			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "1-0 1\n");
 			fprintf(f, "-11 1\n");
 		} else if (si.type == G(AOI3)) {
-			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "-00 1\n");
 			fprintf(f, "0-0 1\n");
 		} else if (si.type == G(OAI3)) {
-			fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
 			fprintf(f, "00- 1\n");
 			fprintf(f, "--0 1\n");
 		} else if (si.type == G(AOI4)) {
-			fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
 			fprintf(f, "-0-0 1\n");
 			fprintf(f, "-00- 1\n");
 			fprintf(f, "0--0 1\n");
 			fprintf(f, "0-0- 1\n");
 		} else if (si.type == G(OAI4)) {
-			fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
+			fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
 			fprintf(f, "00-- 1\n");
 			fprintf(f, "--00 1\n");
 		} else if (si.type == G(FF)) {
 			if (si.init == State::S0 || si.init == State::S1) {
-				fprintf(f, ".latch n%d n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
+				fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
 				recover_init = true;
 			} else
-				fprintf(f, ".latch n%d n%d 2\n", si.in1, si.id);
+				fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
 		} else if (si.type != G(NONE))
 			log_abort();
 		if (si.type != G(NONE))
@@ -889,7 +902,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
 			count_gates, GetSize(signal_list), count_input, count_output);
 	log_push();
-
 	if (count_output > 0)
 	{
 		log_header(design, "Executing ABC.\n");
@@ -1213,7 +1225,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		for (auto &si : signal_list)
 			if (si.is_port) {
 				char buffer[100];
-				snprintf(buffer, 100, "\\n%d", si.id);
+				snprintf(buffer, 100, "\\ys__n%d", si.id);
 				RTLIL::SigSig conn;
 				if (si.type != G(NONE)) {
 					conn.first = si.bit;
@@ -1407,6 +1419,11 @@ struct AbcPass : public Pass {
 		log("        this attribute is a unique integer for each ABC process started. This\n");
 		log("        is useful for debugging the partitioning of clock domains.\n");
 		log("\n");
+		log("    -dress\n");
+		log("        run the 'dress' command after all other ABC commands. This aims to\n");
+		log("        preserve naming by an equivalence check between the original and post-ABC\n");
+		log("        netlists (experimental).\n");
+		log("\n");
 		log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
 		log("loaded into ABC before the ABC script is executed.\n");
 		log("\n");
@@ -1441,6 +1458,7 @@ struct AbcPass : public Pass {
 		std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
 		bool show_tempdir = false, sop_mode = false;
+		bool abc_dress = false;
 		vector<int> lut_costs;
 		markgroups = false;
 
@@ -1555,6 +1573,10 @@ struct AbcPass : public Pass {
 				map_mux16 = true;
 				continue;
 			}
+			if (arg == "-dress") {
+				abc_dress = true;
+				continue;
+			}
 			if (arg == "-g" && argidx+1 < args.size()) {
 				for (auto g : split_tokens(args[++argidx], ",")) {
 					vector<string> gate_list;
@@ -1704,7 +1726,7 @@ struct AbcPass : public Pass {
 
 			if (!dff_mode || !clk_str.empty()) {
 				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
-						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
+						delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
 				continue;
 			}
 
@@ -1849,7 +1871,7 @@ struct AbcPass : public Pass {
 				en_polarity = std::get<2>(it.first);
 				en_sig = assign_map(std::get<3>(it.first));
 				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
-						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
+						keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
 				assign_map.set(mod);
 			}
 		}

From 7ef2333497940a9f235d36f38a727f2533bab902 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 16 Dec 2018 17:43:57 +0000
Subject: [PATCH 331/528] ice40: Use abc -dress in synth_ice40

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ice40/synth_ice40.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..ba013fef2 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -282,7 +282,7 @@ struct SynthIce40Pass : public ScriptPass
 				run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
 			}
 			if (!noabc) {
-				run("abc -lut 4", "(skip if -noabc)");
+				run("abc -dress -lut 4", "(skip if -noabc)");
 			}
 			run("clean");
 			if (relut || help_mode) {

From 58c22dae31cd65010bd525ad7b4241709e773314 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Sun, 16 Dec 2018 17:44:37 +0000
Subject: [PATCH 332/528] abc: Improved recovered netnames, also preserve src
 on nets with dress

Signed-off-by: David Shah <davey1576@gmail.com>
---
 passes/techmap/abc.cc | 17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d3bdd555b..21b70f492 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -327,16 +327,22 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
 	}
 }
 
-std::string remap_name(RTLIL::IdString abc_name)
+std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr)
 {
 	std::string abc_sname = abc_name.substr(1);
 	if (abc_sname.substr(0, 5) == "ys__n") {
 		int sid = std::stoi(abc_sname.substr(5));
 		bool inv = abc_sname.back() == 'v';
 		for (auto sig : signal_list) {
-			if (sig.id == sid) {
+			if (sig.id == sid && sig.bit.wire != nullptr) {
 				std::stringstream sstr;
-				sstr << "$abc$" << map_autoidx << "$" << log_signal(sig.bit) << (inv ? "_inv" : "");
+				sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
+				if (sig.bit.wire->width != 1)
+					sstr << "[" << sig.bit.offset << "]";
+				if (inv)
+					sstr << "_inv";
+				if (orig_wire != nullptr)
+					*orig_wire = sig.bit.wire;
 				return sstr.str();
 			}
 		}
@@ -1000,7 +1006,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 			log_error("ABC output file does not contain a module `netlist'.\n");
 		for (auto &it : mapped_mod->wires_) {
 			RTLIL::Wire *w = it.second;
-			RTLIL::Wire *wire = module->addWire(remap_name(w->name));
+			RTLIL::Wire *orig_wire = nullptr;
+			RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
+			if (orig_wire != nullptr && orig_wire->attributes.count("\\src"))
+				wire->attributes["\\src"] = orig_wire->attributes["\\src"];
 			if (markgroups) wire->attributes["\\abcgroup"] = map_autoidx;
 			design->select(module, wire);
 		}

From 95789c61360d3842265409bd948115f471e005b4 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Wed, 6 Feb 2019 22:20:39 +0100
Subject: [PATCH 333/528] ecp5: Use abc -dress

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/synth_ecp5.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 2e9176a84..bda03d251 100644
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -268,9 +268,9 @@ struct SynthEcp5Pass : public ScriptPass
 			}
 			run("techmap -map +/ecp5/latches_map.v");
 			if (nomux)
-				run("abc -lut 4");
+				run("abc -lut 4 -dress");
 			else
-				run("abc -lut 4:7");
+				run("abc -lut 4:7 -dress");
 			run("clean");
 		}
 

From 03cf1532a70d705ada69dcb8ae79ae405a86b7da Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:02:11 -0800
Subject: [PATCH 334/528] Extend testcase

---
 tests/simple/dff_init.v | 36 ++++++++++++++++++++++++++++++++++--
 1 file changed, 34 insertions(+), 2 deletions(-)

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
index aad378346..be947042e 100644
--- a/tests/simple/dff_init.v
+++ b/tests/simple/dff_init.v
@@ -1,6 +1,5 @@
-module dff_test(n1, n1_inv, clk);
+module dff0_test(n1, n1_inv, clk);
   input clk;
-  (* init = 32'd0 *)
   output n1;
   reg n1 = 32'd0;
   output n1_inv;
@@ -8,3 +7,36 @@ module dff_test(n1, n1_inv, clk);
       n1 <= n1_inv;
   assign n1_inv = ~n1;
 endmodule
+
+module dff1_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *)
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff0a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff1a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule

From 281f2aadcab01465f83a3f3a697eec42503e9f8b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:14:55 -0800
Subject: [PATCH 335/528] Add -B option to autotest.sh to append to
 backend_opts

---
 tests/tools/autotest.sh | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..800fa3ad5 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -22,7 +22,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:B: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -59,8 +59,10 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+        B)
+			backend_opts="$backend_opts $OPTARG" ;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] verilog-files\n" >&2
 			exit 1
 	esac
 done

From 115883f467cb79688ffb93c136a6ee61368765e8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:15:17 -0800
Subject: [PATCH 336/528] Add tests for simple cases using defparam

---
 tests/simple_defparam/run-test.sh | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100755 tests/simple_defparam/run-test.sh

diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
new file mode 100755
index 000000000..137e15076
--- /dev/null
+++ b/tests/simple_defparam/run-test.sh
@@ -0,0 +1,21 @@
+#!/bin/bash
+
+OPTIND=1
+seed=""    # default to no seed specified
+while getopts "S:" opt
+do
+    case "$opt" in
+	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
+	   seed="SEED=$arg" ;;
+    esac
+done
+shift "$((OPTIND-1))"
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+  echo "$0: Error: Icarus Verilog 'iverilog' not found."
+  exit 1
+fi
+
+cp ../simple/*.v .
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""

From 742b4e01b498ae2e735d40565f43607d69a015d8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:16:26 -0800
Subject: [PATCH 337/528] Add INIT parameter to all ff/latch cells

---
 techlibs/common/simcells.v | 111 ++++++++++++++++++++++++-------------
 techlibs/common/simlib.v   |  18 ++++--
 2 files changed, 86 insertions(+), 43 deletions(-)

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 289673e82..b9957bd5e 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -451,8 +451,9 @@ endmodule
 //-                 1 1 | y
 //-
 module \$_SR_NN_ (S, R, Q);
+parameter INIT = 1'bx;
 input S, R;
-output reg Q;
+output reg Q = INIT;
 always @(negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -475,8 +476,9 @@ endmodule
 //-                 1 0 | y
 //-
 module \$_SR_NP_ (S, R, Q);
+parameter INIT = 1'bx;
 input S, R;
-output reg Q;
+output reg Q = INIT;
 always @(negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -499,8 +501,9 @@ endmodule
 //-                 0 1 | y
 //-
 module \$_SR_PN_ (S, R, Q);
+parameter INIT = 1'bx;
 input S, R;
-output reg Q;
+output reg Q = INIT;
 always @(posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -523,8 +526,9 @@ endmodule
 //-                 0 0 | y
 //-
 module \$_SR_PP_ (S, R, Q);
+parameter INIT = 1'bx;
 input S, R;
-output reg Q;
+output reg Q = INIT;
 always @(posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -542,8 +546,9 @@ endmodule
 //- type is usually only used in netlists for formal verification.)
 //-
 module \$_FF_ (D, Q);
+parameter INIT = 1'bx;
 input D;
-output reg Q;
+output reg Q = INIT;
 always @($global_clock) begin
 	Q <= D;
 end
@@ -562,8 +567,9 @@ endmodule
 //-                 - - | q
 //-
 module \$_DFF_N_ (D, C, Q);
+parameter INIT = 1'bx;
 input D, C;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C) begin
 	Q <= D;
 end
@@ -581,8 +587,9 @@ endmodule
 //-                 - - | q
 //-
 module \$_DFF_P_ (D, C, Q);
+parameter INIT = 1'bx;
 input D, C;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C) begin
 	Q <= D;
 end
@@ -600,8 +607,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_NN_ (D, C, E, Q);
+parameter INIT = 1'bx;
 input D, C, E;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C) begin
 	if (!E) Q <= D;
 end
@@ -619,8 +627,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_NP_ (D, C, E, Q);
+parameter INIT = 1'bx;
 input D, C, E;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C) begin
 	if (E) Q <= D;
 end
@@ -638,8 +647,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_PN_ (D, C, E, Q);
+parameter INIT = 1'bx;
 input D, C, E;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C) begin
 	if (!E) Q <= D;
 end
@@ -657,8 +667,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_PP_ (D, C, E, Q);
+parameter INIT = 1'bx;
 input D, C, E;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C) begin
 	if (E) Q <= D;
 end
@@ -677,8 +688,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NN0_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -700,8 +712,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NN1_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 1;
@@ -723,8 +736,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NP0_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -746,8 +760,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NP1_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 1;
@@ -769,8 +784,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PN0_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -792,8 +808,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PN1_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 1;
@@ -815,8 +832,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PP0_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -838,8 +856,9 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PP1_ (D, C, R, Q);
+parameter INIT = 1'bx;
 input D, C, R;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 1;
@@ -862,8 +881,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NNN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C, negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -889,8 +909,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NNP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C, negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -916,8 +937,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NPN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C, posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -942,8 +964,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NPP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(negedge C, posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -968,8 +991,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PNN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C, negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -995,8 +1019,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PNP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C, negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -1022,8 +1047,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PPN_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C, posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -1048,8 +1074,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PPP_ (C, S, R, D, Q);
+parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @(posedge C, posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -1072,8 +1099,9 @@ endmodule
 //-                 - - | q
 //-
 module \$_DLATCH_N_ (E, D, Q);
+parameter INIT = 1'bx;
 input E, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (E == 0)
 		Q <= D;
@@ -1092,8 +1120,9 @@ endmodule
 //-                 - - | q
 //-
 module \$_DLATCH_P_ (E, D, Q);
+parameter INIT = 1'bx;
 input E, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (E == 1)
 		Q <= D;
@@ -1114,8 +1143,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1141,8 +1171,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1168,8 +1199,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1194,8 +1226,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1220,8 +1253,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1247,8 +1281,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1274,8 +1309,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1300,8 +1336,9 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
+parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q;
+output reg Q = INIT;
 always @* begin
 	if (R == 1)
 		Q <= 0;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 8e43fe058..9b6008140 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,10 +1464,11 @@ module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1483,10 +1484,11 @@ module \$dffe (CLK, EN, D, Q);
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter EN_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK, EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1504,10 +1506,11 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 
 wire pos_clk = CLK == CLK_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
@@ -1537,10 +1540,11 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter ARST_POLARITY = 1'b1;
 parameter ARST_VALUE = 0;
+parameter INIT = {WIDTH{1'bx}};
 
 input CLK, ARST;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 wire pos_clk = CLK == CLK_POLARITY;
 wire pos_arst = ARST == ARST_POLARITY;
 
@@ -1559,10 +1563,11 @@ module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 
 always @* begin
 	if (EN == EN_POLARITY)
@@ -1580,10 +1585,11 @@ parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
+parameter INIT = {WIDTH{1'bx}};
 
 input EN;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q;
+output reg [WIDTH-1:0] Q = INIT;
 
 wire pos_en = EN == EN_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;

From 8241db6960d17469678e8c71fd7d6c1b7ddc4fe7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:17:09 -0800
Subject: [PATCH 338/528] write_verilog to cope with init attr on q when
 -noexpr

---
 backends/verilog/verilog_backend.cc | 34 +++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index a7f329ef8..04191443a 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1247,7 +1247,30 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	dump_attributes(f, indent, cell->attributes);
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
-	if (!defparam && cell->parameters.size() > 0) {
+	std::string init;
+	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+		auto q_wire = cell->getPort("\\Q");
+
+		Const initval;
+		bool gotinit = false;
+
+		for (auto bit : active_sigmap(q_wire)) {
+			if (active_initdata.count(bit)) {
+				initval.bits.push_back(active_initdata.at(bit));
+				gotinit = true;
+			} else {
+				initval.bits.push_back(State::Sx);
+			}
+		}
+
+		if (gotinit) {
+			std::stringstream ss;
+			dump_const(ss, initval);
+			init = ss.str();
+		}
+	}
+
+	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
 		f << stringf(" #(");
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
@@ -1257,6 +1280,11 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(")");
 		}
+		if (!init.empty()) {
+			if (!cell->parameters.empty())
+				f << stringf(",");
+			f << stringf("\n%s  .INIT(%s)", indent.c_str(), init.c_str());
+		}
 		f << stringf("\n%s" ")", indent.c_str());
 	}
 
@@ -1298,13 +1326,15 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 	f << stringf("\n%s" ");\n", indent.c_str());
 
-	if (defparam && cell->parameters.size() > 0) {
+	if (defparam && (cell->parameters.size() > 0 || !init.empty())) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
 			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(";\n");
 		}
+		if (!init.empty())
+			f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str());
 	}
 
 }

From c373640a3ac6c2f76f0a8dce4e44236154ca24bc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:28:44 -0800
Subject: [PATCH 339/528] Refactor

---
 backends/verilog/verilog_backend.cc | 26 +++++---------------------
 1 file changed, 5 insertions(+), 21 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 04191443a..66a9e70d3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	}
 }
 
-void dump_reg_init(std::ostream &f, SigSpec sig)
+void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
 {
 	Const initval;
 	bool gotinit = false;
@@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig)
 	}
 
 	if (gotinit) {
-		f << " = ";
+		if (write_equals) f << " = ";
 		dump_const(f, initval);
 	}
 }
@@ -1249,25 +1249,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	std::string init;
 	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
-		auto q_wire = cell->getPort("\\Q");
-
-		Const initval;
-		bool gotinit = false;
-
-		for (auto bit : active_sigmap(q_wire)) {
-			if (active_initdata.count(bit)) {
-				initval.bits.push_back(active_initdata.at(bit));
-				gotinit = true;
-			} else {
-				initval.bits.push_back(State::Sx);
-			}
-		}
-
-		if (gotinit) {
-			std::stringstream ss;
-			dump_const(ss, initval);
-			init = ss.str();
-		}
+		std::stringstream ss;
+		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
+		init = ss.str();
 	}
 
 	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {

From 3f87cf86ccefe6e66f768fbf19c34db97cf7246d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:30:19 -0800
Subject: [PATCH 340/528] Revert most of autotest.sh; for non *.v use Yosys to
 translate

---
 tests/tools/autotest.sh | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index c01ce5611..3bce003e1 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -113,16 +113,18 @@ do
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		else
-			cp ../$fn ${bn}_ref.${ext}
+			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
+			frontend="verilog"
 		fi
 
 		if [ ! -f ../${bn}_tb.v ]; then
-			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${ext}
+			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
 		else
 			cp ../${bn}_tb.v ${bn}_tb.v
 		fi
 		if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
-		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs
+		compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
+					"$toolsdir"/../../techlibs/common/simlib.v
 		if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
 
 		test_count=0
@@ -143,16 +145,16 @@ do
 		fi
 
 		if [ -n "$scriptfiles" ]; then
-			test_passes -f "$frontend $include_opts" ${bn}_ref.${ext} $scriptfiles
+			test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
 		elif [ -n "$scriptopt" ]; then
-			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${ext}
+			test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
 		elif [ "$frontend" = "verific" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
 		elif [ "$frontend" = "verific_gates" ]; then
 			test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
 		else
-			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${ext}
-			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${ext}
+			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
+			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
 		fi
 		touch ../${bn}.log
 	}

From 20ca795b87b810063cdcee6e92e3922281f6b092 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:53:40 -0800
Subject: [PATCH 341/528] Remove check for cell->name[0] == '$'

---
 backends/verilog/verilog_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 66a9e70d3..7b3a60e61 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1248,7 +1248,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
 	std::string init;
-	if (cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
 		init = ss.str();

From 40db2f2eb61287071f59f3e15bd1cd1bf2838d1d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 14:58:47 -0800
Subject: [PATCH 342/528] Refactor

---
 frontends/aiger/aigerparse.cc | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c7a9aecb9..7f9feee4a 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -30,15 +30,22 @@ YOSYS_NAMESPACE_BEGIN
 
 #define log_debug log
 
+static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name);
+
 void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
 {
     std::string header;
     f >> header;
-    if (header != "aag") {
+    if (header == "aag")
+        return parse_aiger_ascii(design, f, clk_name);
+    else {
         log_error("Unsupported AIGER file!\n");
         return;
     }
+}
 
+static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name)
+{
     int M, I, L, O, A;
     int B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
     if (!(f >> M >> I >> L >> O >> A)) {

From e8f4dc739c5cf1129800aaa88df3f7c6f9c99360 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 6 Feb 2019 15:51:12 -0800
Subject: [PATCH 343/528] Cope WIDTH of ff/latch cells is default of zero

---
 techlibs/common/simlib.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 9b6008140..a1e0c1575 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,7 +1464,7 @@ module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] D;
@@ -1484,7 +1484,7 @@ module \$dffe (CLK, EN, D, Q);
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, EN;
 input [WIDTH-1:0] D;
@@ -1506,7 +1506,7 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] SET, CLR, D;
@@ -1540,7 +1540,7 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter ARST_POLARITY = 1'b1;
 parameter ARST_VALUE = 0;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, ARST;
 input [WIDTH-1:0] D;
@@ -1563,7 +1563,7 @@ module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] D;
@@ -1585,7 +1585,7 @@ parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH{1'bx}};
+parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] SET, CLR, D;

From a4515712cb4ebf62168583fae0f3d60418c803c6 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Thu, 7 Feb 2019 10:35:36 +0000
Subject: [PATCH 344/528] fsm_opt: Fix runtime error for FSMs without a reset
 state

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/fsm/fsm_opt.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 3a6ac2746..048daee55 100644
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -72,7 +72,8 @@ struct FsmOpt
 
 			new_transition_table.swap(fsm_data.transition_table);
 			new_state_table.swap(fsm_data.state_table);
-			fsm_data.reset_state = old_to_new_state.at(fsm_data.reset_state);
+			if (fsm_data.reset_state != -1)
+				fsm_data.reset_state = old_to_new_state.at(fsm_data.reset_state);
 		}
 	}
 

From 791f93181df091877e0b233fa21ee5fa34b24b27 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 07:31:04 -0800
Subject: [PATCH 345/528] Stub for binary AIGER

---
 frontends/aiger/aigerparse.cc | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7f9feee4a..a33110ed0 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -31,6 +31,7 @@ YOSYS_NAMESPACE_BEGIN
 #define log_debug log
 
 static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name);
+static void parse_aiger_binary(RTLIL::Design *design, std::istream &f, std::string clk_name);
 
 void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
 {
@@ -38,10 +39,10 @@ void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
     f >> header;
     if (header == "aag")
         return parse_aiger_ascii(design, f, clk_name);
-    else {
+    else if (header == "aig")
+        return parse_aiger_binary(design, f, clk_name);
+    else
         log_error("Unsupported AIGER file!\n");
-        return;
-    }
 }
 
 static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name)
@@ -191,6 +192,10 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     module->fixup_ports();
 }
 
+static void parse_aiger_binary(RTLIL::Design *design, std::istream &f, std::string clk_name)
+{
+}
+
 struct AigerFrontend : public Frontend {
 	AigerFrontend() : Frontend("aiger", "read AIGER file") { }
 	void help() YS_OVERRIDE

From 6dbeda1807b285ff079c15067e2f649180524c08 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:03:40 -0800
Subject: [PATCH 346/528] Add support for symbol tables

---
 frontends/aiger/aigerparse.cc | 50 ++++++++++++++++++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index a33110ed0..7a53bb808 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -107,6 +107,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     int l1, l2, l3;
 
     // Parse inputs
+    std::vector<RTLIL::Wire*> inputs;
     for (int i = 0; i < I; ++i, ++line_count) {
         if (!(f >> l1)) {
             log_error("Line %d cannot be interpreted as an input!\n", line_count);
@@ -116,9 +117,11 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
         RTLIL::Wire *wire = createWireIfNotExists(l1);
         wire->port_input = true;
+        inputs.push_back(wire);
     }
 
     // Parse latches
+    std::vector<RTLIL::Wire*> latches;
     for (int i = 0; i < L; ++i, ++line_count) {
         if (!(f >> l1 >> l2)) {
             log_error("Line %d cannot be interpreted as a latch!\n", line_count);
@@ -139,9 +142,11 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
         // AIGER latches are assumed to be initialized to zero
         q_wire->attributes["\\init"] = RTLIL::Const(0);
+        latches.push_back(q_wire);
     }
 
     // Parse outputs
+    std::vector<RTLIL::Wire*> outputs;
     for (int i = 0; i < O; ++i, ++line_count) {
         if (!(f >> l1)) {
             log_error("Line %d cannot be interpreted as an output!\n", line_count);
@@ -151,9 +156,10 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         log_debug("%d is an output\n", l1);
         RTLIL::Wire *wire = createWireIfNotExists(l1);
         wire->port_output = true;
+        outputs.push_back(wire);
     }
     std::getline(f, line); // Ignore up to start of next line
-    
+
     // TODO: Parse bad state properties
     for (int i = 0; i < B; ++i, ++line_count)
         std::getline(f, line); // Ignore up to start of next line
@@ -188,6 +194,48 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 		and_cell->setPort("\\B", i2_wire);
 		and_cell->setPort("\\Y", o_wire);
     }
+    std::getline(f, line); // Ignore up to start of next line
+
+    std::string s;
+    for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
+        if (c == 'i' || c == 'o') {
+            f.ignore(1);
+            if (!(f >> l1 >> s)) {
+                log_error("Line %d cannot be interpreted as a symbol entry!\n", line_count);
+                return;
+            }
+
+            if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) {
+                log_error("Line %d has invalid symbol position!\n", line_count);
+                return;
+            }
+
+            RTLIL::Wire* wire;
+            if (c == 'i') wire = inputs[l1];
+            else if (c == 'l') wire = latches[l1];
+            else if (c == 'o') wire = outputs[l1];
+            else log_abort();
+
+            module->rename(wire, stringf("\\%s", s.c_str()));
+        }
+        else if (c == 'l') {
+        }
+        else if (c == 'b' || c == 'j' || c == 'f') {
+            // TODO
+        }
+        else if (c == 'c') {
+            f.ignore(1);
+            if (f.peek() == '\n')
+                break;
+            // Else constraint (TODO)
+            break;
+        }
+        else {
+            log_error("Line %d: cannot interpret first character '%c'!\n", line_count, c);
+            return;
+        }
+        std::getline(f, line); // Ignore up to start of next line
+    }
 
     module->fixup_ports();
 }

From 5a593ff41c44329e9a103d8c9f7a7351b1848043 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:04:48 -0800
Subject: [PATCH 347/528] Remove return after log_error

---
 frontends/aiger/aigerparse.cc | 36 +++++++++--------------------------
 1 file changed, 9 insertions(+), 27 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7a53bb808..950432578 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -49,16 +49,12 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 {
     int M, I, L, O, A;
     int B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
-    if (!(f >> M >> I >> L >> O >> A)) {
+    if (!(f >> M >> I >> L >> O >> A))
         log_error("Invalid AIGER header\n");
-        return;
-    }
     for (auto &i : std::array<std::reference_wrapper<int>,4>{B, C, J, F}) {
         if (f.peek() != ' ') break;
-        if (!(f >> i)) {
+        if (!(f >> i))
             log_error("Invalid AIGER header\n");
-            return;
-        }
     }
 
     std::string line;
@@ -109,10 +105,8 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     // Parse inputs
     std::vector<RTLIL::Wire*> inputs;
     for (int i = 0; i < I; ++i, ++line_count) {
-        if (!(f >> l1)) {
+        if (!(f >> l1))
             log_error("Line %d cannot be interpreted as an input!\n", line_count);
-            return;
-        }
         log_debug("%d is an input\n", l1);
         log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
         RTLIL::Wire *wire = createWireIfNotExists(l1);
@@ -123,10 +117,8 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     // Parse latches
     std::vector<RTLIL::Wire*> latches;
     for (int i = 0; i < L; ++i, ++line_count) {
-        if (!(f >> l1 >> l2)) {
+        if (!(f >> l1 >> l2))
             log_error("Line %d cannot be interpreted as a latch!\n", line_count);
-            return;
-        }
         log_debug("%d %d is a latch\n", l1, l2);
         log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
         RTLIL::Wire *q_wire = createWireIfNotExists(l1);
@@ -148,10 +140,8 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     // Parse outputs
     std::vector<RTLIL::Wire*> outputs;
     for (int i = 0; i < O; ++i, ++line_count) {
-        if (!(f >> l1)) {
+        if (!(f >> l1))
             log_error("Line %d cannot be interpreted as an output!\n", line_count);
-            return;
-        }
 
         log_debug("%d is an output\n", l1);
         RTLIL::Wire *wire = createWireIfNotExists(l1);
@@ -178,10 +168,8 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
     // Parse AND
     for (int i = 0; i < A; ++i, ++line_count) {
-        if (!(f >> l1 >> l2 >> l3)) {
+        if (!(f >> l1 >> l2 >> l3))
             log_error("Line %d cannot be interpreted as an AND!\n", line_count);
-            return;
-        }
 
         log_debug("%d %d %d is an AND\n", l1, l2, l3);
         log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
@@ -200,15 +188,11 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
         if (c == 'i' || c == 'o') {
             f.ignore(1);
-            if (!(f >> l1 >> s)) {
+            if (!(f >> l1 >> s))
                 log_error("Line %d cannot be interpreted as a symbol entry!\n", line_count);
-                return;
-            }
 
-            if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size())) {
+            if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
                 log_error("Line %d has invalid symbol position!\n", line_count);
-                return;
-            }
 
             RTLIL::Wire* wire;
             if (c == 'i') wire = inputs[l1];
@@ -230,10 +214,8 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
             // Else constraint (TODO)
             break;
         }
-        else {
+        else
             log_error("Line %d: cannot interpret first character '%c'!\n", line_count, c);
-            return;
-        }
         std::getline(f, line); // Ignore up to start of next line
     }
 

From 02f603ac1a43f3f98048c146b1950c776f73c070 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:05:27 -0800
Subject: [PATCH 348/528] Handle latch symbols too

---
 frontends/aiger/aigerparse.cc | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 950432578..a2b2f611e 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -186,7 +186,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
     std::string s;
     for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
-        if (c == 'i' || c == 'o') {
+        if (c == 'i' || c == 'l' || c == 'o') {
             f.ignore(1);
             if (!(f >> l1 >> s))
                 log_error("Line %d cannot be interpreted as a symbol entry!\n", line_count);
@@ -202,8 +202,6 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
             module->rename(wire, stringf("\\%s", s.c_str()));
         }
-        else if (c == 'l') {
-        }
         else if (c == 'b' || c == 'j' || c == 'f') {
             // TODO
         }

From fafa972238e91f6d25bfa307a4ead4035477df18 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:08:49 -0800
Subject: [PATCH 349/528] Create clk outside of latch loop

---
 frontends/aiger/aigerparse.cc | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index a2b2f611e..abff6d8d9 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -116,6 +116,15 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
     // Parse latches
     std::vector<RTLIL::Wire*> latches;
+    RTLIL::Wire *clk_wire = nullptr;
+    if (L > 0) {
+        RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
+        clk_wire = module->wire(clk_id);
+        log_assert(!clk_wire);
+        log_debug("Creating %s\n", clk_id.c_str());
+        clk_wire = module->addWire(clk_id);
+        clk_wire->port_input = true;
+    }
     for (int i = 0; i < L; ++i, ++line_count) {
         if (!(f >> l1 >> l2))
             log_error("Line %d cannot be interpreted as a latch!\n", line_count);
@@ -123,13 +132,6 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
         RTLIL::Wire *q_wire = createWireIfNotExists(l1);
         RTLIL::Wire *d_wire = createWireIfNotExists(l2);
-        RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
-        RTLIL::Wire *clk_wire = module->wire(clk_id);
-        if (!clk_wire) {
-            log_debug("Creating %s\n", clk_id.c_str());
-            clk_wire = module->addWire(clk_id);
-            clk_wire->port_input = true;
-        }
 
         module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
         // AIGER latches are assumed to be initialized to zero

From 652e414392b8e9e8c7dde74e6f2c2369d8d65a20 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:09:30 -0800
Subject: [PATCH 350/528] Change literal vars from int to unsigned

---
 frontends/aiger/aigerparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index abff6d8d9..0414d3db3 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -100,7 +100,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         return wire;
     };
 
-    int l1, l2, l3;
+    unsigned l1, l2, l3;
 
     // Parse inputs
     std::vector<RTLIL::Wire*> inputs;

From 5e24251a61b8798e597ac49bdc8aff2f378f625d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:37:18 -0800
Subject: [PATCH 351/528] Handle reset logic in latches

---
 frontends/aiger/aigerparse.cc | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 0414d3db3..c3cc6b321 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -134,8 +134,23 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         RTLIL::Wire *d_wire = createWireIfNotExists(l2);
 
         module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
-        // AIGER latches are assumed to be initialized to zero
-        q_wire->attributes["\\init"] = RTLIL::Const(0);
+
+        if (f.peek() == ' ') {
+            if (!(f >> l3))
+                log_error("Line %d cannot be interpreted as a latch!\n", line_count);
+
+            if (l3 == 0 || l3 == 1)
+                q_wire->attributes["\\init"] = RTLIL::Const(0);
+            else if (l3 == l1) {
+                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
+            }
+            else
+                log_error("Line %d has invalid reset literal for latch!\n", line_count);
+        }
+        else {
+            // AIGER latches are assumed to be initialized to zero
+            q_wire->attributes["\\init"] = RTLIL::Const(0);
+        }
         latches.push_back(q_wire);
     }
 

From 36c56bf4127edc1ed0f8fbbd62bd70a859263570 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 08:37:44 -0800
Subject: [PATCH 352/528] Add comment

---
 frontends/aiger/aigerparse.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c3cc6b321..56e4f3b2c 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -135,6 +135,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
         module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
 
+        // Reset logic is optional in AIGER 1.9
         if (f.peek() == ' ') {
             if (!(f >> l3))
                 log_error("Line %d cannot be interpreted as a latch!\n", line_count);

From 09d758f0a31e3b4290bfcd3d9864733e84c83628 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 10:54:31 -0800
Subject: [PATCH 353/528] Refactor to parse_aiger_header()

---
 frontends/aiger/aigerparse.cc | 58 +++++++++++++++++++----------------
 1 file changed, 32 insertions(+), 26 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 56e4f3b2c..4c15e34d2 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -45,13 +45,11 @@ void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
         log_error("Unsupported AIGER file!\n");
 }
 
-static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name)
+static void parse_aiger_header(std::istream &f, unsigned &M, unsigned &I, unsigned &L, unsigned &O, unsigned &A, unsigned &B, unsigned &C, unsigned &J, unsigned &F)
 {
-    int M, I, L, O, A;
-    int B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
     if (!(f >> M >> I >> L >> O >> A))
         log_error("Invalid AIGER header\n");
-    for (auto &i : std::array<std::reference_wrapper<int>,4>{B, C, J, F}) {
+    for (auto &i : std::array<std::reference_wrapper<unsigned>,4>{B, C, J, F}) {
         if (f.peek() != ' ') break;
         if (!(f >> i))
             log_error("Invalid AIGER header\n");
@@ -62,19 +60,27 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
                            // says anything that follows could be used for
                            // optional sections
     
-    log_debug("M=%d I=%d L=%d O=%d A=%d B=%d C=%d J=%d F=%d\n", M, I, L, O, A, B, C, J, F);
+    log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
+}
 
-    int line_count = 1;
+static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name)
+{
+    unsigned M, I, L, O, A;
+    unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
+    parse_aiger_header(f, M, I, L, O, A, B, C, J, F);
+
+    unsigned line_count = 1;
+    std::string line;
     std::stringstream ss;
 
     auto module = new RTLIL::Module;
     module->name = RTLIL::escape_id("aig"); // TODO: Name?
     if (design->module(module->name))
-        log_error("Duplicate definition of module %s in line %d!\n", log_id(module->name), line_count);
+        log_error("Duplicate definition of module %s in line %u!\n", log_id(module->name), line_count);
     design->add(module);
 
-    auto createWireIfNotExists = [module](int literal) {
-        const int variable = literal >> 1;
+    auto createWireIfNotExists = [module](unsigned literal) {
+        const unsigned variable = literal >> 1;
         const bool invert = literal & 1;
         RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
         RTLIL::Wire *wire = module->wire(wire_name);
@@ -104,9 +110,9 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
     // Parse inputs
     std::vector<RTLIL::Wire*> inputs;
-    for (int i = 0; i < I; ++i, ++line_count) {
+    for (unsigned i = 0; i < I; ++i, ++line_count) {
         if (!(f >> l1))
-            log_error("Line %d cannot be interpreted as an input!\n", line_count);
+            log_error("Line %u cannot be interpreted as an input!\n", line_count);
         log_debug("%d is an input\n", l1);
         log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
         RTLIL::Wire *wire = createWireIfNotExists(l1);
@@ -125,9 +131,9 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         clk_wire = module->addWire(clk_id);
         clk_wire->port_input = true;
     }
-    for (int i = 0; i < L; ++i, ++line_count) {
+    for (unsigned i = 0; i < L; ++i, ++line_count) {
         if (!(f >> l1 >> l2))
-            log_error("Line %d cannot be interpreted as a latch!\n", line_count);
+            log_error("Line %u cannot be interpreted as a latch!\n", line_count);
         log_debug("%d %d is a latch\n", l1, l2);
         log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
         RTLIL::Wire *q_wire = createWireIfNotExists(l1);
@@ -138,7 +144,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         // Reset logic is optional in AIGER 1.9
         if (f.peek() == ' ') {
             if (!(f >> l3))
-                log_error("Line %d cannot be interpreted as a latch!\n", line_count);
+                log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
             if (l3 == 0 || l3 == 1)
                 q_wire->attributes["\\init"] = RTLIL::Const(0);
@@ -146,7 +152,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
                 //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
             }
             else
-                log_error("Line %d has invalid reset literal for latch!\n", line_count);
+                log_error("Line %u has invalid reset literal for latch!\n", line_count);
         }
         else {
             // AIGER latches are assumed to be initialized to zero
@@ -157,9 +163,9 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
     // Parse outputs
     std::vector<RTLIL::Wire*> outputs;
-    for (int i = 0; i < O; ++i, ++line_count) {
+    for (unsigned i = 0; i < O; ++i, ++line_count) {
         if (!(f >> l1))
-            log_error("Line %d cannot be interpreted as an output!\n", line_count);
+            log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
         log_debug("%d is an output\n", l1);
         RTLIL::Wire *wire = createWireIfNotExists(l1);
@@ -169,25 +175,25 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     std::getline(f, line); // Ignore up to start of next line
 
     // TODO: Parse bad state properties
-    for (int i = 0; i < B; ++i, ++line_count)
+    for (unsigned i = 0; i < B; ++i, ++line_count)
         std::getline(f, line); // Ignore up to start of next line
 
     // TODO: Parse invariant constraints
-    for (int i = 0; i < C; ++i, ++line_count)
+    for (unsigned i = 0; i < C; ++i, ++line_count)
         std::getline(f, line); // Ignore up to start of next line
 
     // TODO: Parse justice properties
-    for (int i = 0; i < J; ++i, ++line_count)
+    for (unsigned i = 0; i < J; ++i, ++line_count)
         std::getline(f, line); // Ignore up to start of next line
 
     // TODO: Parse fairness constraints
-    for (int i = 0; i < F; ++i, ++line_count)
+    for (unsigned i = 0; i < F; ++i, ++line_count)
         std::getline(f, line); // Ignore up to start of next line
 
     // Parse AND
-    for (int i = 0; i < A; ++i, ++line_count) {
+    for (unsigned i = 0; i < A; ++i, ++line_count) {
         if (!(f >> l1 >> l2 >> l3))
-            log_error("Line %d cannot be interpreted as an AND!\n", line_count);
+            log_error("Line %u cannot be interpreted as an AND!\n", line_count);
 
         log_debug("%d %d %d is an AND\n", l1, l2, l3);
         log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
@@ -207,10 +213,10 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
         if (c == 'i' || c == 'l' || c == 'o') {
             f.ignore(1);
             if (!(f >> l1 >> s))
-                log_error("Line %d cannot be interpreted as a symbol entry!\n", line_count);
+                log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
 
             if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
-                log_error("Line %d has invalid symbol position!\n", line_count);
+                log_error("Line %u has invalid symbol position!\n", line_count);
 
             RTLIL::Wire* wire;
             if (c == 'i') wire = inputs[l1];
@@ -231,7 +237,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
             break;
         }
         else
-            log_error("Line %d: cannot interpret first character '%c'!\n", line_count, c);
+            log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
         std::getline(f, line); // Ignore up to start of next line
     }
 

From 4e6c5e46725bb99e0c919a5f82ce5290da2ce2f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 11:41:25 -0800
Subject: [PATCH 354/528] Add binary AIGs converted from AAG

---
 tests/aiger/and.aig       | 3 +++
 tests/aiger/buffer.aig    | 2 ++
 tests/aiger/cnt1.aig      | 3 +++
 tests/aiger/cnt1e.aig     | 4 ++++
 tests/aiger/empty.aig     | 1 +
 tests/aiger/false.aig     | 2 ++
 tests/aiger/halfadder.aig | 9 +++++++++
 tests/aiger/inverter.aig  | 2 ++
 tests/aiger/notcnt1.aig   | 4 ++++
 tests/aiger/notcnt1e.aig  | 4 ++++
 tests/aiger/or.aig        | 3 +++
 tests/aiger/toggle-re.aig | 8 ++++++++
 tests/aiger/toggle.aig    | 4 ++++
 tests/aiger/true.aig      | 2 ++
 14 files changed, 51 insertions(+)
 create mode 100644 tests/aiger/and.aig
 create mode 100644 tests/aiger/buffer.aig
 create mode 100644 tests/aiger/cnt1.aig
 create mode 100644 tests/aiger/cnt1e.aig
 create mode 100644 tests/aiger/empty.aig
 create mode 100644 tests/aiger/false.aig
 create mode 100644 tests/aiger/halfadder.aig
 create mode 100644 tests/aiger/inverter.aig
 create mode 100644 tests/aiger/notcnt1.aig
 create mode 100644 tests/aiger/notcnt1e.aig
 create mode 100644 tests/aiger/or.aig
 create mode 100644 tests/aiger/toggle-re.aig
 create mode 100644 tests/aiger/toggle.aig
 create mode 100644 tests/aiger/true.aig

diff --git a/tests/aiger/and.aig b/tests/aiger/and.aig
new file mode 100644
index 000000000..da0fa0719
--- /dev/null
+++ b/tests/aiger/and.aig
@@ -0,0 +1,3 @@
+aig 3 2 0 1 1
+6
+
\ No newline at end of file
diff --git a/tests/aiger/buffer.aig b/tests/aiger/buffer.aig
new file mode 100644
index 000000000..0c715fdeb
--- /dev/null
+++ b/tests/aiger/buffer.aig
@@ -0,0 +1,2 @@
+aig 1 1 0 1 0
+2
diff --git a/tests/aiger/cnt1.aig b/tests/aiger/cnt1.aig
new file mode 100644
index 000000000..8d0ba13b1
--- /dev/null
+++ b/tests/aiger/cnt1.aig
@@ -0,0 +1,3 @@
+aig 1 0 1 0 0 1
+3
+2
diff --git a/tests/aiger/cnt1e.aig b/tests/aiger/cnt1e.aig
new file mode 100644
index 000000000..d8d159f11
--- /dev/null
+++ b/tests/aiger/cnt1e.aig
@@ -0,0 +1,4 @@
+aig 5 1 1 0 3 1
+10
+4
+

b0 AIGER_NEVER
diff --git a/tests/aiger/empty.aig b/tests/aiger/empty.aig
new file mode 100644
index 000000000..a28373cd3
--- /dev/null
+++ b/tests/aiger/empty.aig
@@ -0,0 +1 @@
+aig 0 0 0 0 0
diff --git a/tests/aiger/false.aig b/tests/aiger/false.aig
new file mode 100644
index 000000000..ad7d039fa
--- /dev/null
+++ b/tests/aiger/false.aig
@@ -0,0 +1,2 @@
+aig 0 0 0 1 0
+0
diff --git a/tests/aiger/halfadder.aig b/tests/aiger/halfadder.aig
new file mode 100644
index 000000000..83727ee63
--- /dev/null
+++ b/tests/aiger/halfadder.aig
@@ -0,0 +1,9 @@
+aig 5 2 0 2 3
+10
+6
+
i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder
diff --git a/tests/aiger/inverter.aig b/tests/aiger/inverter.aig
new file mode 100644
index 000000000..525d82392
--- /dev/null
+++ b/tests/aiger/inverter.aig
@@ -0,0 +1,2 @@
+aig 1 1 0 1 0
+3
diff --git a/tests/aiger/notcnt1.aig b/tests/aiger/notcnt1.aig
new file mode 100644
index 000000000..f8a667f1f
--- /dev/null
+++ b/tests/aiger/notcnt1.aig
@@ -0,0 +1,4 @@
+aig 1 0 1 0 0 1
+3
+3
+b0 AIGER_NEVER
diff --git a/tests/aiger/notcnt1e.aig b/tests/aiger/notcnt1e.aig
new file mode 100644
index 000000000..7c85a7290
--- /dev/null
+++ b/tests/aiger/notcnt1e.aig
@@ -0,0 +1,4 @@
+aig 5 1 1 0 3 1
+10
+5
+

b0 AIGER_NEVER
diff --git a/tests/aiger/or.aig b/tests/aiger/or.aig
new file mode 100644
index 000000000..75c9e4480
--- /dev/null
+++ b/tests/aiger/or.aig
@@ -0,0 +1,3 @@
+aig 3 2 0 1 1
+7
+

\ No newline at end of file
diff --git a/tests/aiger/toggle-re.aig b/tests/aiger/toggle-re.aig
new file mode 100644
index 000000000..9d6730f21
--- /dev/null
+++ b/tests/aiger/toggle-re.aig
@@ -0,0 +1,8 @@
+aig 7 2 1 2 4
+14
+6
+7
+
i0 enable
+i1 reset
+o0 Q
+o1 !Q
diff --git a/tests/aiger/toggle.aig b/tests/aiger/toggle.aig
new file mode 100644
index 000000000..b69e21aaf
--- /dev/null
+++ b/tests/aiger/toggle.aig
@@ -0,0 +1,4 @@
+aig 1 0 1 2 0
+3
+2
+3
diff --git a/tests/aiger/true.aig b/tests/aiger/true.aig
new file mode 100644
index 000000000..10086f389
--- /dev/null
+++ b/tests/aiger/true.aig
@@ -0,0 +1,2 @@
+aig 0 0 0 1 0
+1

From 2a8cc36578be9a9d1645e435c3a79eb7d1abc7b2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 11:45:16 -0800
Subject: [PATCH 355/528] Parse binary AIG files

---
 frontends/aiger/aigerparse.cc | 215 ++++++++++++++++++++++++++--------
 1 file changed, 165 insertions(+), 50 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 4c15e34d2..4bc3918be 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -30,19 +30,55 @@ YOSYS_NAMESPACE_BEGIN
 
 #define log_debug log
 
-static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name);
-static void parse_aiger_binary(RTLIL::Design *design, std::istream &f, std::string clk_name);
+static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::string clk_name);
+static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::string clk_name);
 
 void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
 {
+    auto module = new RTLIL::Module;
+    module->name = RTLIL::escape_id("aig"); // TODO: Name?
+    if (design->module(module->name))
+        log_error("Duplicate definition of module %s!\n", log_id(module->name));
+
     std::string header;
     f >> header;
     if (header == "aag")
-        return parse_aiger_ascii(design, f, clk_name);
+        parse_aiger_ascii(module, f, clk_name);
     else if (header == "aig")
-        return parse_aiger_binary(design, f, clk_name);
+        parse_aiger_binary(module, f, clk_name);
     else
         log_error("Unsupported AIGER file!\n");
+
+    module->fixup_ports();
+    design->add(module);
+}
+
+static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
+{
+    const unsigned variable = literal >> 1;
+    const bool invert = literal & 1;
+    RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
+    RTLIL::Wire *wire = module->wire(wire_name);
+    if (wire) return wire;
+    log_debug("Creating %s\n", wire_name.c_str());
+    wire = module->addWire(wire_name);
+    if (!invert) return wire;
+    RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
+    RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
+    if (wire_inv) {
+        if (module->cell(wire_inv_name)) return wire;
+    }
+    else {
+        log_debug("Creating %s\n", wire_inv_name.c_str());
+        wire_inv = module->addWire(wire_inv_name);
+    }
+
+    log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
+    RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
+    inv->setPort("\\A", wire_inv);
+    inv->setPort("\\Y", wire);
+
+    return wire;
 }
 
 static void parse_aiger_header(std::istream &f, unsigned &M, unsigned &I, unsigned &L, unsigned &O, unsigned &A, unsigned &B, unsigned &C, unsigned &J, unsigned &F)
@@ -56,14 +92,14 @@ static void parse_aiger_header(std::istream &f, unsigned &M, unsigned &I, unsign
     }
 
     std::string line;
-    std::getline(f, line); // Ignore up to start of next ine, as standard
+    std::getline(f, line); // Ignore up to start of next line, as standard
                            // says anything that follows could be used for
                            // optional sections
     
     log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
 }
 
-static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::string clk_name)
+static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::string clk_name)
 {
     unsigned M, I, L, O, A;
     unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
@@ -73,39 +109,6 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
     std::string line;
     std::stringstream ss;
 
-    auto module = new RTLIL::Module;
-    module->name = RTLIL::escape_id("aig"); // TODO: Name?
-    if (design->module(module->name))
-        log_error("Duplicate definition of module %s in line %u!\n", log_id(module->name), line_count);
-    design->add(module);
-
-    auto createWireIfNotExists = [module](unsigned literal) {
-        const unsigned variable = literal >> 1;
-        const bool invert = literal & 1;
-        RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
-        RTLIL::Wire *wire = module->wire(wire_name);
-        if (wire) return wire;
-        log_debug("Creating %s\n", wire_name.c_str());
-        wire = module->addWire(wire_name);
-        if (!invert) return wire;
-        RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
-        RTLIL::Wire *wire_inv = module->wire(wire_inv_name); 
-        if (wire_inv) {
-            if (module->cell(wire_inv_name)) return wire;
-        } 
-        else {
-            log_debug("Creating %s\n", wire_inv_name.c_str());
-            wire_inv = module->addWire(wire_inv_name);
-        }
-
-        log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-        RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
-        inv->setPort("\\A", wire_inv);
-        inv->setPort("\\Y", wire);
-
-        return wire;
-    };
-
     unsigned l1, l2, l3;
 
     // Parse inputs
@@ -115,7 +118,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
             log_error("Line %u cannot be interpreted as an input!\n", line_count);
         log_debug("%d is an input\n", l1);
         log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
-        RTLIL::Wire *wire = createWireIfNotExists(l1);
+        RTLIL::Wire *wire = createWireIfNotExists(module, l1);
         wire->port_input = true;
         inputs.push_back(wire);
     }
@@ -136,8 +139,8 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
             log_error("Line %u cannot be interpreted as a latch!\n", line_count);
         log_debug("%d %d is a latch\n", l1, l2);
         log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
-        RTLIL::Wire *q_wire = createWireIfNotExists(l1);
-        RTLIL::Wire *d_wire = createWireIfNotExists(l2);
+        RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
+        RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
         module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
 
@@ -147,7 +150,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
                 log_error("Line %u cannot be interpreted as a latch!\n", line_count);
 
             if (l3 == 0 || l3 == 1)
-                q_wire->attributes["\\init"] = RTLIL::Const(0);
+                q_wire->attributes["\\init"] = RTLIL::Const(l3);
             else if (l3 == l1) {
                 //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
             }
@@ -168,7 +171,7 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
             log_error("Line %u cannot be interpreted as an output!\n", line_count);
 
         log_debug("%d is an output\n", l1);
-        RTLIL::Wire *wire = createWireIfNotExists(l1);
+        RTLIL::Wire *wire = createWireIfNotExists(module, l1);
         wire->port_output = true;
         outputs.push_back(wire);
     }
@@ -197,9 +200,9 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
 
         log_debug("%d %d %d is an AND\n", l1, l2, l3);
         log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
-        RTLIL::Wire *o_wire = createWireIfNotExists(l1);
-        RTLIL::Wire *i1_wire = createWireIfNotExists(l2);
-        RTLIL::Wire *i2_wire = createWireIfNotExists(l3);
+        RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
+        RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
+        RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 
 		RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
 		and_cell->setPort("\\A", i1_wire);
@@ -240,12 +243,124 @@ static void parse_aiger_ascii(RTLIL::Design *design, std::istream &f, std::strin
             log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
         std::getline(f, line); // Ignore up to start of next line
     }
-
-    module->fixup_ports();
 }
 
-static void parse_aiger_binary(RTLIL::Design *design, std::istream &f, std::string clk_name)
+static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
 {
+    unsigned x = 0, i = 0;
+    unsigned char ch;
+    while ((ch = f.get()) & 0x80)
+        x |= (ch & 0x7f) << (7 * i++);
+    return ref - (x | (ch << (7 * i)));
+}
+
+static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::string clk_name)
+{
+    unsigned M, I, L, O, A;
+    unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
+    parse_aiger_header(f, M, I, L, O, A, B, C, J, F);
+
+    unsigned line_count = 1;
+    unsigned l1, l2, l3;
+    std::string line;
+
+    // Parse inputs
+    std::vector<RTLIL::Wire*> inputs;
+    for (unsigned i = 1; i <= I; ++i) {
+        RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
+        wire->port_input = true;
+        inputs.push_back(wire);
+    }
+
+    // Parse latches
+    std::vector<RTLIL::Wire*> latches;
+    RTLIL::Wire *clk_wire = nullptr;
+    if (L > 0) {
+        RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
+        clk_wire = module->wire(clk_id);
+        log_assert(!clk_wire);
+        log_debug("Creating %s\n", clk_id.c_str());
+        clk_wire = module->addWire(clk_id);
+        clk_wire->port_input = true;
+    }
+    l1 = (I+1) * 2;
+    for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
+        if (!(f >> l2))
+            log_error("Line %u cannot be interpreted as a latch!\n", line_count);
+        log_debug("%d %d is a latch\n", l1, l2);
+        RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
+        RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
+
+        module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+
+        // Reset logic is optional in AIGER 1.9
+        if (f.peek() == ' ') {
+            if (!(f >> l3))
+                log_error("Line %u cannot be interpreted as a latch!\n", line_count);
+
+            if (l3 == 0 || l3 == 1)
+                q_wire->attributes["\\init"] = RTLIL::Const(l3);
+            else if (l3 == l1) {
+                //q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
+            }
+            else
+                log_error("Line %u has invalid reset literal for latch!\n", line_count);
+        }
+        else {
+            // AIGER latches are assumed to be initialized to zero
+            q_wire->attributes["\\init"] = RTLIL::Const(0);
+        }
+        latches.push_back(q_wire);
+    }
+
+    // Parse outputs
+    std::vector<RTLIL::Wire*> outputs;
+    for (unsigned i = 0; i < O; ++i, ++line_count) {
+        if (!(f >> l1))
+            log_error("Line %u cannot be interpreted as an output!\n", line_count);
+
+        log_debug("%d is an output\n", l1);
+        RTLIL::Wire *wire = createWireIfNotExists(module, l1);
+        wire->port_output = true;
+        outputs.push_back(wire);
+    }
+    std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse bad state properties
+    for (unsigned i = 0; i < B; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse invariant constraints
+    for (unsigned i = 0; i < C; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse justice properties
+    for (unsigned i = 0; i < J; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // TODO: Parse fairness constraints
+    for (unsigned i = 0; i < F; ++i, ++line_count)
+        std::getline(f, line); // Ignore up to start of next line
+
+    // Parse AND
+    l1 = (I+L+1) << 1;
+    for (unsigned i = 0; i < A; ++i, ++line_count, l1 += 2) {
+        l2 = parse_next_delta_literal(f, l1);
+        l3 = parse_next_delta_literal(f, l2);
+
+        log_debug("%d %d %d is an AND\n", l1, l2, l3);
+        log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
+        RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
+        RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
+        RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
+
+		RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
+		and_cell->setPort("\\A", i1_wire);
+		and_cell->setPort("\\B", i2_wire);
+		and_cell->setPort("\\Y", o_wire);
+    }
+    std::getline(f, line); // Ignore up to start of next line
+
 }
 
 struct AigerFrontend : public Frontend {

From f1befe1b44ada400e979f43e1b35ebe022ff8fe8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 12:04:26 -0800
Subject: [PATCH 356/528] Refactor into AigerReader class

---
 frontends/aiger/aigerparse.cc | 154 ++++++++++++++++------------------
 frontends/aiger/aigerparse.h  |  21 ++++-
 2 files changed, 94 insertions(+), 81 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 4bc3918be..365bf1b69 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -30,25 +30,85 @@ YOSYS_NAMESPACE_BEGIN
 
 #define log_debug log
 
-static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::string clk_name);
-static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::string clk_name);
-
-void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name)
+AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name)
+    : design(design), f(f), clk_name(clk_name)
 {
-    auto module = new RTLIL::Module;
+    module = new RTLIL::Module;
     module->name = RTLIL::escape_id("aig"); // TODO: Name?
     if (design->module(module->name))
         log_error("Duplicate definition of module %s!\n", log_id(module->name));
+}
 
+void AigerReader::parse_aiger()
+{
     std::string header;
     f >> header;
-    if (header == "aag")
-        parse_aiger_ascii(module, f, clk_name);
-    else if (header == "aig")
-        parse_aiger_binary(module, f, clk_name);
-    else
+    if (header != "aag" && header != "aig")
         log_error("Unsupported AIGER file!\n");
 
+    // Parse rest of header
+    if (!(f >> M >> I >> L >> O >> A))
+        log_error("Invalid AIGER header\n");
+
+    // Optional values
+    B = C = J = F = 0;
+    for (auto &i : std::array<std::reference_wrapper<unsigned>,4>{B, C, J, F}) {
+        if (f.peek() != ' ') break;
+        if (!(f >> i))
+            log_error("Invalid AIGER header\n");
+    }
+
+    std::string line;
+    std::getline(f, line); // Ignore up to start of next line, as standard
+                           // says anything that follows could be used for
+                           // optional sections
+
+    log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
+
+    line_count = 1;
+
+    if (header == "aag")
+        parse_aiger_ascii();
+    else if (header == "aig")
+        parse_aiger_binary();
+    else
+        log_abort();
+
+    // Parse footer (symbol table, comments, etc.)
+    unsigned l1;
+    std::string s;
+    for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
+        if (c == 'i' || c == 'l' || c == 'o') {
+            f.ignore(1);
+            if (!(f >> l1 >> s))
+                log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
+
+            if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
+                log_error("Line %u has invalid symbol position!\n", line_count);
+
+            RTLIL::Wire* wire;
+            if (c == 'i') wire = inputs[l1];
+            else if (c == 'l') wire = latches[l1];
+            else if (c == 'o') wire = outputs[l1];
+            else log_abort();
+
+            module->rename(wire, stringf("\\%s", s.c_str()));
+        }
+        else if (c == 'b' || c == 'j' || c == 'f') {
+            // TODO
+        }
+        else if (c == 'c') {
+            f.ignore(1);
+            if (f.peek() == '\n')
+                break;
+            // Else constraint (TODO)
+            break;
+        }
+        else
+            log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
+        std::getline(f, line); // Ignore up to start of next line
+    }
+
     module->fixup_ports();
     design->add(module);
 }
@@ -81,38 +141,14 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
     return wire;
 }
 
-static void parse_aiger_header(std::istream &f, unsigned &M, unsigned &I, unsigned &L, unsigned &O, unsigned &A, unsigned &B, unsigned &C, unsigned &J, unsigned &F)
+void AigerReader::parse_aiger_ascii()
 {
-    if (!(f >> M >> I >> L >> O >> A))
-        log_error("Invalid AIGER header\n");
-    for (auto &i : std::array<std::reference_wrapper<unsigned>,4>{B, C, J, F}) {
-        if (f.peek() != ' ') break;
-        if (!(f >> i))
-            log_error("Invalid AIGER header\n");
-    }
-
-    std::string line;
-    std::getline(f, line); // Ignore up to start of next line, as standard
-                           // says anything that follows could be used for
-                           // optional sections
-    
-    log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
-}
-
-static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::string clk_name)
-{
-    unsigned M, I, L, O, A;
-    unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
-    parse_aiger_header(f, M, I, L, O, A, B, C, J, F);
-
-    unsigned line_count = 1;
     std::string line;
     std::stringstream ss;
 
     unsigned l1, l2, l3;
 
     // Parse inputs
-    std::vector<RTLIL::Wire*> inputs;
     for (unsigned i = 0; i < I; ++i, ++line_count) {
         if (!(f >> l1))
             log_error("Line %u cannot be interpreted as an input!\n", line_count);
@@ -124,7 +160,6 @@ static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::strin
     }
 
     // Parse latches
-    std::vector<RTLIL::Wire*> latches;
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
         RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
@@ -165,7 +200,6 @@ static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::strin
     }
 
     // Parse outputs
-    std::vector<RTLIL::Wire*> outputs;
     for (unsigned i = 0; i < O; ++i, ++line_count) {
         if (!(f >> l1))
             log_error("Line %u cannot be interpreted as an output!\n", line_count);
@@ -210,39 +244,6 @@ static void parse_aiger_ascii(RTLIL::Module *module, std::istream &f, std::strin
 		and_cell->setPort("\\Y", o_wire);
     }
     std::getline(f, line); // Ignore up to start of next line
-
-    std::string s;
-    for (int c = f.peek(); c != EOF; c = f.peek(), ++line_count) {
-        if (c == 'i' || c == 'l' || c == 'o') {
-            f.ignore(1);
-            if (!(f >> l1 >> s))
-                log_error("Line %u cannot be interpreted as a symbol entry!\n", line_count);
-
-            if ((c == 'i' && l1 > inputs.size()) || (c == 'l' && l1 > latches.size()) || (c == 'o' && l1 > outputs.size()))
-                log_error("Line %u has invalid symbol position!\n", line_count);
-
-            RTLIL::Wire* wire;
-            if (c == 'i') wire = inputs[l1];
-            else if (c == 'l') wire = latches[l1];
-            else if (c == 'o') wire = outputs[l1];
-            else log_abort();
-
-            module->rename(wire, stringf("\\%s", s.c_str()));
-        }
-        else if (c == 'b' || c == 'j' || c == 'f') {
-            // TODO
-        }
-        else if (c == 'c') {
-            f.ignore(1);
-            if (f.peek() == '\n')
-                break;
-            // Else constraint (TODO)
-            break;
-        }
-        else
-            log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
-        std::getline(f, line); // Ignore up to start of next line
-    }
 }
 
 static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
@@ -254,18 +255,12 @@ static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
     return ref - (x | (ch << (7 * i)));
 }
 
-static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::string clk_name)
+void AigerReader::parse_aiger_binary()
 {
-    unsigned M, I, L, O, A;
-    unsigned B=0, C=0, J=0, F=0; // Optional in AIGER 1.9
-    parse_aiger_header(f, M, I, L, O, A, B, C, J, F);
-
-    unsigned line_count = 1;
     unsigned l1, l2, l3;
     std::string line;
 
     // Parse inputs
-    std::vector<RTLIL::Wire*> inputs;
     for (unsigned i = 1; i <= I; ++i) {
         RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
         wire->port_input = true;
@@ -273,7 +268,6 @@ static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::stri
     }
 
     // Parse latches
-    std::vector<RTLIL::Wire*> latches;
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
         RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
@@ -314,7 +308,6 @@ static void parse_aiger_binary(RTLIL::Module *module, std::istream &f, std::stri
     }
 
     // Parse outputs
-    std::vector<RTLIL::Wire*> outputs;
     for (unsigned i = 0; i < O; ++i, ++line_count) {
         if (!(f >> l1))
             log_error("Line %u cannot be interpreted as an output!\n", line_count);
@@ -385,7 +378,8 @@ struct AigerFrontend : public Frontend {
 		}
 		extra_args(f, filename, args, argidx);
 
-		parse_aiger(design, *f);
+        AigerReader reader(design, *f);
+		reader.parse_aiger();
 	}
 } AigerFrontend;
 
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 6a250aa67..3e8ef09fc 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -24,7 +24,26 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-extern void parse_aiger(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
+struct AigerReader
+{
+    RTLIL::Design *design;
+    std::istream &f;
+    std::string clk_name;
+    RTLIL::Module *module;
+
+    unsigned M, I, L, O, A;
+    unsigned B, C, J, F; // Optional in AIGER 1.9
+    unsigned line_count;
+
+    std::vector<RTLIL::Wire*> inputs;
+    std::vector<RTLIL::Wire*> latches;
+    std::vector<RTLIL::Wire*> outputs;
+
+    AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
+    void parse_aiger();
+    void parse_aiger_ascii();
+    void parse_aiger_binary();
+};
 
 YOSYS_NAMESPACE_END
 

From fb8ad440a32da850e32765ec29119cacb3f3c27c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 12:40:43 -0800
Subject: [PATCH 357/528] Allow module name to be determined by argument too

---
 frontends/aiger/aigerparse.cc | 54 +++++++++++++++++++++++++++--------
 frontends/aiger/aigerparse.h  |  4 +--
 2 files changed, 44 insertions(+), 14 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 365bf1b69..6ebb524bd 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -30,11 +30,11 @@ YOSYS_NAMESPACE_BEGIN
 
 #define log_debug log
 
-AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name)
+AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
     : design(design), f(f), clk_name(clk_name)
 {
     module = new RTLIL::Module;
-    module->name = RTLIL::escape_id("aig"); // TODO: Name?
+    module->name = module_name;
     if (design->module(module->name))
         log_error("Duplicate definition of module %s!\n", log_id(module->name));
 }
@@ -162,11 +162,10 @@ void AigerReader::parse_aiger_ascii()
     // Parse latches
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
-        RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
-        clk_wire = module->wire(clk_id);
+        clk_wire = module->wire(clk_name);
         log_assert(!clk_wire);
-        log_debug("Creating %s\n", clk_id.c_str());
-        clk_wire = module->addWire(clk_id);
+        log_debug("Creating %s\n", clk_name.c_str());
+        clk_wire = module->addWire(clk_name);
         clk_wire->port_input = true;
     }
     for (unsigned i = 0; i < L; ++i, ++line_count) {
@@ -270,11 +269,10 @@ void AigerReader::parse_aiger_binary()
     // Parse latches
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
-        RTLIL::IdString clk_id = RTLIL::escape_id(clk_name.c_str());
-        clk_wire = module->wire(clk_id);
+        clk_wire = module->wire(clk_name);
         log_assert(!clk_wire);
-        log_debug("Creating %s\n", clk_id.c_str());
-        clk_wire = module->addWire(clk_id);
+        log_debug("Creating %s\n", clk_name.c_str());
+        clk_wire = module->addWire(clk_name);
         clk_wire->port_input = true;
     }
     l1 = (I+1) * 2;
@@ -364,21 +362,53 @@ struct AigerFrontend : public Frontend {
 		log("\n");
 		log("    read_aiger [options] [filename]\n");
 		log("\n");
-		log("Load modules from an AIGER file into the current design.\n");
+		log("Load module from an AIGER file into the current design.\n");
+		log("\n");
+		log("    -clk_name <wire_name>\n");
+		log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
+        log("        this name (default: clk)\n");
+        log("\n");
+		log("    -module_name <module_name>\n");
+		log("        Name of module to be created (default: <filename>)"
+#ifdef _WIN32
+		                                                   "top" // FIXME
+#else
+		                                                   "<filename>"
+#endif
+                                                           ")\n");
 		log("\n");
 	}
 	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		log_header(design, "Executing AIGER frontend.\n");
 
+        RTLIL::IdString clk_name = "\\clk";
+        RTLIL::IdString module_name;
+
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
+			if (arg == "-clk_name" && argidx+1 < args.size()) {
+				clk_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (arg == "-module_name" && argidx+1 < args.size()) {
+				module_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);
 
-        AigerReader reader(design, *f);
+        if (module_name.empty()) {
+#ifdef _WIN32
+            module_name = "top"; // FIXME: basename equivalent on Win32?
+#else
+            module_name = RTLIL::escape_id(basename(filename.c_str()));
+#endif
+        }
+
+        AigerReader reader(design, *f, module_name, clk_name);
 		reader.parse_aiger();
 	}
 } AigerFrontend;
diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 3e8ef09fc..39a77bd93 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -28,7 +28,7 @@ struct AigerReader
 {
     RTLIL::Design *design;
     std::istream &f;
-    std::string clk_name;
+    RTLIL::IdString clk_name;
     RTLIL::Module *module;
 
     unsigned M, I, L, O, A;
@@ -39,7 +39,7 @@ struct AigerReader
     std::vector<RTLIL::Wire*> latches;
     std::vector<RTLIL::Wire*> outputs;
 
-    AigerReader(RTLIL::Design *design, std::istream &f, std::string clk_name="clk");
+    AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
     void parse_aiger();
     void parse_aiger_ascii();
     void parse_aiger_binary();

From 391ec75b07cc8c10818884f19329d719847957d3 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 12:41:39 -0800
Subject: [PATCH 358/528] Add missing "[options]" to read_blif help

---
 frontends/blif/blifparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc
index 9116b257f..a6a07863f 100644
--- a/frontends/blif/blifparse.cc
+++ b/frontends/blif/blifparse.cc
@@ -584,7 +584,7 @@ struct BlifFrontend : public Frontend {
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    read_blif [filename]\n");
+		log("    read_blif [options] [filename]\n");
 		log("\n");
 		log("Load modules from a BLIF file into the current design.\n");
 		log("\n");

From 587872236ecd1ca2f2a466bccc8d41618feb0dfb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 12:41:59 -0800
Subject: [PATCH 359/528] Support and differentiate between ASCII and binary
 AIG testing

---
 tests/aiger/run-test.sh | 6 +++++-
 tests/tools/autotest.sh | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index 308578f01..e0a34f023 100755
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -17,4 +17,8 @@ if ! which iverilog > /dev/null ; then
   exit 1
 fi
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
+echo "===== AAG ======"
+${MAKE:-make} -f ../tools/autotest.mk $seed *.aag EXTRA_FLAGS="-f aiger"
+
+echo "===== AIG ======"
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.aig EXTRA_FLAGS="-f aiger"
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 3e1325b33..0ffa062e3 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -90,7 +90,7 @@ for fn
 do
 	bn=${fn%.*}
 	ext=${fn##*.}
-	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]]; then
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi

From aa66d8f12f89b457a4a23c04de706a36ee8fc114 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 12:49:55 -0800
Subject: [PATCH 360/528] -module_name arg to go before -clk_name

---
 frontends/aiger/aigerparse.cc | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 6ebb524bd..5c982fb59 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -363,13 +363,13 @@ struct AigerFrontend : public Frontend {
 		log("    read_aiger [options] [filename]\n");
 		log("\n");
 		log("Load module from an AIGER file into the current design.\n");
+        log("\n");
+		log("    -module_name <module_name>\n");
+		log("        Name of module to be created (default: <filename>)"
 		log("\n");
 		log("    -clk_name <wire_name>\n");
 		log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
         log("        this name (default: clk)\n");
-        log("\n");
-		log("    -module_name <module_name>\n");
-		log("        Name of module to be created (default: <filename>)"
 #ifdef _WIN32
 		                                                   "top" // FIXME
 #else
@@ -388,14 +388,14 @@ struct AigerFrontend : public Frontend {
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
 			std::string arg = args[argidx];
-			if (arg == "-clk_name" && argidx+1 < args.size()) {
-				clk_name = RTLIL::escape_id(args[++argidx]);
-				continue;
-			}
 			if (arg == "-module_name" && argidx+1 < args.size()) {
 				module_name = RTLIL::escape_id(args[++argidx]);
 				continue;
 			}
+			if (arg == "-clk_name" && argidx+1 < args.size()) {
+				clk_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
 			break;
 		}
 		extra_args(f, filename, args, argidx);

From afc3c4b6139db528b58062f544fb0b098ab212b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 13:17:02 -0800
Subject: [PATCH 361/528] Fix tabulation

---
 frontends/aiger/aigerparse.cc | 56 +++++++++++++++++------------------
 1 file changed, 28 insertions(+), 28 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 5c982fb59..154581179 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -237,10 +237,10 @@ void AigerReader::parse_aiger_ascii()
         RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
         RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 
-		RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-		and_cell->setPort("\\A", i1_wire);
-		and_cell->setPort("\\B", i2_wire);
-		and_cell->setPort("\\Y", o_wire);
+        RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
+        and_cell->setPort("\\A", i1_wire);
+        and_cell->setPort("\\B", i2_wire);
+        and_cell->setPort("\\Y", o_wire);
     }
     std::getline(f, line); // Ignore up to start of next line
 }
@@ -345,42 +345,42 @@ void AigerReader::parse_aiger_binary()
         RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
         RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 
-		RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-		and_cell->setPort("\\A", i1_wire);
-		and_cell->setPort("\\B", i2_wire);
-		and_cell->setPort("\\Y", o_wire);
+        RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
+        and_cell->setPort("\\A", i1_wire);
+        and_cell->setPort("\\B", i2_wire);
+        and_cell->setPort("\\Y", o_wire);
     }
     std::getline(f, line); // Ignore up to start of next line
 
 }
 
 struct AigerFrontend : public Frontend {
-	AigerFrontend() : Frontend("aiger", "read AIGER file") { }
-	void help() YS_OVERRIDE
-	{
-		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    read_aiger [options] [filename]\n");
-		log("\n");
-		log("Load module from an AIGER file into the current design.\n");
+    AigerFrontend() : Frontend("aiger", "read AIGER file") { }
+    void help() YS_OVERRIDE
+    {
+        //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
         log("\n");
-		log("    -module_name <module_name>\n");
-		log("        Name of module to be created (default: <filename>)"
-		log("\n");
-		log("    -clk_name <wire_name>\n");
-		log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
-        log("        this name (default: clk)\n");
+        log("    read_aiger [options] [filename]\n");
+        log("\n");
+        log("Load module from an AIGER file into the current design.\n");
+        log("\n");
+        log("    -module_name <module_name>\n");
+        log("        Name of module to be created (default: <filename>)"
 #ifdef _WIN32
 		                                                   "top" // FIXME
 #else
 		                                                   "<filename>"
 #endif
                                                            ")\n");
-		log("\n");
-	}
-	void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
-	{
-		log_header(design, "Executing AIGER frontend.\n");
+        log("\n");
+        log("    -clk_name <wire_name>\n");
+        log("        AIGER latches to be transformed into posedge DFFs clocked by wire of");
+        log("        this name (default: clk)\n");
+        log("\n");
+    }
+    void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+    {
+        log_header(design, "Executing AIGER frontend.\n");
 
         RTLIL::IdString clk_name = "\\clk";
         RTLIL::IdString module_name;
@@ -410,7 +410,7 @@ struct AigerFrontend : public Frontend {
 
         AigerReader reader(design, *f, module_name, clk_name);
 		reader.parse_aiger();
-	}
+    }
 } AigerFrontend;
 
 YOSYS_NAMESPACE_END

From 8886fa5506b227229398e5ac884203e799bce22c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Fri, 8 Feb 2019 13:17:53 -0800
Subject: [PATCH 362/528] addDff -> addDffGate as per @daveshah1

---
 frontends/aiger/aigerparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 154581179..c45de8531 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -176,7 +176,7 @@ void AigerReader::parse_aiger_ascii()
         RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
         RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
 
-        module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
+        module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
 
         // Reset logic is optional in AIGER 1.9
         if (f.peek() == ' ') {

From bb4164481d8b6eeec6bbc6f5b36f1286ada51eb5 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 11 Feb 2019 11:51:44 -0800
Subject: [PATCH 363/528] Do not ignore newline after AND in binary AIG

---
 frontends/aiger/aigerparse.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c45de8531..ed91b6990 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -242,7 +242,6 @@ void AigerReader::parse_aiger_ascii()
         and_cell->setPort("\\B", i2_wire);
         and_cell->setPort("\\Y", o_wire);
     }
-    std::getline(f, line); // Ignore up to start of next line
 }
 
 static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)

From 727ba52504c65be1fcda9b03f6c2e1498e10061d Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 11 Feb 2019 13:24:21 -0800
Subject: [PATCH 364/528] No increment line_count for binary ANDs

---
 frontends/aiger/aigerparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index ed91b6990..096e269b2 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -227,7 +227,7 @@ void AigerReader::parse_aiger_ascii()
         std::getline(f, line); // Ignore up to start of next line
 
     // Parse AND
-    for (unsigned i = 0; i < A; ++i, ++line_count) {
+    for (unsigned i = 0; i < A; ++i) {
         if (!(f >> l1 >> l2 >> l3))
             log_error("Line %u cannot be interpreted as an AND!\n", line_count);
 

From 04c580fde7a0d1d50c2d93bb6661b3f17a7d61a9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Mon, 11 Feb 2019 13:28:00 -0800
Subject: [PATCH 365/528] Do not break for constraints

---
 frontends/aiger/aigerparse.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 096e269b2..1e13e1124 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -102,7 +102,6 @@ void AigerReader::parse_aiger()
             if (f.peek() == '\n')
                 break;
             // Else constraint (TODO)
-            break;
         }
         else
             log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);

From 7913baedd8c776243cbcf5ce73549943d1fe83a2 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 12 Feb 2019 12:04:41 +0000
Subject: [PATCH 366/528] ecp5: Full set of IO-related blackboxes

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 102 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 32fb5c1ef..5b8d6bb4a 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -181,6 +181,31 @@ module IDDRX1F(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module IDDRX2F(
+	input D, SCLK, ECLK, RST,
+	output Q0, Q1, Q2, Q3
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDR71B(
+	input D, SCLK, ECLK, RST, ALIGNWD,
+	output Q0, Q1, Q2, Q3, Q4, Q5, Q6
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module IDDRX2DQA(
+	input D, DQSR90, ECLK, SCLK, RST,
+	input RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
+	output Q0, Q1, Q2, Q3, QWL
+);
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module ODDRX1F(
 	input SCLK, RST, D0, D1,
@@ -189,6 +214,83 @@ module ODDRX1F(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module ODDRX2F(
+	input SCLK, ECLK, RST, D0, D1, D2, D3,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDR71B(
+	input SCLK, ECLK, RST, D0, D1, D2, D3, D4, D5, D6,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module OSHX2A(
+	input D0, D1, RST, ECLK, SCLK,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2DQA(
+	input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW270,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module ODDRX2DQSB(
+	input D0, D1, D2, D3, RST, ECLK, SCLK, DQSW,
+	output Q
+);
+	parameter GSR = "ENABLED";
+endmodule
+
+(* blackbox *)
+module TSHX2DQA(
+	input T0, T1, SCLK, ECLK, DQSW270, RST,
+	output Q
+);
+	parameter GSR = "ENABLED";
+	parameter REGSET = "SET";
+endmodule
+
+(* blackbox *)
+module TSHX2DQSA(
+	input T0, T1, SCLK, ECLK, DQSW, RST,
+	output Q
+);
+	parameter GSR = "ENABLED";
+	parameter REGSET = "SET";
+endmodule
+
+
+(* blackbox *)
+module DQSBUFM(
+	input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
+	input ECLK, SCLK,
+	input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4,
+	input DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, 
+	input RST, RDLOADN, RDMOVE, RDDIRECTION, WRLOADN, WRMOVE, WRDIRECTION, PAUSE,
+	output DQSR90, DQSW, DQSW270,
+	output RDPNTR2, RDPNTR1, RDPNTR0, WRPNTR2, WRPNTR1, WRPNTR0,
+	output DATAVALID, BURSTDET, RDCFLAG, WRCFLAG
+);
+	parameter DQS_LI_DEL_ADJ = "FACTORYONLY";
+	parameter DQS_LI_DEL_VAL = 0;
+	parameter DQS_LO_DEL_ADJ = "FACTORYONLY";
+	parameter DQS_LO_DEL_VAL = 0;
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module CLKDIVF(
 	input CLKI, RST, ALIGNWD,

From a2ae39381124ccfec348293c7c7926597c26a5b8 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 12 Feb 2019 09:21:15 -0800
Subject: [PATCH 367/528] Use module->add{Not,And}Gate() functions

---
 frontends/aiger/aigerparse.cc | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c45de8531..888a4afe6 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -134,9 +134,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
     }
 
     log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
-    RTLIL::Cell *inv = module->addCell(stringf("\\n%d_not", variable), "$_NOT_"); // FIXME: is "_not" the right suffix?
-    inv->setPort("\\A", wire_inv);
-    inv->setPort("\\Y", wire);
+    module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
 
     return wire;
 }
@@ -236,11 +234,7 @@ void AigerReader::parse_aiger_ascii()
         RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
         RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
         RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
-
-        RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-        and_cell->setPort("\\A", i1_wire);
-        and_cell->setPort("\\B", i2_wire);
-        and_cell->setPort("\\Y", o_wire);
+        module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
     }
     std::getline(f, line); // Ignore up to start of next line
 }

From c23e3f07517d4818d9ab1b532250353492cf50c2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 12 Feb 2019 09:24:13 -0800
Subject: [PATCH 368/528] Missing headers for Xcode?

---
 passes/techmap/abc.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index d2d15a4a9..b215b1ea4 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -52,6 +52,8 @@
 #include <cerrno>
 #include <sstream>
 #include <climits>
+#include <array>
+#include <functional>
 
 #ifndef _WIN32
 #  include <unistd.h>

From e0bc190879d1c722c267ae9370a16ce202345b76 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 13 Feb 2019 11:23:25 +0000
Subject: [PATCH 369/528] ecp5: Add ECLKSYNCB blackbox

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/cells_bb.v | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 5b8d6bb4a..1de623fcd 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -272,7 +272,6 @@ module TSHX2DQSA(
 	parameter REGSET = "SET";
 endmodule
 
-
 (* blackbox *)
 module DQSBUFM(
 	input DQSI, READ1, READ0, READCLKSEL2, READCLKSEL1, READCLKSEL0, DDRDEL,
@@ -300,6 +299,13 @@ module CLKDIVF(
 	parameter DIV = "2.0";
 endmodule
 
+(* blackbox *)
+module ECLKSYNCB(
+	input ECLKI, STOP,
+	output ECLKO
+);
+endmodule
+
 (* blackbox *)
 module DCCA(
 	input CLKI, CE,

From 807b3c769733b8cf07f5b14674df41bd2788e09d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 13 Feb 2019 12:36:47 +0100
Subject: [PATCH 370/528] Fix sign handling of real constants

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 9531dd356..e66625228 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -942,16 +942,15 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 
 	// simply return the corresponding RTLIL::SigSpec for an AST_CONSTANT node
 	case AST_CONSTANT:
+	case AST_REALVALUE:
 		{
 			if (width_hint < 0)
 				detectSignWidth(width_hint, sign_hint);
-
 			is_signed = sign_hint;
-			return RTLIL::SigSpec(bitsAsConst());
-		}
 
-	case AST_REALVALUE:
-		{
+			if (type == AST_CONSTANT)
+				return RTLIL::SigSpec(bitsAsConst());
+
 			RTLIL::SigSpec sig = realAsConst(width_hint);
 			log_file_warning(filename, linenum, "converting real value %e to binary %s.\n", realvalue, log_signal(sig));
 			return sig;

From fc1c9aa11fbfbb1ea5b63e1830549d453ba01dfb Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:14:17 -0800
Subject: [PATCH 371/528] Update cells supported for verilog to FIRRTL
 conversion. Issue warning messages for missing parameterized modules and
 attempts to set initial values. Replace simple "if (cell-type)" with "else
 if" chain. Fix FIRRTL shift handling. Add support for parameterized modules,
 $shift, $shiftx. Handle default output file. Deal with no top module.
 Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be
 set in the environment for tests/tools/autotest.mk. Support FIRRTL regression
 testing in tests/tools/autotest.sh Add xfirrtl files to test directories to
 exclude files from FIRRTL regression tests that are known to fail.

---
 backends/firrtl/firrtl.cc | 273 +++++++++++++++++++++++++++++++-------
 tests/asicworld/xfirrtl   |  24 ++++
 tests/simple/xfirrtl      |  26 ++++
 tests/tools/autotest.mk   |   6 +-
 tests/tools/autotest.sh   |  43 +++++-
 5 files changed, 317 insertions(+), 55 deletions(-)
 create mode 100644 tests/asicworld/xfirrtl
 create mode 100644 tests/simple/xfirrtl

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 32410a651..7ca5dc756 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -23,7 +23,11 @@
 #include "kernel/celltypes.h"
 #include "kernel/cellaigs.h"
 #include "kernel/log.h"
+#include <algorithm>
 #include <string>
+#include <regex>
+#include <vector>
+#include <cmath>
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -37,6 +41,7 @@ static const FDirection FD_NODIRECTION = 0x0;
 static const FDirection FD_IN = 0x1;
 static const FDirection FD_OUT = 0x2;
 static const FDirection FD_INOUT = 0x3;
+static const int FIRRTL_MAX_DSH_WIDTH_ERROR = 20; // For historic reasons, this is actually one greater than the maximum allowed shift width
 
 // Get a port direction with respect to a specific module.
 FDirection getPortFDirection(IdString id, Module *module)
@@ -91,6 +96,23 @@ const char *make_id(IdString id)
 	return namecache.at(id).c_str();
 }
 
+static std::vector<string> Tokenize( const string str, const std::regex regex )
+{
+	using namespace std;
+
+	std::vector<string> result;
+
+	sregex_token_iterator it( str.begin(), str.end(), regex, -1 );
+	sregex_token_iterator reg_end;
+
+	for ( ; it != reg_end; ++it ) {
+		if ( !it->str().empty() ) //token could be empty:check
+			result.emplace_back( it->str() );
+	}
+
+	return result;
+}
+
 struct FirrtlWorker
 {
 	Module *module;
@@ -173,6 +195,26 @@ struct FirrtlWorker
 	void process_instance(RTLIL::Cell *cell, vector<string> &wire_exprs)
 	{
 		std::string cell_type = fid(cell->type);
+		std::string instanceOf;
+		// If this is a parameterized module, its parent module is encoded in the cell type
+		if (cell->type.substr(0, 8) == "$paramod")
+		{
+			std::string::iterator it;
+			for (it = cell_type.begin(); it < cell_type.end(); it++)
+			{
+				switch (*it) {
+					case '\\': /* FALL_THROUGH */
+					case '=': /* FALL_THROUGH */
+					case '\'': /* FALL_THROUGH */
+					case '$': instanceOf.append("_"); break;
+					default: instanceOf.append(1, *it); break;
+				}
+			}
+		}
+		else
+		{
+			instanceOf = cell_type;
+		}
 
 		std::string cell_name = cellname(cell);
 		std::string cell_name_comment;
@@ -182,7 +224,13 @@ struct FirrtlWorker
 			cell_name_comment = "";
 		// Find the module corresponding to this instance.
 		auto instModule = design->module(cell->type);
-		wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), cell_type.c_str()));
+		// If there is no instance for this, just return.
+		if (instModule == NULL)
+		{
+			log_warning("No instance for %s.%s\n", cell_type.c_str(), cell_name.c_str());
+			return;
+		}
+		wire_exprs.push_back(stringf("%s" "inst %s%s of %s", indent.c_str(), cell_name.c_str(), cell_name_comment.c_str(), instanceOf.c_str()));
 
 		for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
 			if (it->second.size() > 0) {
@@ -194,20 +242,20 @@ struct FirrtlWorker
 				std::string source, sink;
 				switch (dir) {
 					case FD_INOUT:
-						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", log_id(cell_type), log_signal(it->second));
+						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second));
 					case FD_OUT:
 						source = firstName;
 						sink = secondName;
 						break;
 					case FD_NODIRECTION:
-						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", log_id(cell_type), log_signal(it->second));
+						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second));
 						/* FALL_THROUGH */
 					case FD_IN:
 						source = secondName;
 						sink = firstName;
 						break;
 					default:
-						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", log_id(cell_type), log_signal(it->second), dir);
+						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
 						break;
 				}
 				wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sink.c_str(), source.c_str()));
@@ -217,6 +265,20 @@ struct FirrtlWorker
 
 	}
 
+	// Given an expression for a shift amount, and a maximum width,
+	//  generate the FIRRTL expression for equivalent dynamic shift taking into account FIRRTL shift semantics.
+	std::string gen_dshl(const string b_expr, const int b_padded_width)
+	{
+		string result = b_expr;
+		if (b_padded_width >= FIRRTL_MAX_DSH_WIDTH_ERROR) {
+			int max_shift_width_bits = FIRRTL_MAX_DSH_WIDTH_ERROR - 1;
+			string max_shift_string = stringf("UInt<%d>(%d)", max_shift_width_bits, (1<<max_shift_width_bits) - 1);
+			// Deal with the difference in semantics between FIRRTL and verilog
+			result = stringf("mux(gt(%s, %s), %s, bits(%s, %d, 0))", b_expr.c_str(), max_shift_string.c_str(), max_shift_string.c_str(), b_expr.c_str(), max_shift_width_bits - 1);
+		}
+		return result;
+	}
+
 	void run()
 	{
 		f << stringf("  module %s:\n", make_id(module->name));
@@ -225,6 +287,12 @@ struct FirrtlWorker
 		for (auto wire : module->wires())
 		{
 			const auto wireName = make_id(wire->name);
+			// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
+			if (wire->attributes.count("\\init")) {
+				log_warning("Initial value (%s) for (%s.%s) not supported\n",
+							wire->attributes.at("\\init").as_string().c_str(),
+							log_id(module), log_id(wire));
+			}
 			if (wire->port_id)
 			{
 				if (wire->port_input && wire->port_output)
@@ -240,7 +308,8 @@ struct FirrtlWorker
 
 		for (auto cell : module->cells())
 		{
-		  // Is this cell is a module instance?
+			bool extract_y_bits = false;		// Assume no extraction of final bits will be required.
+		    // Is this cell is a module instance?
 			if (cell->type[0] != '$')
 			{
 				process_instance(cell, wire_exprs);
@@ -264,21 +333,21 @@ struct FirrtlWorker
 				}
 
 				string primop;
-                                bool always_uint = false;
+				bool always_uint = false;
 				if (cell->type == "$not") primop = "not";
-				if (cell->type == "$neg") primop = "neg";
-				if (cell->type == "$logic_not") {
+				else if (cell->type == "$neg") primop = "neg";
+				else if (cell->type == "$logic_not") {
                                         primop = "eq";
                                         a_expr = stringf("%s, UInt(0)", a_expr.c_str());
                                 }
-				if (cell->type == "$reduce_and") primop = "andr";
-				if (cell->type == "$reduce_or") primop = "orr";
-				if (cell->type == "$reduce_xor") primop = "xorr";
-				if (cell->type == "$reduce_xnor") {
+				else if (cell->type == "$reduce_and") primop = "andr";
+				else if (cell->type == "$reduce_or") primop = "orr";
+				else if (cell->type == "$reduce_xor") primop = "xorr";
+				else if (cell->type == "$reduce_xnor") {
                                         primop = "not";
                                         a_expr = stringf("xorr(%s)", a_expr.c_str());
                                 }
-				if (cell->type == "$reduce_bool") {
+				else if (cell->type == "$reduce_bool") {
 					primop = "neq";
 					// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
 					bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool();
@@ -297,14 +366,16 @@ struct FirrtlWorker
 				continue;
 			}
 			if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$and", "$or", "$eq", "$eqx",
-                                        "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
-                                        "$logic_and", "$logic_or"))
+							  "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
+							  "$logic_and", "$logic_or"))
 			{
 				string y_id = make_id(cell->name);
 				bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 				int y_width =  cell->parameters.at("\\Y_WIDTH").as_int();
 				string a_expr = make_expr(cell->getPort("\\A"));
+				int a_padded_width = cell->parameters.at("\\A_WIDTH").as_int();
 				string b_expr = make_expr(cell->getPort("\\B"));
+				int b_padded_width = cell->parameters.at("\\B_WIDTH").as_int();
 				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
 
 				if (cell->parameters.at("\\A_SIGNED").as_bool()) {
@@ -315,67 +386,93 @@ struct FirrtlWorker
 					if (cell->parameters.at("\\B_SIGNED").as_bool()) {
 						b_expr = "asSInt(" + b_expr + ")";
 					}
-					b_expr = stringf("pad(%s, %d)", b_expr.c_str(), y_width);
+					if (b_padded_width < y_width) {
+						auto b_sig = cell->getPort("\\B");
+						b_padded_width = y_width;
+					}
 				}
 
-				a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
+				auto a_sig = cell->getPort("\\A");
 
 				if (cell->parameters.at("\\A_SIGNED").as_bool()  & (cell->type == "$shr")) {
 					a_expr = "asUInt(" + a_expr + ")";
 				}
 
 				string primop;
-                                bool always_uint = false;
+				bool always_uint = false;
 				if (cell->type == "$add") primop = "add";
-				if (cell->type == "$sub") primop = "sub";
-				if (cell->type == "$mul") primop = "mul";
-				if (cell->type == "$div") primop = "div";
-				if (cell->type == "$mod") primop = "rem";
-				if (cell->type == "$and") {
+				else if (cell->type == "$sub") primop = "sub";
+				else if (cell->type == "$mul") primop = "mul";
+				else if (cell->type == "$div") primop = "div";
+				else if (cell->type == "$mod") primop = "rem";
+				else if (cell->type == "$and") {
                                         primop = "and";
                                         always_uint = true;
                                 }
-				if (cell->type == "$or" ) {
+				else if (cell->type == "$or" ) {
                                         primop =  "or";
                                         always_uint = true;
                                 }
-				if (cell->type == "$xor") {
+				else if (cell->type == "$xor") {
                                         primop = "xor";
                                         always_uint = true;
                                 }
-				if ((cell->type == "$eq") | (cell->type == "$eqx")) {
+				else if ((cell->type == "$eq") | (cell->type == "$eqx")) {
                                         primop = "eq";
                                         always_uint = true;
                                 }
-				if ((cell->type == "$ne") | (cell->type == "$nex")) {
+				else if ((cell->type == "$ne") | (cell->type == "$nex")) {
                                         primop = "neq";
                                         always_uint = true;
                                 }
-				if (cell->type == "$gt") {
+				else if (cell->type == "$gt") {
                                         primop = "gt";
                                         always_uint = true;
                                 }
-				if (cell->type == "$ge") {
+				else if (cell->type == "$ge") {
                                         primop = "geq";
                                         always_uint = true;
                                 }
-				if (cell->type == "$lt") {
+				else if (cell->type == "$lt") {
                                         primop = "lt";
                                         always_uint = true;
                                 }
-				if (cell->type == "$le") {
+				else if (cell->type == "$le") {
                                         primop = "leq";
                                         always_uint = true;
                                 }
-				if ((cell->type == "$shl") | (cell->type == "$sshl")) primop = "dshl";
-				if ((cell->type == "$shr") | (cell->type == "$sshr")) primop = "dshr";
-				if ((cell->type == "$logic_and")) {
+				else if ((cell->type == "$shl") | (cell->type == "$sshl")) {
+					// FIRRTL will widen the result (y) by the amount of the shift.
+					// We'll need to offset this by extracting the un-widened portion as Verilog would do.
+					extract_y_bits = true;
+					// Is the shift amount constant?
+					auto b_sig = cell->getPort("\\B");
+					if (b_sig.is_fully_const()) {
+						primop = "shl";
+					} else {
+						primop = "dshl";
+						// Convert from FIRRTL left shift semantics.
+						b_expr = gen_dshl(b_expr, b_padded_width);
+					}
+				}
+				else if ((cell->type == "$shr") | (cell->type == "$sshr")) {
+					// We don't need to extract a specific range of bits.
+					extract_y_bits = false;
+					// Is the shift amount constant?
+					auto b_sig = cell->getPort("\\B");
+					if (b_sig.is_fully_const()) {
+						primop = "shr";
+					} else {
+						primop = "dshr";
+					}
+				}
+				else if ((cell->type == "$logic_and")) {
                                         primop = "and";
                                         a_expr = "neq(" + a_expr + ", UInt(0))";
                                         b_expr = "neq(" + b_expr + ", UInt(0))";
                                         always_uint = true;
                                 }
-				if ((cell->type == "$logic_or")) {
+				else if ((cell->type == "$logic_or")) {
                                         primop = "or";
                                         a_expr = "neq(" + a_expr + ", UInt(0))";
                                         b_expr = "neq(" + b_expr + ", UInt(0))";
@@ -388,6 +485,11 @@ struct FirrtlWorker
 
 				string expr = stringf("%s(%s, %s)", primop.c_str(), a_expr.c_str(), b_expr.c_str());
 
+				// Deal with FIRRTL's "shift widens" semantics
+				if (extract_y_bits) {
+					expr = stringf("bits(%s, %d, 0)", expr.c_str(), y_width - 1);
+				}
+
 				if ((is_signed && !always_uint) || cell->type.in("$sub"))
 					expr = stringf("asUInt(%s)", expr.c_str());
 
@@ -513,7 +615,67 @@ struct FirrtlWorker
 				continue;
 			}
 
-			log_error("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
+			// This may be a parameterized module - paramod.
+			if (cell->type.substr(0, 8) == "$paramod")
+			{
+				auto paramod_module = log_id(module);
+				auto paramod_instance = log_id(cell);
+				process_instance(cell, wire_exprs);
+				continue;
+			}
+			if (cell->type == "$shiftx") {
+				// assign y = a[b +: y_width];
+				// We'll extract the correct bits as part of the primop.
+
+				string y_id = make_id(cell->name);
+				int y_width =  cell->parameters.at("\\Y_WIDTH").as_int();
+				string a_expr = make_expr(cell->getPort("\\A"));
+				// Get the initial bit selector
+				string b_expr = make_expr(cell->getPort("\\B"));
+				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
+
+				if (cell->getParam("\\B_SIGNED").as_bool()) {
+					// Use validif to constrain the selection (test the sign bit)
+					auto b_string = b_expr.c_str();
+					int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1;
+					b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
+				}
+				string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
+
+				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
+				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+				continue;
+			}
+			if (cell->type == "$shift") {
+				// assign y = a >> b;
+				//  where b may be negative
+
+				string y_id = make_id(cell->name);
+				int y_width =  cell->parameters.at("\\Y_WIDTH").as_int();
+				string a_expr = make_expr(cell->getPort("\\A"));
+				string b_expr = make_expr(cell->getPort("\\B"));
+				auto b_string = b_expr.c_str();
+				int b_padded_width = cell->parameters.at("\\B_WIDTH").as_int();
+				string expr;
+				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
+
+				if (cell->getParam("\\B_SIGNED").as_bool()) {
+					// We generate a left or right shift based on the sign of b.
+					std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_padded_width).c_str(), y_width);
+					std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
+					expr = stringf("mux(%s < 0, %s, %s)",
+									 b_string,
+									 dshl.c_str(),
+									 dshr.c_str()
+									 );
+				} else {
+					expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
+				}
+				cell_exprs.push_back(stringf("    %s <= %s\n", y_id.c_str(), expr.c_str()));
+				register_reverse_wire_map(y_id, cell->getPort("\\Y"));
+				continue;
+			}
+			log_warning("Cell type not supported: %s (%s.%s)\n", log_id(cell->type), log_id(module), log_id(cell));
 		}
 
 		for (auto conn : module->connections())
@@ -629,38 +791,53 @@ struct FirrtlBackend : public Backend {
 		log("    write_firrtl [options] [filename]\n");
 		log("\n");
 		log("Write a FIRRTL netlist of the current design.\n");
+		log("The following commands are executed by this command:\n");
+		log("        pmuxtree\n");
 		log("\n");
 	}
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// if (args[argidx] == "-aig") {
-			// 	aig_mode = true;
-			// 	continue;
-			// }
-			break;
+		size_t argidx = args.size();	// We aren't expecting any arguments.
+
+		// If we weren't explicitly passed a filename, use the last argument (if it isn't a flag).
+		if (filename == "") {
+			if (argidx > 0 && args[argidx - 1][0] != '-') {
+				// extra_args and friends need to see this argument.
+				argidx -= 1;
+				filename = args[argidx];
+			}
 		}
 		extra_args(f, filename, args, argidx);
 
+		if (!design->full_selection())
+			log_cmd_error("This command only operates on fully selected designs!\n");
+
 		log_header(design, "Executing FIRRTL backend.\n");
+		log_push();
 
-		Module *top = design->top_module();
-
-		if (top == nullptr)
-			log_error("No top module found!\n");
+		Pass::call(design, stringf("pmuxtree"));
 
 		namecache.clear();
 		autoid_counter = 0;
 
+		// Get the top module, or a reasonable facsimile - we need something for the circuit name.
+		Module *top = design->top_module();
+		Module *last = nullptr;
+		// Generate module and wire names.
 		for (auto module : design->modules()) {
 			make_id(module->name);
+			last = module;
+			if (top == nullptr && module->get_bool_attribute("\\top")) {
+				top = module;
+			}
 			for (auto wire : module->wires())
 				if (wire->port_id)
 					make_id(wire->name);
 		}
 
+		if (top == nullptr)
+			top = last;
+
 		*f << stringf("circuit %s:\n", make_id(top->name));
 
 		for (auto module : design->modules())
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl
new file mode 100644
index 000000000..c782a2bd6
--- /dev/null
+++ b/tests/asicworld/xfirrtl
@@ -0,0 +1,24 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+code_hdl_models_arbiter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_hdl_models_clk_div_45.v	yosys issue: 2nd PMUXTREE pass yields: ERROR: Negative edge clock on FF clk_div_45.$procdff$49.
+code_hdl_models_d_ff_gates.v	combinational loop
+code_hdl_models_d_latch_gates.v	combinational loop
+code_hdl_models_dff_async_reset.v	$adff
+code_hdl_models_tff_async_reset.v	$adff
+code_hdl_models_uart.v	$adff
+code_specman_switch_fabric.v	subfield assignment (bits() <= ...)
+code_tidbits_asyn_reset.v	$adff
+code_tidbits_reg_seq_example.v	$adff
+code_verilog_tutorial_always_example.v	empty module
+code_verilog_tutorial_escape_id.v	make_id issues (name begins with a digit)
+code_verilog_tutorial_explicit.v	firrtl backend bug (empty module)
+code_verilog_tutorial_first_counter.v	error: reg rst; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_fsm_full.v	error: reg reset; cannot be driven by primitives or continuous assignment.
+code_verilog_tutorial_if_else.v	empty module (everything is under 'always @ (posedge clk)')
+[code_verilog_tutorial_n_out_primitive.v	empty module
+code_verilog_tutorial_parallel_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_simple_function.v	empty module (no hardware)
+code_verilog_tutorial_simple_if.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_task_global.v	empty module (everything is under 'always @ (posedge clk)')
+code_verilog_tutorial_v2k_reg.v		empty module
+code_verilog_tutorial_which_clock.v	 $adff
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
new file mode 100644
index 000000000..00e89b389
--- /dev/null
+++ b/tests/simple/xfirrtl
@@ -0,0 +1,26 @@
+# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
+arraycells.v	inst id[0] of
+dff_different_styles.v
+generate.v	combinational loop
+hierdefparam.v	inst id[0] of
+i2c_master_tests.v   $adff
+macros.v	drops modules
+mem2reg.v	drops modules
+mem_arst.v	$adff
+memory.v	$adff
+multiplier.v	inst id[0] of
+muxtree.v	drops modules
+omsp_dbg_uart.v	$adff
+operators.v	$pow
+paramods.v	subfield assignment (bits() <= ...)
+partsel.v	drops modules
+process.v	drops modules
+realexpr.v	drops modules
+scopes.v	original verilog issues ( -x where x isn't declared signed)
+sincos.v	$adff
+specify.v	no code (empty module generates error
+subbytes.v	$adff
+task_func.v	drops modules
+values.v	combinational loop
+vloghammer.v	combinational loop
+wreduce.v	original verilog issues ( -x where x isn't declared signed)
diff --git a/tests/tools/autotest.mk b/tests/tools/autotest.mk
index c68678929..e0f2bcdc1 100644
--- a/tests/tools/autotest.mk
+++ b/tests/tools/autotest.mk
@@ -1,7 +1,7 @@
 
-EXTRA_FLAGS=
-SEED=
-
+# Don't bother defining default values for SEED and EXTRA_FLAGS.
+# Their "natural" default values should be sufficient,
+#   and they may be overridden in the environment.
 ifneq ($(strip $(SEED)),)
 SEEDOPT=-S$(SEED)
 endif
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index d6216244f..218edf931 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -17,12 +17,18 @@ scriptfiles=""
 scriptopt=""
 toolsdir="$(cd $(dirname $0); pwd)"
 warn_iverilog_git=false
+# The following are used in verilog to firrtl regression tests.
+# Typically these will be passed as environment variables:
+#EXTRA_FLAGS="--firrtl2verilog 'java -cp /.../firrtl/utils/bin/firrtl.jar firrtl.Driver'"
+# The tests are skipped if firrtl2verilog is the empty string (the default).
+firrtl2verilog=""
+xfirrtl="../xfirrtl"
 
 if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdata ]; then
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -59,8 +65,24 @@ while getopts xmGl:wkjvref:s:p:n:S:I: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
+		-)
+			case "${OPTARG}" in
+			    xfirrtl)
+			    	xfirrtl="${!OPTIND}"
+				OPTIND=$(( $OPTIND + 1 ))
+				;;
+			    firrtl2verilog)
+			    	firrtl2verilog="${!OPTIND}"
+				OPTIND=$(( $OPTIND + 1 ))
+				;;
+			    *)
+			    	if [ "$OPTERR" == 1 ] && [ "${optspec:0:1}" != ":" ]; then
+				    echo "Unknown option --${OPTARG}" >&2
+				fi
+				;;
+			esac;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
 			exit 1
 	esac
 done
@@ -109,6 +131,8 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
+		rm -f ${bn}_ref.fir
+
 		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
 
 		if [ ! -f ../${bn}_tb.v ]; then
@@ -148,6 +172,13 @@ do
 		else
 			test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
 			test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
+			if [ -n "$firrtl2verilog" ]; then
+			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
+				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
+				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v  -X verilog
+				test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
+			    fi
+			fi
 		fi
 		touch ../${bn}.log
 	}
@@ -160,14 +191,18 @@ do
 		( set -ex; body; ) > ${bn}.err 2>&1
 	fi
 
+	did_firrtl=""
+	if [ -f ${bn}.out/${bn}_ref.fir ]; then
+	    did_firrtl="+FIRRTL "
+	fi
 	if [ -f ${bn}.log ]; then
 		mv ${bn}.err ${bn}.log
-		echo "${status_prefix}-> ok"
+		echo "${status_prefix}${did_firrtl}-> ok"
 	elif [ -f ${bn}.skip ]; then
 		mv ${bn}.err ${bn}.skip
 		echo "${status_prefix}-> skip"
 	else
-		echo "${status_prefix}-> ERROR!"
+		echo "${status_prefix}${did_firrtl}-> ERROR!"
 		if $warn_iverilog_git; then
 			echo "Note: Make sure that 'iverilog' is an up-to-date git checkout of Icarus Verilog."
 		fi

From 5c504c5ae676488f7e0b53f827f189fa7cacb2c8 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:31:37 -0800
Subject: [PATCH 372/528] Define basic_cell_type() function and use it to
 derive the cell type for array references (instead of duplicating the code).

---
 passes/hierarchy/hierarchy.cc | 50 ++++++++++++++++++++++++++++-------
 1 file changed, 40 insertions(+), 10 deletions(-)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 0e28dbca2..332ebdfbb 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -140,6 +140,23 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
 	}
 }
 
+// Return the "basic" type for an array item.
+std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) {
+	std::string basicType = celltype;
+	if (celltype.substr(0, 7) == "$array:") {
+		int pos_idx = celltype.find_first_of(':');
+		int pos_num = celltype.find_first_of(':', pos_idx + 1);
+		int pos_type = celltype.find_first_of(':', pos_num + 1);
+		basicType = celltype.substr(pos_type + 1);
+		if (pos != nullptr) {
+			pos[0] = pos_idx;
+			pos[1] = pos_num;
+			pos[2] = pos_type;
+		}
+	}
+	return basicType;
+}
+
 bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, std::vector<std::string> &libdirs)
 {
 	bool did_something = false;
@@ -178,9 +195,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
 		std::vector<RTLIL::SigSpec> connections_to_add_signal;
 
 		if (cell->type.substr(0, 7) == "$array:") {
-			int pos_idx = cell->type.str().find_first_of(':');
-			int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
-			int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
+			int pos[3];
+			basic_cell_type(cell->type.str(), pos);
+			int pos_idx = pos[0];
+			int pos_num = pos[1];
+			int pos_type = pos[2];
 			int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
 			int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
 			array_cells[cell] = std::pair<int, int>(idx, num);
@@ -439,10 +458,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
 	for (auto cell : mod->cells()) {
 		std::string celltype = cell->type.str();
 		if (celltype.substr(0, 7) == "$array:") {
-			int pos_idx = celltype.find_first_of(':');
-			int pos_num = celltype.find_first_of(':', pos_idx + 1);
-			int pos_type = celltype.find_first_of(':', pos_num + 1);
-			celltype = celltype.substr(pos_type + 1);
+			celltype = basic_cell_type(celltype);
 		}
 		if (design->module(celltype))
 			hierarchy_worker(design, used, design->module(celltype), indent+4);
@@ -502,9 +518,23 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 	if (db.count(module) == 0) {
 		int score = 0;
 		db[module] = 0;
-		for (auto cell : module->cells())
-			if (design->module(cell->type))
-				score = max(score, find_top_mod_score(design, design->module(cell->type), db) + 1);
+		for (auto cell : module->cells()) {
+			std::string celltype = cell->type.str();
+			// Is this an array instance
+			if (celltype.substr(0, 7) == "$array:") {
+				celltype = basic_cell_type(celltype);
+				// Is this cell is a module instance?
+				if (celltype[0] != '$') {
+					auto instModule = design->module(celltype);
+					// If there is no instance for this, issue a warning.
+					if (instModule == NULL) {
+						log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
+					}
+					if (instModule != NULL)
+						score = max(score, find_top_mod_score(design, instModule, db) + 1);
+				}
+			}
+		}
 		db[module] = score;
 	}
 	return db.at(module);

From 34153adef408bc226430f05d14cd4af9384359f9 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 11:56:51 -0800
Subject: [PATCH 373/528] Append (instead of over-writing) EXTRA_FLAGS

---
 tests/asicworld/run-test.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/asicworld/run-test.sh b/tests/asicworld/run-test.sh
index d5708c456..c22ab6928 100755
--- a/tests/asicworld/run-test.sh
+++ b/tests/asicworld/run-test.sh
@@ -11,4 +11,4 @@ do
 done
 shift "$((OPTIND-1))"
 
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS="-e" *.v
+exec ${MAKE:-make} -f ../tools/autotest.mk $seed EXTRA_FLAGS+="-e" *.v

From c245041bfe2ee0d5b5504fa5e9459ac52e836c33 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 15 Feb 2019 12:00:28 -0800
Subject: [PATCH 374/528] Removed unused variables, functions.

---
 backends/firrtl/firrtl.cc | 20 --------------------
 1 file changed, 20 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 7ca5dc756..0917ecba6 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -96,23 +96,6 @@ const char *make_id(IdString id)
 	return namecache.at(id).c_str();
 }
 
-static std::vector<string> Tokenize( const string str, const std::regex regex )
-{
-	using namespace std;
-
-	std::vector<string> result;
-
-	sregex_token_iterator it( str.begin(), str.end(), regex, -1 );
-	sregex_token_iterator reg_end;
-
-	for ( ; it != reg_end; ++it ) {
-		if ( !it->str().empty() ) //token could be empty:check
-			result.emplace_back( it->str() );
-	}
-
-	return result;
-}
-
 struct FirrtlWorker
 {
 	Module *module;
@@ -373,7 +356,6 @@ struct FirrtlWorker
 				bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
 				int y_width =  cell->parameters.at("\\Y_WIDTH").as_int();
 				string a_expr = make_expr(cell->getPort("\\A"));
-				int a_padded_width = cell->parameters.at("\\A_WIDTH").as_int();
 				string b_expr = make_expr(cell->getPort("\\B"));
 				int b_padded_width = cell->parameters.at("\\B_WIDTH").as_int();
 				wire_decls.push_back(stringf("    wire %s: UInt<%d>\n", y_id.c_str(), y_width));
@@ -618,8 +600,6 @@ struct FirrtlWorker
 			// This may be a parameterized module - paramod.
 			if (cell->type.substr(0, 8) == "$paramod")
 			{
-				auto paramod_module = log_id(module);
-				auto paramod_instance = log_id(cell);
 				process_instance(cell, wire_exprs);
 				continue;
 			}

From 5a853ed46cd3a41df9da4c8206f9416748788487 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 17 Feb 2019 15:35:48 +0100
Subject: [PATCH 375/528] Add actual DSP inference to ice40_dsp pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.cc  | 197 +++++++++++++++++++++++++++++++++----
 passes/pmgen/ice40_dsp.pmg |  18 +++-
 passes/pmgen/pmgen.py      |  23 ++++-
 3 files changed, 214 insertions(+), 24 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 78b5bad33..7463d598f 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -24,6 +24,180 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+void create_ice40_dsp(ice40_dsp_pm &pm)
+{
+#if 0
+	log("\n");
+	log("ffA:   %s\n", log_id(pm.st.ffA, "--"));
+	log("ffB:   %s\n", log_id(pm.st.ffB, "--"));
+	log("mul:   %s\n", log_id(pm.st.mul, "--"));
+	log("ffY:   %s\n", log_id(pm.st.ffY, "--"));
+	log("addAB: %s\n", log_id(pm.st.addAB, "--"));
+	log("muxAB: %s\n", log_id(pm.st.muxAB, "--"));
+	log("ffS:   %s\n", log_id(pm.st.ffS, "--"));
+#endif
+
+	log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(pm.st.mul));
+
+	if (GetSize(pm.st.sigA) > 16) {
+		log("  input A (%s) is too large (%d > 16).\n", log_signal(pm.st.sigA), GetSize(pm.st.sigA));
+		return;
+	}
+
+	if (GetSize(pm.st.sigB) > 16) {
+		log("  input B (%s) is too large (%d > 16).\n", log_signal(pm.st.sigB), GetSize(pm.st.sigB));
+		return;
+	}
+
+	if (GetSize(pm.st.sigS) > 32) {
+		log("  accumulator (%s) is too large (%d > 32).\n", log_signal(pm.st.sigS), GetSize(pm.st.sigS));
+		return;
+	}
+
+	if (GetSize(pm.st.sigY) > 32) {
+		log("  output (%s) is too large (%d > 32).\n", log_signal(pm.st.sigY), GetSize(pm.st.sigY));
+		return;
+	}
+
+	log("  replacing $mul with SB_MAC16 cell.\n");
+
+	bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool();
+
+	Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
+	pm.module->swap_names(cell, pm.st.mul);
+
+	// SB_MAC16 Input Interface
+
+	SigSpec A = pm.st.sigA;
+	A.extend_u0(16, mul_signed);
+
+	SigSpec B = pm.st.sigB;
+	B.extend_u0(16, mul_signed);
+
+	SigSpec CD;
+	if (pm.st.muxA)
+		CD = pm.st.muxA->getPort("\\B");
+	if (pm.st.muxB)
+		CD = pm.st.muxB->getPort("\\A");
+	CD.extend_u0(32, mul_signed);
+
+	cell->setPort("\\A", A);
+	cell->setPort("\\B", B);
+	cell->setPort("\\C", CD.extract(0, 16));
+	cell->setPort("\\D", CD.extract(16, 16));
+
+	cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1);
+	cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1);
+
+	cell->setPort("\\AHOLD", State::S0);
+	cell->setPort("\\BHOLD", State::S0);
+	cell->setPort("\\CHOLD", State::S0);
+	cell->setPort("\\DHOLD", State::S0);
+
+	cell->setPort("\\IRSTTOP", State::S0);
+	cell->setPort("\\IRSTBOT", State::S0);
+
+	if (pm.st.clock_vld)
+	{
+		cell->setPort("\\CLK", pm.st.clock);
+		cell->setPort("\\CE", State::S1);
+		cell->setParam("\\NEG_TRIGGER", pm.st.clock_pol ? State::S0 : State::S1);
+
+		log("  clock: %s (%s)", log_signal(pm.st.clock), pm.st.clock_pol ? "posedge" : "negedge");
+
+		if (pm.st.ffA)
+			log(" ffA:%s", log_id(pm.st.ffA));
+
+		if (pm.st.ffB)
+			log(" ffB:%s", log_id(pm.st.ffB));
+
+		if (pm.st.ffY)
+			log(" ffY:%s", log_id(pm.st.ffY));
+
+		if (pm.st.ffS)
+			log(" ffS:%s", log_id(pm.st.ffS));
+
+		log("\n");
+	}
+	else
+	{
+		cell->setPort("\\CLK", State::S0);
+		cell->setPort("\\CE", State::S0);
+		cell->setParam("\\NEG_TRIGGER", State::S0);
+	}
+
+	// SB_MAC16 Cascade Interface
+
+	cell->setPort("\\SIGNEXTIN", State::Sx);
+	cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
+
+	cell->setPort("\\CI", State::Sx);
+	cell->setPort("\\CO", pm.module->addWire(NEW_ID));
+
+	cell->setPort("\\ACCUMCI", State::Sx);
+	cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
+
+	// SB_MAC16 Output Interface
+
+	SigSpec O = pm.st.ffS ? pm.st.sigS : pm.st.sigY;
+	if (GetSize(O) < 32)
+		O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
+
+	cell->setPort("\\O", O);
+
+	if (pm.st.addAB) {
+		log("  accumulator %s (%s)\n", log_id(pm.st.addAB), log_id(pm.st.addAB->type));
+		cell->setPort("\\ADDSUBTOP", pm.st.addAB->type == "$add" ? State::S0 : State::S1);
+		cell->setPort("\\ADDSUBBOT", pm.st.addAB->type == "$add" ? State::S0 : State::S1);
+	} else {
+		cell->setPort("\\ADDSUBTOP", State::S0);
+		cell->setPort("\\ADDSUBBOT", State::S0);
+	}
+
+	cell->setPort("\\ORTSTOP", State::S0);
+	cell->setPort("\\ORTSBOT", State::S0);
+
+	cell->setPort("\\OHOLDTOP", State::S0);
+	cell->setPort("\\OHOLDBOT", State::S0);
+
+	SigSpec acc_reset = State::S0;
+	if (pm.st.muxA)
+		acc_reset = pm.st.muxA->getPort("\\S");
+	if (pm.st.muxB)
+		acc_reset = pm.module->Not(NEW_ID, pm.st.muxB->getPort("\\S"));
+
+	cell->setPort("\\OLOADTOP", acc_reset);
+	cell->setPort("\\OLOADBOT", acc_reset);
+
+	// SB_MAC16 Remaining Parameters
+
+	cell->setParam("\\C_REG", State::S0);
+	cell->setParam("\\D_REG", State::S0);
+
+	cell->setParam("\\TOP_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0);
+	cell->setParam("\\BOT_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0);
+	cell->setParam("\\PIPELINE_16X16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0);
+	cell->setParam("\\PIPELINE_16X16_MULT_REG2", State::S0);
+
+	cell->setParam("\\TOPOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2));
+	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
+	cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0);
+	cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
+
+	cell->setParam("\\BOTOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2));
+	cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
+	cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0);
+	cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
+
+	cell->setParam("\\MODE_8x8", State::S0);
+	cell->setParam("\\A_SIGNED", mul_signed ? State::S1 : State::S0);
+	cell->setParam("\\B_SIGNED", mul_signed ? State::S1 : State::S0);
+
+	pm.autoremove(pm.st.mul);
+	pm.autoremove(pm.st.ffY);
+	pm.autoremove(pm.st.ffS);
+}
+
 struct Ice40DspPass : public Pass {
 	Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
 	void help() YS_OVERRIDE
@@ -32,7 +206,7 @@ struct Ice40DspPass : public Pass {
 		log("\n");
 		log("    ice40_dsp [options] [selection]\n");
 		log("\n");
-		log("Map multipliers and iCE40 DSP resources.\n");
+		log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -51,26 +225,7 @@ struct Ice40DspPass : public Pass {
 		extra_args(args, argidx, design);
 
 		for (auto module : design->selected_modules())
-		{
-			ice40_dsp_pm pm(module, module->selected_cells());
-			pm.run([&]()
-			{
-				log("\n");
-				log("ffA:   %s\n", log_id(pm.st.ffA, "--"));
-				log("ffB:   %s\n", log_id(pm.st.ffB, "--"));
-				log("mul:   %s\n", log_id(pm.st.mul, "--"));
-				log("ffY:   %s\n", log_id(pm.st.ffY, "--"));
-				log("addAB: %s\n", log_id(pm.st.addAB, "--"));
-				log("muxAB: %s\n", log_id(pm.st.muxAB, "--"));
-				log("ffS:   %s\n", log_id(pm.st.ffS, "--"));
-
-				pm.blacklist(pm.st.mul);
-				pm.blacklist(pm.st.ffA);
-				pm.blacklist(pm.st.ffB);
-				pm.blacklist(pm.st.ffY);
-				pm.blacklist(pm.st.ffS);
-			});
-		}
+			ice40_dsp_pm(module, module->selected_cells()).run(create_ice40_dsp);
 	}
 } Ice40DspPass;
 
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 1370cb66a..58e1ce0e0 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -63,7 +63,7 @@ code sigY clock clock_pol clock_vld
 	sigY = port(mul, \Y);
 
 	if (ffY) {
-		sigY = port(ffY, \D);
+		sigY = port(ffY, \Q);
 		SigBit c = port(ffY, \CLK).as_bit();
 		bool cp = param(ffY, \CLK_POLARITY).as_bool();
 
@@ -77,7 +77,7 @@ code sigY clock clock_pol clock_vld
 endcode
 
 match addA
-	select addA->type.in($add, $sub)
+	select addA->type.in($add)
 	select nusers(port(addA, \A)) == 2
 	index <SigSpec> port(addA, \A) === sigY
 	optional
@@ -134,3 +134,17 @@ match ffS
 	index <SigSpec> port(ffS, \D) === port(muxAB, \Y)
 	index <SigSpec> port(ffS, \Q) === sigS
 endmatch
+
+code clock clock_pol clock_vld
+	if (ffS) {
+		SigBit c = port(ffS, \CLK).as_bit();
+		bool cp = param(ffS, \CLK_POLARITY).as_bool();
+
+		if (clock_vld && (c != clock || cp != clock_pol))
+			reject;
+
+		clock = c;
+		clock_pol = cp;
+		clock_vld = true;
+	}
+endcode
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index a59cf5a81..e688a4567 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -203,6 +203,7 @@ with open("%s_pm.h" % prefix, "w") as f:
             print("  dict<index_{}_key_type, vector<Cell*>> index_{};".format(index, index), file=f)
     print("  dict<SigBit, pool<Cell*>> sigusers;", file=f)
     print("  pool<Cell*> blacklist_cells;", file=f)
+    print("  pool<Cell*> autoremove_cells;", file=f)
     print("  bool blacklist_dirty;", file=f)
     print("  int rollback;", file=f)
     print("", file=f)
@@ -244,6 +245,15 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
+    print("  void autoremove(Cell *cell) {", file=f)
+    print("    if (cell != nullptr) {", file=f)
+    print("      if (blacklist_cells.insert(cell).second)", file=f)
+    print("        blacklist_dirty = true;", file=f)
+    print("      autoremove_cells.insert(cell);", file=f)
+    print("    }", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
     print("  void check_blacklist() {", file=f)
     print("    if (!blacklist_dirty)", file=f)
     print("      return;", file=f)
@@ -308,7 +318,13 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  void run(std::function<void()> on_accept_f) {{".format(prefix), file=f)
+    print("  ~{}_pm() {{".format(prefix), file=f)
+    print("    for (auto cell : autoremove_cells)", file=f)
+    print("      module->remove(cell);", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
+    print("  void run(std::function<void()> on_accept_f) {", file=f)
     print("    on_accept = on_accept_f;", file=f)
     print("    rollback = 0;", file=f)
     print("    blacklist_dirty = false;", file=f)
@@ -321,6 +337,11 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
+    print("  void run(std::function<void({}_pm&)> on_accept_f) {{".format(prefix), file=f)
+    print("    run([&](){on_accept_f(*this);});", file=f)
+    print("  }", file=f)
+    print("", file=f)
+
     for index in range(len(blocks)):
         block = blocks[index]
 

From 430a7548bca6046c812f713877253f8c3d81d805 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 11:50:55 -0800
Subject: [PATCH 376/528] One more merge conflict

---
 tests/tools/autotest.sh | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 2722cba19..b5abc3570 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -134,18 +134,13 @@ do
 		fn=$(basename $fn)
 		bn=$(basename $bn)
 
-<<<<<<< HEAD
+		rm -f ${bn}_ref.fir
 		if [[ "$ext" == "v" ]]; then
 			egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
 		else
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
 			frontend="verilog"
 		fi
-=======
-		rm -f ${bn}_ref.fir
-
-		egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.v
->>>>>>> e45f62b0c56717a23099425f078d1e56212aa632
 
 		if [ ! -f ../${bn}_tb.v ]; then
 			"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v

From 9268a271fb8b22b089927d63f0b36d620e19704c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 12:07:14 -0800
Subject: [PATCH 377/528] read_aiger to ignore line after ands for ascii, not
 binary

---
 frontends/aiger/aigerparse.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 7df28fe87..a1a0a08a0 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -235,6 +235,7 @@ void AigerReader::parse_aiger_ascii()
         RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
         module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
     }
+    std::getline(f, line); // Ignore up to start of next line
 }
 
 static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)
@@ -342,8 +343,6 @@ void AigerReader::parse_aiger_binary()
         and_cell->setPort("\\B", i2_wire);
         and_cell->setPort("\\Y", o_wire);
     }
-    std::getline(f, line); // Ignore up to start of next line
-
 }
 
 struct AigerFrontend : public Frontend {

From 3d3353e02005883af916b1b1da2c670a29060169 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 12:11:52 -0800
Subject: [PATCH 378/528] Revert "Add INIT parameter to all ff/latch cells"

This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.
---
 techlibs/common/simcells.v | 111 +++++++++++++------------------------
 techlibs/common/simlib.v   |  18 ++----
 2 files changed, 43 insertions(+), 86 deletions(-)

diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index b9957bd5e..289673e82 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -451,9 +451,8 @@ endmodule
 //-                 1 1 | y
 //-
 module \$_SR_NN_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -476,9 +475,8 @@ endmodule
 //-                 1 0 | y
 //-
 module \$_SR_NP_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -501,9 +499,8 @@ endmodule
 //-                 0 1 | y
 //-
 module \$_SR_PN_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -526,9 +523,8 @@ endmodule
 //-                 0 0 | y
 //-
 module \$_SR_PP_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -546,9 +542,8 @@ endmodule
 //- type is usually only used in netlists for formal verification.)
 //-
 module \$_FF_ (D, Q);
-parameter INIT = 1'bx;
 input D;
-output reg Q = INIT;
+output reg Q;
 always @($global_clock) begin
 	Q <= D;
 end
@@ -567,9 +562,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DFF_N_ (D, C, Q);
-parameter INIT = 1'bx;
 input D, C;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C) begin
 	Q <= D;
 end
@@ -587,9 +581,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DFF_P_ (D, C, Q);
-parameter INIT = 1'bx;
 input D, C;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C) begin
 	Q <= D;
 end
@@ -607,9 +600,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_NN_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C) begin
 	if (!E) Q <= D;
 end
@@ -627,9 +619,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_NP_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C) begin
 	if (E) Q <= D;
 end
@@ -647,9 +638,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_PN_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C) begin
 	if (!E) Q <= D;
 end
@@ -667,9 +657,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_PP_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C) begin
 	if (E) Q <= D;
 end
@@ -688,9 +677,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NN0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -712,9 +700,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NN1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 1;
@@ -736,9 +723,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NP0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -760,9 +746,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NP1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 1;
@@ -784,9 +769,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PN0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -808,9 +792,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PN1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 1;
@@ -832,9 +815,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PP0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -856,9 +838,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PP1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 1;
@@ -881,9 +862,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NNN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -909,9 +889,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NNP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -937,9 +916,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NPN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -964,9 +942,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NPP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -991,9 +968,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PNN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -1019,9 +995,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PNP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -1047,9 +1022,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PPN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -1074,9 +1048,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PPP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -1099,9 +1072,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DLATCH_N_ (E, D, Q);
-parameter INIT = 1'bx;
 input E, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (E == 0)
 		Q <= D;
@@ -1120,9 +1092,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DLATCH_P_ (E, D, Q);
-parameter INIT = 1'bx;
 input E, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (E == 1)
 		Q <= D;
@@ -1143,9 +1114,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1171,9 +1141,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1199,9 +1168,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1226,9 +1194,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1253,9 +1220,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1281,9 +1247,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1309,9 +1274,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1336,9 +1300,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a1e0c1575..8e43fe058 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,11 +1464,10 @@ module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1484,11 +1483,10 @@ module \$dffe (CLK, EN, D, Q);
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1506,11 +1504,10 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 
 wire pos_clk = CLK == CLK_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
@@ -1540,11 +1537,10 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter ARST_POLARITY = 1'b1;
 parameter ARST_VALUE = 0;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, ARST;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 wire pos_clk = CLK == CLK_POLARITY;
 wire pos_arst = ARST == ARST_POLARITY;
 
@@ -1563,11 +1559,10 @@ module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 
 always @* begin
 	if (EN == EN_POLARITY)
@@ -1585,11 +1580,10 @@ parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 
 wire pos_en = EN == EN_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;

From 11480b4fa3ba031541e22b52d9ccd658a3e52ff1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 12:18:12 -0800
Subject: [PATCH 379/528] Instead of INIT param on cells, use initial statement
 with hier ref as per @cliffordwolf

---
 backends/verilog/verilog_backend.cc | 31 ++++++++++++-----------------
 1 file changed, 13 insertions(+), 18 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 4b5a13941..d351a6266 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -293,7 +293,7 @@ void dump_const(std::ostream &f, const RTLIL::Const &data, int width = -1, int o
 	}
 }
 
-void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
+void dump_reg_init(std::ostream &f, SigSpec sig)
 {
 	Const initval;
 	bool gotinit = false;
@@ -308,7 +308,7 @@ void dump_reg_init(std::ostream &f, SigSpec sig, bool write_equals = true)
 	}
 
 	if (gotinit) {
-		if (write_equals) f << " = ";
+		f << " = ";
 		dump_const(f, initval);
 	}
 }
@@ -1250,14 +1250,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	dump_attributes(f, indent, cell->attributes);
 	f << stringf("%s" "%s", indent.c_str(), id(cell->type, false).c_str());
 
-	std::string init;
-	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
-		std::stringstream ss;
-		dump_reg_init(ss, cell->getPort("\\Q"), false /* write_equals */);
-		init = ss.str();
-	}
-
-	if (!defparam && (cell->parameters.size() > 0 || !init.empty())) {
+	if (!defparam && cell->parameters.size() > 0) {
 		f << stringf(" #(");
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
@@ -1267,11 +1260,6 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(")");
 		}
-		if (!init.empty()) {
-			if (!cell->parameters.empty())
-				f << stringf(",");
-			f << stringf("\n%s  .INIT(%s)", indent.c_str(), init.c_str());
-		}
 		f << stringf("\n%s" ")", indent.c_str());
 	}
 
@@ -1313,17 +1301,24 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	}
 	f << stringf("\n%s" ");\n", indent.c_str());
 
-	if (defparam && (cell->parameters.size() > 0 || !init.empty())) {
+	if (defparam && cell->parameters.size() > 0) {
 		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			f << stringf("%sdefparam %s.%s = ", indent.c_str(), cell_name.c_str(), id(it->first).c_str());
 			bool is_signed = (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0;
 			dump_const(f, it->second, -1, 0, false, is_signed);
 			f << stringf(";\n");
 		}
-		if (!init.empty())
-			f << stringf("%sdefparam %s.INIT = %s;\n", indent.c_str(), cell_name.c_str(), init.c_str());
 	}
 
+	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+		std::stringstream ss;
+		dump_reg_init(ss, cell->getPort("\\Q"));
+		if (!ss.str().empty()) {
+			f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str());
+			f << ss.str();
+			f << ";\n";
+		}
+	}
 }
 
 void dump_conn(std::ostream &f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)

From de1dc7947b3d4bfc4e611740a906915a0c2490b0 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 20:59:15 -0800
Subject: [PATCH 380/528] Revert "Missing headers for Xcode?"

This reverts commit c23e3f07517d4818d9ab1b532250353492cf50c2.
---
 passes/techmap/abc.cc | 2 --
 1 file changed, 2 deletions(-)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index b215b1ea4..d2d15a4a9 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -52,8 +52,6 @@
 #include <cerrno>
 #include <sstream>
 #include <climits>
-#include <array>
-#include <functional>
 
 #ifndef _WIN32
 #  include <unistd.h>

From 8e1dbfac3af64339f021ed674bdd98e71cd7fb90 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Sun, 17 Feb 2019 20:59:53 -0800
Subject: [PATCH 381/528] Missing OSX headers?

---
 frontends/aiger/aigerparse.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index a1a0a08a0..778b8b070 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -22,6 +22,11 @@
 // Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
 // http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
 
+#ifdef __linux__
+#include <libgen.h>
+#endif
+#include <array>
+
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "aigerparse.h"

From 62493c91b24c1775f82e64712bf42b175944fe08 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 19 Feb 2019 13:42:21 +0100
Subject: [PATCH 382/528] Add first draft of functional SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v               | 228 +++++++++++++++++------
 techlibs/ice40/tests/test_dsp_model.gtkw |  87 +++++++++
 techlibs/ice40/tests/test_dsp_model.sh   |   6 +
 techlibs/ice40/tests/test_dsp_model.v    | 199 ++++++++++++++++++++
 4 files changed, 467 insertions(+), 53 deletions(-)
 create mode 100644 techlibs/ice40/tests/test_dsp_model.gtkw
 create mode 100644 techlibs/ice40/tests/test_dsp_model.sh
 create mode 100644 techlibs/ice40/tests/test_dsp_model.v

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 38ed45981..4a92fccdf 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -886,59 +886,6 @@ module SB_WARMBOOT (
 );
 endmodule
 
-// UltraPlus feature cells
-(* blackbox *)
-module SB_MAC16 (
-	input CLK,
-	input CE,
-	input [15:0] C,
-	input [15:0] A,
-	input [15:0] B,
-	input [15:0] D,
-	input AHOLD,
-	input BHOLD,
-	input CHOLD,
-	input DHOLD,
-	input IRSTTOP,
-	input IRSTBOT,
-	input ORSTTOP,
-	input ORSTBOT,
-	input OLOADTOP,
-	input OLOADBOT,
-	input ADDSUBTOP,
-	input ADDSUBBOT,
-	input OHOLDTOP,
-	input OHOLDBOT,
-	input CI,
-	input ACCUMCI,
-	input SIGNEXTIN,
-	output [31:0] O,
-	output CO,
-	output ACCUMCO,
-	output SIGNEXTOUT
-);
-parameter NEG_TRIGGER = 1'b0;
-parameter C_REG = 1'b0;
-parameter A_REG = 1'b0;
-parameter B_REG = 1'b0;
-parameter D_REG = 1'b0;
-parameter TOP_8x8_MULT_REG = 1'b0;
-parameter BOT_8x8_MULT_REG = 1'b0;
-parameter PIPELINE_16x16_MULT_REG1 = 1'b0;
-parameter PIPELINE_16x16_MULT_REG2 = 1'b0;
-parameter TOPOUTPUT_SELECT =  2'b00;
-parameter TOPADDSUB_LOWERINPUT = 2'b00;
-parameter TOPADDSUB_UPPERINPUT = 1'b0;
-parameter TOPADDSUB_CARRYSELECT = 2'b00;
-parameter BOTOUTPUT_SELECT =  2'b00;
-parameter BOTADDSUB_LOWERINPUT = 2'b00;
-parameter BOTADDSUB_UPPERINPUT = 1'b0;
-parameter BOTADDSUB_CARRYSELECT = 2'b00;
-parameter MODE_8x8 = 1'b0;
-parameter A_SIGNED = 1'b0;
-parameter B_SIGNED = 1'b0;
-endmodule
-
 module SB_SPRAM256KA (
 	input [13:0] ADDRESS,
 	input [15:0] DATAIN,
@@ -1273,3 +1220,178 @@ module SB_IO_OD (
 	endgenerate
 `endif
 endmodule
+
+module SB_MAC16 (
+	input CLK, CE,
+	input [15:0] C, A, B, D,
+	input AHOLD, BHOLD, CHOLD, DHOLD,
+	input IRSTTOP, IRSTBOT,
+	input ORSTTOP, ORSTBOT,
+	input OLOADTOP, OLOADBOT,
+	input ADDSUBTOP, ADDSUBBOT,
+	input OHOLDTOP, OHOLDBOT,
+	input CI, ACCUMCI, SIGNEXTIN,
+	output [31:0] O,
+	output CO, ACCUMCO, SIGNEXTOUT
+);
+	parameter [0:0] NEG_TRIGGER = 0;
+	parameter [0:0] C_REG = 0;
+	parameter [0:0] A_REG = 0;
+	parameter [0:0] B_REG = 0;
+	parameter [0:0] D_REG = 0;
+	parameter [0:0] TOP_8x8_MULT_REG = 0;
+	parameter [0:0] BOT_8x8_MULT_REG = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
+	parameter [1:0] TOPOUTPUT_SELECT = 0;
+	parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
+	parameter [0:0] TOPADDSUB_UPPERINPUT = 0;
+	parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
+	parameter [1:0] BOTOUTPUT_SELECT = 0;
+	parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
+	parameter [0:0] BOTADDSUB_UPPERINPUT = 0;
+	parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
+	parameter [0:0] MODE_8x8 = 0;
+	parameter [0:0] A_SIGNED = 0;
+	parameter [0:0] B_SIGNED = 0;
+
+	wire clock = CLK ^ NEG_TRIGGER;
+
+	// internal wires, compare Figure on page 133 of ICE Technology Library 3.0 and Fig 2 on page 2 of Lattice TN1295-DSP
+	// http://www.latticesemi.com/~/media/LatticeSemi/Documents/TechnicalBriefs/SBTICETechnologyLibrary201608.pdf
+	// https://www.latticesemi.com/-/media/LatticeSemi/Documents/ApplicationNotes/AD/DSPFunctionUsageGuideforICE40Devices.ashx
+	wire [15:0] iA, iB, iC, iD;
+	wire [15:0] iF, iJ, iK, iG;
+	wire [31:0] iL, iH;
+	wire [15:0] iW, iX, iP, iQ;
+	wire [15:0] iY, iZ, iR, iS;
+	wire HCI, LCI, LCO;
+
+	// Regs C and A
+	reg [15:0] rC, rA;
+	always @(posedge clock, posedge IRSTTOP) begin
+		if (IRSTTOP) begin
+			rC <= 0;
+			rA <= 0;
+		end else if (CE) begin
+			if (!CHOLD) rC <= C;
+			if (!AHOLD) rA <= A;
+		end
+	end
+	assign iC = C_REG ? rC : C;
+	assign iA = A_REG ? rA : A;
+
+	// Regs B and D
+	reg [15:0] rB, rD;
+	always @(posedge clock, posedge IRSTTOP) begin
+		if (IRSTBOT) begin
+			rB <= 0;
+			rD <= 0;
+		end else if (CE) begin
+			if (!BHOLD) rB <= B;
+			if (!DHOLD) rD <= D;
+		end
+	end
+	assign iB = B_REG ? rB : B;
+	assign iD = D_REG ? rD : D;
+
+	// Multiplier Stage
+	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
+	wire [15:0] Ah, Al, Bh, Bl;
+	assign Ah = A_SIGNED ? {{8{iA[15]}}, iA[15: 8]} : iA[15: 8];
+	assign Al = A_SIGNED ? {{8{iA[ 7]}}, iA[ 7: 0]} : iA[15: 8];
+	assign Bh = B_SIGNED ? {{8{iB[15]}}, iB[15: 8]} : iB[15: 8];
+	assign Bl = B_SIGNED ? {{8{iB[ 7]}}, iB[ 7: 0]} : iB[15: 8];
+	assign p_Ah_Bh = Ah * Bh;
+	assign p_Al_Bh = Al * Bh;
+	assign p_Ah_Bl = Ah * Bl;
+	assign p_Al_Bl = Al * Bl;
+
+	// Regs F and J
+	reg [15:0] rF, rJ;
+	always @(posedge clock, posedge IRSTTOP) begin
+		if (IRSTTOP) begin
+			rF <= 0;
+			rJ <= 0;
+		end else if (CE) begin
+			rF <= p_Ah_Bh;
+			if (!MODE_8x8) rJ <= p_Al_Bh;
+		end
+	end
+	assign iF = TOP_8x8_MULT_REG ? rF : p_Ah_Bh;
+	assign iJ = PIPELINE_16x16_MULT_REG1 ? rJ : p_Al_Bh;
+
+	// Regs K and G
+	reg [15:0] rK, rG;
+	always @(posedge clock, posedge IRSTBOT) begin
+		if (IRSTBOT) begin
+			rK <= 0;
+			rG <= 0;
+		end else if (CE) begin
+			if (!MODE_8x8) rK <= p_Ah_Bl;
+			rG <= p_Al_Bl;
+		end
+	end
+	assign iK = PIPELINE_16x16_MULT_REG1 ? rK : p_Ah_Bl;
+	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
+
+	// Adder Stage
+	reg [31:0] P;
+	always @* begin
+		P = iG[7:0];
+		P = P + (iG[15:8] + iK[7:0]) << 8;
+		P = P + (iK[15:8] + iJ[7:0]) << 16;
+		P = P + (iJ[15:8] + iF[7:0]) << 24;
+	end
+	assign iL = P;
+
+	// Reg H
+	reg [15:0] rH;
+	always @(posedge clock, posedge IRSTBOT) begin
+		if (IRSTBOT) begin
+			rH <= 0;
+		end else if (CE) begin
+			if (!MODE_8x8) rH <= iL;
+		end
+	end
+	assign iH = PIPELINE_16x16_MULT_REG2 ? rH : iL;
+
+	// Hi Output Stage
+	wire [15:0] XW, Oh;
+	reg [15:0] rQ;
+	assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ[31:16];
+	assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
+	assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
+	assign CO = ACCUMCO ^ ADDSUBTOP;
+	assign iP = OLOADTOP ? iC : XW ^ {16{ADDSUBTOP}};
+	always @(posedge clock, posedge ORSTTOP) begin
+		if (ORSTTOP) begin
+			rQ <= 0;
+		end else if (CE) begin
+			if (!OHOLDTOP) rQ <= iP;
+		end
+	end
+	assign iQ = rQ;
+	assign Oh = (TOPOUTPUT_SELECT == 0) ? iP : (TOPOUTPUT_SELECT == 1) ? iQ : (TOPOUTPUT_SELECT == 2) ? iF : iH[31:16];
+	assign HCI = (TOPADDSUB_CARRYSELECT == 0) ? 1'b0 : (TOPADDSUB_CARRYSELECT == 1) ? 1'b1 : (TOPADDSUB_CARRYSELECT == 2) ? LCO : LCO ^ ADDSUBBOT;
+	assign SIGNEXTOUT = iX[15];
+
+	// Lo Output Stage
+	wire [15:0] YZ, Ol;
+	reg [15:0] rS;
+	assign iY = BOTADDSUB_UPPERINPUT ? iD : iQ[15:0];
+	assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
+	assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
+	assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
+	always @(posedge clock, posedge ORSTBOT) begin
+		if (ORSTBOT) begin
+			rS <= 0;
+		end else if (CE) begin
+			if (!OHOLDTOP) rS <= iR;
+		end
+	end
+	assign iS = rS;
+	assign Ol = (BOTOUTPUT_SELECT == 0) ? iR : (BOTOUTPUT_SELECT == 1) ? iS : (BOTOUTPUT_SELECT == 2) ? iG : iH[15:0];
+	assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI;
+	assign O = {Oh, Ol};
+endmodule
diff --git a/techlibs/ice40/tests/test_dsp_model.gtkw b/techlibs/ice40/tests/test_dsp_model.gtkw
new file mode 100644
index 000000000..dafe8916f
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.gtkw
@@ -0,0 +1,87 @@
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Tue Feb 19 13:33:31 2019
+[*]
+[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd"
+[dumpfile_mtime] "Tue Feb 19 13:29:34 2019"
+[dumpfile_size] 119605
+[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw"
+[timestart] 0
+[size] 1850 1362
+[pos] 1816 32
+*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 223
+[signals_width] 142
+[sst_expanded] 1
+[sst_vpaned_height] 420
+@28
+testbench.CLK
+testbench.CE
+@200
+-
+@28
+testbench.REF_ACCUMCO
+testbench.UUT_ACCUMCO
+@200
+-
+@28
+testbench.REF_CO
+testbench.UUT_CO
+@200
+-
+@22
+testbench.REF_O[31:0]
+testbench.UUT_O[31:0]
+@200
+-
+@28
+testbench.REF_SIGNEXTOUT
+testbench.UUT_SIGNEXTOUT
+@200
+-
+@22
+testbench.A[15:0]
+testbench.B[15:0]
+testbench.C[15:0]
+testbench.D[15:0]
+@200
+-
+@28
+testbench.AHOLD
+testbench.BHOLD
+testbench.CHOLD
+testbench.DHOLD
+@200
+-
+@28
+testbench.SIGNEXTIN
+testbench.ACCUMCI
+testbench.CI
+@200
+-
+@28
+testbench.ADDSUBTOP
+testbench.ADDSUBBOT
+@200
+-
+@28
+testbench.IRSTTOP
+testbench.IRSTBOT
+@200
+-
+@29
+testbench.OHOLDTOP
+@28
+testbench.OHOLDBOT
+@200
+-
+@28
+testbench.OLOADTOP
+testbench.OLOADBOT
+@200
+-
+@28
+testbench.ORSTTOP
+testbench.ORSTBOT
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
new file mode 100644
index 000000000..ad079b2b6
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -ex
+sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
+cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
+iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
+./test_dsp_model
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
new file mode 100644
index 000000000..919bb7917
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -0,0 +1,199 @@
+`timescale 1ns / 1ps
+
+module testbench;
+	parameter [0:0] NEG_TRIGGER = 0;
+	parameter [0:0] C_REG = 0;
+	parameter [0:0] A_REG = 0;
+	parameter [0:0] B_REG = 0;
+	parameter [0:0] D_REG = 0;
+	parameter [0:0] TOP_8x8_MULT_REG = 0;
+	parameter [0:0] BOT_8x8_MULT_REG = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
+	parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
+	parameter [1:0] TOPOUTPUT_SELECT = 0;
+	parameter [1:0] TOPADDSUB_LOWERINPUT = 2;
+	parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
+	parameter [1:0] TOPADDSUB_CARRYSELECT = 2;
+	parameter [1:0] BOTOUTPUT_SELECT = 0;
+	parameter [1:0] BOTADDSUB_LOWERINPUT = 2;
+	parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
+	parameter [1:0] BOTADDSUB_CARRYSELECT = 2;
+	parameter [0:0] MODE_8x8 = 0;
+	parameter [0:0] A_SIGNED = 0;
+	parameter [0:0] B_SIGNED = 0;
+
+	reg CLK, CE;
+	reg [15:0] C, A, B, D;
+	reg AHOLD, BHOLD, CHOLD, DHOLD;
+	reg IRSTTOP, IRSTBOT;
+	reg ORSTTOP, ORSTBOT;
+	reg OLOADTOP, OLOADBOT;
+	reg ADDSUBTOP, ADDSUBBOT;
+	reg OHOLDTOP, OHOLDBOT;
+	reg CI, ACCUMCI, SIGNEXTIN;
+
+	output [31:0] REF_O, UUT_O;
+	output REF_CO, REF_ACCUMCO, REF_SIGNEXTOUT;
+	output UUT_CO, UUT_ACCUMCO, UUT_SIGNEXTOUT;
+
+	integer errcount = 0;
+
+	task clkcycle;
+		begin
+			#5;
+			CLK = ~CLK;
+			#10;
+			CLK = ~CLK;
+			#2;
+			if (REF_O !== UUT_O) begin
+				$display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O);
+				errcount = errcount + 1;
+			end
+			if (REF_CO !== UUT_CO) begin
+				$display("ERROR at %1t: REF_CO=%b UUT_CO=%b", $time, REF_CO, UUT_CO);
+				errcount = errcount + 1;
+			end
+			if (REF_ACCUMCO !== UUT_ACCUMCO) begin
+				$display("ERROR at %1t: REF_ACCUMCO=%b UUT_ACCUMCO=%b", $time, REF_ACCUMCO, UUT_ACCUMCO);
+				errcount = errcount + 1;
+			end
+			if (REF_SIGNEXTOUT !== UUT_SIGNEXTOUT) begin
+				$display("ERROR at %1t: REF_SIGNEXTOUT=%b UUT_SIGNEXTOUT=%b", $time, REF_SIGNEXTOUT, UUT_SIGNEXTOUT);
+				errcount = errcount + 1;
+			end
+			#3;
+		end
+	endtask
+
+	initial begin
+		$dumpfile("test_dsp_model.vcd");
+		$dumpvars(0, testbench);
+
+		#5;
+		CLK = NEG_TRIGGER;
+		CE = 1;
+		{C, A, B, D} = 0;
+		{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
+		{IRSTTOP, IRSTBOT} = 0;
+		{ORSTTOP, ORSTBOT} = 0;
+		{OLOADTOP, OLOADBOT} = 0;
+		{ADDSUBTOP, ADDSUBBOT} = 0;
+		{OHOLDTOP, OHOLDBOT} = 0;
+		{CI, ACCUMCI, SIGNEXTIN} = 0;
+
+		// C = 10;
+		// A = 15;
+		// B = 22;
+		// D = 27;
+
+		repeat (10) clkcycle;
+
+		if (errcount == 0) begin
+			$display("All tests passed.");
+		end else begin
+			$display("Caught %1d errors.", errcount);
+		end
+	end
+
+	SB_MAC16 #(
+		.NEG_TRIGGER              (NEG_TRIGGER             ),
+		.C_REG                    (C_REG                   ),
+		.A_REG                    (A_REG                   ),
+		.B_REG                    (B_REG                   ),
+		.D_REG                    (D_REG                   ),
+		.TOP_8x8_MULT_REG         (TOP_8x8_MULT_REG        ),
+		.BOT_8x8_MULT_REG         (BOT_8x8_MULT_REG        ),
+		.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
+		.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
+		.TOPOUTPUT_SELECT         (TOPOUTPUT_SELECT        ),
+		.TOPADDSUB_LOWERINPUT     (TOPADDSUB_LOWERINPUT    ),
+		.TOPADDSUB_UPPERINPUT     (TOPADDSUB_UPPERINPUT    ),
+		.TOPADDSUB_CARRYSELECT    (TOPADDSUB_CARRYSELECT   ),
+		.BOTOUTPUT_SELECT         (BOTOUTPUT_SELECT        ),
+		.BOTADDSUB_LOWERINPUT     (BOTADDSUB_LOWERINPUT    ),
+		.BOTADDSUB_UPPERINPUT     (BOTADDSUB_UPPERINPUT    ),
+		.BOTADDSUB_CARRYSELECT    (BOTADDSUB_CARRYSELECT   ),
+		.MODE_8x8                 (MODE_8x8                ),
+		.A_SIGNED                 (A_SIGNED                ),
+		.B_SIGNED                 (B_SIGNED                )
+	) ref (
+		.CLK        (CLK           ),
+		.CE         (CE            ),
+		.C          (C             ),
+		.A          (A             ),
+		.B          (B             ),
+		.D          (D             ),
+		.AHOLD      (AHOLD         ),
+		.BHOLD      (BHOLD         ),
+		.CHOLD      (CHOLD         ),
+		.DHOLD      (DHOLD         ),
+		.IRSTTOP    (IRSTTOP       ),
+		.IRSTBOT    (IRSTBOT       ),
+		.ORSTTOP    (ORSTTOP       ),
+		.ORSTBOT    (ORSTBOT       ),
+		.OLOADTOP   (OLOADTOP      ),
+		.OLOADBOT   (OLOADBOT      ),
+		.ADDSUBTOP  (ADDSUBTOP     ),
+		.ADDSUBBOT  (ADDSUBBOT     ),
+		.OHOLDTOP   (OHOLDTOP      ),
+		.OHOLDBOT   (OHOLDBOT      ),
+		.CI         (CI            ),
+		.ACCUMCI    (ACCUMCI       ),
+		.SIGNEXTIN  (SIGNEXTIN     ),
+		.O          (REF_O         ),
+		.CO         (REF_CO        ),
+		.ACCUMCO    (REF_ACCUMCO   ),
+		.SIGNEXTOUT (REF_SIGNEXTOUT)
+	);
+
+	SB_MAC16_UUT #(
+		.NEG_TRIGGER              (NEG_TRIGGER             ),
+		.C_REG                    (C_REG                   ),
+		.A_REG                    (A_REG                   ),
+		.B_REG                    (B_REG                   ),
+		.D_REG                    (D_REG                   ),
+		.TOP_8x8_MULT_REG         (TOP_8x8_MULT_REG        ),
+		.BOT_8x8_MULT_REG         (BOT_8x8_MULT_REG        ),
+		.PIPELINE_16x16_MULT_REG1 (PIPELINE_16x16_MULT_REG1),
+		.PIPELINE_16x16_MULT_REG2 (PIPELINE_16x16_MULT_REG2),
+		.TOPOUTPUT_SELECT         (TOPOUTPUT_SELECT        ),
+		.TOPADDSUB_LOWERINPUT     (TOPADDSUB_LOWERINPUT    ),
+		.TOPADDSUB_UPPERINPUT     (TOPADDSUB_UPPERINPUT    ),
+		.TOPADDSUB_CARRYSELECT    (TOPADDSUB_CARRYSELECT   ),
+		.BOTOUTPUT_SELECT         (BOTOUTPUT_SELECT        ),
+		.BOTADDSUB_LOWERINPUT     (BOTADDSUB_LOWERINPUT    ),
+		.BOTADDSUB_UPPERINPUT     (BOTADDSUB_UPPERINPUT    ),
+		.BOTADDSUB_CARRYSELECT    (BOTADDSUB_CARRYSELECT   ),
+		.MODE_8x8                 (MODE_8x8                ),
+		.A_SIGNED                 (A_SIGNED                ),
+		.B_SIGNED                 (B_SIGNED                )
+	) uut (
+		.CLK        (CLK           ),
+		.CE         (CE            ),
+		.C          (C             ),
+		.A          (A             ),
+		.B          (B             ),
+		.D          (D             ),
+		.AHOLD      (AHOLD         ),
+		.BHOLD      (BHOLD         ),
+		.CHOLD      (CHOLD         ),
+		.DHOLD      (DHOLD         ),
+		.IRSTTOP    (IRSTTOP       ),
+		.IRSTBOT    (IRSTBOT       ),
+		.ORSTTOP    (ORSTTOP       ),
+		.ORSTBOT    (ORSTBOT       ),
+		.OLOADTOP   (OLOADTOP      ),
+		.OLOADBOT   (OLOADBOT      ),
+		.ADDSUBTOP  (ADDSUBTOP     ),
+		.ADDSUBBOT  (ADDSUBBOT     ),
+		.OHOLDTOP   (OHOLDTOP      ),
+		.OHOLDBOT   (OHOLDBOT      ),
+		.CI         (CI            ),
+		.ACCUMCI    (ACCUMCI       ),
+		.SIGNEXTIN  (SIGNEXTIN     ),
+		.O          (UUT_O         ),
+		.CO         (UUT_CO        ),
+		.ACCUMCO    (UUT_ACCUMCO   ),
+		.SIGNEXTOUT (UUT_SIGNEXTOUT)
+	);
+endmodule

From c36f15b489c1d47e94901e9286c4f1c2afb815c4 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 14:10:43 +0000
Subject: [PATCH 383/528] ecp5: Add DELAYF/DELAYG blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_bb.v | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index 1de623fcd..bac17260f 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -173,6 +173,24 @@ parameter ER1 = "ENABLED";
 parameter ER2 = "ENABLED";
 endmodule
 
+(* blackbox *)
+module DELAYF(
+	input A, LOADN, MOVE, DIRECTION,
+	output Z, CFLAG
+);
+	parameter DEL_MODE = "USER_DEFINED";
+	parameter DEL_VALUE = 0;
+endmodule
+
+(* blackbox *)
+module DELAYG(
+	input A,
+	output Z
+);
+	parameter DEL_MODE = "USER_DEFINED";
+	parameter DEL_VALUE = 0;
+endmodule
+
 (* blackbox *)
 module IDDRX1F(
 	input D, SCLK, RST,

From 843e7fc8a70b7510ae8dfbad2c9f66d2d64d0e64 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Feb 2019 09:02:37 -0800
Subject: [PATCH 384/528] Fix for using POSIX basename

---
 frontends/aiger/aigerparse.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index 778b8b070..cf7950c85 100644
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -22,7 +22,7 @@
 // Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
 // http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
 
-#ifdef __linux__
+#ifndef _WIN32
 #include <libgen.h>
 #endif
 #include <array>
@@ -400,7 +400,9 @@ struct AigerFrontend : public Frontend {
 #ifdef _WIN32
             module_name = "top"; // FIXME: basename equivalent on Win32?
 #else
-            module_name = RTLIL::escape_id(basename(filename.c_str()));
+            char* bn = strdup(filename.c_str());
+            module_name = RTLIL::escape_id(bn);
+            free(bn);
 #endif
         }
 

From bb56cb738d6586059855cc3deefad12119673157 Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 19:34:37 +0000
Subject: [PATCH 385/528] ecp5: Add DDRDLLA

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_bb.v | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v
index bac17260f..223e19b9e 100644
--- a/techlibs/ecp5/cells_bb.v
+++ b/techlibs/ecp5/cells_bb.v
@@ -308,6 +308,15 @@ module DQSBUFM(
 	parameter GSR = "ENABLED";
 endmodule
 
+(* blackbox *)
+module DDRDLLA(
+	input CLK, RST, UDDCNTLN, FREEZE,
+	output LOCK, DDRDEL, DCNTL7, DCNTL6, DCNTL5, DCNTL4, DCNTL3, DCNTL2, DCNTL1, DCNTL0
+);
+	parameter FORCE_MAX_DELAY = "NO";
+	parameter GSR = "ENABLED";
+endmodule
+
 (* blackbox *)
 module CLKDIVF(
 	input CLKI, RST, ALIGNWD,

From 5c4a72c43ef61420b4b099d87949b0fdba0f4b55 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Tue, 19 Feb 2019 14:35:15 -0800
Subject: [PATCH 386/528] Fix normal (non-array) hierarchy -auto-top. Add
 simple test.

---
 passes/hierarchy/hierarchy.cc | 18 +++++------
 tests/various/hierarchy.sh    | 56 +++++++++++++++++++++++++++++++++++
 tests/various/run-test.sh     | 10 ++++++-
 3 files changed, 74 insertions(+), 10 deletions(-)
 create mode 100644 tests/various/hierarchy.sh

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 332ebdfbb..f112e969e 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -523,15 +523,15 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 			// Is this an array instance
 			if (celltype.substr(0, 7) == "$array:") {
 				celltype = basic_cell_type(celltype);
-				// Is this cell is a module instance?
-				if (celltype[0] != '$') {
-					auto instModule = design->module(celltype);
-					// If there is no instance for this, issue a warning.
-					if (instModule == NULL) {
-						log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
-					}
-					if (instModule != NULL)
-						score = max(score, find_top_mod_score(design, instModule, db) + 1);
+			}
+			// Is this cell a module instance?
+			if (celltype[0] != '$') {
+				auto instModule = design->module(celltype);
+				// If there is no instance for this, issue a warning.
+				if (instModule == NULL) {
+					log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
+				} else {
+					score = max(score, find_top_mod_score(design, instModule, db) + 1);
 				}
 			}
 		}
diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
new file mode 100644
index 000000000..dcb4dc056
--- /dev/null
+++ b/tests/various/hierarchy.sh
@@ -0,0 +1,56 @@
+#!/usr/bin/env bash
+# Simple test of hierarchy -auto-top.
+
+set -e
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+  read_verilog << EOV
+    module TOP(a, y);
+      input a;
+      output [31:0] y;
+
+      aoi12 p [31:0] (a, y);
+    endmodule
+
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+  read_verilog << EOV
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+
+    module TOP(a, y);
+      input a;
+      output [31:0] y;
+
+      aoi12 foo (a, y);
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
+
+../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+  read_verilog << EOV
+    module aoi12(a, y);
+      input a;
+      output y;
+      assign y = ~a;
+    endmodule
+
+    module noTop(a, y);
+      input a;
+      output [31:0] y;
+    endmodule
+  EOV
+  hierarchy -auto-top
+EOY
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 67e1beb23..7cd1a8650 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -1,6 +1,14 @@
-#!/bin/bash
+#!/usr/bin/env bash
 set -e
 for x in *.ys; do
 	echo "Running $x.."
 	../../yosys -ql ${x%.ys}.log $x
 done
+# Run any .sh files in this directory (with the exception of the file - run-test.sh
+shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
+if [ "$shell_tests" ]; then
+    for s in $shell_tests; do
+        echo "Running $s.."
+        bash $s >& ${s%.sh}.log
+    done
+fi

From d365682a21147b6a06d9548a6f4b99d347931441 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Feb 2019 15:25:47 -0800
Subject: [PATCH 387/528] Add aiger tests to make tests

---
 Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Makefile b/Makefile
index d83a71256..4324b2eec 100644
--- a/Makefile
+++ b/Makefile
@@ -580,6 +580,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/sat && bash run-test.sh
 	+cd tests/svinterfaces && bash run-test.sh $(SEEDOPT)
 	+cd tests/opt && bash run-test.sh
+	+cd tests/aiger && bash run-test.sh
 	@echo ""
 	@echo "  Passed \"make test\"."
 	@echo ""

From dca65d83a0037539464d303ea8751a3e06a92e03 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 11:18:19 +0100
Subject: [PATCH 388/528] Detect and reject cases that do not map well to iCE40
 DSPs (yet)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.cc  |  9 +++++++--
 passes/pmgen/ice40_dsp.pmg | 10 ++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 7463d598f..8c50a9393 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -59,10 +59,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		return;
 	}
 
-	log("  replacing $mul with SB_MAC16 cell.\n");
-
 	bool mul_signed = pm.st.mul->getParam("\\A_SIGNED").as_bool();
 
+	if (mul_signed) {
+		log("  inference of signed iCE40 DSP arithmetic is currently not supported.\n");
+		return;
+	}
+
+	log("  replacing $mul with SB_MAC16 cell.\n");
+
 	Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
 	pm.module->swap_names(cell, pm.st.mul);
 
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg
index 58e1ce0e0..96c62e313 100644
--- a/passes/pmgen/ice40_dsp.pmg
+++ b/passes/pmgen/ice40_dsp.pmg
@@ -100,6 +100,16 @@ code addAB sigS
 		addAB = addB;
 		sigS = port(addB, \A);
 	}
+	if (addAB) {
+		int natural_mul_width = GetSize(sigA) + GetSize(sigB);
+		int actual_mul_width = GetSize(sigY);
+		int actual_acc_width = GetSize(sigS);
+
+		if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
+			reject;
+		if ((actual_acc_width != actual_mul_width) && (param(mul, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
+			reject;
+	}
 endcode
 
 match muxA

From 7bf4e4a1855df442191e3d1cc28eeda7e01d051c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 12:55:20 +0100
Subject: [PATCH 389/528] Improve iCE40 SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v               |  27 ++--
 techlibs/ice40/tests/.gitignore          |   8 +-
 techlibs/ice40/tests/test_dsp_model.gtkw |  87 ------------
 techlibs/ice40/tests/test_dsp_model.sh   |   9 +-
 techlibs/ice40/tests/test_dsp_model.v    | 169 +++++++++++++++++++++--
 5 files changed, 179 insertions(+), 121 deletions(-)
 delete mode 100644 techlibs/ice40/tests/test_dsp_model.gtkw

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 4a92fccdf..2041693cc 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -1283,7 +1283,7 @@ module SB_MAC16 (
 
 	// Regs B and D
 	reg [15:0] rB, rD;
-	always @(posedge clock, posedge IRSTTOP) begin
+	always @(posedge clock, posedge IRSTBOT) begin
 		if (IRSTBOT) begin
 			rB <= 0;
 			rD <= 0;
@@ -1298,10 +1298,10 @@ module SB_MAC16 (
 	// Multiplier Stage
 	wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl;
 	wire [15:0] Ah, Al, Bh, Bl;
-	assign Ah = A_SIGNED ? {{8{iA[15]}}, iA[15: 8]} : iA[15: 8];
-	assign Al = A_SIGNED ? {{8{iA[ 7]}}, iA[ 7: 0]} : iA[15: 8];
-	assign Bh = B_SIGNED ? {{8{iB[15]}}, iB[15: 8]} : iB[15: 8];
-	assign Bl = B_SIGNED ? {{8{iB[ 7]}}, iB[ 7: 0]} : iB[15: 8];
+	assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]};
+	assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]};
+	assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]};
+	assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]};
 	assign p_Ah_Bh = Ah * Bh;
 	assign p_Al_Bh = Al * Bh;
 	assign p_Ah_Bl = Ah * Bl;
@@ -1336,17 +1336,10 @@ module SB_MAC16 (
 	assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl;
 
 	// Adder Stage
-	reg [31:0] P;
-	always @* begin
-		P = iG[7:0];
-		P = P + (iG[15:8] + iK[7:0]) << 8;
-		P = P + (iK[15:8] + iJ[7:0]) << 16;
-		P = P + (iJ[15:8] + iF[7:0]) << 24;
-	end
-	assign iL = P;
+	assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16);
 
 	// Reg H
-	reg [15:0] rH;
+	reg [31:0] rH;
 	always @(posedge clock, posedge IRSTBOT) begin
 		if (IRSTBOT) begin
 			rH <= 0;
@@ -1359,7 +1352,7 @@ module SB_MAC16 (
 	// Hi Output Stage
 	wire [15:0] XW, Oh;
 	reg [15:0] rQ;
-	assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ[31:16];
+	assign iW = TOPADDSUB_UPPERINPUT ? iC : iQ;
 	assign iX = (TOPADDSUB_LOWERINPUT == 0) ? iA : (TOPADDSUB_LOWERINPUT == 1) ? iF : (TOPADDSUB_LOWERINPUT == 2) ? iH[31:16] : {16{iZ[15]}};
 	assign {ACCUMCO, XW} = iX + (iW ^ {16{ADDSUBTOP}}) + HCI;
 	assign CO = ACCUMCO ^ ADDSUBTOP;
@@ -1379,7 +1372,7 @@ module SB_MAC16 (
 	// Lo Output Stage
 	wire [15:0] YZ, Ol;
 	reg [15:0] rS;
-	assign iY = BOTADDSUB_UPPERINPUT ? iD : iQ[15:0];
+	assign iY = BOTADDSUB_UPPERINPUT ? iD : iS;
 	assign iZ = (BOTADDSUB_LOWERINPUT == 0) ? iB : (BOTADDSUB_LOWERINPUT == 1) ? iG : (BOTADDSUB_LOWERINPUT == 2) ? iH[15:0] : {16{SIGNEXTIN}};
 	assign {LCO, YZ} = iZ + (iY ^ {16{ADDSUBBOT}}) + LCI;
 	assign iR = OLOADBOT ? iD : YZ ^ {16{ADDSUBBOT}};
@@ -1387,7 +1380,7 @@ module SB_MAC16 (
 		if (ORSTBOT) begin
 			rS <= 0;
 		end else if (CE) begin
-			if (!OHOLDTOP) rS <= iR;
+			if (!OHOLDBOT) rS <= iR;
 		end
 	end
 	assign iS = rS;
diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index b58f9ad4a..9795152c2 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -1,2 +1,6 @@
-test_ffs_[01][01][01][01][01]_*
-test_bram_[0-9]*
+/test_ffs_[01][01][01][01][01]_*
+/test_bram_[0-9]*
+/test_dsp_model
+/test_dsp_model.vcd
+/test_dsp_model_ref.v
+/test_dsp_model_uut.v
diff --git a/techlibs/ice40/tests/test_dsp_model.gtkw b/techlibs/ice40/tests/test_dsp_model.gtkw
deleted file mode 100644
index dafe8916f..000000000
--- a/techlibs/ice40/tests/test_dsp_model.gtkw
+++ /dev/null
@@ -1,87 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Tue Feb 19 13:33:31 2019
-[*]
-[dumpfile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.vcd"
-[dumpfile_mtime] "Tue Feb 19 13:29:34 2019"
-[dumpfile_size] 119605
-[savefile] "/home/clifford/Work/yosys/techlibs/ice40/tests/test_dsp_model.gtkw"
-[timestart] 0
-[size] 1850 1362
-[pos] 1816 32
-*-16.399944 42300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[sst_width] 223
-[signals_width] 142
-[sst_expanded] 1
-[sst_vpaned_height] 420
-@28
-testbench.CLK
-testbench.CE
-@200
--
-@28
-testbench.REF_ACCUMCO
-testbench.UUT_ACCUMCO
-@200
--
-@28
-testbench.REF_CO
-testbench.UUT_CO
-@200
--
-@22
-testbench.REF_O[31:0]
-testbench.UUT_O[31:0]
-@200
--
-@28
-testbench.REF_SIGNEXTOUT
-testbench.UUT_SIGNEXTOUT
-@200
--
-@22
-testbench.A[15:0]
-testbench.B[15:0]
-testbench.C[15:0]
-testbench.D[15:0]
-@200
--
-@28
-testbench.AHOLD
-testbench.BHOLD
-testbench.CHOLD
-testbench.DHOLD
-@200
--
-@28
-testbench.SIGNEXTIN
-testbench.ACCUMCI
-testbench.CI
-@200
--
-@28
-testbench.ADDSUBTOP
-testbench.ADDSUBBOT
-@200
--
-@28
-testbench.IRSTTOP
-testbench.IRSTBOT
-@200
--
-@29
-testbench.OHOLDTOP
-@28
-testbench.OHOLDBOT
-@200
--
-@28
-testbench.OLOADTOP
-testbench.OLOADBOT
-@200
--
-@28
-testbench.ORSTTOP
-testbench.ORSTBOT
-[pattern_trace] 1
-[pattern_trace] 0
diff --git a/techlibs/ice40/tests/test_dsp_model.sh b/techlibs/ice40/tests/test_dsp_model.sh
index ad079b2b6..1bc0cc688 100644
--- a/techlibs/ice40/tests/test_dsp_model.sh
+++ b/techlibs/ice40/tests/test_dsp_model.sh
@@ -2,5 +2,10 @@
 set -ex
 sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
 cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
-iverilog -s testbench -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
-./test_dsp_model
+for tb in testbench \
+		testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
+		testbench_seq_16x16_A testbench_seq_16x16_B
+do
+	iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
+	vvp -N ./test_dsp_model
+done
diff --git a/techlibs/ice40/tests/test_dsp_model.v b/techlibs/ice40/tests/test_dsp_model.v
index 919bb7917..594bd4ad3 100644
--- a/techlibs/ice40/tests/test_dsp_model.v
+++ b/techlibs/ice40/tests/test_dsp_model.v
@@ -11,13 +11,13 @@ module testbench;
 	parameter [0:0] PIPELINE_16x16_MULT_REG1 = 0;
 	parameter [0:0] PIPELINE_16x16_MULT_REG2 = 0;
 	parameter [1:0] TOPOUTPUT_SELECT = 0;
-	parameter [1:0] TOPADDSUB_LOWERINPUT = 2;
+	parameter [1:0] TOPADDSUB_LOWERINPUT = 0;
 	parameter [0:0] TOPADDSUB_UPPERINPUT = 1;
-	parameter [1:0] TOPADDSUB_CARRYSELECT = 2;
+	parameter [1:0] TOPADDSUB_CARRYSELECT = 0;
 	parameter [1:0] BOTOUTPUT_SELECT = 0;
-	parameter [1:0] BOTADDSUB_LOWERINPUT = 2;
+	parameter [1:0] BOTADDSUB_LOWERINPUT = 0;
 	parameter [0:0] BOTADDSUB_UPPERINPUT = 1;
-	parameter [1:0] BOTADDSUB_CARRYSELECT = 2;
+	parameter [1:0] BOTADDSUB_CARRYSELECT = 0;
 	parameter [0:0] MODE_8x8 = 0;
 	parameter [0:0] A_SIGNED = 0;
 	parameter [0:0] B_SIGNED = 0;
@@ -46,7 +46,7 @@ module testbench;
 			CLK = ~CLK;
 			#2;
 			if (REF_O !== UUT_O) begin
-				$display("ERROR at %1t: REF_O=%b UUT_O=%b", $time, REF_O, UUT_O);
+				$display("ERROR at %1t: REF_O=%b UUT_O=%b DIFF=%b", $time, REF_O, UUT_O, REF_O ^ UUT_O);
 				errcount = errcount + 1;
 			end
 			if (REF_CO !== UUT_CO) begin
@@ -69,29 +69,47 @@ module testbench;
 		$dumpfile("test_dsp_model.vcd");
 		$dumpvars(0, testbench);
 
-		#5;
+		#2;
 		CLK = NEG_TRIGGER;
 		CE = 1;
 		{C, A, B, D} = 0;
 		{AHOLD, BHOLD, CHOLD, DHOLD} = 0;
-		{IRSTTOP, IRSTBOT} = 0;
-		{ORSTTOP, ORSTBOT} = 0;
 		{OLOADTOP, OLOADBOT} = 0;
 		{ADDSUBTOP, ADDSUBBOT} = 0;
 		{OHOLDTOP, OHOLDBOT} = 0;
 		{CI, ACCUMCI, SIGNEXTIN} = 0;
 
-		// C = 10;
-		// A = 15;
-		// B = 22;
-		// D = 27;
+		{IRSTTOP, IRSTBOT} = ~0;
+		{ORSTTOP, ORSTBOT} = ~0;
 
-		repeat (10) clkcycle;
+		#3;
+		{IRSTTOP, IRSTBOT} = 0;
+		{ORSTTOP, ORSTBOT} = 0;
+
+		repeat (300) begin
+			clkcycle;
+
+			A = $urandom;
+			B = $urandom;
+			C = $urandom;
+			D = $urandom;
+
+			{AHOLD, BHOLD, CHOLD, DHOLD} = $urandom & $urandom & $urandom;
+			{OLOADTOP, OLOADBOT} = $urandom & $urandom & $urandom;
+			{ADDSUBTOP, ADDSUBBOT} = $urandom & $urandom & $urandom;
+			{OHOLDTOP, OHOLDBOT} = $urandom & $urandom & $urandom;
+			{CI, ACCUMCI, SIGNEXTIN} = $urandom & $urandom & $urandom;
+
+			{IRSTTOP, IRSTBOT} = $urandom & $urandom & $urandom;
+			{ORSTTOP, ORSTBOT} = $urandom & $urandom & $urandom;
+		end
 
 		if (errcount == 0) begin
 			$display("All tests passed.");
+			$finish;
 		end else begin
 			$display("Caught %1d errors.", errcount);
+			$stop;
 		end
 	end
 
@@ -197,3 +215,128 @@ module testbench;
 		.SIGNEXTOUT (UUT_SIGNEXTOUT)
 	);
 endmodule
+
+module testbench_comb_8x8_A;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (2),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (0),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (2),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (0),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_8x8_B;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (1),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (1),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (0),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_comb_16x16;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (0),
+		.A_REG                     (0),
+		.B_REG                     (0),
+		.D_REG                     (0),
+		.TOP_8x8_MULT_REG          (0),
+		.BOT_8x8_MULT_REG          (0),
+		.PIPELINE_16x16_MULT_REG1  (0),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_seq_16x16_A;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (1),
+		.A_REG                     (1),
+		.B_REG                     (1),
+		.D_REG                     (1),
+		.TOP_8x8_MULT_REG          (1),
+		.BOT_8x8_MULT_REG          (1),
+		.PIPELINE_16x16_MULT_REG1  (1),
+		.PIPELINE_16x16_MULT_REG2  (1),
+		.TOPOUTPUT_SELECT          (0),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (1),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (0),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (1),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule
+
+module testbench_seq_16x16_B;
+	testbench #(
+		.NEG_TRIGGER               (0),
+		.C_REG                     (1),
+		.A_REG                     (1),
+		.B_REG                     (1),
+		.D_REG                     (1),
+		.TOP_8x8_MULT_REG          (1),
+		.BOT_8x8_MULT_REG          (1),
+		.PIPELINE_16x16_MULT_REG1  (1),
+		.PIPELINE_16x16_MULT_REG2  (0),
+		.TOPOUTPUT_SELECT          (1),   // 0=P, 1=Q, 2=8x8, 3=16x16
+		.TOPADDSUB_LOWERINPUT      (2),   // 0=A, 1=8x8, 2=16x16, 3=S-EXT
+		.TOPADDSUB_UPPERINPUT      (0),   // 0=Q, 1=C
+		.TOPADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.BOTOUTPUT_SELECT          (1),   // 0=R, 1=S, 2=8x8, 3=16x16
+		.BOTADDSUB_LOWERINPUT      (2),   // 0=B, 1=8x8, 2=16x16, 3=S-EXT
+		.BOTADDSUB_UPPERINPUT      (0),   // 0=S, 1=D
+		.BOTADDSUB_CARRYSELECT     (2),   // 0=0, 1=1, 2=ACI, 3=CI
+		.MODE_8x8                  (0),
+		.A_SIGNED                  (0),
+		.B_SIGNED                  (0)
+	) testbench ();
+endmodule

From 246391200e3e0d47ee571d4d77dd0744dba0e164 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 16:36:42 +0100
Subject: [PATCH 390/528] Add FF support to wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/rtlil.cc       |  3 ++
 passes/opt/wreduce.cc | 71 ++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8404db5e9..d4aebcda9 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2410,6 +2410,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 	if (connections_.count("\\Y"))
 		parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
 
+	if (connections_.count("\\Q"))
+		parameters["\\WIDTH"] = GetSize(connections_["\\Q"]);
+
 	check();
 }
 
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 8063b86a6..3aa916ec2 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -38,7 +38,8 @@ struct WreduceConfig
 			"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
 			"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
 			"$add", "$sub", "$mul", // "$div", "$mod", "$pow",
-			"$mux", "$pmux"
+			"$mux", "$pmux",
+			"$dff", "$adff"
 		});
 	}
 };
@@ -134,6 +135,71 @@ struct WreduceWorker
 		module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
 	}
 
+	void run_cell_dff(Cell *cell)
+	{
+		// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
+
+		SigSpec sig_d = mi.sigmap(cell->getPort("\\D"));
+		SigSpec sig_q = mi.sigmap(cell->getPort("\\Q"));
+
+		int width_before = GetSize(sig_q);
+
+		if (width_before == 0)
+			return;
+
+		bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
+		bool sign_ext = !zero_ext;
+
+		for (int i = GetSize(sig_q)-1; i >= 0; i--)
+		{
+			if (zero_ext && sig_d[i] == State::S0) {
+				module->connect(sig_q[i], State::S0);
+				sig_d.remove(i);
+				sig_q.remove(i);
+				continue;
+			}
+
+			if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1]) {
+				module->connect(sig_q[i], sig_q[i-1]);
+				sig_d.remove(i);
+				sig_q.remove(i);
+				continue;
+			}
+
+			auto info = mi.query(sig_q[i]);
+			if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
+				sig_d.remove(i);
+				sig_q.remove(i);
+				zero_ext = false;
+				sign_ext = false;
+				continue;
+			}
+
+			break;
+		}
+
+		if (width_before == GetSize(sig_q))
+			return;
+
+		if (GetSize(sig_q) == 0) {
+			log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
+			return;
+		}
+
+		log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
+				log_id(module), log_id(cell), log_id(cell->type));
+
+		for (auto bit : sig_d)
+			work_queue_bits.insert(bit);
+
+		for (auto bit : sig_q)
+			work_queue_bits.insert(bit);
+
+		cell->setPort("\\D", sig_d);
+		cell->setPort("\\Q", sig_q);
+		cell->fixup_parameters();
+	}
+
 	void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something)
 	{
 		port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
@@ -176,6 +242,9 @@ struct WreduceWorker
 		if (cell->type.in("$mux", "$pmux"))
 			return run_cell_mux(cell);
 
+		if (cell->type.in("$dff", "$adff"))
+			return run_cell_dff(cell);
+
 		SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
 
 		if (sig.has_const())

From 218e9051bbdbbd00620a21e6918e6a4b9bc07867 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 16:42:27 +0100
Subject: [PATCH 391/528] Add "synth_ice40 -dsp"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.cc     |  8 ++++----
 techlibs/ice40/synth_ice40.cc | 30 +++++++++++++++++++++++++++---
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 8c50a9393..3e342453d 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -159,8 +159,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 		cell->setPort("\\ADDSUBBOT", State::S0);
 	}
 
-	cell->setPort("\\ORTSTOP", State::S0);
-	cell->setPort("\\ORTSBOT", State::S0);
+	cell->setPort("\\ORSTTOP", State::S0);
+	cell->setPort("\\ORSTBOT", State::S0);
 
 	cell->setPort("\\OHOLDTOP", State::S0);
 	cell->setPort("\\OHOLDBOT", State::S0);
@@ -181,8 +181,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	cell->setParam("\\TOP_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0);
 	cell->setParam("\\BOT_8x8_MULT_REG", pm.st.ffY ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16X16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0);
-	cell->setParam("\\PIPELINE_16X16_MULT_REG2", State::S0);
+	cell->setParam("\\PIPELINE_16x16_MULT_REG1", pm.st.ffY ? State::S1 : State::S0);
+	cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
 
 	cell->setParam("\\TOPOUTPUT_SELECT", Const(pm.st.ffS ? 1 : 3, 2));
 	cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index f900453e8..d6d047fe7 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -79,6 +79,9 @@ struct SynthIce40Pass : public ScriptPass
 		log("    -nobram\n");
 		log("        do not use SB_RAM40_4K* cells in output netlist\n");
 		log("\n");
+		log("    -dsp\n");
+		log("        use iCE40 UltraPlus DSP cells for large arithmetic\n");
+		log("\n");
 		log("    -noabc\n");
 		log("        use built-in Yosys LUT techmapping instead of abc\n");
 		log("\n");
@@ -96,7 +99,7 @@ struct SynthIce40Pass : public ScriptPass
 	}
 
 	string top_opt, blif_file, edif_file, json_file;
-	bool nocarry, nodffe, nobram, flatten, retime, relut, noabc, abc2, vpr;
+	bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
 	int min_ce_use;
 
 	void clear_flags() YS_OVERRIDE
@@ -109,6 +112,7 @@ struct SynthIce40Pass : public ScriptPass
 		nodffe = false;
 		min_ce_use = -1;
 		nobram = false;
+		dsp = false;
 		flatten = true;
 		retime = false;
 		relut = false;
@@ -181,6 +185,10 @@ struct SynthIce40Pass : public ScriptPass
 				nobram = true;
 				continue;
 			}
+			if (args[argidx] == "-dsp") {
+				dsp = true;
+				continue;
+			}
 			if (args[argidx] == "-noabc") {
 				noabc = true;
 				continue;
@@ -214,11 +222,11 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			run("read_verilog -lib +/ice40/cells_sim.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
+			run("proc");
 		}
 
 		if (flatten && check_label("flatten", "(unless -noflatten)"))
 		{
-			run("proc");
 			run("flatten");
 			run("tribuf -logic");
 			run("deminout");
@@ -226,7 +234,23 @@ struct SynthIce40Pass : public ScriptPass
 
 		if (check_label("coarse"))
 		{
-			run("synth -lut 4 -run coarse");
+			run("opt_expr");
+			run("opt_clean");
+			run("check");
+			run("opt");
+			run("wreduce");
+			run("share");
+			run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
+			run("opt_expr");
+			run("opt_clean");
+			if (help_mode || dsp)
+				run("ice40_dsp", "(if -dsp)");
+			run("alumacc");
+			run("opt");
+			run("fsm");
+			run("opt -fast");
+			run("memory -nomap");
+			run("opt_clean");
 		}
 
 		if (!nobram && check_label("bram", "(skip if -nobram)"))

From 84999a7e680648dff674ce55f634a675852b7dc3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Feb 2019 17:18:59 +0100
Subject: [PATCH 392/528] Add ice40 test_dsp_map test case generator

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/tests/.gitignore      |  4 ++
 techlibs/ice40/tests/test_dsp_map.sh | 95 ++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 techlibs/ice40/tests/test_dsp_map.sh

diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index 9795152c2..300ce9aa6 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -4,3 +4,7 @@
 /test_dsp_model.vcd
 /test_dsp_model_ref.v
 /test_dsp_model_uut.v
+/test_dsp_map
+/test_dsp_map_tb.v
+/test_dsp_map_top.v
+/test_dsp_map_syn.v
diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh
new file mode 100644
index 000000000..5982e5b34
--- /dev/null
+++ b/techlibs/ice40/tests/test_dsp_map.sh
@@ -0,0 +1,95 @@
+#!/bin/bash
+set -ex
+
+SZA=$(( 3 + $RANDOM % 13 ))
+SZB=$(( 3 + $RANDOM % 13 ))
+SZO=$(( 3 + $RANDOM % 29 ))
+
+C0=clk$(( $RANDOM & 1))
+C1=clk$(( $RANDOM & 1))
+C2=clk$(( $RANDOM & 1))
+C3=clk$(( $RANDOM & 1))
+
+E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+
+SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
+
+RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
+RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
+
+cat > test_dsp_map_top.v << EOT
+module top (
+	input clk0, clk1, reset,
+	input  [$SZA:0] A,
+	input  [$SZB:0] B,
+	output [$SZO:0] O
+);
+	reg [15:0] AA, BB;
+	reg [31:0] P, S;
+
+	always @($E0 $C0) AA <= A;
+	always @($E1 $C1) BB <= B;
+	always @($E2 $C2) P <= AA * BB;
+	always @($E3 $C3) S <= $RC ? $RV : S + P;
+	assign O = $SP;
+endmodule
+EOT
+
+cat > test_dsp_map_tb.v << EOT
+\`timescale 1ns / 1ps
+module testbench;
+	reg clk1, clk0, reset;
+	reg [$SZA:0] A;
+	reg [$SZB:0] B;
+
+	wire [$SZO:0] O_top, O_syn;
+
+	top top_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_top));
+	syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
+
+	initial begin
+		#2;
+		clk0 = 0;
+		clk1 = 0;
+		reset = 1;
+		A = 0;
+		B = 0;
+
+		repeat (3) begin
+			#2; clk0 = ~clk0;
+			#2; clk0 = ~clk0;
+			#2; clk1 = ~clk1;
+			#2; clk1 = ~clk1;
+		end
+
+		repeat (100) begin
+			#2;
+			A = \$urandom;
+			B = \$urandom;
+			reset = \$urandom & \$urandom & \$urandom & \$urandom;
+			if (\$urandom & 1) begin
+				#2; clk0 = ~clk0;
+				#2; clk0 = ~clk0;
+			end else begin
+				#2; clk1 = ~clk1;
+				#2; clk1 = ~clk1;
+			end
+			#2;
+			if (O_top !== O_syn) begin
+				\$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
+				\$stop;
+			end
+			\$display("OK O_top=O_syn=%b", O_top);
+		end
+
+		\$finish;
+	end
+endmodule
+EOT
+
+../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
+iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
+vvp -N test_dsp_map

From 4035ec8933cd187670788fb6eca5cefa80fe7170 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 20 Feb 2019 15:45:45 -0800
Subject: [PATCH 393/528] Remove simple_defparam tests

---
 tests/simple_defparam/run-test.sh | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100755 tests/simple_defparam/run-test.sh

diff --git a/tests/simple_defparam/run-test.sh b/tests/simple_defparam/run-test.sh
deleted file mode 100755
index 137e15076..000000000
--- a/tests/simple_defparam/run-test.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/bash
-
-OPTIND=1
-seed=""    # default to no seed specified
-while getopts "S:" opt
-do
-    case "$opt" in
-	S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
-	   seed="SEED=$arg" ;;
-    esac
-done
-shift "$((OPTIND-1))"
-
-# check for Icarus Verilog
-if ! which iverilog > /dev/null ; then
-  echo "$0: Error: Icarus Verilog 'iverilog' not found."
-  exit 1
-fi
-
-cp ../simple/*.v .
-exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-B \"-defparam\""

From 2fe1c830eb8aea783c75529b42cab04208cea690 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 13:28:46 +0100
Subject: [PATCH 394/528] Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/ice40_dsp.cc            |  4 +--
 techlibs/ice40/tests/.gitignore      |  1 +
 techlibs/ice40/tests/test_dsp_map.sh | 52 +++++++++++++++++-----------
 3 files changed, 35 insertions(+), 22 deletions(-)

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 3e342453d..3a054a463 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -91,8 +91,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 	cell->setPort("\\C", CD.extract(0, 16));
 	cell->setPort("\\D", CD.extract(16, 16));
 
-	cell->setParam("\\A_REG", pm.st.ffA ? State::S0 : State::S1);
-	cell->setParam("\\B_REG", pm.st.ffB ? State::S0 : State::S1);
+	cell->setParam("\\A_REG", pm.st.ffA ? State::S1 : State::S0);
+	cell->setParam("\\B_REG", pm.st.ffB ? State::S1 : State::S0);
 
 	cell->setPort("\\AHOLD", State::S0);
 	cell->setPort("\\BHOLD", State::S0);
diff --git a/techlibs/ice40/tests/.gitignore b/techlibs/ice40/tests/.gitignore
index 300ce9aa6..120286550 100644
--- a/techlibs/ice40/tests/.gitignore
+++ b/techlibs/ice40/tests/.gitignore
@@ -5,6 +5,7 @@
 /test_dsp_model_ref.v
 /test_dsp_model_uut.v
 /test_dsp_map
+/test_dsp_map.vcd
 /test_dsp_map_tb.v
 /test_dsp_map_top.v
 /test_dsp_map_syn.v
diff --git a/techlibs/ice40/tests/test_dsp_map.sh b/techlibs/ice40/tests/test_dsp_map.sh
index 5982e5b34..3f7f134e4 100644
--- a/techlibs/ice40/tests/test_dsp_map.sh
+++ b/techlibs/ice40/tests/test_dsp_map.sh
@@ -1,26 +1,28 @@
 #!/bin/bash
 set -ex
 
-SZA=$(( 3 + $RANDOM % 13 ))
-SZB=$(( 3 + $RANDOM % 13 ))
-SZO=$(( 3 + $RANDOM % 29 ))
+for iter in {1..100}
+do
+	SZA=$(( 3 + $RANDOM % 13 ))
+	SZB=$(( 3 + $RANDOM % 13 ))
+	SZO=$(( 3 + $RANDOM % 29 ))
 
-C0=clk$(( $RANDOM & 1))
-C1=clk$(( $RANDOM & 1))
-C2=clk$(( $RANDOM & 1))
-C3=clk$(( $RANDOM & 1))
+	C0=clk$(( $RANDOM & 1))
+	C1=clk$(( $RANDOM & 1))
+	C2=clk$(( $RANDOM & 1))
+	C3=clk$(( $RANDOM & 1))
 
-E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
-E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E0=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E1=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E2=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
+	E3=$( test $(( $RANDOM & 1 )) -eq 0 && echo posedge || echo negedge )
 
-SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
+	SP=$( test $(( $RANDOM & 1 )) -eq 0 && echo S || echo P )
 
-RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
-RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
+	RC=$( test $(( $RANDOM & 1 )) -eq 0 && echo "reset" || echo "!reset" )
+	RV="32'h$( echo $RANDOM | md5sum | cut -c1-8 )"
 
-cat > test_dsp_map_top.v << EOT
+	cat > test_dsp_map_top.v << EOT
 module top (
 	input clk0, clk1, reset,
 	input  [$SZA:0] A,
@@ -38,7 +40,7 @@ module top (
 endmodule
 EOT
 
-cat > test_dsp_map_tb.v << EOT
+	cat > test_dsp_map_tb.v << EOT
 \`timescale 1ns / 1ps
 module testbench;
 	reg clk1, clk0, reset;
@@ -51,10 +53,14 @@ module testbench;
 	syn syn_inst (.clk0(clk0), .clk1(clk1), .reset(reset), .A(A), .B(B), .O(O_syn));
 
 	initial begin
+		// \$dumpfile("test_dsp_map.vcd");
+		// \$dumpvars(0, testbench);
+
 		#2;
 		clk0 = 0;
 		clk1 = 0;
 		reset = 1;
+		reset = $RC;
 		A = 0;
 		B = 0;
 
@@ -82,14 +88,20 @@ module testbench;
 				\$display("ERROR: O_top=%b O_syn=%b", O_top, O_syn);
 				\$stop;
 			end
-			\$display("OK O_top=O_syn=%b", O_top);
+			// \$display("OK O_top=O_syn=%b", O_top);
 		end
 
+		\$display("Test passed.");
 		\$finish;
 	end
 endmodule
 EOT
 
-../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
-iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
-vvp -N test_dsp_map
+	../../../yosys -p 'read_verilog test_dsp_map_top.v; synth_ice40 -dsp; rename top syn; write_verilog test_dsp_map_syn.v'
+	iverilog -o test_dsp_map -s testbench test_dsp_map_tb.v test_dsp_map_top.v test_dsp_map_syn.v ../cells_sim.v
+	vvp -N test_dsp_map
+done
+
+: ""
+: "####  All tests passed.  ####"
+: ""

From 2da4c9c8f0a849434f657ac4a56de11d35e1c41e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 13:48:23 +0100
Subject: [PATCH 395/528] Fix opt_rmdff handling of $_DFFSR_???_ and
 $_DLATCHSR_???_, fixes #816

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/opt_rmdff.cc | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 5880254c1..e8570f0eb 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -174,8 +174,6 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 			cell->unsetParam("\\CLR_POLARITY");
 			cell->unsetPort("\\SET");
 			cell->unsetPort("\\CLR");
-
-			return true;
 		}
 		else
 		{
@@ -186,11 +184,12 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 			cell->unsetParam("\\CLR_POLARITY");
 			cell->unsetPort("\\SET");
 			cell->unsetPort("\\CLR");
-
-			return true;
 		}
+
+		return true;
 	}
-	else
+
+	if (!hasreset)
 	{
 		IdString new_type;
 
@@ -207,8 +206,10 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
 		cell->unsetPort("\\S");
 		cell->unsetPort("\\R");
 
-		return did_something;
+		return true;
 	}
+
+	return did_something;
 }
 
 bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)

From 953e0bf88d363180619452dd0049268ee9cfbb67 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 14:27:46 +0100
Subject: [PATCH 396/528] Rename "yosys -D" to "yosys -U", add "yosys -D" with
 expected behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/driver.cc | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/kernel/driver.cc b/kernel/driver.cc
index 178641101..ca8f6a7b5 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -179,6 +179,7 @@ int main(int argc, char **argv)
 {
 	std::string frontend_command = "auto";
 	std::string backend_command = "auto";
+	std::vector<std::string> vlog_defines;
 	std::vector<std::string> passes_commands;
 	std::vector<std::string> plugin_filenames;
 	std::string output_filename = "";
@@ -268,7 +269,10 @@ int main(int argc, char **argv)
 		printf("    -A\n");
 		printf("        will call abort() at the end of the script. for debugging\n");
 		printf("\n");
-		printf("    -D <header_id>[:<filename>]\n");
+		printf("    -D <macro>[=<value>]\n");
+		printf("        set the specified Verilog define (via \"read -define\")\n");
+		printf("\n");
+		printf("    -U <header_id>[:<filename>]\n");
 		printf("        dump the design when printing the specified log header to a file.\n");
 		printf("        yosys_dump_<header_id>.il is used as filename if none is specified.\n");
 		printf("        Use 'ALL' as <header_id> to dump at every header.\n");
@@ -307,7 +311,7 @@ int main(int argc, char **argv)
 	}
 
 	int opt;
-	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:E:")) != -1)
+	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:U:E:")) != -1)
 	{
 		switch (opt)
 		{
@@ -408,6 +412,9 @@ int main(int argc, char **argv)
 					std::regex_constants::egrep));
 			break;
 		case 'D':
+			vlog_defines.push_back(optarg);
+			break;
+		case 'U':
 			{
 				auto args = split_tokens(optarg, ":");
 				if (!args.empty() && args[0] == "ALL") {
@@ -473,6 +480,13 @@ int main(int argc, char **argv)
 		shell(yosys_design);
 	}
 
+	if (!vlog_defines.empty()) {
+		std::string vdef_cmd = "read -define";
+		for (auto vdef : vlog_defines)
+			vdef_cmd += " " + vdef;
+		run_pass(vdef_cmd);
+	}
+
 	while (optind < argc)
 		run_frontend(argv[optind++], frontend_command, output_filename == "-" ? &backend_command : NULL);
 

From 0a6588569bb859d74876bf50956cb5f02cf3a31d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 15:51:59 +0100
Subject: [PATCH 397/528] Rename "yosys -U" to "yosys -P" to avoid confusion
 about "undefine"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/driver.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/kernel/driver.cc b/kernel/driver.cc
index ca8f6a7b5..a0bb7e60a 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -272,7 +272,7 @@ int main(int argc, char **argv)
 		printf("    -D <macro>[=<value>]\n");
 		printf("        set the specified Verilog define (via \"read -define\")\n");
 		printf("\n");
-		printf("    -U <header_id>[:<filename>]\n");
+		printf("    -P <header_id>[:<filename>]\n");
 		printf("        dump the design when printing the specified log header to a file.\n");
 		printf("        yosys_dump_<header_id>.il is used as filename if none is specified.\n");
 		printf("        Use 'ALL' as <header_id> to dump at every header.\n");
@@ -311,7 +311,7 @@ int main(int argc, char **argv)
 	}
 
 	int opt;
-	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:U:E:")) != -1)
+	while ((opt = getopt(argc, argv, "MXAQTVSm:f:Hh:b:o:p:l:L:qv:tds:c:W:w:e:D:P:E:")) != -1)
 	{
 		switch (opt)
 		{
@@ -414,7 +414,7 @@ int main(int argc, char **argv)
 		case 'D':
 			vlog_defines.push_back(optarg);
 			break;
-		case 'U':
+		case 'P':
 			{
 				auto args = split_tokens(optarg, ":");
 				if (!args.empty() && args[0] == "ALL") {

From 28fba903c595710c401a6c7d49e7bfd3f8c64efc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 17:36:51 +0100
Subject: [PATCH 398/528] Fix segfault in printing of some internal error
 messages

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index e66625228..bdc34d490 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -792,7 +792,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 	// everything should have been handled above -> print error if not.
 	default:
 		for (auto f : log_files)
-			current_ast->dumpAst(f, "verilog-ast> ");
+			current_ast_mod->dumpAst(f, "verilog-ast> ");
 		log_file_error(filename, linenum, "Don't know how to detect sign and width for %s node!\n", type2str(type).c_str());
 	}
 
@@ -1565,7 +1565,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// everything should have been handled above -> print error if not.
 	default:
 		for (auto f : log_files)
-			current_ast->dumpAst(f, "verilog-ast> ");
+			current_ast_mod->dumpAst(f, "verilog-ast> ");
 		type_name = type2str(type);
 		log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());
 	}

From 974927adcf916fc953ae4b756fd1806cfa423655 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 17:55:33 +0100
Subject: [PATCH 399/528] Fix handling of expression width in $past, fixes #810

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 83714f897..6ae62ead8 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1778,7 +1778,7 @@ skip_dynamic_range_lvalue_expansion:;
 
 			if (str == "\\$past")
 			{
-				if (width_hint <= 0)
+				if (width_hint < 0)
 					goto replace_fcall_later;
 
 				int num_steps = 1;

From 8e789da74c6702ededc668e3dbd899de8d0c2821 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Thu, 21 Feb 2019 09:22:29 -0800
Subject: [PATCH 400/528] Revert "Add -B option to autotest.sh to append to
 backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
---
 tests/tools/autotest.sh | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 6fdd1e80a..218edf931 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -28,7 +28,7 @@ if [ ! -f $toolsdir/cmp_tbdata -o $toolsdir/cmp_tbdata.c -nt $toolsdir/cmp_tbdat
 	( set -ex; ${CC:-gcc} -Wall -o $toolsdir/cmp_tbdata $toolsdir/cmp_tbdata.c; ) || exit 1
 fi
 
-while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
+while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 	case "$opt" in
 		x)
 			use_xsim=true ;;
@@ -65,8 +65,6 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
 			include_opts="$include_opts -I $OPTARG"
 			xinclude_opts="$xinclude_opts -i $OPTARG"
 			minclude_opts="$minclude_opts +incdir+$OPTARG" ;;
-        B)
-			backend_opts="$backend_opts $OPTARG" ;;
 		-)
 			case "${OPTARG}" in
 			    xfirrtl)
@@ -84,7 +82,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:B:-: opt; do
 				;;
 			esac;;
 		*)
-			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [-B backend_opt] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
+			echo "Usage: $0 [-x|-m] [-G] [-w] [-k] [-j] [-v] [-r] [-e] [-l libs] [-f frontend] [-s script] [-p cmdstring] [-n iters] [-S seed] [-I incdir] [--xfirrtl FIRRTL test exclude file] [--firrtl2verilog command to generate verilog from firrtl] verilog-files\n" >&2
 			exit 1
 	esac
 done

From 23148ffae14318bb34cb311eb13494e25ebf4593 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 18:40:11 +0100
Subject: [PATCH 401/528] Fixes related to handling of autowires and
 upto-ranges, fixes #814

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc |  4 ++--
 frontends/ast/simplify.cc | 17 ++++++++++-------
 2 files changed, 12 insertions(+), 9 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index bdc34d490..2d591b29d 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -644,7 +644,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 				while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
 					log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
-				this_width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
+				this_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
 				delete left_at_zero_ast;
 				delete right_at_zero_ast;
 			} else
@@ -1034,7 +1034,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 					while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 					if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
 						log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
-					int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
+					int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
 					AstNode *fake_ast = new AstNode(AST_NONE, clone(), children[0]->children.size() >= 2 ?
 							children[0]->children[1]->clone() : children[0]->children[0]->clone());
 					fake_ast->children[0]->delete_children();
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 6ae62ead8..737fb300c 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -934,12 +934,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			}
 		}
 		if (current_scope.count(str) == 0) {
-			// log_warning("Creating auto-wire `%s' in module `%s'.\n", str.c_str(), current_ast_mod->str.c_str());
-			AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
-			auto_wire->str = str;
-			current_ast_mod->children.push_back(auto_wire);
-			current_scope[str] = auto_wire;
-			did_something = true;
+			if (flag_autowire) {
+				AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
+				auto_wire->str = str;
+				current_ast_mod->children.push_back(auto_wire);
+				current_scope[str] = auto_wire;
+				did_something = true;
+			} else {
+				log_file_error(filename, linenum, "Identifier `%s' is implicitly declared and `default_nettype is set to none.\n", str.c_str());
+			}
 		}
 		if (id2ast != current_scope[str]) {
 			id2ast = current_scope[str];
@@ -1689,7 +1692,7 @@ skip_dynamic_range_lvalue_expansion:;
 				while (right_at_zero_ast->simplify(true, true, false, 1, -1, false, false)) { }
 				if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
 					log_file_error(filename, linenum, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
-				int width = left_at_zero_ast->integer - right_at_zero_ast->integer + 1;
+				int width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
 
 				assign_data = new AstNode(AST_ASSIGN_LE, new AstNode(AST_IDENTIFIER),
 						new AstNode(AST_SHIFT_LEFT, children[1]->clone(), offset_ast->clone()));

From 893194689daee52ea870fef839c237c61e14c6c9 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 18:50:02 +0100
Subject: [PATCH 402/528] Fix typo in passes/pmgen/README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index 27e54b43e..a1007dc62 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -65,7 +65,7 @@ list of variable names. For example:
 State variables are automatically managed by the generated backtracking algorithm
 and saved and restored as needed.
 
-They are atomatically initialzed to the default constructed value of their type
+They are automatically initialized to the default constructed value of their type
 when `.run(callback_function)` is called.
 
 Declaring udata variables

From 4c82ddf39412fa7f90d71f259d578f98e732c865 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Thu, 21 Feb 2019 10:16:38 -0800
Subject: [PATCH 403/528] Add -params mode to force undef parameters in
 selected cells.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 passes/cmds/setundef.cc | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 56ef2d125..aea3165e4 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -143,6 +143,9 @@ struct SetundefPass : public Pass {
 		log("    -init\n");
 		log("        also create/update init values for flip-flops\n");
 		log("\n");
+		log("    -params\n");
+		log("        replace undef in cell parameters\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -150,6 +153,7 @@ struct SetundefPass : public Pass {
 		bool undriven_mode = false;
 		bool expose_mode = false;
 		bool init_mode = false;
+		bool params_mode = false;
 		SetundefWorker worker;
 
 		log_header(design, "Executing SETUNDEF pass (replace undef values with defined constants).\n");
@@ -199,6 +203,10 @@ struct SetundefPass : public Pass {
 				init_mode = true;
 				continue;
 			}
+			if (args[argidx] == "-params") {
+				params_mode = true;
+				continue;
+			}
 			if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) {
 				got_value = true;
 				worker.next_bit_mode = MODE_RANDOM;
@@ -228,6 +236,27 @@ struct SetundefPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
+			if (params_mode)
+			{
+				for (auto *cell : module->cells())
+				{
+					// Only modify selected cells.
+					if (!design->selected(module, it)) {
+						continue;
+					}
+
+					for (auto &parameter : cell->parameters)
+					{
+						for (auto &bit : parameter.second.bits) {
+							if (bit > RTLIL::State::S1)
+							{
+								bit = worker.next_bit();
+							}
+						}
+					}
+				}
+			}
+
 			if (undriven_mode)
 			{
 				if (!module->processes.empty())

From d55790909c3b4244889d092c8eae630c7efd1aee Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 19:27:23 +0100
Subject: [PATCH 404/528] Hotfix for 4c82ddf

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/cmds/setundef.cc | 13 ++-----------
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index aea3165e4..f6949c820 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -238,20 +238,11 @@ struct SetundefPass : public Pass {
 		{
 			if (params_mode)
 			{
-				for (auto *cell : module->cells())
-				{
-					// Only modify selected cells.
-					if (!design->selected(module, it)) {
-						continue;
-					}
-
-					for (auto &parameter : cell->parameters)
-					{
+				for (auto *cell : module->selected_cells()) {
+					for (auto &parameter : cell->parameters) {
 						for (auto &bit : parameter.second.bits) {
 							if (bit > RTLIL::State::S1)
-							{
 								bit = worker.next_bit();
-							}
 						}
 					}
 				}

From 362ef36ccdcb3023f9db259b983c08811f794edd Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Feb 2019 23:13:14 +0100
Subject: [PATCH 405/528] Fix Travis

It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .travis/build-and-test.sh |  2 ++
 .travis/setup.sh          | 49 +++++++--------------------------------
 Makefile                  |  2 +-
 3 files changed, 11 insertions(+), 42 deletions(-)

diff --git a/.travis/build-and-test.sh b/.travis/build-and-test.sh
index 096dde64f..b8c35041d 100755
--- a/.travis/build-and-test.sh
+++ b/.travis/build-and-test.sh
@@ -36,6 +36,8 @@ echo
 
 ##########################################################################
 
+./yosys tests/simple/fiedler-cooley.v
+
 echo
 echo 'Testing...' && echo -en 'travis_fold:start:script.test\\r'
 echo
diff --git a/.travis/setup.sh b/.travis/setup.sh
index d689cd2bd..4af0b8ee9 100755
--- a/.travis/setup.sh
+++ b/.travis/setup.sh
@@ -6,48 +6,15 @@ source .travis/common.sh
 
 ##########################################################################
 
-# Fixing Travis's git clone
-echo
-echo 'Fixing git setup...' && echo -en 'travis_fold:start:before_install.git\\r'
-echo
-git fetch --unshallow && git fetch --tags
-
-# For pull requests, we get more info about the git source.
-if [ z"$TRAVIS_PULL_REQUEST_SLUG" != z ]; then
-	echo "- Fetching from pull request source"
-	git remote add source https://github.com/$TRAVIS_PULL_REQUEST_SLUG.git
-	git fetch source && git fetch --tags
-
-	echo "- Fetching the actual pull request"
-	git fetch origin pull/$TRAVIS_PULL_REQUEST/head:pull-$TRAVIS_PULL_REQUEST-head
-	git fetch origin pull/$TRAVIS_PULL_REQUEST/merge:pull-$TRAVIS_PULL_REQUEST-merge
-
-	git log -n 5 --graph pull-$TRAVIS_PULL_REQUEST-merge
-fi
-
-# For building branches we need to fix the "detached head" state.
-if [ z"$TRAVIS_BRANCH" != z ]; then
-	TRAVIS_COMMIT_ACTUAL=$(git log --pretty=format:'%H' -n 1)
-	echo "- Fixing detached head (current $TRAVIS_COMMIT_ACTUAL -> $TRAVIS_COMMIT)"
-	git remote -v
-	git branch -v
-	if [ x"$(git show-ref -s HEAD)" = x"$TRAVIS_COMMIT" ]; then
-		echo "Checked out at $TRAVIS_COMMIT"
-	else
-		if [ z"$TRAVIS_PULL_REQUEST_SLUG" != z ]; then
-			git fetch source $TRAVIS_COMMIT || echo "Unable to fetch $TRAVIS_COMMIT from source"
-		fi
-		git fetch origin $TRAVIS_COMMIT || echo "Unable to fetch $TRAVIS_COMMIT from origin"
-	fi
-	git branch -D $TRAVIS_BRANCH || true
-	git checkout $TRAVIS_COMMIT -b $TRAVIS_BRANCH
-	git branch -v
-fi
-
 # Output status information.
-git status
-git describe --tags
-git log -n 5 --graph
+(
+	set +e
+	set -x
+	git status
+	git branch -v
+	git log -n 5 --graph
+	git log --format=oneline -n 20 --graph
+)
 echo
 echo -en 'travis_fold:end:before_install.git\\r'
 echo
diff --git a/Makefile b/Makefile
index d83a71256..8e93cd285 100644
--- a/Makefile
+++ b/Makefile
@@ -100,7 +100,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. | wc -l; })
+YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; })
 GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

From 25680f6a078bb32f157bd580705656496717bafb Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 22 Feb 2019 10:28:28 -0800
Subject: [PATCH 406/528] Fix WREDUCE on FF not fixing ARST_VALUE parameter.

Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 passes/opt/wreduce.cc | 13 +++++++++++++
 tests/opt/opt_ff.v    | 21 +++++++++++++++++++++
 tests/opt/opt_ff.ys   |  3 +++
 3 files changed, 37 insertions(+)
 create mode 100644 tests/opt/opt_ff.v
 create mode 100644 tests/opt/opt_ff.ys

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 3aa916ec2..c550b402e 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -195,6 +195,19 @@ struct WreduceWorker
 		for (auto bit : sig_q)
 			work_queue_bits.insert(bit);
 
+		// Narrow ARST_VALUE parameter to new size.
+		//
+		// Note: This works because earlier loop only removes signals from
+		// the upper bits of the DFF.
+		if(cell->parameters.count("\\ARST_VALUE") > 0) {
+			RTLIL::Const old_arst_value = cell->parameters.at("\\ARST_VALUE");
+			std::vector<RTLIL::State> new_arst_value(GetSize(sig_q));
+			for(int i = 0; i < GetSize(sig_q); ++i) {
+				new_arst_value[i] = old_arst_value[i];
+			}
+			cell->parameters["\\ARST_VALUE"] = RTLIL::Const(new_arst_value);
+		}
+
 		cell->setPort("\\D", sig_d);
 		cell->setPort("\\Q", sig_q);
 		cell->fixup_parameters();
diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v
new file mode 100644
index 000000000..a01b64b61
--- /dev/null
+++ b/tests/opt/opt_ff.v
@@ -0,0 +1,21 @@
+module top(
+    input clk,
+    input rst,
+    input [2:0] a,
+    output [1:0] b
+);
+    reg [2:0] b_reg;
+    initial begin
+        b_reg <= 3'b0;
+    end
+
+    assign b = b_reg[1:0];
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+            b_reg <= 3'b0;
+        end else begin
+            b_reg <= a;
+        end
+    end
+endmodule
+
diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys
new file mode 100644
index 000000000..704c7acf3
--- /dev/null
+++ b/tests/opt/opt_ff.ys
@@ -0,0 +1,3 @@
+read_verilog opt_ff.v
+synth_ice40
+ice40_unlut

From 71bcc4c644b0dafa760ff8b6d7bd1109836be621 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Fri, 22 Feb 2019 16:06:10 -0800
Subject: [PATCH 407/528] Address requested changes - don't require non-$ name.
 Suppress warning if name does begin with a `$`. Fix hierachy tests so they
 have something to grep. Announce hierarchy test types.

---
 passes/hierarchy/hierarchy.cc | 14 +++++++-------
 tests/various/hierarchy.sh    |  9 ++++++---
 tests/various/run-test.sh     |  2 +-
 3 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index f112e969e..cb54ffa58 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -525,14 +525,14 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 				celltype = basic_cell_type(celltype);
 			}
 			// Is this cell a module instance?
-			if (celltype[0] != '$') {
-				auto instModule = design->module(celltype);
-				// If there is no instance for this, issue a warning.
-				if (instModule == NULL) {
+			auto instModule = design->module(celltype);
+			// If there is no instance for this, issue a warning.
+			if (instModule == NULL) {
+				//  but only if we're sure it is a reference to a module.
+				if (celltype[0] != '$')
 					log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
-				} else {
-					score = max(score, find_top_mod_score(design, instModule, db) + 1);
-				}
+			} else {
+				score = max(score, find_top_mod_score(design, instModule, db) + 1);
 			}
 		}
 		db[module] = score;
diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh
index dcb4dc056..d33a247be 100644
--- a/tests/various/hierarchy.sh
+++ b/tests/various/hierarchy.sh
@@ -3,7 +3,8 @@
 
 set -e
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n "  TOP first - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module TOP(a, y);
       input a;
@@ -21,7 +22,8 @@ set -e
   hierarchy -auto-top
 EOY
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected TOP as design top module"
+echo -n "  TOP last - "
+../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module"
   read_verilog << EOV
     module aoi12(a, y);
       input a;
@@ -39,7 +41,8 @@ EOY
   hierarchy -auto-top
 EOY
 
-../../yosys -q -s - <<- EOY 2>&1 | grep "Automatically selected noTop as design top module."
+echo -n "  no explicit top - "
+../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module."
   read_verilog << EOV
     module aoi12(a, y);
       input a;
diff --git a/tests/various/run-test.sh b/tests/various/run-test.sh
index 7cd1a8650..d49553ede 100755
--- a/tests/various/run-test.sh
+++ b/tests/various/run-test.sh
@@ -9,6 +9,6 @@ shell_tests=$(echo *.sh | sed -e 's/run-test.sh//')
 if [ "$shell_tests" ]; then
     for s in $shell_tests; do
         echo "Running $s.."
-        bash $s >& ${s%.sh}.log
+        bash $s
     done
 fi

From a516b4fb5af0d8389fa8aede95ae5a76bec13dcf Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Feb 2019 19:51:30 +0100
Subject: [PATCH 408/528] Check if Verific was built with
 DB_PRESERVE_INITIAL_VALUE

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 94138cdd6..8ee951d20 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1920,6 +1920,10 @@ struct VerificPass : public Pass {
 			// WARNING: instantiating unknown module 'XYZ' (VERI-1063)
 			Message::SetMessageType("VERI-1063", VERIFIC_ERROR);
 
+#ifndef DB_PRESERVE_INITIAL_VALUE
+#  warning Verific was built without DB_PRESERVE_INITIAL_VALUE.
+#endif
+
 			set_verific_global_flags = false;
 		}
 

From 1816fe06af9ab2c50bd293dc10359238acc88f12 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Feb 2019 20:09:41 +0100
Subject: [PATCH 409/528] Fix handling of defparam for when default_nettype is
 none

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc   | 4 ++++
 tests/simple/hierdefparam.v | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 737fb300c..46013544b 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -642,6 +642,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	// (iterate by index as e.g. auto wires can add new children in the process)
 	for (size_t i = 0; i < children.size(); i++) {
 		bool did_something_here = true;
+		bool backup_flag_autowire = flag_autowire;
 		if ((type == AST_GENFOR || type == AST_FOR) && i >= 3)
 			break;
 		if ((type == AST_GENIF || type == AST_GENCASE) && i >= 1)
@@ -652,6 +653,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			break;
 		if (type == AST_PREFIX && i >= 1)
 			break;
+		if (type == AST_DEFPARAM && i == 0)
+			flag_autowire = true;
 		while (did_something_here && i < children.size()) {
 			bool const_fold_here = const_fold, in_lvalue_here = in_lvalue;
 			int width_hint_here = width_hint;
@@ -686,6 +689,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			children.erase(children.begin() + (i--));
 			did_something = true;
 		}
+		flag_autowire = backup_flag_autowire;
 	}
 	for (auto &attr : attributes) {
 		while (attr.second->simplify(true, false, false, stage, -1, false, true))
diff --git a/tests/simple/hierdefparam.v b/tests/simple/hierdefparam.v
index ff92c38bd..c9368ca7a 100644
--- a/tests/simple/hierdefparam.v
+++ b/tests/simple/hierdefparam.v
@@ -1,3 +1,5 @@
+`default_nettype none
+
 module hierdefparam_top(input [7:0] A, output [7:0] Y);
   generate begin:foo
     hierdefparam_a mod_a(.A(A), .Y(Y));

From cd722f26a5437e145c02c49b5736bd03b13927da Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Feb 2019 20:34:23 +0100
Subject: [PATCH 410/528] Cleanups in ARST handling in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/wreduce.cc | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index c550b402e..09983bc67 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -196,16 +196,10 @@ struct WreduceWorker
 			work_queue_bits.insert(bit);
 
 		// Narrow ARST_VALUE parameter to new size.
-		//
-		// Note: This works because earlier loop only removes signals from
-		// the upper bits of the DFF.
-		if(cell->parameters.count("\\ARST_VALUE") > 0) {
-			RTLIL::Const old_arst_value = cell->parameters.at("\\ARST_VALUE");
-			std::vector<RTLIL::State> new_arst_value(GetSize(sig_q));
-			for(int i = 0; i < GetSize(sig_q); ++i) {
-				new_arst_value[i] = old_arst_value[i];
-			}
-			cell->parameters["\\ARST_VALUE"] = RTLIL::Const(new_arst_value);
+		if (cell->parameters.count("\\ARST_VALUE")) {
+			Const arst_value = cell->getParam("\\ARST_VALUE");
+			arst_value.bits.resize(GetSize(sig_q));
+			cell->setParam("\\ARST_VALUE", arst_value);
 		}
 
 		cell->setPort("\\D", sig_d);

From c258b99040c8414952a3aceae874dc47563540dc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Feb 2019 20:41:36 +0100
Subject: [PATCH 411/528] Minor changes ontop of 71bcc4c: Remove hierarchy
 warning that is redundant to -check

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/hierarchy/hierarchy.cc | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index cb54ffa58..2d8edebb5 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -527,11 +527,7 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
 			// Is this cell a module instance?
 			auto instModule = design->module(celltype);
 			// If there is no instance for this, issue a warning.
-			if (instModule == NULL) {
-				//  but only if we're sure it is a reference to a module.
-				if (celltype[0] != '$')
-					log_warning("find_top_mod_score: no instance for %s.%s\n", celltype.c_str(), cell->name.c_str());
-			} else {
+			if (instModule != nullptr) {
 				score = max(score, find_top_mod_score(design, instModule, db) + 1);
 			}
 		}

From fa2f595cfa240b86edb26e859449c1c54eaf49ef Mon Sep 17 00:00:00 2001
From: David Shah <davey1576@gmail.com>
Date: Tue, 19 Feb 2019 19:35:10 +0000
Subject: [PATCH 412/528] ecp5: Compatibility with Migen AsyncResetSynchronizer

Signed-off-by: David Shah <davey1576@gmail.com>
---
 techlibs/ecp5/cells_map.v |  3 +++
 techlibs/ecp5/cells_sim.v | 17 +++++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/techlibs/ecp5/cells_map.v b/techlibs/ecp5/cells_map.v
index 23182bdeb..6ab4b69f2 100644
--- a/techlibs/ecp5/cells_map.v
+++ b/techlibs/ecp5/cells_map.v
@@ -47,6 +47,9 @@ module  \$__DFFSE_NP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"
 module  \$__DFFSE_PP0 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 module  \$__DFFSE_PP1 (input D, C, E, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C), .CE(E), .LSR(R), .DI(D), .Q(Q)); endmodule
 
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC"))  _TECHMAP_REPLACE_ (.CLK(CK), .LSR(PD), .DI(D), .Q(Q)); endmodule
+
 `ifndef NO_LUT
 module \$lut (A, Y);
     parameter WIDTH = 0;
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index ca5d020f3..d2d8b5793 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -556,3 +556,20 @@ module DP16KD(
   parameter INITVAL_3E = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
   parameter INITVAL_3F = 320'h00000000000000000000000000000000000000000000000000000000000000000000000000000000;
 endmodule
+
+// For Diamond compatibility, FIXME: add all Diamond flipflop mappings
+module FD1S3BX(input PD, D, CK, output Q);
+	TRELLIS_FF #(
+		.GSR("DISABLED"),
+		.CEMUX("1"),
+		.CLKMUX("CLK"),
+		.LSRMUX("LSR"),
+		.REGSET("SET"),
+		.SRMODE("ASYNC")
+	) tff_i (
+		.CLK(CK),
+		.LSR(PD),
+		.DI(D),
+		.Q(Q)
+	);
+endmodule

From 171c425cf9addb61ef3f03596fd26355ed8af76d Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Mon, 25 Feb 2019 16:18:13 -0800
Subject: [PATCH 413/528] Fix FIRRTL to Verilog process instance subfield
 assignment. Don't emit subfield assignments: bits(x, y, z) <= ... - but
 instead, add them to the reverse-wire-map where they'll be treated at the end
 of the module. Enable tests which were disabled due to incorrect treatment of
 subfields. Assume the `$firrtl2verilog` variable contains any additional
 switches to control verilog generation (i.e. `--no-dedup -X mverilog`)

---
 backends/firrtl/firrtl.cc | 28 ++++++++++++++++++++--------
 tests/asicworld/xfirrtl   |  1 -
 tests/simple/xfirrtl      |  1 -
 tests/tools/autotest.sh   |  2 +-
 4 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 0917ecba6..88c1038b7 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -169,7 +169,6 @@ struct FirrtlWorker
 		return *str == '\\' ? str + 1 : str;
 	}
 
-
 	std::string cellname(RTLIL::Cell *cell)
 	{
 		return fid(cell->name).c_str();
@@ -219,29 +218,42 @@ struct FirrtlWorker
 			if (it->second.size() > 0) {
 				const SigSpec &secondSig = it->second;
 				const std::string firstName = cell_name + "." + make_id(it->first);
-				const std::string secondName = make_expr(secondSig);
+				const std::string secondExpr = make_expr(secondSig);
 				// Find the direction for this port.
 				FDirection dir = getPortFDirection(it->first, instModule);
-				std::string source, sink;
+				std::string sourceExpr, sinkExpr;
+				const SigSpec *sinkSig = nullptr;
 				switch (dir) {
 					case FD_INOUT:
 						log_warning("Instance port connection %s.%s is INOUT; treating as OUT\n", cell_type.c_str(), log_signal(it->second));
 					case FD_OUT:
-						source = firstName;
-						sink = secondName;
+						sourceExpr = firstName;
+						sinkExpr = secondExpr;
+						sinkSig = &secondSig;
 						break;
 					case FD_NODIRECTION:
 						log_warning("Instance port connection %s.%s is NODIRECTION; treating as IN\n", cell_type.c_str(), log_signal(it->second));
 						/* FALL_THROUGH */
 					case FD_IN:
-						source = secondName;
-						sink = firstName;
+						sourceExpr = secondExpr;
+						sinkExpr = firstName;
 						break;
 					default:
 						log_error("Instance port %s.%s unrecognized connection direction 0x%x !\n", cell_type.c_str(), log_signal(it->second), dir);
 						break;
 				}
-				wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sink.c_str(), source.c_str()));
+				// Check for subfield assignment.
+				std::string bitsString = "bits(";
+				if (sinkExpr.substr(0, bitsString.length()) == bitsString ) {
+					if (sinkSig == nullptr)
+						log_error("Unknown subfield %s.%s\n", cell_type.c_str(), sinkExpr.c_str());
+					// Don't generate the assignment here.
+					// Add the source and sink to the "reverse_wire_map" and we'll output the assignment
+					//  as part of the coalesced subfield assignments for this wire.
+					register_reverse_wire_map(sourceExpr, *sinkSig);
+				} else {
+					wire_exprs.push_back(stringf("\n%s%s <= %s", indent.c_str(), sinkExpr.c_str(), sourceExpr.c_str()));
+				}
 			}
 		}
 		wire_exprs.push_back(stringf("\n"));
diff --git a/tests/asicworld/xfirrtl b/tests/asicworld/xfirrtl
index c782a2bd6..08bf4ccd8 100644
--- a/tests/asicworld/xfirrtl
+++ b/tests/asicworld/xfirrtl
@@ -6,7 +6,6 @@ code_hdl_models_d_latch_gates.v	combinational loop
 code_hdl_models_dff_async_reset.v	$adff
 code_hdl_models_tff_async_reset.v	$adff
 code_hdl_models_uart.v	$adff
-code_specman_switch_fabric.v	subfield assignment (bits() <= ...)
 code_tidbits_asyn_reset.v	$adff
 code_tidbits_reg_seq_example.v	$adff
 code_verilog_tutorial_always_example.v	empty module
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
index 00e89b389..5bc75347b 100644
--- a/tests/simple/xfirrtl
+++ b/tests/simple/xfirrtl
@@ -12,7 +12,6 @@ multiplier.v	inst id[0] of
 muxtree.v	drops modules
 omsp_dbg_uart.v	$adff
 operators.v	$pow
-paramods.v	subfield assignment (bits() <= ...)
 partsel.v	drops modules
 process.v	drops modules
 realexpr.v	drops modules
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 218edf931..99ec3e7cd 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -175,7 +175,7 @@ do
 			if [ -n "$firrtl2verilog" ]; then
 			    if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
 				"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
-				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v  -X verilog
+				$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
 				test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
 			    fi
 			fi

From 61fc411c5d7237e420ee6eb9f6eb093e70d1007d Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Sun, 24 Feb 2019 22:08:52 -0800
Subject: [PATCH 414/528] Clean up some whitepsace outliers

---
 passes/techmap/dfflibmap.cc | 4 ++--
 passes/techmap/flowmap.cc   | 4 ++--
 techlibs/ecp5/cells_sim.v   | 4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index b0528d473..274177a68 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -660,8 +660,8 @@ struct DfflibmapPass : public Pass {
 		map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_");
 		map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_");
 
- 		log("  final dff cell mappings:\n");
- 		logmap_all();
+		log("  final dff cell mappings:\n");
+		logmap_all();
 
 		for (auto &it : design->modules_)
 			if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc
index ddbd7bf5d..0b7931e48 100644
--- a/passes/techmap/flowmap.cc
+++ b/passes/techmap/flowmap.cc
@@ -132,9 +132,9 @@ static void dump_dot_graph(string filename,
                            pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges,
                            pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs,
                            std::function<GraphStyle(RTLIL::SigBit)> node_style =
-                           		[](RTLIL::SigBit) { return GraphStyle{}; },
+                                   [](RTLIL::SigBit) { return GraphStyle{}; },
                            std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style =
-                           		[](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
+                                   [](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
                            string name = "")
 {
 	FILE *f = fopen(filename.c_str(), "w");
diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 507ab1beb..f27540bd7 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -57,7 +57,7 @@ module TRELLIS_RAM16X2 (
 	input RAD0, RAD1, RAD2, RAD3,
 	output DO0, DO1
 );
-  	parameter WCKMUX = "WCK";
+	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter INITVAL_0 = 16'h0000;
 	parameter INITVAL_1 = 16'h0000;
@@ -104,7 +104,7 @@ module TRELLIS_DPR16X4 (
 	input [3:0] RAD,
 	output [3:0] DO
 );
-  	parameter WCKMUX = "WCK";
+	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";
 	parameter [63:0] INITVAL = 64'h0000000000000000;
 

From 7a40294e93490fa462343244b1e2881c3c249c3f Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Sun, 24 Feb 2019 22:09:54 -0800
Subject: [PATCH 415/528] techlibs/greenpak4/cells_map.v: Harmonize whitespace
 within lut module

---
 techlibs/greenpak4/cells_map.v | 44 +++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v
index b971a51fa..51c85183d 100644
--- a/techlibs/greenpak4/cells_map.v
+++ b/techlibs/greenpak4/cells_map.v
@@ -112,14 +112,14 @@ module GP_OBUFT(input IN, input OE, output OUT);
 endmodule
 
 module \$lut (A, Y);
-  parameter WIDTH = 0;
-  parameter LUT = 0;
+	parameter WIDTH = 0;
+	parameter LUT = 0;
 
-  input [WIDTH-1:0] A;
-  output Y;
+	input [WIDTH-1:0] A;
+	output Y;
 
-  generate
-    if (WIDTH == 1) begin
+	generate
+		if (WIDTH == 1) begin
 		if(LUT == 2'b01) begin
 			GP_INV _TECHMAP_REPLACE_ (.OUT(Y), .IN(A[0]) );
 		end
@@ -127,22 +127,22 @@ module \$lut (A, Y);
 			GP_2LUT #(.INIT({2'b00, LUT})) _TECHMAP_REPLACE_ (.OUT(Y),
 				.IN0(A[0]), .IN1(1'b0));
 		end
-    end else
-    if (WIDTH == 2) begin
-      GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
-      	.IN0(A[0]), .IN1(A[1]));
-    end else
-    if (WIDTH == 3) begin
-      GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
-      	.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
-    end else
-    if (WIDTH == 4) begin
-      GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
-      	.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
-    end else begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-  endgenerate
+		end else
+		if (WIDTH == 2) begin
+			GP_2LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+				.IN0(A[0]), .IN1(A[1]));
+		end else
+		if (WIDTH == 3) begin
+			GP_3LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+				.IN0(A[0]), .IN1(A[1]), .IN2(A[2]));
+		end else
+		if (WIDTH == 4) begin
+			GP_4LUT #(.INIT(LUT)) _TECHMAP_REPLACE_ (.OUT(Y),
+				.IN0(A[0]), .IN1(A[1]), .IN2(A[2]), .IN3(A[3]));
+		end else begin
+			wire _TECHMAP_FAIL_ = 1;
+		end
+	endgenerate
 endmodule
 
 module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);

From a58dbcf2bae38835cdc2964718d4562ae4be4cc5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Feb 2019 11:37:08 -0800
Subject: [PATCH 416/528] Add "supercover" skeleton

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/Makefile.inc  |  1 +
 passes/sat/supercover.cc | 76 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 77 insertions(+)
 create mode 100644 passes/sat/supercover.cc

diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc
index 8ab0280c0..6cb1ea644 100644
--- a/passes/sat/Makefile.inc
+++ b/passes/sat/Makefile.inc
@@ -8,4 +8,5 @@ OBJS += passes/sat/expose.o
 OBJS += passes/sat/assertpmux.o
 OBJS += passes/sat/clk2fflogic.o
 OBJS += passes/sat/async2sync.o
+OBJS += passes/sat/supercover.o
 
diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc
new file mode 100644
index 000000000..9b208b0bf
--- /dev/null
+++ b/passes/sat/supercover.cc
@@ -0,0 +1,76 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct SupercoverPass : public Pass {
+	SupercoverPass() : Pass("supercover", "add hi/lo cover cells for each wire bit") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    supercover [options] [selection]\n");
+		log("\n");
+		log("This command adds two cover cells for each bit of each selected wire, one\n");
+		log("checking for a hi signal level and one checking for lo level.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		// bool flag_noinit = false;
+
+		log_header(design, "Executing SUPERCOVER pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-noinit") {
+			// 	flag_noinit = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			int cnt_wire = 0, cnt_bits = 0;
+			log("Adding cover cells to module %s.\n", log_id(module));
+			for (auto wire : module->selected_wires())
+			{
+				std::string src = wire->get_src_attribute();
+				cnt_wire++;
+				for (auto bit : SigSpec(wire))
+				{
+					SigSpec inv = module->Not(NEW_ID, bit);
+					module->addCover(NEW_ID, bit, State::S1, src);
+					module->addCover(NEW_ID, inv, State::S1, src);
+					cnt_bits++;
+				}
+			}
+			log("  added cover cells to %d wires, %d bits.\n", cnt_wire, cnt_bits);
+		}
+	}
+} SupercoverPass;
+
+PRIVATE_NAMESPACE_END

From 63be3f3bab9293cf5b8f7416fce13cdeaa030727 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Feb 2019 11:45:13 -0800
Subject: [PATCH 417/528] Improvements in "supercover" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/supercover.cc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/passes/sat/supercover.cc b/passes/sat/supercover.cc
index 9b208b0bf..ba44f02d8 100644
--- a/passes/sat/supercover.cc
+++ b/passes/sat/supercover.cc
@@ -54,17 +54,33 @@ struct SupercoverPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
+			SigMap sigmap(module);
+			pool<SigBit> handled_bits;
+
 			int cnt_wire = 0, cnt_bits = 0;
 			log("Adding cover cells to module %s.\n", log_id(module));
 			for (auto wire : module->selected_wires())
 			{
+				bool counted_wire = false;
 				std::string src = wire->get_src_attribute();
-				cnt_wire++;
-				for (auto bit : SigSpec(wire))
+
+				for (auto bit : sigmap(SigSpec(wire)))
 				{
+					if (bit.wire == nullptr)
+						continue;
+
+					if (handled_bits.count(bit))
+						continue;
+
 					SigSpec inv = module->Not(NEW_ID, bit);
 					module->addCover(NEW_ID, bit, State::S1, src);
 					module->addCover(NEW_ID, inv, State::S1, src);
+
+					handled_bits.insert(bit);
+					if (!counted_wire) {
+						counted_wire = false;
+						cnt_wire++;
+					}
 					cnt_bits++;
 				}
 			}

From f570aa5e1d3ac201089da2198f8e5084185fd92f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 12:15:58 -0800
Subject: [PATCH 418/528] Fix smt2 code generation for partially initialized
 memowy words, fixes #831

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smt2.cc | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 418f8d766..7f3cc94ca 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -1103,20 +1103,27 @@ struct Smt2Worker
 							break;
 
 						Const initword = init_data.extract(i*width, width, State::Sx);
+						Const initmask = initword;
 						bool gen_init_constr = false;
 
-						for (auto bit : initword.bits)
-							if (bit == State::S0 || bit == State::S1)
+						for (int k = 0; k < GetSize(initword); k++) {
+							if (initword[k] == State::S0 || initword[k] == State::S1) {
 								gen_init_constr = true;
+								initmask[k] = State::S1;
+							} else {
+								initmask[k] = State::S0;
+								initword[k] = State::S0;
+							}
+						}
 
 						if (gen_init_constr)
 						{
 							if (statebv)
 								/* FIXME */;
 							else
-								init_list.push_back(stringf("(= (select (|%s#%d#0| state) #b%s) #b%s) ; %s[%d]",
+								init_list.push_back(stringf("(= (bvand (select (|%s#%d#0| state) #b%s) #b%s) #b%s) ; %s[%d]",
 										get_id(module), arrayid, Const(i, abits).as_string().c_str(),
-										initword.as_string().c_str(), get_id(cell), i));
+										initmask.as_string().c_str(), initword.as_string().c_str(), get_id(cell), i));
 						}
 					}
 				}

From 64d91219b4e81366976a0e0a9b28efa4bd825022 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 14:00:58 -0800
Subject: [PATCH 419/528] Fix pmgen for out-of-tree build

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/Makefile.inc | 4 ++--
 passes/pmgen/pmgen.py     | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index 33baaca30..b9682612b 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -4,5 +4,5 @@ passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
 EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
 .SECONDARY: passes/pmgen/ice40_dsp_pm.h
 
-passes/pmgen/ice40_dsp_pm.h: passes/pmgen/ice40_dsp.pmg passes/pmgen/pmgen.py
-	$(P) cd passes/pmgen && python3 pmgen.py ice40_dsp
+passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
+	$(P) mkdir -p passes/pmgen && cd passes/pmgen && python3 $^
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index e688a4567..166d3963a 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -6,7 +6,9 @@ import pprint
 
 pp = pprint.PrettyPrinter(indent=4)
 
-prefix = sys.argv[1]
+pmgfile = sys.argv[1]
+prefix = pmgfile.split("/")[-1]
+prefix = prefix.split(".")[0]
 
 state_types = dict()
 udata_types = dict()
@@ -73,7 +75,7 @@ def rewrite_cpp(s):
 
     return "".join(t)
 
-with open("%s.pmg" % prefix, "r") as f:
+with open(pmgfile, "r") as f:
     while True:
         line = f.readline()
         if line == "": break

From 68a693717347cefc057cbf1a1c8d0f66500dec4f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 14:56:05 -0800
Subject: [PATCH 420/528] Fix pmgen for in-tree builds

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/pmgen/Makefile.inc |  2 +-
 passes/pmgen/pmgen.py     | 15 ++++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index b9682612b..e0dd0fc06 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -5,4 +5,4 @@ EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
 .SECONDARY: passes/pmgen/ice40_dsp_pm.h
 
 passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
-	$(P) mkdir -p passes/pmgen && cd passes/pmgen && python3 $^
+	$(P) mkdir -p passes/pmgen && python3 $^
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 166d3963a..034ac27aa 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -7,8 +7,9 @@ import pprint
 pp = pprint.PrettyPrinter(indent=4)
 
 pmgfile = sys.argv[1]
-prefix = pmgfile.split("/")[-1]
-prefix = prefix.split(".")[0]
+assert pmgfile.endswith(".pmg")
+prefix = pmgfile[0:-4]
+pmname = prefix.split('/')[-1]
 
 state_types = dict()
 udata_types = dict()
@@ -189,10 +190,10 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("YOSYS_NAMESPACE_BEGIN", file=f)
     print("", file=f)
 
-    print("struct {}_pm {{".format(prefix), file=f)
+    print("struct {}_pm {{".format(pmname), file=f)
     print("  Module *module;", file=f)
     print("  SigMap sigmap;", file=f)
-    print("  std::function<void()> on_accept;".format(prefix), file=f)
+    print("  std::function<void()> on_accept;".format(pmname), file=f)
     print("", file=f)
 
     for index in range(len(blocks)):
@@ -290,7 +291,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
+    print("  {}_pm(Module *module, const vector<Cell*> &cells) :".format(pmname), file=f)
     print("      module(module), sigmap(module) {", file=f)
     for s, t in sorted(udata_types.items()):
         if t.endswith("*"):
@@ -320,7 +321,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  ~{}_pm() {{".format(prefix), file=f)
+    print("  ~{}_pm() {{".format(pmname), file=f)
     print("    for (auto cell : autoremove_cells)", file=f)
     print("      module->remove(cell);", file=f)
     print("  }", file=f)
@@ -339,7 +340,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  void run(std::function<void({}_pm&)> on_accept_f) {{".format(prefix), file=f)
+    print("  void run(std::function<void({}_pm&)> on_accept_f) {{".format(pmname), file=f)
     print("    run([&](){on_accept_f(*this);});", file=f)
     print("  }", file=f)
     print("", file=f)

From e2fc18f27b5e9f506724a486787c2106b9f7fb4f Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Tue, 26 Feb 2019 10:28:42 -0800
Subject: [PATCH 421/528] Reduce amount of trailing whitespace in code base

---
 backends/protobuf/protobuf.cc              |  6 +++---
 misc/yosys.proto                           | 12 ++++++------
 passes/pmgen/pmgen.py                      |  2 +-
 techlibs/achronix/speedster22i/cells_sim.v |  6 +++---
 techlibs/anlogic/anlogic_eqn.cc            |  4 ++--
 techlibs/gowin/arith_map.v                 | 12 ++++++------
 techlibs/gowin/synth_gowin.cc              |  2 +-
 techlibs/intel/cycloneive/arith_map.v      | 10 +++++-----
 techlibs/intel/cyclonev/cells_map.v        |  4 ++--
 9 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/backends/protobuf/protobuf.cc b/backends/protobuf/protobuf.cc
index f56147cef..549fc73ae 100644
--- a/backends/protobuf/protobuf.cc
+++ b/backends/protobuf/protobuf.cc
@@ -48,7 +48,7 @@ struct ProtobufDesignSerializer
 
 	ProtobufDesignSerializer(bool use_selection, bool aig_mode) :
 			aig_mode_(aig_mode), use_selection_(use_selection) { }
-	
+
 	string get_name(IdString name)
 	{
 		return RTLIL::unescape_id(name);
@@ -60,7 +60,7 @@ struct ProtobufDesignSerializer
 	{
 		for (auto &param : parameters) {
 			std::string key = get_name(param.first);
-			
+
 
 			yosys::pb::Parameter pb_param;
 
@@ -207,7 +207,7 @@ struct ProtobufDesignSerializer
 			(*models)[aig.name] = pb_model;
 		}
 	}
-	
+
 	void serialize_design(yosys::pb::Design *pb, Design *design)
 	{
 		GOOGLE_PROTOBUF_VERIFY_VERSION;
diff --git a/misc/yosys.proto b/misc/yosys.proto
index 2870176cb..a583e6265 100644
--- a/misc/yosys.proto
+++ b/misc/yosys.proto
@@ -1,12 +1,12 @@
 //
 // yosys -- Yosys Open SYnthesis Suite
-// 
+//
 // Copyright (C) 2018  Serge Bazanski <q3k@symbioticeda.com>
-// 
+//
 // Permission to use, copy, modify, and/or distribute this software for any
 // purpose with or without fee is hereby granted, provided that the above
 // copyright notice and this permission notice appear in all copies.
-// 
+//
 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -73,7 +73,7 @@ message Module {
         BitVector bits = 2;
     }
     map<string, Port> port = 2;
-    
+
     // Named cells in this module.
     message Cell {
         // Set to true when the name of this cell is automatically created and
@@ -129,7 +129,7 @@ message Model {
             TYPE_FALSE = 6;
         };
         Type type = 1;
-    
+
         message Port {
             // Name of port.
             string portname = 1;
@@ -148,7 +148,7 @@ message Model {
             // Set for AND, NAND.
             Gate gate = 3;
         }
-    
+
         // Set when the node drives given output port(s).
         message OutPort {
             // Name of port.
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 034ac27aa..762d8621f 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -85,7 +85,7 @@ with open(pmgfile, "r") as f:
         cmd = line.split()
         if len(cmd) == 0 or cmd[0].startswith("//"): continue
         cmd = cmd[0]
-        
+
         if cmd == "state":
             m = re.match(r"^state\s+<(.*?)>\s+(([A-Za-z_][A-Za-z_0-9]*\s+)*[A-Za-z_][A-Za-z_0-9]*)\s*$", line)
             assert m
diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index a94dce9b1..a0c60b4be 100755
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -30,7 +30,7 @@ endmodule
 module PADOUT (output padout, input padin, input oe);
    assign padout  = padin;
    assign oe = oe;
-endmodule 
+endmodule
 
 module LUT4 (output dout,
              input  din0, din1, din2, din3);
@@ -66,14 +66,14 @@ always @(dataa_w or datab_w or datac_w or datad_w) begin
                          datac_w, datad_w);
 end
 assign dout = combout_rt & 1'b1;
-endmodule 
+endmodule
 
 module DFF (output q,
             input  d, ck);
    reg             q;
    always @(posedge ck)
      q <= d;
-   
+
 endmodule
 
 
diff --git a/techlibs/anlogic/anlogic_eqn.cc b/techlibs/anlogic/anlogic_eqn.cc
index c025c65c4..741bf04cc 100644
--- a/techlibs/anlogic/anlogic_eqn.cc
+++ b/techlibs/anlogic/anlogic_eqn.cc
@@ -52,13 +52,13 @@ struct AnlogicEqnPass : public Pass {
 						eqn += names[j];
 					else
 						eqn += std::string("~") + names[j];
-					
+
 					if (j!=(inputs-1)) eqn += "*";
 				}
 				eqn += ")+";
 			}
 		}
-		if (eqn.empty()) return Const("0");		
+		if (eqn.empty()) return Const("0");
 		eqn = eqn.substr(0, eqn.length()-1);
 		return Const(eqn);
 	}
diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v
index 25e789e4a..e15de6423 100644
--- a/techlibs/gowin/arith_map.v
+++ b/techlibs/gowin/arith_map.v
@@ -25,24 +25,24 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO);
    parameter A_WIDTH = 1;
    parameter B_WIDTH = 1;
    parameter Y_WIDTH = 1;
-   
+
    input [A_WIDTH-1:0] A;
    input [B_WIDTH-1:0] B;
    output [Y_WIDTH-1:0] X, Y;
-   
+
    input 		CI, BI;
    output [Y_WIDTH-1:0] CO;
-   
+
    wire 		_TECHMAP_FAIL_ = Y_WIDTH <= 2;
-   
+
    wire [Y_WIDTH-1:0] 	A_buf, B_buf;
    \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
    \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
-   
+
    wire [Y_WIDTH-1:0] 	AA = A_buf;
    wire [Y_WIDTH-1:0] 	BB = BI ? ~B_buf : B_buf;
    wire [Y_WIDTH-1:0] 	C = {CO, CI};
-   
+
    genvar 		i;
    generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
       ALU #(.ALU_MODE(32'b0))
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 96128a680..9a3fcdbb6 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -111,7 +111,7 @@ struct SynthGowinPass : public ScriptPass
 			if (args[argidx] == "-noflatten") {
 				flatten = false;
 				continue;
-			}			
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
diff --git a/techlibs/intel/cycloneive/arith_map.v b/techlibs/intel/cycloneive/arith_map.v
index b3a11272b..49e36aa25 100644
--- a/techlibs/intel/cycloneive/arith_map.v
+++ b/techlibs/intel/cycloneive/arith_map.v
@@ -32,7 +32,7 @@ module fa
    wire   VCC;
 
    assign VCC = 1'b1;
-   
+
    cycloneiv_lcell_comb gen_sum_0 (.combout(sum_x),
                                    .dataa(a_c),
                                    .datab(b_c),
@@ -40,7 +40,7 @@ module fa
                                    .datad(VCC));
    defparam syn__05_.lut_mask = 16'b1001011010010110;
    defparam syn__05_.sum_lutc_input = "datac";
-   
+
    cycloneiv_lcell_comb gen_cout_0 (.combout(cout_t),
                                     .dataa(cin_c),
                                     .datab(b_c),
@@ -48,11 +48,11 @@ module fa
                                     .datad(VCC));
    defparam syn__06_.lut_mask = 16'b1110000011100000;
    defparam syn__06_.sum_lutc_input = "datac";
-   
+
 endmodule // fa
 
 module f_stage();
-   
+
 endmodule // f_stage
 
 module f_end();
@@ -88,7 +88,7 @@ module _80_cycloneive_alu (A, B, CI, BI, X, Y, CO);
           .cin_c(C[0]),
           .cout_t(C0[1]),
           .sum_x(Y[0]));
-   
+
    genvar i;
    generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
       cycloneive_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
diff --git a/techlibs/intel/cyclonev/cells_map.v b/techlibs/intel/cyclonev/cells_map.v
index bd60d4e17..f8d142bc9 100644
--- a/techlibs/intel/cyclonev/cells_map.v
+++ b/techlibs/intel/cyclonev/cells_map.v
@@ -76,7 +76,7 @@ module \$lut (A, Y);
    wire              VCC;
    wire              GND;
    assign {VCC,GND} = {1'b1,1'b0};
-   
+
    generate
       if (WIDTH == 1) begin
 	 assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
@@ -151,7 +151,7 @@ module \$lut (A, Y);
                     TODO: There's not a just 7-input function on Cyclone V, see the following note:
                     **Extended LUT Mode**
                     Use extended LUT mode to implement a specific set of 7-input functions. The set must
-                    be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs. 
+                    be a 2-to-1 multiplexer fed by two arbitrary 5-input functions sharing four inputs.
                     [source](Device Interfaces and Integration Basics for Cyclone V Devices).
                   end*/
                   else

From 241901461ae02c6a41837e254088f277b8167476 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 14:56:55 -0800
Subject: [PATCH 422/528] Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc | 13 +++++++++++--
 tests/tools/autotest.sh             |  2 +-
 2 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d351a6266..6818edb7a 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -33,7 +33,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal;
+bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit;
 int auto_name_counter, auto_name_offset, auto_name_digits;
 std::map<RTLIL::IdString, int> auto_name_map;
 std::set<RTLIL::IdString> reg_wires, reg_ct;
@@ -1310,7 +1310,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		}
 	}
 
-	if (reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
+	if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) {
 		std::stringstream ss;
 		dump_reg_init(ss, cell->getPort("\\Q"));
 		if (!ss.str().empty()) {
@@ -1607,6 +1607,10 @@ struct VerilogBackend : public Backend {
 		log("        without this option all internal cells are converted to Verilog\n");
 		log("        expressions.\n");
 		log("\n");
+		log("    -siminit\n");
+		log("        add initial statements with hierarchical refs to initialize FFs when\n");
+		log("        in -noexpr mode.\n");
+		log("\n");
 		log("    -nodec\n");
 		log("        32-bit constant values are by default dumped as decimal numbers,\n");
 		log("        not bit pattern. This option deactivates this feature and instead\n");
@@ -1663,6 +1667,7 @@ struct VerilogBackend : public Backend {
 		nostr = false;
 		defparam = false;
 		decimal = false;
+		siminit = false;
 		auto_prefix = "";
 
 		bool blackboxes = false;
@@ -1739,6 +1744,10 @@ struct VerilogBackend : public Backend {
 				decimal = true;
 				continue;
 			}
+			if (arg == "-siminit") {
+				siminit = true;
+				continue;
+			}
 			if (arg == "-blackboxes") {
 				blackboxes = true;
 				continue;
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 99ec3e7cd..0b9aceacc 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -8,7 +8,7 @@ verbose=false
 keeprunning=false
 makejmode=false
 frontend="verilog"
-backend_opts="-noattr -noexpr"
+backend_opts="-noattr -noexpr -siminit"
 autotb_opts=""
 include_opts=""
 xinclude_opts=""

From cd2902ab1fec57503320e32ba5620c6487f9cb85 Mon Sep 17 00:00:00 2001
From: Elms <elms@freshred.net>
Date: Thu, 28 Feb 2019 16:22:24 -0800
Subject: [PATCH 423/528] ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>
---
 techlibs/ice40/brams_map.v | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v
index 19a61d73b..ad3bccd21 100644
--- a/techlibs/ice40/brams_map.v
+++ b/techlibs/ice40/brams_map.v
@@ -7,8 +7,8 @@ module \$__ICE40_RAM4K (
 	input  [10:0] WADDR,
 	input  [15:0] MASK, WDATA
 );
-	parameter integer READ_MODE = 0;
-	parameter integer WRITE_MODE = 0;
+	parameter [1:0] READ_MODE = 0;
+	parameter [1:0] WRITE_MODE = 0;
 	parameter [0:0] NEGCLK_R = 0;
 	parameter [0:0] NEGCLK_W = 0;
 

From e847690bda520511735680bd4cb65b416edcdc3f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 17:24:46 -0800
Subject: [PATCH 424/528] Fix multiple issues in wreduce FF handling, fixes
 #835

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/wreduce.cc | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 09983bc67..1f7222e49 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -53,6 +53,7 @@ struct WreduceWorker
 	std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
 	std::set<SigBit> work_queue_bits;
 	pool<SigBit> keep_bits;
+	dict<SigBit, State> init_bits;
 
 	WreduceWorker(WreduceConfig *config, Module *module) :
 			config(config), module(module), mi(module) { }
@@ -141,6 +142,7 @@ struct WreduceWorker
 
 		SigSpec sig_d = mi.sigmap(cell->getPort("\\D"));
 		SigSpec sig_q = mi.sigmap(cell->getPort("\\Q"));
+		Const initval;
 
 		int width_before = GetSize(sig_q);
 
@@ -150,16 +152,24 @@ struct WreduceWorker
 		bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
 		bool sign_ext = !zero_ext;
 
+		for (int i = 0; i < GetSize(sig_q); i++) {
+			SigBit bit = sig_q[i];
+			if (init_bits.count(bit))
+				initval.bits.push_back(init_bits.at(bit));
+			else
+				initval.bits.push_back(State::Sx);
+		}
+
 		for (int i = GetSize(sig_q)-1; i >= 0; i--)
 		{
-			if (zero_ext && sig_d[i] == State::S0) {
+			if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
 				module->connect(sig_q[i], State::S0);
 				sig_d.remove(i);
 				sig_q.remove(i);
 				continue;
 			}
 
-			if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1]) {
+			if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
 				module->connect(sig_q[i], sig_q[i-1]);
 				sig_d.remove(i);
 				sig_q.remove(i);
@@ -167,7 +177,7 @@ struct WreduceWorker
 			}
 
 			auto info = mi.query(sig_q[i]);
-			if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
+			if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
 				sig_d.remove(i);
 				sig_q.remove(i);
 				zero_ext = false;
@@ -183,10 +193,11 @@ struct WreduceWorker
 
 		if (GetSize(sig_q) == 0) {
 			log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
+			module->remove(cell);
 			return;
 		}
 
-		log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
+		log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width_before,
 				log_id(module), log_id(cell), log_id(cell->type));
 
 		for (auto bit : sig_d)
@@ -376,10 +387,18 @@ struct WreduceWorker
 
 	void run()
 	{
-		for (auto w : module->wires())
+		for (auto w : module->wires()) {
 			if (w->get_bool_attribute("\\keep"))
 				for (auto bit : mi.sigmap(w))
 					keep_bits.insert(bit);
+			if (w->attributes.count("\\init")) {
+				Const initval = w->attributes.at("\\init");
+				SigSpec initsig = mi.sigmap(w);
+				int width = std::min(GetSize(initval), GetSize(initsig));
+				for (int i = 0; i < width; i++)
+					init_bits[initsig[i]] = initval[i];
+			}
+		}
 
 		for (auto c : module->selected_cells())
 			work_queue_cells.insert(c);

From b84febafd75bc66d64cdc573265e086800b3e420 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 20:26:54 -0800
Subject: [PATCH 425/528] Hotfix for "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 tests/tools/autotest.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 0b9aceacc..84e62e011 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -49,7 +49,7 @@ while getopts xmGl:wkjvref:s:p:n:S:I:-: opt; do
 		r)
 			backend_opts="$backend_opts -norename" ;;
 		e)
-			backend_opts="$( echo " $backend_opts " | sed 's, -noexpr ,,; s,^ ,,; s, $,,;'; )" ;;
+			backend_opts="$( echo " $backend_opts " | sed 's, -noexpr , ,; s,^ ,,; s, $,,;'; )" ;;
 		f)
 			frontend="$OPTARG" ;;
 		s)

From 60e3c38054f10251021fa2f504ad2424da33aa1d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 28 Feb 2019 20:34:42 -0800
Subject: [PATCH 426/528] Improve "read" error msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 8ee951d20..9f52ffdc2 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2316,7 +2316,7 @@ struct ReadPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		if (args.size() < 2)
+		if (args.size() < 2 || args[1][0] != '-')
 			log_cmd_error("Missing mode parameter.\n");
 
 		if (args.size() < 3)

From ca2b3feed82f923f06d0cf57787818f0f6793157 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 1 Mar 2019 19:25:23 +0100
Subject: [PATCH 427/528] Fix ECP5 cells_sim for iverilog

---
 techlibs/ecp5/cells_sim.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index 8320ee70a..1e4002ee0 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -223,11 +223,12 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
 
 	wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
 	wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
+	wire srval;
 	generate
 		if (LSRMODE == "PRLD")
-			wire srval = M;
+			assign srval = M;
 		else
-			localparam srval = (REGSET == "SET") ? 1'b1 : 1'b0;
+			assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
 	endgenerate
 
 	initial Q = srval;

From 3090951d54859c331d28232481361bb9c26b3d48 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 1 Mar 2019 11:21:07 -0800
Subject: [PATCH 428/528] Changes required for VPR place and route
 synth_xilinx.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 manual/command-reference-manual.tex |  19 +-
 techlibs/xilinx/Makefile.inc        |   3 +-
 techlibs/xilinx/arith_map.v         | 282 +++++++++++++++++++++++++++-
 techlibs/xilinx/brams_map.v         |  24 +--
 techlibs/xilinx/cells_map.v         | 104 ++--------
 techlibs/xilinx/cells_sim.v         | 105 +++++++----
 techlibs/xilinx/cells_xtra.sh       |   4 +-
 techlibs/xilinx/cells_xtra.v        |  19 ++
 techlibs/xilinx/ff_map.v            |  42 +++++
 techlibs/xilinx/lut2lut.v           |  65 -------
 techlibs/xilinx/lut_map.v           |  94 ++++++++++
 techlibs/xilinx/synth_xilinx.cc     |  68 +++++--
 12 files changed, 601 insertions(+), 228 deletions(-)
 create mode 100644 techlibs/xilinx/ff_map.v
 delete mode 100644 techlibs/xilinx/lut2lut.v
 create mode 100644 techlibs/xilinx/lut_map.v

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index bed6326e2..257bf7986 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -4244,9 +4244,15 @@ compatible with 7-Series Xilinx devices.
         is omitted if this parameter is not specified.
 
     -vpr
-        generate an output netlist (and BLIF file) suitable for VPR
+        generate an output netlist (and BLIF file) suitable for VPR.
         (this feature is experimental and incomplete)
 
+    -no-brams
+		disable infering of block rams
+
+    -no-drams
+        disable infering of distributed rams
+
     -run <from_label>:<to_label>
         only run the commands between the labels (see below). an empty
         from label is synonymous to 'begin', and empty to label is
@@ -4274,11 +4280,11 @@ The following commands are executed by this synthesis command:
     coarse:
         synth -run coarse
 
-    bram:
+    bram: (only executed when '-no-brams' is not given)
         memory_bram -rules +/xilinx/brams.txt
         techmap -map +/xilinx/brams_map.v
 
-    dram:
+    dram: (only executed when '-no-drams' is not given)
         memory_bram -rules +/xilinx/drams.txt
         techmap -map +/xilinx/drams_map.v
 
@@ -4288,16 +4294,17 @@ The following commands are executed by this synthesis command:
         dffsr2dff
         dff2dffe
         opt -full
-        techmap -map +/techmap.v -map +/xilinx/arith_map.v
+        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v
         opt -fast
 
     map_luts:
-        abc -luts 2:2,3,6:5,10,20 [-dff]
+        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)
+        abc -lut 5 [-dff] (with '-vpr' only!)
         clean
 
     map_cells:
         techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)
-        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
+        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT
         clean
 
     check:
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc
index 887ea27d9..d68f03bb4 100644
--- a/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@ -28,7 +28,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
 $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
-$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut2lut.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
+$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
 
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
 $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
diff --git a/techlibs/xilinx/arith_map.v b/techlibs/xilinx/arith_map.v
index 03719659b..09a5f07e8 100644
--- a/techlibs/xilinx/arith_map.v
+++ b/techlibs/xilinx/arith_map.v
@@ -17,6 +17,9 @@
  *
  */
 
+// ============================================================================
+// LCU
+
 (* techmap_celltype = "$lcu" *)
 module _80_xilinx_lcu (P, G, CI, CO);
 	parameter WIDTH = 2;
@@ -28,10 +31,78 @@ module _80_xilinx_lcu (P, G, CI, CO);
 
 	wire _TECHMAP_FAIL_ = WIDTH <= 2;
 
+	genvar i;
+
+`ifdef _CLB_CARRY
+
+	localparam CARRY4_COUNT = (WIDTH + 3) / 4;
+	localparam MAX_WIDTH    = CARRY4_COUNT * 4;
+	localparam PAD_WIDTH    = MAX_WIDTH - WIDTH;
+
+	wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, P & ~G};
+	wire [MAX_WIDTH-1:0] C  = CO;
+
+	generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
+
+		// Partially occupied CARRY4
+		if ((i+1)*4 > WIDTH) begin
+
+			// First one
+			if (i == 0) begin
+				CARRY4 carry4_1st_part
+				(
+				.CYINIT(CI),
+				.CI    (1'd0),
+				.DI    (G [(Y_WIDTH - 1):i*4]),
+				.S     (S [(Y_WIDTH - 1):i*4]),
+				.CO    (CO[(Y_WIDTH - 1):i*4]),
+				);
+			// Another one
+			end else begin
+				CARRY4 carry4_part
+				(
+				.CYINIT(1'd0),
+				.CI    (C [i*4 - 1]),
+				.DI    (G [(Y_WIDTH - 1):i*4]),
+				.S     (S [(Y_WIDTH - 1):i*4]),
+				.CO    (CO[(Y_WIDTH - 1):i*4]),
+				);
+			end
+
+		// Fully occupied CARRY4
+		end else begin
+
+			// First one
+			if (i == 0) begin
+				CARRY4 carry4_1st_full
+				(
+				.CYINIT(CI),
+				.CI    (1'd0),
+				.DI    (G [((i+1)*4 - 1):i*4]),
+				.S     (S [((i+1)*4 - 1):i*4]),
+				.CO    (CO[((i+1)*4 - 1):i*4]),
+				);
+			// Another one
+			end else begin
+				CARRY4 carry4_full
+				(
+				.CYINIT(1'd0),
+				.CI    (C [i*4 - 1]),
+				.DI    (G [((i+1)*4 - 1):i*4]),
+				.S     (S [((i+1)*4 - 1):i*4]),
+				.CO    (CO[((i+1)*4 - 1):i*4]),
+				);
+			end
+
+		end
+
+	end endgenerate
+
+`elsif _EXPLICIT_CARRY
+
 	wire [WIDTH-1:0] C = {CO, CI};
 	wire [WIDTH-1:0] S = P & ~G;
 
-	genvar i;
 	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
 		MUXCY muxcy (
 			.CI(C[i]),
@@ -40,8 +111,28 @@ module _80_xilinx_lcu (P, G, CI, CO);
 			.O(CO[i])
 		);
 	end endgenerate
+
+`else
+
+	wire [WIDTH-1:0] C = {CO, CI};
+	wire [WIDTH-1:0] S = P & ~G;
+
+	generate for (i = 0; i < WIDTH; i = i + 1) begin:slice
+		MUXCY muxcy (
+			.CI(C[i]),
+			.DI(G[i]),
+			.S(S[i]),
+			.O(CO[i])
+		);
+	end endgenerate
+`endif
+
 endmodule
 
+
+// ============================================================================
+// ALU
+
 (* techmap_celltype = "$alu" *)
 module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 	parameter A_SIGNED = 0;
@@ -49,6 +140,8 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 	parameter A_WIDTH = 1;
 	parameter B_WIDTH = 1;
 	parameter Y_WIDTH = 1;
+	parameter _TECHMAP_CONSTVAL_CI_ = 0;
+	parameter _TECHMAP_CONSTMSK_CI_ = 0;
 
 	input [A_WIDTH-1:0] A;
 	input [B_WIDTH-1:0] B;
@@ -66,16 +159,189 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 	wire [Y_WIDTH-1:0] AA = A_buf;
 	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
 
-	wire [Y_WIDTH-1:0] P = AA ^ BB;
-	wire [Y_WIDTH-1:0] G = AA & BB;
-	wire [Y_WIDTH-1:0] C = {CO, CI};
-	wire [Y_WIDTH-1:0] S = P & ~G;
+	genvar i;
+
+`ifdef _CLB_CARRY
+
+	localparam CARRY4_COUNT = (Y_WIDTH + 3) / 4;
+	localparam MAX_WIDTH    = CARRY4_COUNT * 4;
+	localparam PAD_WIDTH    = MAX_WIDTH - Y_WIDTH;
+
+	wire [MAX_WIDTH-1:0] S  = {{PAD_WIDTH{1'b0}}, AA ^ BB};
+	wire [MAX_WIDTH-1:0] DI = {{PAD_WIDTH{1'b0}}, AA & BB};
+
+	wire [MAX_WIDTH-1:0] C  = CO;
 
 	genvar i;
+	generate for (i = 0; i < CARRY4_COUNT; i = i + 1) begin:slice
+
+		// Partially occupied CARRY4
+		if ((i+1)*4 > Y_WIDTH) begin
+
+			// First one
+			if (i == 0) begin
+				CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part
+				(
+				.CYINIT(CI),
+				.CI    (1'd0),
+				.DI    (DI[(Y_WIDTH - 1):i*4]),
+				.S     (S [(Y_WIDTH - 1):i*4]),
+				.O     (Y [(Y_WIDTH - 1):i*4]),
+				.CO    (CO[(Y_WIDTH - 1):i*4])
+				);
+			// Another one
+			end else begin
+				CARRY4 carry4_part
+				(
+				.CYINIT(1'd0),
+				.CI    (C [i*4 - 1]),
+				.DI    (DI[(Y_WIDTH - 1):i*4]),
+				.S     (S [(Y_WIDTH - 1):i*4]),
+				.O     (Y [(Y_WIDTH - 1):i*4]),
+				.CO    (CO[(Y_WIDTH - 1):i*4])
+				);
+			end
+
+		// Fully occupied CARRY4
+		end else begin
+
+			// First one
+			if (i == 0) begin
+				CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full
+				(
+				.CYINIT(CI),
+				.CI    (1'd0),
+				.DI    (DI[((i+1)*4 - 1):i*4]),
+				.S     (S [((i+1)*4 - 1):i*4]),
+				.O     (Y [((i+1)*4 - 1):i*4]),
+				.CO    (CO[((i+1)*4 - 1):i*4])
+				);
+			// Another one
+			end else begin
+				CARRY4 carry4_full
+				(
+				.CYINIT(1'd0),
+				.CI    (C [i*4 - 1]),
+				.DI    (DI[((i+1)*4 - 1):i*4]),
+				.S     (S [((i+1)*4 - 1):i*4]),
+				.O     (Y [((i+1)*4 - 1):i*4]),
+				.CO    (CO[((i+1)*4 - 1):i*4])
+				);
+			end
+
+		end
+
+	end endgenerate
+
+`elsif _EXPLICIT_CARRY
+
+	wire [Y_WIDTH-1:0] S = AA ^ BB;
+	wire [Y_WIDTH-1:0] DI = AA & BB;
+
+	wire CINIT;
+	// Carry chain.
+	//
+	// VPR requires that the carry chain never hit the fabric.	The CO input
+	// to this techmap is the carry outputs for synthesis, e.g. might hit the
+	// fabric.
+	//
+	// So we maintain two wire sets, CO_CHAIN is the carry that is for VPR,
+	// e.g. off fabric dedicated chain.  CO is the carry outputs that are
+	// available to the fabric.
+	wire [Y_WIDTH-1:0] CO_CHAIN;
+	wire [Y_WIDTH-1:0] C = {CO_CHAIN, CINIT};
+
+	// If carry chain is being initialized to a constant, techmap the constant
+	// source.	Otherwise techmap the fabric source.
+	generate for (i = 0; i < 1; i = i + 1) begin:slice
+		CARRY0 #(.CYINIT_FABRIC(1)) carry(
+			.CI_INIT(CI),
+			.DI(DI[0]),
+			.S(S[0]),
+			.CO_CHAIN(CO_CHAIN[0]),
+			.CO_FABRIC(CO[0]),
+			.O(Y[0])
+		);
+	end endgenerate
+
+	generate for (i = 1; i < Y_WIDTH-1; i = i + 1) begin:slice
+		if(i % 4 == 0) begin
+			CARRY0 carry (
+				.CI(C[i]),
+				.DI(DI[i]),
+				.S(S[i]),
+				.CO_CHAIN(CO_CHAIN[i]),
+				.CO_FABRIC(CO[i]),
+				.O(Y[i])
+			);
+		end
+		else
+		begin
+			CARRY carry (
+				.CI(C[i]),
+				.DI(DI[i]),
+				.S(S[i]),
+				.CO_CHAIN(CO_CHAIN[i]),
+				.CO_FABRIC(CO[i]),
+				.O(Y[i])
+			);
+		end
+	end endgenerate
+
+	generate for (i = Y_WIDTH-1; i < Y_WIDTH; i = i + 1) begin:slice
+		if(i % 4 == 0) begin
+			CARRY0 top_of_carry (
+				.CI(C[i]),
+				.DI(DI[i]),
+				.S(S[i]),
+				.CO_CHAIN(CO_CHAIN[i]),
+				.O(Y[i])
+			);
+		end
+		else
+		begin
+			CARRY top_of_carry (
+				.CI(C[i]),
+				.DI(DI[i]),
+				.S(S[i]),
+				.CO_CHAIN(CO_CHAIN[i]),
+				.O(Y[i])
+			);
+		end
+		// Turns out CO_FABRIC and O both use [ABCD]MUX, so provide
+		// a non-congested path to output the top of the carry chain.
+		// Registering the output of the CARRY block would solve this, but not
+		// all designs do that.
+		if((i+1) % 4 == 0) begin
+			CARRY0 carry_output (
+				.CI(CO_CHAIN[i]),
+				.DI(0),
+				.S(0),
+				.O(CO[i])
+			);
+		end
+		else
+		begin
+			CARRY carry_output (
+				.CI(CO_CHAIN[i]),
+				.DI(0),
+				.S(0),
+				.O(CO[i])
+			);
+		end
+	end endgenerate
+
+`else
+
+	wire [Y_WIDTH-1:0] S = AA ^ BB;
+	wire [Y_WIDTH-1:0] DI = AA & BB;
+
+	wire [Y_WIDTH-1:0] C = {CO, CI};
+
 	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
 		MUXCY muxcy (
 			.CI(C[i]),
-			.DI(G[i]),
+			.DI(DI[i]),
 			.S(S[i]),
 			.O(CO[i])
 		);
@@ -86,6 +352,8 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
 		);
 	end endgenerate
 
-	assign X = P;
+`endif
+
+	assign X = S;
 endmodule
 
diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index 7ea49158d..2a23b2553 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -30,8 +30,8 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(72),
 		.WRITE_WIDTH_B(72),
-		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST"),
+		.WRITE_MODE_A("WRITE_FIRST"),
+		.WRITE_MODE_B("WRITE_FIRST"),
 		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 		`include "brams_init_36.vh"
@@ -95,8 +95,8 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(36),
 		.WRITE_WIDTH_B(36),
-		.WRITE_MODE_A("READ_FIRST"),
-		.WRITE_MODE_B("READ_FIRST"),
+		.WRITE_MODE_A("WRITE_FIRST"),
+		.WRITE_MODE_B("WRITE_FIRST"),
 		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 		`include "brams_init_18.vh"
@@ -171,8 +171,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("READ_FIRST"),
-			.WRITE_MODE_B("READ_FIRST"),
+			.WRITE_MODE_A("WRITE_FIRST"),
+			.WRITE_MODE_B("WRITE_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_36.vh"
@@ -209,8 +209,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("READ_FIRST"),
-			.WRITE_MODE_B("READ_FIRST"),
+			.WRITE_MODE_A("WRITE_FIRST"),
+			.WRITE_MODE_B("WRITE_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_32.vh"
@@ -285,8 +285,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("READ_FIRST"),
-			.WRITE_MODE_B("READ_FIRST"),
+			.WRITE_MODE_A("WRITE_FIRST"),
+			.WRITE_MODE_B("WRITE_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_18.vh"
@@ -323,8 +323,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("READ_FIRST"),
-			.WRITE_MODE_B("READ_FIRST"),
+			.WRITE_MODE_A("WRITE_FIRST"),
+			.WRITE_MODE_B("WRITE_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_16.vh"
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v
index 0771be0b9..d5801c0fc 100644
--- a/techlibs/xilinx/cells_map.v
+++ b/techlibs/xilinx/cells_map.v
@@ -1,86 +1,20 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
 
-module  \$_DFF_N_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-module  \$_DFF_P_ (input D, C, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
-
-module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
-module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_R_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E), .R(1'b0)); endmodule
-
-module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
-module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
-module  \$_DFF_PN0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
-module  \$_DFF_PP0_ (input D, C, R, output Q); FDCE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_CLR_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(R)); endmodule
-
-module  \$_DFF_NN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
-module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|1), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
-module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
-module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE #(.INIT(|0), .IS_C_INVERTED(|0), .IS_D_INVERTED(|0), .IS_PRE_INVERTED(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(R)); endmodule
-
-`ifndef NO_LUT
-module \$lut (A, Y);
-  parameter WIDTH = 0;
-  parameter LUT = 0;
-
-  input [WIDTH-1:0] A;
-  output Y;
-
-  generate
-    if (WIDTH == 1) begin
-      LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]));
-    end else
-    if (WIDTH == 2) begin
-      LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]));
-    end else
-    if (WIDTH == 3) begin
-      LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]));
-    end else
-    if (WIDTH == 4) begin
-      LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]));
-    end else
-    if (WIDTH == 5) begin
-      LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]));
-    end else
-    if (WIDTH == 6) begin
-      LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-    end else
-    if (WIDTH == 7) begin
-      wire T0, T1;
-      LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-      LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-      MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
-    end else
-    if (WIDTH == 8) begin
-      wire T0, T1, T2, T3, T4, T5;
-      LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-      LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-      LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-      LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
-        .I0(A[0]), .I1(A[1]), .I2(A[2]),
-        .I3(A[3]), .I4(A[4]), .I5(A[5]));
-      MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
-      MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
-      MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
-    end else begin
-      wire _TECHMAP_FAIL_ = 1;
-    end
-  endgenerate
-endmodule
-`endif
+// Empty for now
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index eba17ac9c..787b37cc8 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -1,3 +1,21 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
 
 // See Xilinx UG953 and UG474 for a description of the cell types below.
 // http://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
@@ -104,56 +122,75 @@ module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
   assign CO[3] = S[3] ? CO[2] : DI[3];
 endmodule
 
+`ifdef _EXPLICIT_CARRY
+
+module CARRY0(output CO_CHAIN, CO_FABRIC, O, input CI, CI_INIT, DI, S);
+  parameter CYINIT_FABRIC = 0;
+  wire CI_COMBINE;
+  if(CYINIT_FABRIC) begin
+    assign CI_COMBINE = CI_INIT;
+  end else begin
+    assign CI_COMBINE = CI;
+  end
+  assign CO_CHAIN = S ? CI_COMBINE : DI;
+  assign CO_FABRIC = S ? CI_COMBINE : DI;
+  assign O = S ^ CI_COMBINE;
+endmodule
+
+module CARRY(output CO_CHAIN, CO_FABRIC, O, input CI, DI, S);
+  assign CO_CHAIN = S ? CI : DI;
+  assign CO_FABRIC = S ? CI : DI;
+  assign O = S ^ CI;
+endmodule
+
+`endif
+
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  always @(posedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_S_INVERTED = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  always @(posedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
-    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  always @(posedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  parameter [0:0] INIT = 1'b1;
   initial Q <= INIT;
-  generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
-    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+endmodule
+
+module FDRE_1 (output reg Q, input C, CE, D, R);
+  parameter [0:0] INIT = 1'b0;
+  initial Q <= INIT;
+  always @(negedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
+endmodule
+
+module FDSE_1 (output reg Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b1;
+  initial Q <= INIT;
+  always @(negedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+endmodule
+
+module FDCE_1 (output reg Q, input C, CE, D, CLR);
+  parameter [0:0] INIT = 1'b0;
+  initial Q <= INIT;
+  always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+endmodule
+
+module FDPE_1 (output reg Q, input C, CE, D, PRE);
+  parameter [0:0] INIT = 1'b1;
+  initial Q <= INIT;
+  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
 module RAM64X1D (
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 0480410f5..37c3e5480 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -115,7 +115,7 @@ function xtract_cell_decl()
 	xtract_cell_decl PS7
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
-	# xtract_cell_decl RAM128X1D
+	xtract_cell_decl RAM128X1D
 	xtract_cell_decl RAM128X1S
 	xtract_cell_decl RAM256X1S
 	xtract_cell_decl RAM32M
@@ -124,7 +124,7 @@ function xtract_cell_decl()
 	xtract_cell_decl RAM32X1S_1
 	xtract_cell_decl RAM32X2S
 	xtract_cell_decl RAM64M
-	# xtract_cell_decl RAM64X1D
+	xtract_cell_decl RAM64X1D
 	xtract_cell_decl RAM64X1S
 	xtract_cell_decl RAM64X1S_1
 	xtract_cell_decl RAM64X2S
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 8d8b91ddc..995d62e18 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3695,6 +3695,25 @@ module RAM128X1S (...);
     input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
 endmodule
 
+module RAM128X1D (
+  output       DPO, SPO,
+  input        D, WCLK, WE,
+  input  [6:0] A, DPRA
+);
+	parameter [127:0] INIT = 128'bx;
+	parameter IS_WCLK_INVERTED = 0;
+endmodule
+
+module RAM64X1D (
+  output DPO, SPO,
+  input  D, WCLK, WE,
+  input  A0, A1, A2, A3, A4, A5,
+  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
+);
+	parameter [63:0] INIT = 64'bx;
+	parameter IS_WCLK_INVERTED = 0;
+endmodule
+
 module RAM256X1S (...);
     parameter [255:0] INIT = 256'h0;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/ff_map.v b/techlibs/xilinx/ff_map.v
new file mode 100644
index 000000000..13beaa6ae
--- /dev/null
+++ b/techlibs/xilinx/ff_map.v
@@ -0,0 +1,42 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+// FF mapping
+
+`ifndef _NO_FFS
+
+module  \$_DFF_N_   (input D, C, output Q);    FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
+module  \$_DFF_P_   (input D, C, output Q);    FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .R(1'b0)); endmodule
+
+module  \$_DFFE_NP_ (input D, C, E, output Q); FDRE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
+module  \$_DFFE_PP_ (input D, C, E, output Q); FDRE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(E),    .R(1'b0)); endmodule
+
+module  \$_DFF_NN0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
+module  \$_DFF_NP0_ (input D, C, R, output Q); FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
+module  \$_DFF_PN0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR(!R)); endmodule
+module  \$_DFF_PP0_ (input D, C, R, output Q); FDCE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .CLR( R)); endmodule
+
+module  \$_DFF_NN1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
+module  \$_DFF_NP1_ (input D, C, R, output Q); FDPE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
+module  \$_DFF_PN1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE(!R)); endmodule
+module  \$_DFF_PP1_ (input D, C, R, output Q); FDPE   #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(1'b1), .PRE( R)); endmodule
+
+`endif
+
diff --git a/techlibs/xilinx/lut2lut.v b/techlibs/xilinx/lut2lut.v
deleted file mode 100644
index 061ad2041..000000000
--- a/techlibs/xilinx/lut2lut.v
+++ /dev/null
@@ -1,65 +0,0 @@
-module LUT1(output O, input I0);
-  parameter [1:0] INIT = 0;
-  \$lut #(
-    .WIDTH(1),
-    .LUT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .A(I0),
-    .Y(O)
-  );
-endmodule
-
-module LUT2(output O, input I0, I1);
-  parameter [3:0] INIT = 0;
-  \$lut #(
-    .WIDTH(2),
-    .LUT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .A({I1, I0}),
-    .Y(O)
-  );
-endmodule
-
-module LUT3(output O, input I0, I1, I2);
-  parameter [7:0] INIT = 0;
-  \$lut #(
-    .WIDTH(3),
-    .LUT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .A({I2, I1, I0}),
-    .Y(O)
-  );
-endmodule
-
-module LUT4(output O, input I0, I1, I2, I3);
-  parameter [15:0] INIT = 0;
-  \$lut #(
-    .WIDTH(4),
-    .LUT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .A({I3, I2, I1, I0}),
-    .Y(O)
-  );
-endmodule
-
-module LUT5(output O, input I0, I1, I2, I3, I4);
-  parameter [31:0] INIT = 0;
-  \$lut #(
-    .WIDTH(5),
-    .LUT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .A({I4, I3, I2, I1, I0}),
-    .Y(O)
-  );
-endmodule
-
-module LUT6(output O, input I0, I1, I2, I3, I4, I5);
-  parameter [63:0] INIT = 0;
-  \$lut #(
-    .WIDTH(6),
-    .LUT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .A({I5, I4, I3, I2, I1, I0}),
-    .Y(O)
-  );
-endmodule
diff --git a/techlibs/xilinx/lut_map.v b/techlibs/xilinx/lut_map.v
new file mode 100644
index 000000000..d07c59dee
--- /dev/null
+++ b/techlibs/xilinx/lut_map.v
@@ -0,0 +1,94 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+// ============================================================================
+// LUT mapping
+
+`ifndef _NO_LUTS
+
+module \$lut (A, Y);
+  parameter WIDTH = 0;
+  parameter LUT = 0;
+
+  input [WIDTH-1:0] A;
+  output Y;
+
+  generate
+    if (WIDTH == 1) begin
+      LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(A[0]));
+    end else
+    if (WIDTH == 2) begin
+      LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(A[0]), .I1(A[1]));
+    end else
+    if (WIDTH == 3) begin
+      LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]));
+    end else
+    if (WIDTH == 4) begin
+      LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]));
+    end else
+    if (WIDTH == 5) begin
+      LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]));
+    end else
+    if (WIDTH == 6) begin
+      LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+    end else
+    if (WIDTH == 7) begin
+      wire T0, T1;
+      LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+      LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+      MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
+    end else
+    if (WIDTH == 8) begin
+      wire T0, T1, T2, T3, T4, T5;
+      LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+      LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+      LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+      LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
+        .I0(A[0]), .I1(A[1]), .I2(A[2]),
+        .I3(A[3]), .I4(A[4]), .I5(A[5]));
+      MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
+      MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
+      MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
+    end else begin
+      wire _TECHMAP_FAIL_ = 1;
+    end
+  endgenerate
+endmodule
+
+`endif
+
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c11d885d..60cfde604 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,6 +63,12 @@ struct SynthXilinxPass : public Pass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
+		log("    -no-brams\n");
+		log("        disable infering of block rams\n");
+		log("\n");
+		log("    -no-drams\n");
+		log("        disable infering of distributed rams\n");
+		log("\n");
 		log("    -run <from_label>:<to_label>\n");
 		log("        only run the commands between the labels (see below). an empty\n");
 		log("        from label is synonymous to 'begin', and empty to label is\n");
@@ -90,11 +96,11 @@ struct SynthXilinxPass : public Pass
 		log("    coarse:\n");
 		log("        synth -run coarse\n");
 		log("\n");
-		log("    bram:\n");
+		log("    bram: (only executed when '-no-brams' is not given)\n");
 		log("        memory_bram -rules +/xilinx/brams.txt\n");
 		log("        techmap -map +/xilinx/brams_map.v\n");
 		log("\n");
-		log("    dram:\n");
+		log("    dram: (only executed when '-no-drams' is not given)\n");
 		log("        memory_bram -rules +/xilinx/drams.txt\n");
 		log("        techmap -map +/xilinx/drams_map.v\n");
 		log("\n");
@@ -104,16 +110,17 @@ struct SynthXilinxPass : public Pass
 		log("        dffsr2dff\n");
 		log("        dff2dffe\n");
 		log("        opt -full\n");
-		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
+		log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
 		log("        opt -fast\n");
 		log("\n");
 		log("    map_luts:\n");
-		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
+		log("        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)\n");
+		log("        abc -lut 5 [-dff] (with '-vpr' only!)\n");
 		log("        clean\n");
 		log("\n");
 		log("    map_cells:\n");
-		log("        techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)\n");
-		log("        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT\n");
+		log("        techmap -map +/xilinx/cells_map.v\n");
+		log("        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n");
 		log("        clean\n");
 		log("\n");
 		log("    check:\n");
@@ -137,6 +144,8 @@ struct SynthXilinxPass : public Pass
 		bool flatten = false;
 		bool retime = false;
 		bool vpr = false;
+		bool noBrams = false;
+		bool noDrams = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -173,6 +182,14 @@ struct SynthXilinxPass : public Pass
 				vpr = true;
 				continue;
 			}
+			if (args[argidx] == "-no-brams") {
+				noBrams = true;
+				continue;
+			}
+			if (args[argidx] == "-no-drams") {
+				noDrams = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -187,9 +204,18 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "begin"))
 		{
-			Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
+			if (vpr) {
+				Pass::call(design, "read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+			} else {
+				Pass::call(design, "read_verilog -lib +/xilinx/cells_sim.v");
+			}
+
 			Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
-			Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
+
+			if (!noBrams) {
+				Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
+			}
+
 			Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
 		}
 
@@ -206,14 +232,18 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "bram"))
 		{
-			Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
-			Pass::call(design, "techmap -map +/xilinx/brams_map.v");
+			if (!noBrams) {
+				Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
+				Pass::call(design, "techmap -map +/xilinx/brams_map.v");
+			}
 		}
 
 		if (check_label(active, run_from, run_to, "dram"))
 		{
-			Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
-			Pass::call(design, "techmap -map +/xilinx/drams_map.v");
+			if (!noDrams) {
+				Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
+				Pass::call(design, "techmap -map +/xilinx/drams_map.v");
+			}
 		}
 
 		if (check_label(active, run_from, run_to, "fine"))
@@ -223,7 +253,14 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "dffsr2dff");
 			Pass::call(design, "dff2dffe");
 			Pass::call(design, "opt -full");
-			Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
+
+			if (vpr) {
+				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
+			} else {
+				Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
+			}
+
+			Pass::call(design, "hierarchy -check");
 			Pass::call(design, "opt -fast");
 		}
 
@@ -231,14 +268,13 @@ struct SynthXilinxPass : public Pass
 		{
 			Pass::call(design, "abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
 			Pass::call(design, "clean");
+			Pass::call(design, "techmap -map +/xilinx/lut_map.v");
 		}
 
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
 			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
-			if (vpr)
-			    Pass::call(design, "techmap -map +/xilinx/lut2lut.v");
-			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT");
+			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT");
 			Pass::call(design, "clean");
 		}
 

From eccaf101d8324f518ed89134b4f21d2bdc636a8d Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 1 Mar 2019 12:14:27 -0800
Subject: [PATCH 429/528] Modify arguments to match existing style.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 manual/command-reference-manual.tex | 10 +++++-----
 techlibs/xilinx/synth_xilinx.cc     | 12 ++++++------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index 257bf7986..bb9d7238c 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -4247,10 +4247,10 @@ compatible with 7-Series Xilinx devices.
         generate an output netlist (and BLIF file) suitable for VPR.
         (this feature is experimental and incomplete)
 
-    -no-brams
-		disable infering of block rams
+    -nobrams
+        disable infering of block rams
 
-    -no-drams
+    -nodrams
         disable infering of distributed rams
 
     -run <from_label>:<to_label>
@@ -4280,11 +4280,11 @@ The following commands are executed by this synthesis command:
     coarse:
         synth -run coarse
 
-    bram: (only executed when '-no-brams' is not given)
+    bram: (only executed when '-nobrams' is not given)
         memory_bram -rules +/xilinx/brams.txt
         techmap -map +/xilinx/brams_map.v
 
-    dram: (only executed when '-no-drams' is not given)
+    dram: (only executed when '-nodrams' is not given)
         memory_bram -rules +/xilinx/drams.txt
         techmap -map +/xilinx/drams_map.v
 
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 60cfde604..12ad9fdaf 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
-		log("    -no-brams\n");
+		log("    -nobrams\n");
 		log("        disable infering of block rams\n");
 		log("\n");
-		log("    -no-drams\n");
+		log("    -nodrams\n");
 		log("        disable infering of distributed rams\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
@@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass
 		log("    coarse:\n");
 		log("        synth -run coarse\n");
 		log("\n");
-		log("    bram: (only executed when '-no-brams' is not given)\n");
+		log("    bram: (only executed when '-nobrams' is not given)\n");
 		log("        memory_bram -rules +/xilinx/brams.txt\n");
 		log("        techmap -map +/xilinx/brams_map.v\n");
 		log("\n");
-		log("    dram: (only executed when '-no-drams' is not given)\n");
+		log("    dram: (only executed when '-nodrams' is not given)\n");
 		log("        memory_bram -rules +/xilinx/drams.txt\n");
 		log("        techmap -map +/xilinx/drams_map.v\n");
 		log("\n");
@@ -182,11 +182,11 @@ struct SynthXilinxPass : public Pass
 				vpr = true;
 				continue;
 			}
-			if (args[argidx] == "-no-brams") {
+			if (args[argidx] == "-nobrams") {
 				noBrams = true;
 				continue;
 			}
-			if (args[argidx] == "-no-drams") {
+			if (args[argidx] == "-nodrams") {
 				noDrams = true;
 				continue;
 			}

From 03237de68605bb6eae73b96379faab0af6f8ce73 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Mar 2019 12:59:07 -0800
Subject: [PATCH 430/528] Fix "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/edif/edif.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 2d25f879d..7e30b67af 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -130,7 +130,7 @@ struct EdifBackend : public Backend {
 		bool port_rename = false;
 		bool attr_properties = false;
 		std::map<RTLIL::IdString, std::map<RTLIL::IdString, int>> lib_cell_ports;
-		bool nogndvcc = false, gndvccy = true;
+		bool nogndvcc = false, gndvccy = false;
 		CellTypes ct(design);
 		EdifNames edif_names;
 

From 7cfae2c52fb8e210a68032a109646785e4353dcc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Mar 2019 13:35:09 -0800
Subject: [PATCH 431/528] Use mem2reg on memories that only have constant-index
 write ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/ast.h       |  2 ++
 frontends/ast/simplify.cc | 11 +++++++++++
 2 files changed, 13 insertions(+)

diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 08f91c9c3..89f7e6e4f 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -214,6 +214,8 @@ namespace AST
 			MEM2REG_FL_SET_ASYNC = 0x00000800,
 			MEM2REG_FL_EQ2       = 0x00001000,
 			MEM2REG_FL_CMPLX_LHS = 0x00002000,
+			MEM2REG_FL_CONST_LHS = 0x00004000,
+			MEM2REG_FL_VAR_LHS   = 0x00008000,
 
 			/* proc flags */
 			MEM2REG_FL_EQ1       = 0x01000000,
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 46013544b..589c683f8 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -113,6 +113,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				if (memflags & AstNode::MEM2REG_FL_CMPLX_LHS)
 					goto verbose_activate;
 
+				if ((memflags & AstNode::MEM2REG_FL_CONST_LHS) && !(memflags & AstNode::MEM2REG_FL_VAR_LHS))
+					goto verbose_activate;
+
 				// log("Note: Not replacing memory %s with list of registers (flags=0x%08lx).\n", mem->str.c_str(), long(memflags));
 				continue;
 
@@ -2936,6 +2939,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 				proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
 			}
 
+			// remember if this is a constant index or not
+			if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) {
+				if (children[0]->children[0]->children[0]->type == AST_CONSTANT)
+					mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS;
+				else
+					mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS;
+			}
+
 			// remember where this is
 			if (flags & MEM2REG_FL_INIT) {
 				if (!(mem2reg_candidates[mem] & AstNode::MEM2REG_FL_SET_INIT))

From a02d61576ec42931ed3a67c6900bcd5aeddaf8b8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 1 Mar 2019 14:29:17 -0800
Subject: [PATCH 432/528] Minor improvements in README

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 README.md | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index 883f2b0a5..f17046488 100644
--- a/README.md
+++ b/README.md
@@ -34,11 +34,24 @@ compatible license that is similar in terms to the MIT license
 or the 2-clause BSD license).
 
 
-Web Site
-========
+Web Site and Other Resources
+============================
 
 More information and documentation can be found on the Yosys web site:
-http://www.clifford.at/yosys/
+- http://www.clifford.at/yosys/
+
+The "Documentation" page on the web site contains links to more resources,
+including a manual that even describes some of the Yosys internals:
+- http://www.clifford.at/yosys/documentation.html
+
+The file `CodingReadme` in this directory contains additional information
+for people interested in using the Yosys C++ APIs.
+
+Users interested in formal verification might want to use the formal verification
+front-end for Yosys, SymbiYosys:
+- https://symbiyosys.readthedocs.io/en/latest/
+- https://github.com/YosysHQ/SymbiYosys
+
 
 Setup
 ======

From 5ebeca12eb0bf9317acec3d619021ab337d445ba Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 1 Mar 2019 14:35:14 -0800
Subject: [PATCH 433/528] Use singular for disabling of DRAM or BRAM inference.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 manual/command-reference-manual.tex | 19 ++++++-------------
 techlibs/xilinx/synth_xilinx.cc     | 26 +++++++++++++-------------
 2 files changed, 19 insertions(+), 26 deletions(-)

diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex
index bb9d7238c..bed6326e2 100644
--- a/manual/command-reference-manual.tex
+++ b/manual/command-reference-manual.tex
@@ -4244,15 +4244,9 @@ compatible with 7-Series Xilinx devices.
         is omitted if this parameter is not specified.
 
     -vpr
-        generate an output netlist (and BLIF file) suitable for VPR.
+        generate an output netlist (and BLIF file) suitable for VPR
         (this feature is experimental and incomplete)
 
-    -nobrams
-        disable infering of block rams
-
-    -nodrams
-        disable infering of distributed rams
-
     -run <from_label>:<to_label>
         only run the commands between the labels (see below). an empty
         from label is synonymous to 'begin', and empty to label is
@@ -4280,11 +4274,11 @@ The following commands are executed by this synthesis command:
     coarse:
         synth -run coarse
 
-    bram: (only executed when '-nobrams' is not given)
+    bram:
         memory_bram -rules +/xilinx/brams.txt
         techmap -map +/xilinx/brams_map.v
 
-    dram: (only executed when '-nodrams' is not given)
+    dram:
         memory_bram -rules +/xilinx/drams.txt
         techmap -map +/xilinx/drams_map.v
 
@@ -4294,17 +4288,16 @@ The following commands are executed by this synthesis command:
         dffsr2dff
         dff2dffe
         opt -full
-        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v
+        techmap -map +/techmap.v -map +/xilinx/arith_map.v
         opt -fast
 
     map_luts:
-        abc -luts 2:2,3,6:5,10,20 [-dff] (without '-vpr' only!)
-        abc -lut 5 [-dff] (with '-vpr' only!)
+        abc -luts 2:2,3,6:5,10,20 [-dff]
         clean
 
     map_cells:
         techmap -map +/xilinx/cells_map.v (with -D NO_LUT in vpr mode)
-        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT
+        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT
         clean
 
     check:
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 12ad9fdaf..9e7559944 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -63,10 +63,10 @@ struct SynthXilinxPass : public Pass
 		log("        generate an output netlist (and BLIF file) suitable for VPR\n");
 		log("        (this feature is experimental and incomplete)\n");
 		log("\n");
-		log("    -nobrams\n");
+		log("    -nobram\n");
 		log("        disable infering of block rams\n");
 		log("\n");
-		log("    -nodrams\n");
+		log("    -nodram\n");
 		log("        disable infering of distributed rams\n");
 		log("\n");
 		log("    -run <from_label>:<to_label>\n");
@@ -96,11 +96,11 @@ struct SynthXilinxPass : public Pass
 		log("    coarse:\n");
 		log("        synth -run coarse\n");
 		log("\n");
-		log("    bram: (only executed when '-nobrams' is not given)\n");
+		log("    bram: (only executed when '-nobram' is not given)\n");
 		log("        memory_bram -rules +/xilinx/brams.txt\n");
 		log("        techmap -map +/xilinx/brams_map.v\n");
 		log("\n");
-		log("    dram: (only executed when '-nodrams' is not given)\n");
+		log("    dram: (only executed when '-nodram' is not given)\n");
 		log("        memory_bram -rules +/xilinx/drams.txt\n");
 		log("        techmap -map +/xilinx/drams_map.v\n");
 		log("\n");
@@ -144,8 +144,8 @@ struct SynthXilinxPass : public Pass
 		bool flatten = false;
 		bool retime = false;
 		bool vpr = false;
-		bool noBrams = false;
-		bool noDrams = false;
+		bool nobram = false;
+		bool nodram = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
@@ -182,12 +182,12 @@ struct SynthXilinxPass : public Pass
 				vpr = true;
 				continue;
 			}
-			if (args[argidx] == "-nobrams") {
-				noBrams = true;
+			if (args[argidx] == "-nobram") {
+				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-nodrams") {
-				noDrams = true;
+			if (args[argidx] == "-nodram") {
+				nodram = true;
 				continue;
 			}
 			break;
@@ -212,7 +212,7 @@ struct SynthXilinxPass : public Pass
 
 			Pass::call(design, "read_verilog -lib +/xilinx/cells_xtra.v");
 
-			if (!noBrams) {
+			if (!nobram) {
 				Pass::call(design, "read_verilog -lib +/xilinx/brams_bb.v");
 			}
 
@@ -232,7 +232,7 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "bram"))
 		{
-			if (!noBrams) {
+			if (!nobram) {
 				Pass::call(design, "memory_bram -rules +/xilinx/brams.txt");
 				Pass::call(design, "techmap -map +/xilinx/brams_map.v");
 			}
@@ -240,7 +240,7 @@ struct SynthXilinxPass : public Pass
 
 		if (check_label(active, run_from, run_to, "dram"))
 		{
-			if (!noDrams) {
+			if (!nodram) {
 				Pass::call(design, "memory_bram -rules +/xilinx/drams.txt");
 				Pass::call(design, "techmap -map +/xilinx/drams_map.v");
 			}

From 3e16f75bc6f490cada2b9c4e9b4962a66b1e8008 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 1 Mar 2019 14:41:21 -0800
Subject: [PATCH 434/528] Revert FF models to include IS_x_INVERTED parameters.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 techlibs/xilinx/cells_sim.v | 40 +++++++++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 6 deletions(-)

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 787b37cc8..ff5ff0726 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -147,26 +147,54 @@ endmodule
 
 module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_R_INVERTED = 1'b0;
   initial Q <= INIT;
-  always @(posedge C) if (R) Q <= 1'b0; else if(CE) Q <= D;
+  generate case (|IS_C_INVERTED)
+    1'b0: always @(posedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (R == !IS_R_INVERTED) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
 endmodule
 
 module FDSE (output reg Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
   initial Q <= INIT;
-  always @(posedge C) if (S) Q <= 1'b1; else if(CE) Q <= D;
+  generate case (|IS_C_INVERTED)
+    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
 endmodule
 
 module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
   initial Q <= INIT;
-  always @(posedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
+  generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
+    2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
 endmodule
 
 module FDPE (output reg Q, input C, CE, D, PRE);
-  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] INIT = 1'b0;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
   initial Q <= INIT;
-  always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
+  generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
+    2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
 endmodule
 
 module FDRE_1 (output reg Q, input C, CE, D, R);

From 57f8bb471feecafad9d9e0bae77ea937b6b03a83 Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Fri, 1 Mar 2019 20:15:20 -0800
Subject: [PATCH 435/528] Try again for passes/pmgen/ice40_dsp_pm.h rule

Tested on both in-tree and out-of-tree builds
---
 passes/pmgen/Makefile.inc |  2 +-
 passes/pmgen/pmgen.py     | 15 ++++++++-------
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc
index e0dd0fc06..e0609d9ba 100644
--- a/passes/pmgen/Makefile.inc
+++ b/passes/pmgen/Makefile.inc
@@ -5,4 +5,4 @@ EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
 .SECONDARY: passes/pmgen/ice40_dsp_pm.h
 
 passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
-	$(P) mkdir -p passes/pmgen && python3 $^
+	$(P) mkdir -p passes/pmgen && python3 $^ $@
diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py
index 762d8621f..d9747b065 100644
--- a/passes/pmgen/pmgen.py
+++ b/passes/pmgen/pmgen.py
@@ -9,7 +9,8 @@ pp = pprint.PrettyPrinter(indent=4)
 pmgfile = sys.argv[1]
 assert pmgfile.endswith(".pmg")
 prefix = pmgfile[0:-4]
-pmname = prefix.split('/')[-1]
+prefix = prefix.split('/')[-1]
+outfile = sys.argv[2]
 
 state_types = dict()
 udata_types = dict()
@@ -179,7 +180,7 @@ with open(pmgfile, "r") as f:
 
             blocks.append(block)
 
-with open("%s_pm.h" % prefix, "w") as f:
+with open(outfile, "w") as f:
     print("// Generated by pmgen.py from {}.pgm".format(prefix), file=f)
     print("", file=f)
 
@@ -190,10 +191,10 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("YOSYS_NAMESPACE_BEGIN", file=f)
     print("", file=f)
 
-    print("struct {}_pm {{".format(pmname), file=f)
+    print("struct {}_pm {{".format(prefix), file=f)
     print("  Module *module;", file=f)
     print("  SigMap sigmap;", file=f)
-    print("  std::function<void()> on_accept;".format(pmname), file=f)
+    print("  std::function<void()> on_accept;".format(prefix), file=f)
     print("", file=f)
 
     for index in range(len(blocks)):
@@ -291,7 +292,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  {}_pm(Module *module, const vector<Cell*> &cells) :".format(pmname), file=f)
+    print("  {}_pm(Module *module, const vector<Cell*> &cells) :".format(prefix), file=f)
     print("      module(module), sigmap(module) {", file=f)
     for s, t in sorted(udata_types.items()):
         if t.endswith("*"):
@@ -321,7 +322,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  ~{}_pm() {{".format(pmname), file=f)
+    print("  ~{}_pm() {{".format(prefix), file=f)
     print("    for (auto cell : autoremove_cells)", file=f)
     print("      module->remove(cell);", file=f)
     print("  }", file=f)
@@ -340,7 +341,7 @@ with open("%s_pm.h" % prefix, "w") as f:
     print("  }", file=f)
     print("", file=f)
 
-    print("  void run(std::function<void({}_pm&)> on_accept_f) {{".format(pmname), file=f)
+    print("  void run(std::function<void({}_pm&)> on_accept_f) {{".format(prefix), file=f)
     print("    run([&](){on_accept_f(*this);});", file=f)
     print("  }", file=f)
     print("", file=f)

From f75aee87e3038f663dc61f9d3098d5056ccdced7 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Mar 2019 08:29:28 -0800
Subject: [PATCH 436/528] Disable macOS builds in Travis

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .travis.yml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 8aacbb8b1..7c6e4e43c 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -132,11 +132,11 @@ matrix:
       env:
         - MATRIX_EVAL="CONFIG=clang && CC=clang-5.0 && CXX=clang++-5.0"
 
-    # Latest clang on Mac OS X
-    - os: osx
-      osx_image: xcode9.4
-      env:
-        - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++"
+#   # Latest clang on Mac OS X
+#   - os: osx
+#     osx_image: xcode9.4
+#     env:
+#       - MATRIX_EVAL="CONFIG=clang && CC=clang && CXX=clang++"
 
 before_install:
   - ./.travis/setup.sh

From 5d93dcce862d281f0df495eeee755cd4bfca342d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Mar 2019 09:58:20 -0800
Subject: [PATCH 437/528] Fix $readmem[hb] for mem2reg memories, fixes #785

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 589c683f8..1c35516d4 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2172,6 +2172,8 @@ skip_dynamic_range_lvalue_expansion:;
 				}
 
 				newNode = readmem(str == "\\$readmemh", node_filename->bitsAsConst().decode_string(), node_memory->id2ast, start_addr, finish_addr, unconditional_init);
+				delete node_filename;
+				delete node_memory;
 				goto apply_newNode;
 			}
 
@@ -3059,6 +3061,39 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 	if (type == AST_FUNCTION || type == AST_TASK)
 		return false;
 
+	if (type == AST_MEMINIT && id2ast && mem2reg_set.count(id2ast))
+	{
+		log_assert(children[0]->type == AST_CONSTANT);
+		log_assert(children[1]->type == AST_CONSTANT);
+		log_assert(children[2]->type == AST_CONSTANT);
+
+		int cursor = children[0]->asInt(false);
+		Const data = children[1]->bitsAsConst();
+		int length = children[2]->asInt(false);
+
+		if (length != 0)
+		{
+			AstNode *block = new AstNode(AST_INITIAL, new AstNode(AST_BLOCK));
+			mod->children.push_back(block);
+			block = block->children[0];
+
+			int wordsz = GetSize(data) / length;
+
+			for (int i = 0; i < length; i++) {
+				block->children.push_back(new AstNode(AST_ASSIGN_EQ, new AstNode(AST_IDENTIFIER, new AstNode(AST_RANGE, AstNode::mkconst_int(cursor+i, false))), mkconst_bits(data.extract(i*wordsz, wordsz).bits, false)));
+				block->children.back()->children[0]->str = str;
+				block->children.back()->children[0]->id2ast = id2ast;
+				block->children.back()->children[0]->was_checked = true;
+			}
+		}
+
+		AstNode *newNode = new AstNode(AST_NONE);
+		newNode->cloneInto(this);
+		delete newNode;
+
+		did_something = true;
+	}
+
 	if (type == AST_ASSIGN && block == NULL && children[0]->mem2reg_check(mem2reg_set))
 	{
 		if (async_block == NULL) {

From ce6695e22c7d2b8856ec5bb93a94264555aa55b5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Mar 2019 10:38:13 -0800
Subject: [PATCH 438/528] Fix $global_clock handling vs autowire

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 1c35516d4..d0b31078a 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -941,7 +941,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 			}
 		}
 		if (current_scope.count(str) == 0) {
-			if (flag_autowire) {
+			if (flag_autowire || str == "\\$global_clock") {
 				AstNode *auto_wire = new AstNode(AST_AUTOWIRE);
 				auto_wire->str = str;
 				current_ast_mod->children.push_back(auto_wire);

From 3a51714451dbd5a0aec5d5167429f899950f2c4e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Mar 2019 11:40:57 -0800
Subject: [PATCH 439/528] Fix error for wire decl in always block, fixes #763

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 2d591b29d..13383845a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -544,7 +544,11 @@ struct AST_INTERNAL::ProcessGenerator
 			break;
 
 		case AST_WIRE:
-			log_file_error(ast->filename, ast->linenum, "Found wire declaration in block without label!\n");
+			log_file_error(ast->filename, ast->linenum, "Found reg declaration in block without label!\n");
+			break;
+
+		case AST_ASSIGN:
+			log_file_error(ast->filename, ast->linenum, "Found continous assignment in always/initial block!\n");
 			break;
 
 		case AST_PARAMETER:

From ae9286386de117991f887f919f5af3fac40173cc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Mar 2019 12:36:46 -0800
Subject: [PATCH 440/528] Only run derive on blackbox modules when ports have
 dynamic size

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 README.md                     |  3 +++
 frontends/ast/ast.h           |  1 +
 frontends/ast/simplify.cc     | 19 +++++++++++++++++++
 passes/hierarchy/hierarchy.cc |  2 +-
 4 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index f17046488..9bac468a7 100644
--- a/README.md
+++ b/README.md
@@ -309,6 +309,9 @@ Verilog Attributes and non-standard features
   passes to identify input and output ports of cells. The Verilog backend
   also does not output blackbox modules on default.
 
+- The ``dynports'' attribute is used by the Verilog front-end to mark modules
+  that have ports with a width that depends on a parameter.
+
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
   have hidden connections that are not part of the netlist, such as IO pads.
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 89f7e6e4f..8b185ff51 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -239,6 +239,7 @@ namespace AST
 		bool has_const_only_constructs(bool &recommend_const_eval);
 		void replace_variables(std::map<std::string, varinfo_t> &variables, AstNode *fcall);
 		AstNode *eval_const_function(AstNode *fcall);
+		bool is_simple_const_expr();
 
 		// create a human-readable text representation of the AST (for debugging)
 		void dumpAst(FILE *f, std::string indent) const;
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index d0b31078a..7160c6c0f 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -328,6 +328,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		for (size_t i = 0; i < children.size(); i++) {
 			AstNode *node = children[i];
 			if (node->type == AST_WIRE) {
+				if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
+					for (auto c : node->children[0]->children) {
+						if (!c->is_simple_const_expr()) {
+							if (attributes.count("\\dynports"))
+								delete attributes.at("\\dynports");
+							attributes["\\dynports"] = AstNode::mkconst_int(1, true);
+						}
+					}
+				}
 				if (this_wire_scope.count(node->str) > 0) {
 					AstNode *first_node = this_wire_scope[node->str];
 					if (first_node->is_input && node->is_reg)
@@ -3323,6 +3332,16 @@ bool AstNode::has_const_only_constructs(bool &recommend_const_eval)
 	return false;
 }
 
+bool AstNode::is_simple_const_expr()
+{
+	if (type == AST_IDENTIFIER)
+		return false;
+	for (auto child : children)
+		if (!child->is_simple_const_expr())
+			return false;
+	return true;
+}
+
 // helper function for AstNode::eval_const_function()
 void AstNode::replace_variables(std::map<std::string, AstNode::varinfo_t> &variables, AstNode *fcall)
 {
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 2d8edebb5..88c339e8c 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -910,7 +910,7 @@ struct HierarchyPass : public Pass {
 			if (m == nullptr)
 				continue;
 
-			if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty()) {
+			if (m->get_bool_attribute("\\blackbox") && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) {
 				IdString new_m_name = m->derive(design, cell->parameters, true);
 				if (new_m_name.empty())
 					continue;

From a176ac95ded8b5aa9efb98b7a8e6981c90827d0e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Mar 2019 21:35:57 -0800
Subject: [PATCH 441/528] Update igloo2 example to Libero v12.0

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/libero.tcl | 9 ++++-----
 examples/igloo2/runme.sh   | 2 +-
 2 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 1f3476316..82e614cd4 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -15,6 +15,7 @@ new_project \
 import_files -hdl_source {netlist.vm}
 import_files -sdc {example.sdc}
 import_files -io_pdc {example.pdc}
+build_design_hierarchy
 set_option -synth 0
 
 organize_tool_files -tool PLACEROUTE \
@@ -44,10 +45,8 @@ puts "**> VERIFYTIMING"
 run_tool -name {VERIFYTIMING}
 puts "<** VERIFYTIMING"
 
-save_project
-
-# puts "**> export_bitstream"
-# export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
-# puts "<** export_bitstream"
+puts "**> export_bitstream"
+export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
+puts "<** export_bitstream"
 
 exit 0
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 54247759f..95f2282ba 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,4 +1,4 @@
 #!/bin/bash
 set -ex
 yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
-LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v11.9/Libero/bin/libero SCRIPT:libero.tcl
+LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl

From 107d8848041289bdf3ed85f2ca6c7e02fa9ec774 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 3 Mar 2019 23:54:35 -0800
Subject: [PATCH 442/528] Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/libero.tcl | 9 +++++++--
 examples/igloo2/runme.sh   | 4 +++-
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 82e614cd4..6f7d4e24b 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -33,20 +33,25 @@ configure_tool -name PLACEROUTE \
     -params EFFORT_LEVEL:false \
     -params REPAIR_MIN_DELAY:false
 
+puts ""
 puts "**> COMPILE"
 run_tool -name {COMPILE}
 puts "<** COMPILE"
 
+puts ""
 puts "**> PLACEROUTE"
 run_tool -name {PLACEROUTE}
 puts "<** PLACEROUTE"
 
+puts ""
 puts "**> VERIFYTIMING"
 run_tool -name {VERIFYTIMING}
 puts "<** VERIFYTIMING"
 
-puts "**> export_bitstream"
+puts ""
+puts "**> BITSTREAM"
 export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
-puts "<** export_bitstream"
+puts "<** BITSTREAM"
 
+puts ""
 exit 0
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 95f2282ba..a08894e0a 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,4 +1,6 @@
 #!/bin/bash
 set -ex
 yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
-LM_LICENSE_FILE=1702@`hostname` /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
+export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
+/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
+cp proj/designer/example/export/example.stp .

From 777864d02ea3382c822a764e928e06b6142da6ec Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Mon, 4 Mar 2019 11:18:53 +0000
Subject: [PATCH 443/528] ecp5: Demote conflicting FF init values to a warning

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/ecp5/ecp5_ffinit.cc | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc
index 02945fff4..dbd16cac9 100644
--- a/techlibs/ecp5/ecp5_ffinit.cc
+++ b/techlibs/ecp5/ecp5_ffinit.cc
@@ -79,10 +79,12 @@ struct Ecp5FfinitPass : public Pass {
 						continue;
 
 					if (initbits.count(bit)) {
-						if (initbits.at(bit) != val)
-							log_error("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
+						if (initbits.at(bit) != val) {
+							log_warning("Conflicting init values for signal %s (%s = %s, %s = %s).\n",
 									log_signal(bit), log_signal(SigBit(wire, i)), log_signal(val),
 									log_signal(initbit_to_wire[bit]), log_signal(initbits.at(bit)));
+							initbits.at(bit) = State::Sx;
+						}
 						continue;
 					}
 
@@ -121,6 +123,9 @@ struct Ecp5FfinitPass : public Pass {
 
 				State val = initbits.at(bit_q);
 
+				if (val == State::Sx)
+					continue;
+
 				log("FF init value for cell %s (%s): %s = %c\n", log_id(cell), log_id(cell->type),
 						log_signal(bit_q), val != State::S0 ? '1' : '0');
 				// Initval is the same as the reset state. Matches hardware, nowt more to do

From 228f132ec388fd8d0791ed3f0944b850de054370 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Mon, 4 Mar 2019 09:22:22 -0800
Subject: [PATCH 444/528] Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 techlibs/xilinx/brams_map.v | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index 2a23b2553..7ea49158d 100644
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -30,8 +30,8 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(72),
 		.WRITE_WIDTH_B(72),
-		.WRITE_MODE_A("WRITE_FIRST"),
-		.WRITE_MODE_B("WRITE_FIRST"),
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST"),
 		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 		`include "brams_init_36.vh"
@@ -95,8 +95,8 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 		.RAM_MODE("SDP"),
 		.READ_WIDTH_A(36),
 		.WRITE_WIDTH_B(36),
-		.WRITE_MODE_A("WRITE_FIRST"),
-		.WRITE_MODE_B("WRITE_FIRST"),
+		.WRITE_MODE_A("READ_FIRST"),
+		.WRITE_MODE_B("READ_FIRST"),
 		.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 		.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 		`include "brams_init_18.vh"
@@ -171,8 +171,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_36.vh"
@@ -209,8 +209,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_32.vh"
@@ -285,8 +285,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_18.vh"
@@ -323,8 +323,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA,
 			.READ_WIDTH_B(CFG_DBITS),
 			.WRITE_WIDTH_A(CFG_DBITS),
 			.WRITE_WIDTH_B(CFG_DBITS),
-			.WRITE_MODE_A("WRITE_FIRST"),
-			.WRITE_MODE_B("WRITE_FIRST"),
+			.WRITE_MODE_A("READ_FIRST"),
+			.WRITE_MODE_B("READ_FIRST"),
 			.IS_CLKARDCLK_INVERTED(!CLKPOL2),
 			.IS_CLKBWRCLK_INVERTED(!CLKPOL3),
 			`include "brams_init_16.vh"

From 32a901ddf21711e2b2fe2a0a8719ff7f69fd9489 Mon Sep 17 00:00:00 2001
From: Kali Prasad <kprasadvnsi@pm.me>
Date: Mon, 4 Mar 2019 23:26:56 +0530
Subject: [PATCH 445/528] Added examples/anlogic/

---
 examples/anlogic/.gitignore |  4 ++++
 examples/anlogic/README     | 13 +++++++++++++
 examples/anlogic/build.sh   |  4 ++++
 examples/anlogic/build.tcl  | 11 +++++++++++
 examples/anlogic/demo.adc   |  2 ++
 examples/anlogic/demo.v     | 18 ++++++++++++++++++
 examples/anlogic/demo.ys    |  3 +++
 7 files changed, 55 insertions(+)
 create mode 100644 examples/anlogic/.gitignore
 create mode 100644 examples/anlogic/README
 create mode 100755 examples/anlogic/build.sh
 create mode 100644 examples/anlogic/build.tcl
 create mode 100644 examples/anlogic/demo.adc
 create mode 100644 examples/anlogic/demo.v
 create mode 100644 examples/anlogic/demo.ys

diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore
new file mode 100644
index 000000000..fa9424cd8
--- /dev/null
+++ b/examples/anlogic/.gitignore
@@ -0,0 +1,4 @@
+demo.bit
+demo_phy.area
+full.v
+*.log
\ No newline at end of file
diff --git a/examples/anlogic/README b/examples/anlogic/README
new file mode 100644
index 000000000..99143cce0
--- /dev/null
+++ b/examples/anlogic/README
@@ -0,0 +1,13 @@
+LED Blink project for Anlogic Lichee Tang board.
+
+Follow the install instructions for the Tang Dynasty IDE from given link below.
+
+https://tang.sipeed.com/en/getting-started/installing-td-ide/linux/
+
+
+set TD_HOME env variable to the full path to the TD <TD Install Directory> as follow.
+
+export TD_HOME=<TD Install Directory>
+
+then run "bash build.sh" in this directory.
+
diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh
new file mode 100755
index 000000000..8b77a32d6
--- /dev/null
+++ b/examples/anlogic/build.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+set -ex
+yosys demo.ys
+$TD_HOME/bin/td build.tcl
\ No newline at end of file
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl
new file mode 100644
index 000000000..db8c3b347
--- /dev/null
+++ b/examples/anlogic/build.tcl
@@ -0,0 +1,11 @@
+import_device eagle_s20.db -package BG256
+read_verilog full.v -top demo
+read_adc demo.adc
+optimize_rtl
+map_macro
+map
+pack
+place
+route
+report_area -io_info -file demo_phy.area
+bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000
diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc
new file mode 100644
index 000000000..c8fbaed3e
--- /dev/null
+++ b/examples/anlogic/demo.adc
@@ -0,0 +1,2 @@
+set_pin_assignment {CLK_IN} { LOCATION = K14;  } ##24MHZ
+set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
\ No newline at end of file
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
new file mode 100644
index 000000000..a7edf4e37
--- /dev/null
+++ b/examples/anlogic/demo.v
@@ -0,0 +1,18 @@
+module demo (
+    input wire CLK_IN,  
+    output wire R_LED 
+);
+    parameter time1 = 30'd12_000_000;
+    reg led_state;
+    reg [29:0] count;
+    
+    always @(posedge CLK_IN)begin
+        if(count == time1)begin
+            count<= 30'd0; 	
+            led_state <= ~led_state;
+        end
+        else
+            count <= count + 1'b1;
+    end
+    assign R_LED = led_state;
+endmodule
\ No newline at end of file
diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys
new file mode 100644
index 000000000..5687bcd31
--- /dev/null
+++ b/examples/anlogic/demo.ys
@@ -0,0 +1,3 @@
+read_verilog demo.v
+synth_anlogic -top demo
+write_verilog full.v
\ No newline at end of file

From d6c4dfb9020ee19eebe3adadca89b65627184d81 Mon Sep 17 00:00:00 2001
From: Jim Lawson <ucbjrl@berkeley.edu>
Date: Mon, 4 Mar 2019 13:23:58 -0800
Subject: [PATCH 446/528] Ensure fid() calls make_id() for consistency;
 tests/simple/dff_init.v fails Mark dff_init.v as expected to fail since it
 uses "initial value".

---
 backends/firrtl/firrtl.cc | 3 +--
 tests/simple/xfirrtl      | 1 +
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 88c1038b7..eef6401b2 100644
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -165,8 +165,7 @@ struct FirrtlWorker
 
 	std::string fid(RTLIL::IdString internal_id)
 	{
-		const char *str = internal_id.c_str();
-		return *str == '\\' ? str + 1 : str;
+		return make_id(internal_id);
 	}
 
 	std::string cellname(RTLIL::Cell *cell)
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl
index 5bc75347b..50d693513 100644
--- a/tests/simple/xfirrtl
+++ b/tests/simple/xfirrtl
@@ -1,6 +1,7 @@
 # This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
 arraycells.v	inst id[0] of
 dff_different_styles.v
+dff_init.v	Initial value not supported
 generate.v	combinational loop
 hierdefparam.v	inst id[0] of
 i2c_master_tests.v   $adff

From 13844c765818b5d8c0d16d62dcc530f688d2c28a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 15:16:13 -0800
Subject: [PATCH 447/528] Use "write_edif -pvector bra" for Xilinx EDIF files

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/xilinx/synth_xilinx.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 6c11d885d..3632f348f 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -252,7 +252,7 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "edif"))
 		{
 			if (!edif_file.empty())
-				Pass::call(design, stringf("write_edif %s", edif_file.c_str()));
+				Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
 		}
 		if (check_label(active, run_from, run_to, "blif"))
 		{

From 3ef427f4a96ac8f890cf94079315e172db409526 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 15:21:04 -0800
Subject: [PATCH 448/528] Add missing newline

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/anlogic/build.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/anlogic/build.sh b/examples/anlogic/build.sh
index 8b77a32d6..e0f6b4cfe 100755
--- a/examples/anlogic/build.sh
+++ b/examples/anlogic/build.sh
@@ -1,4 +1,4 @@
 #!/bin/bash
 set -ex
 yosys demo.ys
-$TD_HOME/bin/td build.tcl
\ No newline at end of file
+$TD_HOME/bin/td build.tcl

From 24d1b92eda20269da7ee7ae713f3ab92b8865349 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 17:27:58 -0800
Subject: [PATCH 449/528] Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.pdc |  7 +++++++
 examples/igloo2/example.sdc |  1 +
 examples/igloo2/example.v   | 12 ++++++------
 examples/igloo2/libero.tcl  |  4 ++--
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
index e6ffd53db..0cf34adb3 100644
--- a/examples/igloo2/example.pdc
+++ b/examples/igloo2/example.pdc
@@ -1 +1,8 @@
 # Add placement constraints here
+set_io clk  -pinname H16 -fixed yes -DIRECTION INPUT
+set_io SW1  -pinname H12 -fixed yes -DIRECTION INPUT
+set_io SW2  -pinname H13 -fixed yes -DIRECTION INPUT
+set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
+set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
+set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
+set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
index c6ff94161..f8b487316 100644
--- a/examples/igloo2/example.sdc
+++ b/examples/igloo2/example.sdc
@@ -1 +1,2 @@
 # Add timing constraints here
+create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}]
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 1a1967d5a..b701c707d 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -1,23 +1,23 @@
 module example (
 	input  clk,
-	input  EN,
+	input  SW1,
+	input  SW2,
 	output LED1,
 	output LED2,
 	output LED3,
-	output LED4,
-	output LED5
+	output LED4
 );
 
-	localparam BITS = 5;
+	localparam BITS = 4;
 	localparam LOG2DELAY = 22;
 
 	reg [BITS+LOG2DELAY-1:0] counter = 0;
 	reg [BITS-1:0] outcnt;
 
 	always @(posedge clk) begin
-		counter <= counter + EN;
+		counter <= counter + SW1 + SW2 + 1;
 		outcnt <= counter >> LOG2DELAY;
 	end
 
-	assign {LED1, LED2, LED3, LED4, LED5} = outcnt ^ (outcnt >> 1);
+	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
 endmodule
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
index 6f7d4e24b..abc94e479 100644
--- a/examples/igloo2/libero.tcl
+++ b/examples/igloo2/libero.tcl
@@ -8,8 +8,8 @@ new_project \
     -block_mode 0 \
     -hdl "VERILOG" \
     -family IGLOO2 \
-    -die PA4MGL500 \
-    -package tq144 \
+    -die PA4MGL2500 \
+    -package vf256 \
     -speed -1
 
 import_files -hdl_source {netlist.vm}

From d03780c3f463bb8ac2c5d300ba7a591f1bc90a8f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 5 Mar 2019 17:55:29 -0800
Subject: [PATCH 450/528] Fix spelling in pmgen/README.md

---
 passes/pmgen/README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/pmgen/README.md b/passes/pmgen/README.md
index a1007dc62..223b43059 100644
--- a/passes/pmgen/README.md
+++ b/passes/pmgen/README.md
@@ -16,7 +16,7 @@ API of Generated Matcher
 ========================
 
 When `pmgen.py` reads a `foobar.pmg` file, it writes `foobar_pm.h` containing
-a class `foobar_pm`. That class is instanciated with an RTLIL module and a
+a class `foobar_pm`. That class is instantiated with an RTLIL module and a
 list of cells from that module:
 
     foobar_pm pm(module, module->selected_cells());
@@ -142,7 +142,7 @@ The `select` lines are evaluated once for each cell when the matcher is
 initialized. A `match` block will only consider cells for which all `select`
 expressions evaluated to `true`. Note that the state variable corresponding to
 the match (in the example `mul`) is the only state variable that may be used
-`select` lines.
+in `select` lines.
 
 Index lines are using the `index <type> expr1 === expr2` syntax.  `expr1` is
 evaluated during matcher initialization and the same restrictions apply as for

From 7c03b0b08209c7e1b3972a05db63b23c0b1d7a5e Mon Sep 17 00:00:00 2001
From: Kali Prasad <kprasadvnsi@pm.me>
Date: Wed, 6 Mar 2019 09:51:11 +0530
Subject: [PATCH 451/528] examples/anlogic/ now also output the SVF file.

---
 examples/anlogic/.gitignore |  5 ++++-
 examples/anlogic/README     |  1 -
 examples/anlogic/build.tcl  |  2 +-
 examples/anlogic/demo.adc   |  2 +-
 examples/anlogic/demo.v     | 10 +++++-----
 examples/anlogic/demo.ys    |  2 +-
 6 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/examples/anlogic/.gitignore b/examples/anlogic/.gitignore
index fa9424cd8..97c978a15 100644
--- a/examples/anlogic/.gitignore
+++ b/examples/anlogic/.gitignore
@@ -1,4 +1,7 @@
 demo.bit
 demo_phy.area
 full.v
-*.log
\ No newline at end of file
+*.log
+*.h
+*.tde
+*.svf
diff --git a/examples/anlogic/README b/examples/anlogic/README
index 99143cce0..35d8e9cb1 100644
--- a/examples/anlogic/README
+++ b/examples/anlogic/README
@@ -10,4 +10,3 @@ set TD_HOME env variable to the full path to the TD <TD Install Directory> as fo
 export TD_HOME=<TD Install Directory>
 
 then run "bash build.sh" in this directory.
-
diff --git a/examples/anlogic/build.tcl b/examples/anlogic/build.tcl
index db8c3b347..06db525c9 100644
--- a/examples/anlogic/build.tcl
+++ b/examples/anlogic/build.tcl
@@ -8,4 +8,4 @@ pack
 place
 route
 report_area -io_info -file demo_phy.area
-bitgen -bit demo.bit -version 0X00 -g ucode:00000000000000000000000000000000
+bitgen -bit demo.bit -version 0X0000 -svf demo.svf -svf_comment_on -g ucode:00000000000000000000000000000000
diff --git a/examples/anlogic/demo.adc b/examples/anlogic/demo.adc
index c8fbaed3e..ec802502e 100644
--- a/examples/anlogic/demo.adc
+++ b/examples/anlogic/demo.adc
@@ -1,2 +1,2 @@
 set_pin_assignment {CLK_IN} { LOCATION = K14;  } ##24MHZ
-set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
\ No newline at end of file
+set_pin_assignment {R_LED} { LOCATION = R3;  } ##R_LED
diff --git a/examples/anlogic/demo.v b/examples/anlogic/demo.v
index a7edf4e37..e17db771e 100644
--- a/examples/anlogic/demo.v
+++ b/examples/anlogic/demo.v
@@ -1,18 +1,18 @@
 module demo (
-    input wire CLK_IN,  
-    output wire R_LED 
+    input wire CLK_IN,
+    output wire R_LED
 );
     parameter time1 = 30'd12_000_000;
     reg led_state;
     reg [29:0] count;
-    
+
     always @(posedge CLK_IN)begin
         if(count == time1)begin
-            count<= 30'd0; 	
+            count<= 30'd0;
             led_state <= ~led_state;
         end
         else
             count <= count + 1'b1;
     end
     assign R_LED = led_state;
-endmodule
\ No newline at end of file
+endmodule
diff --git a/examples/anlogic/demo.ys b/examples/anlogic/demo.ys
index 5687bcd31..cb396cc2b 100644
--- a/examples/anlogic/demo.ys
+++ b/examples/anlogic/demo.ys
@@ -1,3 +1,3 @@
 read_verilog demo.v
 synth_anlogic -top demo
-write_verilog full.v
\ No newline at end of file
+write_verilog full.v

From da5181a3df6ceed96f1762e4cdaec5cbe3ea23db Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 19:49:39 -0800
Subject: [PATCH 452/528] Improvements in SF2 flow and demo

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/.gitignore |  1 +
 examples/igloo2/runme.sh   |  2 +-
 techlibs/sf2/sf2_iobs.cc   | 15 ++++++++++-----
 techlibs/sf2/synth_sf2.cc  | 16 +++++++++++++---
 4 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
index ea58efc9f..33b7182d3 100644
--- a/examples/igloo2/.gitignore
+++ b/examples/igloo2/.gitignore
@@ -1,3 +1,4 @@
 /netlist.edn
 /netlist.vm
+/example.stp
 /proj
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index a08894e0a..838f027db 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -ex
-yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
+yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v
 export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
 /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
 cp proj/designer/example/export/example.stp .
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
index 27141430c..a85552575 100644
--- a/techlibs/sf2/sf2_iobs.cc
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -33,18 +33,23 @@ struct Sf2IobsPass : public Pass {
 		log("\n");
 		log("Add SF2 I/O buffers to top module IOs as needed.\n");
 		log("\n");
+		log("    -noclkbuf\n");
+		log("        Do not insert clock buffers\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
+		bool noclkbuf_mode = false;
+
 		log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-singleton") {
-			// 	singleton_mode = true;
-			// 	continue;
-			// }
+			if (args[argidx] == "-noclkbuf") {
+				noclkbuf_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -94,7 +99,7 @@ struct Sf2IobsPass : public Pass {
 				if (wire->port_output) {
 					buf_type = "\\OUTBUF";
 					buf_port = "\\D";
-				} else if (clk_bits.count(canonical_bit)) {
+				} else if (clk_bits.count(canonical_bit) && !noclkbuf_mode) {
 					buf_type = "\\CLKBUF";
 					buf_port = "\\Y";
 				} else {
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index bdc20456d..b834af07d 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -63,6 +63,9 @@ struct SynthSf2Pass : public ScriptPass
 		log("    -noiobs\n");
 		log("        run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
 		log("\n");
+		log("    -noclkbuf\n");
+		log("        do not inser clock buffers, only simpe IO buffers\n");
+		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
 		log("\n");
@@ -73,7 +76,7 @@ struct SynthSf2Pass : public ScriptPass
 	}
 
 	string top_opt, edif_file, vlog_file, json_file;
-	bool flatten, retime, iobs;
+	bool flatten, retime, iobs, clkbuf;
 
 	void clear_flags() YS_OVERRIDE
 	{
@@ -84,6 +87,7 @@ struct SynthSf2Pass : public ScriptPass
 		flatten = true;
 		retime = false;
 		iobs = true;
+		clkbuf = true;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -130,6 +134,10 @@ struct SynthSf2Pass : public ScriptPass
 				iobs = false;
 				continue;
 			}
+			if (args[argidx] == "-noclkbuf") {
+				clkbuf = false;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -201,8 +209,10 @@ struct SynthSf2Pass : public ScriptPass
 
 		if (check_label("map_iobs"))
 		{
-			if (iobs || help_mode)
-				run("sf2_iobs", "(unless -noiobs)");
+			if (help_mode)
+				run("sf2_iobs [-noclkbuf]", "(unless -noiobs)");
+			else if (iobs)
+				run(clkbuf ? "sf2_iobs" : "sf2_iobs -noclkbuf");
 			run("clean");
 		}
 

From e22afeae907e6340aac7797f60c309916fd72097 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 20:35:48 -0800
Subject: [PATCH 453/528] Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.pdc | 12 ++++++++++
 examples/igloo2/example.v   | 44 +++++++++++++++++++++++++++++++++++--
 2 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
index 0cf34adb3..298d9e934 100644
--- a/examples/igloo2/example.pdc
+++ b/examples/igloo2/example.pdc
@@ -1,8 +1,20 @@
 # Add placement constraints here
+
 set_io clk  -pinname H16 -fixed yes -DIRECTION INPUT
+
 set_io SW1  -pinname H12 -fixed yes -DIRECTION INPUT
 set_io SW2  -pinname H13 -fixed yes -DIRECTION INPUT
+
 set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
 set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
 set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
 set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT
+
+set_io AA   -pinname L12 -fixed yes -DIRECTION OUTPUT
+set_io AB   -pinname L13 -fixed yes -DIRECTION OUTPUT
+set_io AC   -pinname M13 -fixed yes -DIRECTION OUTPUT
+set_io AD   -pinname N15 -fixed yes -DIRECTION OUTPUT
+set_io AE   -pinname L11 -fixed yes -DIRECTION OUTPUT
+set_io AF   -pinname L14 -fixed yes -DIRECTION OUTPUT
+set_io AG   -pinname N14 -fixed yes -DIRECTION OUTPUT
+set_io CA   -pinname M15 -fixed yes -DIRECTION OUTPUT
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index b701c707d..05b6ced5e 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -5,10 +5,13 @@ module example (
 	output LED1,
 	output LED2,
 	output LED3,
-	output LED4
+	output LED4,
+
+	output AA, AB, AC, AD,
+	output AE, AF, AG, CA
 );
 
-	localparam BITS = 4;
+	localparam BITS = 8;
 	localparam LOG2DELAY = 22;
 
 	reg [BITS+LOG2DELAY-1:0] counter = 0;
@@ -20,4 +23,41 @@ module example (
 	end
 
 	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
+
+	// seg7enc seg7encinst (
+	// 	.seg({AA, AB, AC, AD, AE, AF, AG}),
+	// 	.dat(CA ? outcnt[3:0] : outcnt[7:4])
+	// );
+
+	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]);
+	assign CA = counter[10];
+endmodule
+
+module seg7enc (
+	input [3:0] dat,
+	output [6:0] seg
+);
+	reg [6:0] seg_inv;
+	always @* begin
+		seg_inv = 0;
+		case (dat)
+			4'h0: seg_inv = 7'b 0111111;
+			4'h1: seg_inv = 7'b 0000110;
+			4'h2: seg_inv = 7'b 1011011;
+			4'h3: seg_inv = 7'b 1001111;
+			4'h4: seg_inv = 7'b 1100110;
+			4'h5: seg_inv = 7'b 1101101;
+			4'h6: seg_inv = 7'b 1111101;
+			4'h7: seg_inv = 7'b 0000111;
+			4'h8: seg_inv = 7'b 1111111;
+			4'h9: seg_inv = 7'b 1101111;
+			4'hA: seg_inv = 7'b 1110111;
+			4'hB: seg_inv = 7'b 1111100;
+			4'hC: seg_inv = 7'b 0111001;
+			4'hD: seg_inv = 7'b 1011110;
+			4'hE: seg_inv = 7'b 1111001;
+			4'hF: seg_inv = 7'b 1110001;
+		endcase
+	end
+	assign seg = ~seg_inv;
 endmodule

From b1b9edf5cc9e280346ffa0132d570a8ff656eb22 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 5 Mar 2019 20:47:07 -0800
Subject: [PATCH 454/528] Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/example.v | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
index 05b6ced5e..4a9486e50 100644
--- a/examples/igloo2/example.v
+++ b/examples/igloo2/example.v
@@ -24,13 +24,14 @@ module example (
 
 	assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
 
+	// assign CA = counter[10];
 	// seg7enc seg7encinst (
 	// 	.seg({AA, AB, AC, AD, AE, AF, AG}),
 	// 	.dat(CA ? outcnt[3:0] : outcnt[7:4])
 	// );
 
-	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[7:4]);
-	assign CA = counter[10];
+	assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
+	assign CA = outcnt[7];
 endmodule
 
 module seg7enc (

From 78762316aabf6d6fb55cfd4ab5b5a161a69ba203 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Mar 2019 00:41:02 -0800
Subject: [PATCH 455/528] Refactor SF2 iobuf insertion, Add clkint insertion

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 examples/igloo2/runme.sh  |   2 +-
 techlibs/sf2/cells_sim.v  |   7 ++
 techlibs/sf2/sf2_iobs.cc  | 214 ++++++++++++++++++++++++--------------
 techlibs/sf2/synth_sf2.cc |  14 +--
 4 files changed, 153 insertions(+), 84 deletions(-)

diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
index 838f027db..a08894e0a 100644
--- a/examples/igloo2/runme.sh
+++ b/examples/igloo2/runme.sh
@@ -1,6 +1,6 @@
 #!/bin/bash
 set -ex
-yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v
+yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
 export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
 /opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
 cp proj/designer/example/export/example.stp .
diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index f967068af..b49101616 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -74,6 +74,13 @@ module CFG4 (
 	assign Y = INIT >> {D, C, B, A};
 endmodule
 
+module CLKINT (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
 module CLKBUF (
 	input PAD,
 	output Y
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
index a85552575..dea8e353b 100644
--- a/techlibs/sf2/sf2_iobs.cc
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -23,6 +23,136 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+static void handle_iobufs(Module *module, bool clkbuf_mode)
+{
+	SigMap sigmap(module);
+
+	pool<SigBit> clk_bits;
+	pool<SigBit> handled_io_bits;
+	dict<SigBit, SigBit> rewrite_bits;
+	vector<pair<Cell*, SigBit>> pad_bits;
+
+	for (auto cell : module->cells())
+	{
+		if (clkbuf_mode && cell->type == "\\SLE") {
+			for (auto bit : sigmap(cell->getPort("\\CLK")))
+				clk_bits.insert(bit);
+		}
+		if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
+				"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUF_DIFF", "\\CLKBUF_DIFF",
+				"\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
+			for (auto bit : sigmap(cell->getPort("\\PAD")))
+				handled_io_bits.insert(bit);
+		}
+	}
+
+	for (auto wire : vector<Wire*>(module->wires()))
+	{
+		if (!wire->port_input && !wire->port_output)
+			continue;
+
+		for (int index = 0; index < GetSize(wire); index++)
+		{
+			SigBit bit(wire, index);
+			SigBit canonical_bit = sigmap(bit);
+
+			if (handled_io_bits.count(canonical_bit))
+				continue;
+
+			if (wire->port_input && wire->port_output)
+				log_error("Failed to add buffer for inout port bit %s.\n", log_signal(bit));
+
+			IdString buf_type, buf_port;
+
+			if (wire->port_output) {
+				buf_type = "\\OUTBUF";
+				buf_port = "\\D";
+			} else if (clkbuf_mode && clk_bits.count(canonical_bit)) {
+				buf_type = "\\CLKBUF";
+				buf_port = "\\Y";
+			} else {
+				buf_type = "\\INBUF";
+				buf_port = "\\Y";
+			}
+
+			Cell *c = module->addCell(NEW_ID, buf_type);
+			SigBit new_bit = module->addWire(NEW_ID);
+			c->setPort(buf_port, new_bit);
+			pad_bits.push_back(make_pair(c, bit));
+			rewrite_bits[canonical_bit] = new_bit;
+
+			log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
+		}
+	}
+
+	auto rewrite_function = [&](SigSpec &s) {
+		for (auto &bit : s) {
+			SigBit canonical_bit = sigmap(bit);
+			if (rewrite_bits.count(canonical_bit))
+				bit = rewrite_bits.at(canonical_bit);
+		}
+	};
+
+	module->rewrite_sigspecs(rewrite_function);
+
+	for (auto &it : pad_bits)
+		it.first->setPort("\\PAD", it.second);
+}
+
+static void handle_clkint(Module *module)
+{
+	SigMap sigmap(module);
+
+	pool<SigBit> clk_bits;
+	vector<SigBit> handled_clk_bits;
+
+	for (auto cell : module->cells())
+	{
+		if (cell->type == "\\SLE") {
+			for (auto bit : sigmap(cell->getPort("\\CLK")))
+				clk_bits.insert(bit);
+		}
+		if (cell->type.in("\\CLKBUF", "\\CLKBIBUF", "\\CLKBUF_DIFF", "\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF",
+				"\\CLKINT", "\\CLKINT_PRESERVE", "\\GCLKINT", "\\RCLKINT", "\\RGCLKINT")) {
+			for (auto bit : sigmap(cell->getPort("\\Y")))
+				handled_clk_bits.push_back(bit);
+		}
+	}
+
+	for (auto bit : handled_clk_bits)
+		clk_bits.erase(bit);
+
+	for (auto cell : vector<Cell*>(module->cells()))
+	for (auto &conn : cell->connections())
+	{
+		if (!cell->output(conn.first))
+			continue;
+
+		SigSpec sig = conn.second;
+		bool did_something = false;
+
+		for (auto &bit : sig) {
+			SigBit canonical_bit = sigmap(bit);
+			if (clk_bits.count(canonical_bit)) {
+				Cell *c = module->addCell(NEW_ID, "\\CLKINT");
+				SigBit new_bit = module->addWire(NEW_ID);
+				c->setPort("\\A", new_bit);
+				c->setPort("\\Y", bit);
+				log("Added %s cell %s for clock signal %s.\n", log_id(c->type), log_id(c), log_signal(bit));
+				clk_bits.erase(canonical_bit);
+				did_something = true;
+				bit = new_bit;
+			}
+		}
+
+		if (did_something)
+			cell->setPort(conn.first, sig);
+	}
+
+	for (auto bit : clk_bits)
+		log_error("Failed to insert CLKINT for clock signal %s.\n", log_signal(bit));
+}
+
 struct Sf2IobsPass : public Pass {
 	Sf2IobsPass() : Pass("sf2_iobs", "SF2: insert IO buffers") { }
 	void help() YS_OVERRIDE
@@ -31,23 +161,23 @@ struct Sf2IobsPass : public Pass {
 		log("\n");
 		log("    sf2_iobs [options] [selection]\n");
 		log("\n");
-		log("Add SF2 I/O buffers to top module IOs as needed.\n");
+		log("Add SF2 I/O buffers and global buffers to top module as needed.\n");
 		log("\n");
-		log("    -noclkbuf\n");
-		log("        Do not insert clock buffers\n");
+		log("    -clkbuf\n");
+		log("        Insert PAD->global_net clock buffers\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		bool noclkbuf_mode = false;
+		bool clkbuf_mode = false;
 
 		log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			if (args[argidx] == "-noclkbuf") {
-				noclkbuf_mode = true;
+			if (args[argidx] == "-clkbuf") {
+				clkbuf_mode = true;
 				continue;
 			}
 			break;
@@ -59,76 +189,8 @@ struct Sf2IobsPass : public Pass {
 		if (module == nullptr)
 			log_cmd_error("No top module found.\n");
 
-		SigMap sigmap(module);
-
-		pool<SigBit> clk_bits;
-		pool<SigBit> handled_io_bits;
-		dict<SigBit, SigBit> rewrite_bits;
-		vector<pair<Cell*, SigBit>> pad_bits;
-
-		for (auto cell : module->cells())
-		{
-			if (cell->type == "\\SLE") {
-				for (auto bit : sigmap(cell->getPort("\\CLK")))
-					clk_bits.insert(bit);
-			}
-			if (cell->type.in("\\INBUF", "\\OUTBUF", "\\CLKBUF")) {
-				for (auto bit : sigmap(cell->getPort("\\PAD")))
-					handled_io_bits.insert(bit);
-			}
-		}
-
-		for (auto wire : vector<Wire*>(module->wires()))
-		{
-			if (!wire->port_input && !wire->port_output)
-				continue;
-
-			for (int index = 0; index < GetSize(wire); index++)
-			{
-				SigBit bit(wire, index);
-				SigBit canonical_bit = sigmap(bit);
-
-				if (handled_io_bits.count(canonical_bit))
-					continue;
-
-				if (wire->port_input && wire->port_output)
-					log_error("Failed to add buffer for inout port bit %s.\n", log_signal(bit));
-
-				IdString buf_type, buf_port;
-
-				if (wire->port_output) {
-					buf_type = "\\OUTBUF";
-					buf_port = "\\D";
-				} else if (clk_bits.count(canonical_bit) && !noclkbuf_mode) {
-					buf_type = "\\CLKBUF";
-					buf_port = "\\Y";
-				} else {
-					buf_type = "\\INBUF";
-					buf_port = "\\Y";
-				}
-
-				Cell *c = module->addCell(NEW_ID, buf_type);
-				SigBit new_bit = module->addWire(NEW_ID);
-				c->setPort(buf_port, new_bit);
-				pad_bits.push_back(make_pair(c, bit));
-				rewrite_bits[canonical_bit] = new_bit;
-
-				log("Added %s cell %s for port bit %s.\n", log_id(c->type), log_id(c), log_signal(bit));
-			}
-		}
-
-		auto rewrite_function = [&](SigSpec &s) {
-			for (auto &bit : s) {
-				SigBit canonical_bit = sigmap(bit);
-				if (rewrite_bits.count(canonical_bit))
-					bit = rewrite_bits.at(canonical_bit);
-			}
-		};
-
-		module->rewrite_sigspecs(rewrite_function);
-
-		for (auto &it : pad_bits)
-			it.first->setPort("\\PAD", it.second);
+		handle_iobufs(module, clkbuf_mode);
+		handle_clkint(module);
 	}
 } Sf2IobsPass;
 
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index b834af07d..0924df7a6 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -63,8 +63,8 @@ struct SynthSf2Pass : public ScriptPass
 		log("    -noiobs\n");
 		log("        run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
 		log("\n");
-		log("    -noclkbuf\n");
-		log("        do not inser clock buffers, only simpe IO buffers\n");
+		log("    -clkbuf\n");
+		log("        insert direct PAD->global_net buffers\n");
 		log("\n");
 		log("    -retime\n");
 		log("        run 'abc' with -dff option\n");
@@ -87,7 +87,7 @@ struct SynthSf2Pass : public ScriptPass
 		flatten = true;
 		retime = false;
 		iobs = true;
-		clkbuf = true;
+		clkbuf = false;
 	}
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -134,8 +134,8 @@ struct SynthSf2Pass : public ScriptPass
 				iobs = false;
 				continue;
 			}
-			if (args[argidx] == "-noclkbuf") {
-				clkbuf = false;
+			if (args[argidx] == "-clkbuf") {
+				clkbuf = true;
 				continue;
 			}
 			break;
@@ -210,9 +210,9 @@ struct SynthSf2Pass : public ScriptPass
 		if (check_label("map_iobs"))
 		{
 			if (help_mode)
-				run("sf2_iobs [-noclkbuf]", "(unless -noiobs)");
+				run("sf2_iobs [-clkbuf]", "(unless -noiobs)");
 			else if (iobs)
-				run(clkbuf ? "sf2_iobs" : "sf2_iobs -noclkbuf");
+				run(clkbuf ? "sf2_iobs -clkbuf" : "sf2_iobs");
 			run("clean");
 		}
 

From 2d2c1617ee3015368336ceb014a9cd98c60181ed Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Mar 2019 15:47:54 -0800
Subject: [PATCH 456/528] Add sf2 techmap rules for more FF types

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/sf2/cells_map.v | 64 ++++++++++++++++++++++++----------------
 1 file changed, 39 insertions(+), 25 deletions(-)

diff --git a/techlibs/sf2/cells_map.v b/techlibs/sf2/cells_map.v
index 5b8888294..6ad7807d2 100644
--- a/techlibs/sf2/cells_map.v
+++ b/techlibs/sf2/cells_map.v
@@ -1,40 +1,54 @@
-// module  \$_DFF_N_ (input D, C, output Q); SB_DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C)); endmodule
+module  \$_DFF_N_ (input D, C, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(1'b1), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
 
 module  \$_DFF_P_ (input D, C, output Q);
-  SLE _TECHMAP_REPLACE_ (
-    .D(D),
-    .CLK(C),
-    .EN(1'b1),
-    .ALn(1'b1),
-    .ADn(1'b1),
-    .SLn(1'b1),
-    .SD(1'b0),
-    .LAT(1'b0),
-    .Q(Q)
-  );
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(1'b1), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_NN0_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_NN1_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_NP0_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(!R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_NP1_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(!C), .EN(1'b1), .ALn(!R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_PN0_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_PN1_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_PP0_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(!R), .ADn(1'b1), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
+endmodule
+
+module \$_DFF_PP1_ (input D, C, R, output Q);
+  SLE _TECHMAP_REPLACE_ (.D(D), .CLK(C), .EN(1'b1), .ALn(!R), .ADn(1'b0), .SLn(1'b1), .SD(1'b0), .LAT(1'b0), .Q(Q));
 endmodule
 
 // module  \$_DFFE_NN_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
 // module  \$_DFFE_PN_ (input D, C, E, output Q); SB_DFFE  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(!E)); endmodule
-// 
+//
 // module  \$_DFFE_NP_ (input D, C, E, output Q); SB_DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
 // module  \$_DFFE_PP_ (input D, C, E, output Q); SB_DFFE  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E)); endmodule
-// 
-// module  \$_DFF_NN0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
-// module  \$_DFF_NN1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
-// module  \$_DFF_PN0_ (input D, C, R, output Q); SB_DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(!R)); endmodule
-// module  \$_DFF_PN1_ (input D, C, R, output Q); SB_DFFS  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(!R)); endmodule
-// 
-// module  \$_DFF_NP0_ (input D, C, R, output Q); SB_DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
-// module  \$_DFF_NP1_ (input D, C, R, output Q); SB_DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
-// module  \$_DFF_PP0_ (input D, C, R, output Q); SB_DFFR  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(R)); endmodule
-// module  \$_DFF_PP1_ (input D, C, R, output Q); SB_DFFS  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .S(R)); endmodule
-// 
+//
 // module  \$__DFFE_NN0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
 // module  \$__DFFE_NN1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
 // module  \$__DFFE_PN0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(!R)); endmodule
 // module  \$__DFFE_PN1 (input D, C, E, R, output Q); SB_DFFES  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(!R)); endmodule
-// 
+//
 // module  \$__DFFE_NP0 (input D, C, E, R, output Q); SB_DFFNER _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule
 // module  \$__DFFE_NP1 (input D, C, E, R, output Q); SB_DFFNES _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(R)); endmodule
 // module  \$__DFFE_PP0 (input D, C, E, R, output Q); SB_DFFER  _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R)); endmodule

From 8b0719d1e328751a50c0c07ec1fc65884fd119fc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 6 Mar 2019 16:18:49 -0800
Subject: [PATCH 457/528] Improvements in sf2 cells_sim.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/sf2/cells_sim.v | 297 ++++++++++++++++++++++++++++++++++-----
 techlibs/sf2/sf2_iobs.cc |   4 +-
 2 files changed, 261 insertions(+), 40 deletions(-)

diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index b49101616..f3f7695cf 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -1,41 +1,3 @@
-module SLE (
-	output Q,
-	input ADn,
-	input ALn,
-	input CLK,
-	input D,
-	input LAT,
-	input SD,
-	input EN,
-	input SLn
-);
-	reg q_latch, q_ff;
-
-	always @(posedge CLK, negedge ALn) begin
-		if (!ALn) begin
-			q_ff <= !ADn;
-		end else if (EN) begin
-			if (!SLn)
-				q_ff <= SD;
-			else
-				q_ff <= D;
-		end
-	end
-
-	always @* begin
-		if (!ALn) begin
-			q_latch <= !ADn;
-		end else if (CLK && EN) begin
-			if (!SLn)
-				q_ff <= SD;
-			else
-				q_ff <= D;
-		end
-	end
-
-	assign Q = LAT ? q_latch : q_ff;
-endmodule
-
 module CFG1 (
 	output Y,
 	input A
@@ -74,6 +36,41 @@ module CFG4 (
 	assign Y = INIT >> {D, C, B, A};
 endmodule
 
+module ADD2 (
+	input A, B,
+	output Y
+);
+	assign Y = A & B;
+endmodule
+
+module ADD3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A & B & C;
+endmodule
+
+module ADD4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A & B & C & D;
+endmodule
+
+module BUFF (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module BUFD (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
 module CLKINT (
 	input A,
 	output Y
@@ -81,6 +78,217 @@ module CLKINT (
 	assign Y = A;
 endmodule
 
+module CLKINT_PRESERVE (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module GCLKINT (
+	input A, EN,
+	output Y
+);
+	assign Y = A & EN;
+endmodule
+
+module RCLKINT (
+	input A,
+	output Y
+);
+	assign Y = A;
+endmodule
+
+module RGCLKINT (
+	input A, EN,
+	output Y
+);
+	assign Y = A & EN;
+endmodule
+
+module SLE (
+	output Q,
+	input ADn,
+	input ALn,
+	input CLK,
+	input D,
+	input LAT,
+	input SD,
+	input EN,
+	input SLn
+);
+	reg q_latch, q_ff;
+
+	always @(posedge CLK, negedge ALn) begin
+		if (!ALn) begin
+			q_ff <= !ADn;
+		end else if (EN) begin
+			if (!SLn)
+				q_ff <= SD;
+			else
+				q_ff <= D;
+		end
+	end
+
+	always @* begin
+		if (!ALn) begin
+			q_latch <= !ADn;
+		end else if (CLK && EN) begin
+			if (!SLn)
+				q_ff <= SD;
+			else
+				q_ff <= D;
+		end
+	end
+
+	assign Q = LAT ? q_latch : q_ff;
+endmodule
+
+// module AR1
+// module FCEND_BUFF
+// module FCINIT_BUFF
+// module FLASH_FREEZE
+// module OSCILLATOR
+// module SYSRESET
+// module SYSCTRL_RESET_STATUS
+// module LIVE_PROBE_FB
+// module GCLKBUF
+// module GCLKBUF_DIFF
+// module GCLKBIBUF
+// module DFN1
+// module DFN1C0
+// module DFN1E1
+// module DFN1E1C0
+// module DFN1E1P0
+// module DFN1P0
+// module DLN1
+// module DLN1C0
+// module DLN1P0
+
+module INV (
+	input A,
+	output Y
+);
+	assign Y = !A;
+endmodule
+
+module INVD (
+	input A,
+	output Y
+);
+	assign Y = !A;
+endmodule
+
+module MX2 (
+	input A, B, S,
+	output Y
+);
+	assign Y = S ? B : A;
+endmodule
+
+module MX4 (
+	input D0, D1, D2, D3, S0, S1,
+	output Y
+);
+	assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);
+endmodule
+
+module NAND2 (
+	input A, B,
+	output Y
+);
+	assign Y = !(A & B);
+endmodule
+
+module NAND3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = !(A & B & C);
+endmodule
+
+module NAND4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = !(A & B & C & D);
+endmodule
+
+module NOR2 (
+	input A, B,
+	output Y
+);
+	assign Y = !(A | B);
+endmodule
+
+module NOR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = !(A | B | C);
+endmodule
+
+module NOR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = !(A | B | C | D);
+endmodule
+
+module OR2 (
+	input A, B,
+	output Y
+);
+	assign Y = A | B;
+endmodule
+
+module OR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A | B | C;
+endmodule
+
+module OR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A | B | C | D;
+endmodule
+
+module XOR2 (
+	input A, B,
+	output Y
+);
+	assign Y = A ^ B;
+endmodule
+
+module XOR3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A ^ B ^ C;
+endmodule
+
+module XOR4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A ^ B ^ C ^ D;
+endmodule
+
+module XOR8 (
+	input A, B, C, D, E, F, G, H,
+	output Y
+);
+	assign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;
+endmodule
+
+// module UJTAG
+// module BIBUF
+// module BIBUF_DIFF
+// module CLKBIBUF
+
 module CLKBUF (
 	input PAD,
 	output Y
@@ -88,6 +296,8 @@ module CLKBUF (
 	assign Y = PAD;
 endmodule
 
+// module CLKBUF_DIFF
+
 module INBUF (
 	input PAD,
 	output Y
@@ -95,9 +305,20 @@ module INBUF (
 	assign Y = PAD;
 endmodule
 
+// module INBUF_DIFF
+
 module OUTBUF (
 	input D,
 	output PAD
 );
 	assign PAD = D;
 endmodule
+
+// module OUTBUF_DIFF
+// module TRIBUFF
+// module TRIBUFF_DIFF
+// module DDR_IN
+// module DDR_OUT
+// module RAM1K18
+// module RAM64x18
+// module MACC
diff --git a/techlibs/sf2/sf2_iobs.cc b/techlibs/sf2/sf2_iobs.cc
index dea8e353b..3d43332e2 100644
--- a/techlibs/sf2/sf2_iobs.cc
+++ b/techlibs/sf2/sf2_iobs.cc
@@ -38,8 +38,8 @@ static void handle_iobufs(Module *module, bool clkbuf_mode)
 			for (auto bit : sigmap(cell->getPort("\\CLK")))
 				clk_bits.insert(bit);
 		}
-		if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
-				"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUF_DIFF", "\\CLKBUF_DIFF",
+		if (cell->type.in("\\INBUF", "\\OUTBUF", "\\TRIBUFF", "\\BIBUF", "\\CLKBUF", "\\CLKBIBUF",
+				"\\INBUF_DIFF", "\\OUTBUF_DIFF", "\\BIBUFF_DIFF", "\\TRIBUFF_DIFF", "\\CLKBUF_DIFF",
 				"\\GCLKBUF", "\\GCLKBUF_DIFF", "\\GCLKBIBUF")) {
 			for (auto bit : sigmap(cell->getPort("\\PAD")))
 				handled_io_bits.insert(bit);

From 350dfd3745ec2efa92a601d3bab7712fd9bec07c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 09:08:26 -0800
Subject: [PATCH 458/528] Add link to SF2 / igloo2 macro library guide

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/sf2/cells_sim.v | 45 +++++++++++++++++++++-------------------
 1 file changed, 24 insertions(+), 21 deletions(-)

diff --git a/techlibs/sf2/cells_sim.v b/techlibs/sf2/cells_sim.v
index f3f7695cf..c62748b11 100644
--- a/techlibs/sf2/cells_sim.v
+++ b/techlibs/sf2/cells_sim.v
@@ -1,3 +1,27 @@
+// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
+
+module ADD2 (
+
+	input A, B,
+	output Y
+);
+	assign Y = A & B;
+endmodule
+
+module ADD3 (
+	input A, B, C,
+	output Y
+);
+	assign Y = A & B & C;
+endmodule
+
+module ADD4 (
+	input A, B, C, D,
+	output Y
+);
+	assign Y = A & B & C & D;
+endmodule
+
 module CFG1 (
 	output Y,
 	input A
@@ -36,27 +60,6 @@ module CFG4 (
 	assign Y = INIT >> {D, C, B, A};
 endmodule
 
-module ADD2 (
-	input A, B,
-	output Y
-);
-	assign Y = A & B;
-endmodule
-
-module ADD3 (
-	input A, B, C,
-	output Y
-);
-	assign Y = A & B & C;
-endmodule
-
-module ADD4 (
-	input A, B, C, D,
-	output Y
-);
-	assign Y = A & B & C & D;
-endmodule
-
 module BUFF (
 	input A,
 	output Y

From cda37830b060fd46834d8eb7af1171a1ffaee8ca Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 10:52:44 -0800
Subject: [PATCH 459/528] Add hack for handling SVA labels via Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verificsva.cc | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index 6681115df..8ea8372d3 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1666,7 +1666,20 @@ struct VerificSvaImporter
 				log("  importing SVA property at root cell %s (%s) at %s:%d.\n", root->Name(), root->View()->Owner()->Name(),
 						LineFile::GetFileName(root->Linefile()), LineFile::GetLineNo(root->Linefile()));
 
-			RTLIL::IdString root_name = module->uniquify(importer->mode_names || root->IsUserDeclared() ? RTLIL::escape_id(root->Name()) : NEW_ID);
+			bool is_user_declared = root->IsUserDeclared();
+
+			// FIXME
+			if (!is_user_declared) {
+				const char *name = root->Name();
+				for (int i = 0; name[i]; i++) {
+					if (i ? (name[i] < '0' || name[i] > '9') : (name[i] != 'i')) {
+						is_user_declared = true;
+						break;
+					}
+				}
+			}
+
+			RTLIL::IdString root_name = module->uniquify(importer->mode_names || is_user_declared ? RTLIL::escape_id(root->Name()) : NEW_ID);
 
 			// parse SVA sequence into trigger signal
 

From 22ff60850e68b5e98d4693a9a06ec688dac6d5ee Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 11:17:32 -0800
Subject: [PATCH 460/528] Add support for SVA labels in read_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc          |  12 +++-
 frontends/ast/simplify.cc          |   1 +
 frontends/verilog/verilog_parser.y | 102 ++++++++++++++++++++++-------
 3 files changed, 89 insertions(+), 26 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 13383845a..d7da6fb40 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1413,10 +1413,16 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			if (GetSize(en) != 1)
 				en = current_module->ReduceBool(NEW_ID, en);
 
-			std::stringstream sstr;
-			sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
+			IdString cellname;
+			if (str.empty()) {
+				std::stringstream sstr;
+				sstr << celltype << "$" << filename << ":" << linenum << "$" << (autoidx++);
+				cellname = sstr.str();
+			} else {
+				cellname = str;
+			}
 
-			RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
+			RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
 
 			for (auto &attr : attributes) {
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 7160c6c0f..bdd8ccb17 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1511,6 +1511,7 @@ skip_dynamic_range_lvalue_expansion:;
 		newNode->children.push_back(assign_en);
 
 		AstNode *assertnode = new AstNode(type);
+		assertnode->str = str;
 		assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
 		assertnode->children.push_back(new AstNode(AST_IDENTIFIER));
 		assertnode->children[0]->str = id_check;
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index a6718b020..2258f3f6f 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -126,7 +126,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
-%type <string> opt_label tok_prim_wrapper hierarchical_id
+%type <string> opt_label opt_stmt_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
 
@@ -1338,7 +1338,12 @@ opt_property:
 	};
 
 opt_stmt_label:
-	TOK_ID ':' | /* empty */;
+	TOK_ID ':' {
+		$$ = $1;
+	} |
+	/* empty */ {
+		$$ = NULL;
+	};
 
 modport_stmt:
     TOK_MODPORT TOK_ID {
@@ -1377,53 +1382,104 @@ modport_type_token:
 
 assert:
 	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
-		if (noassert_mode)
+		if (noassert_mode) {
 			delete $5;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
+		} else {
+			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' {
-		if (noassume_mode)
+		if (noassume_mode) {
 			delete $5;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5));
+		} else {
+			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
 	} |
 	opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (noassert_mode)
+		if (noassert_mode) {
 			delete $6;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
+		} else {
+			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (noassume_mode)
+		if (noassume_mode) {
 			delete $6;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6));
+		} else {
+			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
 	} |
 	opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));
+		AstNode *node = new AstNode(AST_COVER, $5);
+		if ($1 != nullptr) {
+			node->str = *$1;
+			delete $1;
+		}
+		ast_stack.back()->children.push_back(node);
 	} |
 	opt_stmt_label TOK_COVER opt_property '(' ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
+		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
+		if ($1 != nullptr) {
+			node->str = *$1;
+			delete $1;
+		}
+		ast_stack.back()->children.push_back(node);
 	} |
 	opt_stmt_label TOK_COVER ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, AstNode::mkconst_int(1, false)));
+		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
+		if ($1 != nullptr) {
+			node->str = *$1;
+			delete $1;
+		}
+		ast_stack.back()->children.push_back(node);
 	} |
 	opt_stmt_label TOK_RESTRICT opt_property '(' expr ')' ';' {
-		if (norestrict_mode)
+		if (norestrict_mode) {
 			delete $5;
-		else
-			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
+		} else {
+			AstNode *node = new AstNode(AST_ASSUME, $5);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
 		if (!$3)
 			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
+		if ($1 != nullptr)
+			delete $1;
 	} |
 	opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (norestrict_mode)
+		if (norestrict_mode) {
 			delete $6;
-		else
-			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
+		} else {
+			AstNode *node = new AstNode(AST_FAIR, $6);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
 		if (!$3)
 			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
+		if ($1 != nullptr)
+			delete $1;
 	};
 
 assert_property:

From 5dfc7becca1f1faf6e77fb3b5d07d97171613d90 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 11:31:46 -0800
Subject: [PATCH 461/528] Use SVA label in smt export if available

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smt2.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 7f3cc94ca..a26bff57b 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -887,8 +887,8 @@ struct Smt2Worker
 
 				string name_a = get_bool(cell->getPort("\\A"));
 				string name_en = get_bool(cell->getPort("\\EN"));
-				decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id,
-						cell->attributes.count("\\src") ? cell->attributes.at("\\src").decode_string().c_str() : get_id(cell)));
+				string infostr = (cell->name[0] == '$' && cell->attributes.count("\\src")) ? cell->attributes.at("\\src").decode_string() : get_id(cell);
+				decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str()));
 
 				if (cell->type == "$cover")
 					decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",

From e71055cfe8f3d90e157174b1fd83a06487a0a6a2 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Thu, 7 Mar 2019 23:48:10 +0100
Subject: [PATCH 462/528] ice40: Add ice40_braminit pass to allow
 initialization of BRAM from file

This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/Makefile.inc      |   1 +
 techlibs/ice40/cells_sim.v       |  88 ++++++++++-------
 techlibs/ice40/ice40_braminit.cc | 159 +++++++++++++++++++++++++++++++
 3 files changed, 211 insertions(+), 37 deletions(-)
 create mode 100644 techlibs/ice40/ice40_braminit.cc

diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc
index 2750901c8..723b59d6f 100644
--- a/techlibs/ice40/Makefile.inc
+++ b/techlibs/ice40/Makefile.inc
@@ -1,5 +1,6 @@
 
 OBJS += techlibs/ice40/synth_ice40.o
+OBJS += techlibs/ice40/ice40_braminit.o
 OBJS += techlibs/ice40/ice40_ffssr.o
 OBJS += techlibs/ice40/ice40_ffinit.o
 OBJS += techlibs/ice40/ice40_opt.o
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 2041693cc..bc36cdd14 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -326,6 +326,8 @@ module SB_RAM40_4K (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 `ifndef BLACKBOX
 	wire [15:0] WMASK_I;
 	wire [15:0] RMASK_I;
@@ -408,43 +410,46 @@ module SB_RAM40_4K (
 	reg [15:0] memory [0:255];
 
 	initial begin
-		for (i=0; i<16; i=i+1) begin
+		if (INIT_FILE != "")
+			$readmemh(INIT_FILE, memory);
+		else
+			for (i=0; i<16; i=i+1) begin
 `ifdef YOSYS
-			memory[ 0*16 + i] <= INIT_0[16*i +: 16];
-			memory[ 1*16 + i] <= INIT_1[16*i +: 16];
-			memory[ 2*16 + i] <= INIT_2[16*i +: 16];
-			memory[ 3*16 + i] <= INIT_3[16*i +: 16];
-			memory[ 4*16 + i] <= INIT_4[16*i +: 16];
-			memory[ 5*16 + i] <= INIT_5[16*i +: 16];
-			memory[ 6*16 + i] <= INIT_6[16*i +: 16];
-			memory[ 7*16 + i] <= INIT_7[16*i +: 16];
-			memory[ 8*16 + i] <= INIT_8[16*i +: 16];
-			memory[ 9*16 + i] <= INIT_9[16*i +: 16];
-			memory[10*16 + i] <= INIT_A[16*i +: 16];
-			memory[11*16 + i] <= INIT_B[16*i +: 16];
-			memory[12*16 + i] <= INIT_C[16*i +: 16];
-			memory[13*16 + i] <= INIT_D[16*i +: 16];
-			memory[14*16 + i] <= INIT_E[16*i +: 16];
-			memory[15*16 + i] <= INIT_F[16*i +: 16];
+				memory[ 0*16 + i] <= INIT_0[16*i +: 16];
+				memory[ 1*16 + i] <= INIT_1[16*i +: 16];
+				memory[ 2*16 + i] <= INIT_2[16*i +: 16];
+				memory[ 3*16 + i] <= INIT_3[16*i +: 16];
+				memory[ 4*16 + i] <= INIT_4[16*i +: 16];
+				memory[ 5*16 + i] <= INIT_5[16*i +: 16];
+				memory[ 6*16 + i] <= INIT_6[16*i +: 16];
+				memory[ 7*16 + i] <= INIT_7[16*i +: 16];
+				memory[ 8*16 + i] <= INIT_8[16*i +: 16];
+				memory[ 9*16 + i] <= INIT_9[16*i +: 16];
+				memory[10*16 + i] <= INIT_A[16*i +: 16];
+				memory[11*16 + i] <= INIT_B[16*i +: 16];
+				memory[12*16 + i] <= INIT_C[16*i +: 16];
+				memory[13*16 + i] <= INIT_D[16*i +: 16];
+				memory[14*16 + i] <= INIT_E[16*i +: 16];
+				memory[15*16 + i] <= INIT_F[16*i +: 16];
 `else
-			memory[ 0*16 + i] = INIT_0[16*i +: 16];
-			memory[ 1*16 + i] = INIT_1[16*i +: 16];
-			memory[ 2*16 + i] = INIT_2[16*i +: 16];
-			memory[ 3*16 + i] = INIT_3[16*i +: 16];
-			memory[ 4*16 + i] = INIT_4[16*i +: 16];
-			memory[ 5*16 + i] = INIT_5[16*i +: 16];
-			memory[ 6*16 + i] = INIT_6[16*i +: 16];
-			memory[ 7*16 + i] = INIT_7[16*i +: 16];
-			memory[ 8*16 + i] = INIT_8[16*i +: 16];
-			memory[ 9*16 + i] = INIT_9[16*i +: 16];
-			memory[10*16 + i] = INIT_A[16*i +: 16];
-			memory[11*16 + i] = INIT_B[16*i +: 16];
-			memory[12*16 + i] = INIT_C[16*i +: 16];
-			memory[13*16 + i] = INIT_D[16*i +: 16];
-			memory[14*16 + i] = INIT_E[16*i +: 16];
-			memory[15*16 + i] = INIT_F[16*i +: 16];
+				memory[ 0*16 + i] = INIT_0[16*i +: 16];
+				memory[ 1*16 + i] = INIT_1[16*i +: 16];
+				memory[ 2*16 + i] = INIT_2[16*i +: 16];
+				memory[ 3*16 + i] = INIT_3[16*i +: 16];
+				memory[ 4*16 + i] = INIT_4[16*i +: 16];
+				memory[ 5*16 + i] = INIT_5[16*i +: 16];
+				memory[ 6*16 + i] = INIT_6[16*i +: 16];
+				memory[ 7*16 + i] = INIT_7[16*i +: 16];
+				memory[ 8*16 + i] = INIT_8[16*i +: 16];
+				memory[ 9*16 + i] = INIT_9[16*i +: 16];
+				memory[10*16 + i] = INIT_A[16*i +: 16];
+				memory[11*16 + i] = INIT_B[16*i +: 16];
+				memory[12*16 + i] = INIT_C[16*i +: 16];
+				memory[13*16 + i] = INIT_D[16*i +: 16];
+				memory[14*16 + i] = INIT_E[16*i +: 16];
+				memory[15*16 + i] = INIT_F[16*i +: 16];
 `endif
-		end
+			end
 	end
 
 	always @(posedge WCLK) begin
@@ -504,6 +509,8 @@ module SB_RAM40_4KNR (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 	SB_RAM40_4K #(
 		.WRITE_MODE(WRITE_MODE),
 		.READ_MODE (READ_MODE ),
@@ -522,7 +529,8 @@ module SB_RAM40_4KNR (
 		.INIT_C    (INIT_C    ),
 		.INIT_D    (INIT_D    ),
 		.INIT_E    (INIT_E    ),
-		.INIT_F    (INIT_F    )
+		.INIT_F    (INIT_F    ),
+		.INIT_FILE (INIT_FILE )
 	) RAM (
 		.RDATA(RDATA),
 		.RCLK (~RCLKN),
@@ -566,6 +574,8 @@ module SB_RAM40_4KNW (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 	SB_RAM40_4K #(
 		.WRITE_MODE(WRITE_MODE),
 		.READ_MODE (READ_MODE ),
@@ -584,7 +594,8 @@ module SB_RAM40_4KNW (
 		.INIT_C    (INIT_C    ),
 		.INIT_D    (INIT_D    ),
 		.INIT_E    (INIT_E    ),
-		.INIT_F    (INIT_F    )
+		.INIT_F    (INIT_F    ),
+		.INIT_FILE (INIT_FILE )
 	) RAM (
 		.RDATA(RDATA),
 		.RCLK (RCLK ),
@@ -628,6 +639,8 @@ module SB_RAM40_4KNRNW (
 	parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 	parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
 
+	parameter INIT_FILE = "";
+
 	SB_RAM40_4K #(
 		.WRITE_MODE(WRITE_MODE),
 		.READ_MODE (READ_MODE ),
@@ -646,7 +659,8 @@ module SB_RAM40_4KNRNW (
 		.INIT_C    (INIT_C    ),
 		.INIT_D    (INIT_D    ),
 		.INIT_E    (INIT_E    ),
-		.INIT_F    (INIT_F    )
+		.INIT_F    (INIT_F    ),
+		.INIT_FILE (INIT_FILE )
 	) RAM (
 		.RDATA(RDATA),
 		.RCLK (~RCLKN),
diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
new file mode 100644
index 000000000..bf12f9148
--- /dev/null
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -0,0 +1,159 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include <stdlib.h>
+#include <stdio.h>
+#include <bitset>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void run_ice40_braminit(Module *module)
+{
+	for (auto cell : module->selected_cells())
+	{
+		uint16_t mem[256];
+
+		/* Only consider cells we're interested in */
+		if (cell->type != "\\SB_RAM40_4K" &&
+		    cell->type != "\\SB_RAM40_4KNR" &&
+		    cell->type != "\\SB_RAM40_4KNW" &&
+		    cell->type != "\\SB_RAM40_4KNRNW")
+			continue;
+		if (!cell->hasParam("\\INIT_FILE"))
+			continue;
+		std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
+		cell->unsetParam("\\INIT_FILE");
+		if (init_file == "")
+			continue;
+
+		/* Open file */
+		log("Processing %s : %s\n", RTLIL::id2cstr(cell->name), init_file.c_str());
+
+		std::ifstream f;
+		f.open(init_file.c_str());
+		if (f.fail()) {
+			log("Can not open file `%s`.\n", init_file.c_str());
+			continue;
+		}
+
+		/* Defaults to 0 */
+		memset(mem, 0x00, sizeof(mem));
+
+		/* Process each line */
+		bool in_comment = false;
+		int cursor = 0;
+
+		while (!f.eof())
+		{
+			std::string line, token;
+			std::getline(f, line);
+
+			for (int i = 0; i < GetSize(line); i++)
+			{
+				if (in_comment && line.substr(i, 2) == "*/") {
+					line[i] = ' ';
+					line[i+1] = ' ';
+					in_comment = false;
+					continue;
+				}
+				if (!in_comment && line.substr(i, 2) == "/*")
+					in_comment = true;
+				if (in_comment)
+					line[i] = ' ';
+			}
+
+			while (1)
+			{
+				bool set_cursor = false;
+				long value;
+
+				token = next_token(line, " \t\r\n");
+				if (token.empty() || token.substr(0, 2) == "//")
+					break;
+
+				if (token[0] == '@') {
+					token = token.substr(1);
+					set_cursor = true;
+				}
+
+				const char *nptr = token.c_str();
+				char *endptr;
+				value = strtol(nptr, &endptr, 16);
+				if (!*nptr || *endptr) {
+					log("Can not parse %s `%s` for %s.\n",
+						set_cursor ? "address" : "value",
+						nptr, token.c_str()
+					);
+					continue;
+				}
+
+				if (set_cursor)
+					cursor = value;
+				else if (cursor >= 0 && cursor < 256)
+					mem[cursor++] = value;
+				else
+					log("Attempt to initialize non existent address %d\n", cursor);
+			}
+		}
+
+		/* Set attributes */
+		const char *hex = "0123456789ABCDEF";
+		for (int i=0; i<16; i++) {
+			std::string val = "";
+			for (int j=15; j>=0; j--)
+				val += std::bitset<16>(mem[i*16+j]).to_string();
+			cell->setParam("\\INIT_" + std::string(1, hex[i]), RTLIL::Const::from_string(val));
+		}
+	}
+}
+
+struct Ice40BRAMInitPass : public Pass {
+	Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    ice40_braminit\n");
+		log("\n");
+		log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
+		log("parameter and converts it inti the required INIT_x attributes\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		log_header(design, "Executing ICE40_BRAMINIT pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			// if (args[argidx] == "-???") {
+			//  continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+			run_ice40_braminit(module);
+	}
+} Ice40BRAMInitPass;
+
+PRIVATE_NAMESPACE_END

From 5b6f59103374413e9c64c4f228853ce06b03ce29 Mon Sep 17 00:00:00 2001
From: Sylvain Munaut <tnt@246tNt.com>
Date: Fri, 8 Mar 2019 00:11:17 +0100
Subject: [PATCH 463/528] ice40: Run ice40_braminit pass by default

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
---
 techlibs/ice40/synth_ice40.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 34501b335..8899bfcc4 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -257,6 +257,7 @@ struct SynthIce40Pass : public ScriptPass
 		{
 			run("memory_bram -rules +/ice40/brams.txt");
 			run("techmap -map +/ice40/brams_map.v");
+			run("ice40_braminit");
 		}
 
 		if (check_label("map"))

From a330c6836318d43d52cda68959f2b86c2b2ede9c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 7 Mar 2019 22:44:37 -0800
Subject: [PATCH 464/528] Fix handling of task output ports in clocked always
 blocks, fixes #857

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 35 +++++++++++++++++++----------------
 tests/simple/task_func.v  | 19 +++++++++++++++++++
 2 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 7160c6c0f..d0274cf78 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2224,6 +2224,8 @@ skip_dynamic_range_lvalue_expansion:;
 		std::map<std::string, std::string> replace_rules;
 		vector<AstNode*> added_mod_children;
 		dict<std::string, AstNode*> wire_cache;
+		vector<AstNode*> new_stmts;
+		vector<AstNode*> output_assignments;
 
 		if (current_block == NULL)
 		{
@@ -2348,8 +2350,8 @@ skip_dynamic_range_lvalue_expansion:;
 					wire->port_id = 0;
 					wire->is_input = false;
 					wire->is_output = false;
-					if (!child->is_output)
-						wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
+					wire->is_reg = true;
+					wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
 					wire_cache[child->str] = wire;
 
 					current_ast_mod->children.push_back(wire);
@@ -2371,13 +2373,10 @@ skip_dynamic_range_lvalue_expansion:;
 							new AstNode(AST_ASSIGN_EQ, wire_id, arg) :
 							new AstNode(AST_ASSIGN_EQ, arg, wire_id);
 					assign->children[0]->was_checked = true;
-
-					for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
-						if (*it != current_block_child)
-							continue;
-						current_block->children.insert(it, assign);
-						break;
-					}
+					if (child->is_input)
+						new_stmts.push_back(assign);
+					else
+						output_assignments.push_back(assign);
 				}
 			}
 
@@ -2391,15 +2390,19 @@ skip_dynamic_range_lvalue_expansion:;
 			{
 				AstNode *stmt = child->clone();
 				stmt->replace_ids(prefix, replace_rules);
-
-				for (auto it = current_block->children.begin(); it != current_block->children.end(); it++) {
-					if (*it != current_block_child)
-						continue;
-					current_block->children.insert(it, stmt);
-					break;
-				}
+				new_stmts.push_back(stmt);
 			}
 
+		new_stmts.insert(new_stmts.end(), output_assignments.begin(), output_assignments.end());
+
+		for (auto it = current_block->children.begin(); ; it++) {
+			log_assert(it != current_block->children.end());
+			if (*it == current_block_child) {
+				current_block->children.insert(it, new_stmts.begin(), new_stmts.end());
+				break;
+			}
+		}
+
 	replace_fcall_with_id:
 		if (type == AST_FCALL) {
 			delete_children();
diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index fa50c1d5c..f6e902f63 100644
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -120,3 +120,22 @@ module task_func_test04(input [7:0] in, output [7:0] out1, out2, out3, out4);
 	assign out3 = test3(in);
 	assign out4 = test4(in);
 endmodule
+
+// -------------------------------------------------------------------
+
+// https://github.com/YosysHQ/yosys/issues/857
+module task_func_test05(data_in,data_out,clk);
+	output reg data_out;
+	input data_in;
+	input clk;
+
+	task myTask;
+		output out;
+		input in;
+		out = in;
+	endtask
+
+	always @(posedge clk) begin
+		myTask(data_out,data_in);
+	end
+endmodule

From 1dc060f32eea0df2ba45770365060251163b2857 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 9 Mar 2019 00:43:50 +0000
Subject: [PATCH 465/528] Fix spelling

---
 frontends/verific/README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/frontends/verific/README b/frontends/verific/README
index c76cdd637..89584f2e8 100644
--- a/frontends/verific/README
+++ b/frontends/verific/README
@@ -21,7 +21,7 @@ Then run in the following command in this directory:
 
 	sby -f example.sby
 
-This will generate approximately one page of text outpout. The last lines
+This will generate approximately one page of text output. The last lines
 should be something like this:
 
 	SBY [example] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0)

From 2aa3903757642616f38d1069e1b706fcbf3168c4 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 9 Mar 2019 01:54:01 +0000
Subject: [PATCH 466/528] Add -chparam option to verific command

---
 frontends/verific/verific.cc | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9f52ffdc2..4ba96d251 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1855,6 +1855,12 @@ struct VerificPass : public Pass {
 		log("  -autocover\n");
 		log("    Generate automatic cover statements for all asserts\n");
 		log("\n");
+		log("  -chparam name value \n");
+		log("    Elaborate the specified top modules (all modules when -all given) using\n");
+		log("    this parameter value, for modules where this parameter exists. This option\n");
+		log("    can be specified multiple times to override multiple parameters.\n");
+		log("    String values must be passed in double quotes (\").\n");
+		log("\n");
 		log("  -v, -vv\n");
 		log("    Verbose log messages. (-vv is even more verbose than -v.)\n");
 		log("\n");
@@ -2109,6 +2115,7 @@ struct VerificPass : public Pass {
 			bool mode_autocover = false;
 			bool flatten = false, extnets = false;
 			string dumpfile;
+			Map parameters(STRING_HASH);
 
 			for (argidx++; argidx < GetSize(args); argidx++) {
 				if (args[argidx] == "-all") {
@@ -2147,6 +2154,15 @@ struct VerificPass : public Pass {
 					mode_autocover = true;
 					continue;
 				}
+				if (args[argidx] == "-chparam"  && argidx+2 < GetSize(args)) {
+                                        const std::string &key = args[++argidx];
+                                        const std::string &value = args[++argidx];
+					unsigned new_insertion = parameters.Insert(key.c_str(), value.c_str(),
+									           1 /* force_overwrite */);
+					if (!new_insertion)
+						log_warning_noprefix("-chparam %s already specified: overwriting.\n", key.c_str());
+					continue;
+				}
 				if (args[argidx] == "-V") {
 					mode_verific = true;
 					continue;
@@ -2180,7 +2196,7 @@ struct VerificPass : public Pass {
 				if (vhdl_lib) vhdl_libs.InsertLast(vhdl_lib);
 				if (veri_lib) veri_libs.InsertLast(veri_lib);
 
-				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs);
+				Array *netlists = hier_tree::ElaborateAll(&veri_libs, &vhdl_libs, &parameters);
 				Netlist *nl;
 				int i;
 
@@ -2217,7 +2233,7 @@ struct VerificPass : public Pass {
 				}
 
 				log("Running hier_tree::Elaborate().\n");
-				Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units);
+				Array *netlists = hier_tree::Elaborate(&veri_modules, &vhdl_units, &parameters);
 				Netlist *nl;
 				int i;
 

From ee013fba54f8bca0940143f655f5b4ad3d7b7b96 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 9 Mar 2019 01:56:16 +0000
Subject: [PATCH 467/528] Update help message for -chparam

---
 frontends/verific/verific.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 4ba96d251..c412cd3a3 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1857,7 +1857,8 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("  -chparam name value \n");
 		log("    Elaborate the specified top modules (all modules when -all given) using\n");
-		log("    this parameter value, for modules where this parameter exists. This option\n");
+		log("    this parameter value. Modules on which this parameter does not exist will\n");
+		log("    cause Verific to produce a VERI-1928 or VHDL-1676 message. This option\n");
 		log("    can be specified multiple times to override multiple parameters.\n");
 		log("    String values must be passed in double quotes (\").\n");
 		log("\n");

From e7a34d342ed1dd01074acdafca4f8f5557f8150f Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 8 Mar 2019 22:53:58 -0800
Subject: [PATCH 468/528] Also add support for labels on sva module items,
 fixes #699

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l  |  57 +++++++++++--
 frontends/verilog/verilog_parser.y | 132 +++++++++++++++++------------
 2 files changed, 129 insertions(+), 60 deletions(-)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index 1b1873e24..e51a12f76 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -189,10 +189,57 @@ YOSYS_NAMESPACE_END
 "always_ff"    { SV_KEYWORD(TOK_ALWAYS); }
 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
 
-"assert"     { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
-"assume"     { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
-"cover"      { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
-"restrict"   { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
+ /* parse labels on assert, assume, cover, and restrict right here because it's insanley complex
+    to do it in the parser (because we force the parser too early to reduce when parsing cells..) */
+([a-zA-Z_$][a-zA-Z0-9_$]*[ \t\r\n]*:[ \t\r\n]*)?(assert|assume|cover|restrict)/[^a-zA-Z0-9_$\.] {
+	frontend_verilog_yylval.string = new std::string(yytext);
+	auto &str = *frontend_verilog_yylval.string;
+	std::string keyword;
+	int cursor = 0;
+
+	while (1) {
+		if (cursor == GetSize(str)) {
+			keyword = str;
+			delete frontend_verilog_yylval.string;
+			frontend_verilog_yylval.string = nullptr;
+			goto sva_without_label;
+		}
+		char c = str[cursor];
+		if (c != ' ' && c != '\t' && c != '\r' && c != '\n' && c != ':') {
+			cursor++;
+			continue;
+		}
+
+		keyword = str.substr(cursor);
+		str = "\\" + str.substr(0, cursor);
+		break;
+	}
+
+	cursor = 0;
+	while (1) {
+		log_assert(cursor < GetSize(keyword));
+		char c = keyword[cursor];
+		if (c != ' ' && c != '\t' && c != '\r' && c != '\n' && c != ':') {
+			keyword = keyword.substr(cursor);
+			break;
+		}
+		cursor++;
+	}
+
+	if      (keyword == "assert")     { return TOK_ASSERT;   }
+	else if (keyword == "assume")     { return TOK_ASSUME;   }
+	else if (keyword == "cover")      { return TOK_COVER;    }
+	else if (keyword == "restrict")   { return TOK_RESTRICT; }
+	else log_abort();
+
+sva_without_label:
+	if      (keyword == "assert")     { if (formal_mode) return TOK_ASSERT;   SV_KEYWORD(TOK_ASSERT);   }
+	else if (keyword == "assume")     { if (formal_mode) return TOK_ASSUME;   SV_KEYWORD(TOK_ASSUME);   }
+	else if (keyword == "cover")      { if (formal_mode) return TOK_COVER;    SV_KEYWORD(TOK_COVER);    }
+	else if (keyword == "restrict")   { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
+	else log_abort();
+}
+
 "property"   { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 "rand"       { if (formal_mode) return TOK_RAND; SV_KEYWORD(TOK_RAND); }
 "const"      { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
@@ -303,7 +350,7 @@ supply1 { return TOK_SUPPLY1; }
 
 [a-zA-Z_$][a-zA-Z0-9_$\.]* {
 	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
-    return TOK_ID;
+	return TOK_ID;
 }
 
 "/*"[ \t]*(synopsys|synthesis)[ \t]*translate_off[ \t]*"*/" {
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 2258f3f6f..649dd384f 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -106,6 +106,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 }
 
 %token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
+%token <string> TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
@@ -119,14 +120,13 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR TOK_REAL
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
-%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
-%token TOK_RESTRICT TOK_COVER TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
+%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_PROPERTY TOK_ENUM TOK_TYPEDEF
 %token TOK_RAND TOK_CONST TOK_CHECKER TOK_ENDCHECKER TOK_EVENTUALLY
 %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
-%type <string> opt_label opt_stmt_label tok_prim_wrapper hierarchical_id
+%type <string> opt_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
 
@@ -1337,14 +1337,6 @@ opt_property:
 		$$ = false;
 	};
 
-opt_stmt_label:
-	TOK_ID ':' {
-		$$ = $1;
-	} |
-	/* empty */ {
-		$$ = NULL;
-	};
-
 modport_stmt:
     TOK_MODPORT TOK_ID {
         AstNode *modport = new AstNode(AST_MODPORT);
@@ -1381,11 +1373,35 @@ modport_type_token:
     TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
 
 assert:
-	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
+	TOK_ASSERT opt_property '(' expr ')' ';' {
+		if (noassert_mode) {
+			delete $4;
+		} else {
+			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
+	} |
+	TOK_ASSUME opt_property '(' expr ')' ';' {
+		if (noassume_mode) {
+			delete $4;
+		} else {
+			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $4);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
+	} |
+	TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (noassert_mode) {
 			delete $5;
 		} else {
-			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
+			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1393,11 +1409,11 @@ assert:
 		if ($1 != nullptr)
 			delete $1;
 	} |
-	opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' {
+	TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (noassume_mode) {
 			delete $5;
 		} else {
-			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
+			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $5);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1405,39 +1421,15 @@ assert:
 		if ($1 != nullptr)
 			delete $1;
 	} |
-	opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (noassert_mode) {
-			delete $6;
-		} else {
-			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
-			if ($1 != nullptr)
-				node->str = *$1;
-			ast_stack.back()->children.push_back(node);
-		}
-		if ($1 != nullptr)
-			delete $1;
-	} |
-	opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (noassume_mode) {
-			delete $6;
-		} else {
-			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
-			if ($1 != nullptr)
-				node->str = *$1;
-			ast_stack.back()->children.push_back(node);
-		}
-		if ($1 != nullptr)
-			delete $1;
-	} |
-	opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' {
-		AstNode *node = new AstNode(AST_COVER, $5);
+	TOK_COVER opt_property '(' expr ')' ';' {
+		AstNode *node = new AstNode(AST_COVER, $4);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
 		}
 		ast_stack.back()->children.push_back(node);
 	} |
-	opt_stmt_label TOK_COVER opt_property '(' ')' ';' {
+	TOK_COVER opt_property '(' ')' ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
 		if ($1 != nullptr) {
 			node->str = *$1;
@@ -1445,7 +1437,7 @@ assert:
 		}
 		ast_stack.back()->children.push_back(node);
 	} |
-	opt_stmt_label TOK_COVER ';' {
+	TOK_COVER ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
 		if ($1 != nullptr) {
 			node->str = *$1;
@@ -1453,30 +1445,30 @@ assert:
 		}
 		ast_stack.back()->children.push_back(node);
 	} |
-	opt_stmt_label TOK_RESTRICT opt_property '(' expr ')' ';' {
+	TOK_RESTRICT opt_property '(' expr ')' ';' {
 		if (norestrict_mode) {
-			delete $5;
+			delete $4;
 		} else {
-			AstNode *node = new AstNode(AST_ASSUME, $5);
+			AstNode *node = new AstNode(AST_ASSUME, $4);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
 		}
-		if (!$3)
+		if (!$2)
 			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
 		if ($1 != nullptr)
 			delete $1;
 	} |
-	opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+	TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (norestrict_mode) {
-			delete $6;
+			delete $5;
 		} else {
-			AstNode *node = new AstNode(AST_FAIR, $6);
+			AstNode *node = new AstNode(AST_FAIR, $5);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
 		}
-		if (!$3)
+		if (!$2)
 			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
 		if ($1 != nullptr)
 			delete $1;
@@ -1485,30 +1477,60 @@ assert:
 assert_property:
 	TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4));
+		if ($1 != nullptr) {
+			ast_stack.back()->children.back()->str = *$1;
+			delete $1;
+		}
 	} |
 	TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+		if ($1 != nullptr) {
+			ast_stack.back()->children.back()->str = *$1;
+			delete $1;
+		}
 	} |
 	TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
+		if ($1 != nullptr) {
+			ast_stack.back()->children.back()->str = *$1;
+			delete $1;
+		}
 	} |
 	TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+		if ($1 != nullptr) {
+			ast_stack.back()->children.back()->str = *$1;
+			delete $1;
+		}
 	} |
 	TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
+		if ($1 != nullptr) {
+			ast_stack.back()->children.back()->str = *$1;
+			delete $1;
+		}
 	} |
 	TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
-		if (norestrict_mode)
+		if (norestrict_mode) {
 			delete $4;
-		else
+		} else {
 			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+			if ($1 != nullptr) {
+				ast_stack.back()->children.back()->str = *$1;
+				delete $1;
+			}
+		}
 	} |
 	TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
-		if (norestrict_mode)
+		if (norestrict_mode) {
 			delete $5;
-		else
+		} else {
 			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+			if ($1 != nullptr) {
+				ast_stack.back()->children.back()->str = *$1;
+				delete $1;
+			}
+		}
 	};
 
 simple_behavioral_stmt:

From 399ab16315468df95fc8a180d384d2ce8eed8049 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 9 Mar 2019 11:52:00 -0800
Subject: [PATCH 469/528] Add $dffsr support to async2sync

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/async2sync.cc | 53 ++++++++++++++++++++++++++++++++++++++--
 1 file changed, 51 insertions(+), 2 deletions(-)

diff --git a/passes/sat/async2sync.cc b/passes/sat/async2sync.cc
index c92db7118..d045d0dcb 100644
--- a/passes/sat/async2sync.cc
+++ b/passes/sat/async2sync.cc
@@ -39,7 +39,7 @@ struct Async2syncPass : public Pass {
 		log("reset value in the next cycle regardless of the data-in value at the time of\n");
 		log("the clock edge.\n");
 		log("\n");
-		log("Currently only $adff cells are supported by this pass.\n");
+		log("Currently only $adff and $dffsr cells are supported by this pass.\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
@@ -84,7 +84,7 @@ struct Async2syncPass : public Pass {
 					bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool();
 					Const arst_val = cell->parameters["\\ARST_VALUE"];
 
-					SigSpec sig_clk = cell->getPort("\\CLK");
+					// SigSpec sig_clk = cell->getPort("\\CLK");
 					SigSpec sig_arst = cell->getPort("\\ARST");
 					SigSpec sig_d = cell->getPort("\\D");
 					SigSpec sig_q = cell->getPort("\\Q");
@@ -120,6 +120,55 @@ struct Async2syncPass : public Pass {
 					cell->type = "$dff";
 					continue;
 				}
+
+				if (cell->type.in("$dffsr"))
+				{
+					// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool();
+					bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool();
+					bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool();
+
+					// SigSpec sig_clk = cell->getPort("\\CLK");
+					SigSpec sig_set = cell->getPort("\\SET");
+					SigSpec sig_clr = cell->getPort("\\CLR");
+					SigSpec sig_d = cell->getPort("\\D");
+					SigSpec sig_q = cell->getPort("\\Q");
+
+					log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
+							log_id(module), log_id(cell), log_id(cell->type),
+							log_signal(sig_set), log_signal(sig_clr), log_signal(sig_d), log_signal(sig_q));
+
+					Const init_val;
+					for (int i = 0; i < GetSize(sig_q); i++) {
+						SigBit bit = sigmap(sig_q[i]);
+						init_val.bits.push_back(initbits.count(bit) ? initbits.at(bit) : State::Sx);
+						del_initbits.insert(bit);
+					}
+
+					Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
+					Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
+					new_q->attributes["\\init"] = init_val;
+
+					if (!set_pol)
+						sig_set = module->Not(NEW_ID, sig_set);
+
+					if (clr_pol)
+						sig_clr = module->Not(NEW_ID, sig_clr);
+
+					SigSpec tmp = module->Or(NEW_ID, sig_d, sig_set);
+					module->addAnd(NEW_ID, tmp, sig_clr, new_d);
+
+					tmp = module->Or(NEW_ID, new_q, sig_set);
+					module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
+
+					cell->setPort("\\D", new_d);
+					cell->setPort("\\Q", new_q);
+					cell->unsetPort("\\SET");
+					cell->unsetPort("\\CLR");
+					cell->unsetParam("\\SET_POLARITY");
+					cell->unsetParam("\\CLR_POLARITY");
+					cell->type = "$dff";
+					continue;
+				}
 			}
 
 			for (auto wire : module->wires())

From 94f995ee3784e1a94a484fd399be2be4793d4e41 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 9 Mar 2019 13:19:41 -0800
Subject: [PATCH 470/528] Fix signed $shift/$shiftx handling in write_smt2

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smt2.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index a26bff57b..688535f33 100644
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -416,6 +416,7 @@ struct Smt2Worker
 		for (char ch : expr) {
 			if (ch == 'A') processed_expr += get_bv(sig_a);
 			else if (ch == 'B') processed_expr += get_bv(sig_b);
+			else if (ch == 'P') processed_expr += get_bv(cell->getPort("\\B"));
 			else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
 			else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
 			else processed_expr += ch;
@@ -554,7 +555,7 @@ struct Smt2Worker
 
 			if (cell->type.in("$shift", "$shiftx")) {
 				if (cell->getParam("\\B_SIGNED").as_bool()) {
-					return export_bvop(cell, stringf("(ite (bvsge B #b%0*d) "
+					return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
 							"(bvlshr A B) (bvlshr A (bvneg B)))",
 							GetSize(cell->getPort("\\B")), 0), 's');
 				} else {

From ff4c2a14ae34eeb899c3cf0ca1109f0106b41679 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 9 Mar 2019 13:24:55 -0800
Subject: [PATCH 471/528] Fix typo in ice40_braminit help msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/ice40_braminit.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index bf12f9148..4fa6b0792 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -135,7 +135,7 @@ struct Ice40BRAMInitPass : public Pass {
 		log("    ice40_braminit\n");
 		log("\n");
 		log("This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE\n");
-		log("parameter and converts it inti the required INIT_x attributes\n");
+		log("parameter and converts it into the required INIT_x attributes\n");
 		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE

From b02d9c2634de0898b2c483c438ba56540e0f3f69 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 10 Mar 2019 16:27:18 -0700
Subject: [PATCH 472/528] Fix handling of cases that look like sva labels,
 fixes #862

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verilog/verilog_lexer.l  |  59 +++----------
 frontends/verilog/verilog_parser.y | 131 ++++++++++++++++-------------
 2 files changed, 82 insertions(+), 108 deletions(-)

diff --git a/frontends/verilog/verilog_lexer.l b/frontends/verilog/verilog_lexer.l
index e51a12f76..6ef38252a 100644
--- a/frontends/verilog/verilog_lexer.l
+++ b/frontends/verilog/verilog_lexer.l
@@ -189,57 +189,18 @@ YOSYS_NAMESPACE_END
 "always_ff"    { SV_KEYWORD(TOK_ALWAYS); }
 "always_latch" { SV_KEYWORD(TOK_ALWAYS); }
 
- /* parse labels on assert, assume, cover, and restrict right here because it's insanley complex
-    to do it in the parser (because we force the parser too early to reduce when parsing cells..) */
-([a-zA-Z_$][a-zA-Z0-9_$]*[ \t\r\n]*:[ \t\r\n]*)?(assert|assume|cover|restrict)/[^a-zA-Z0-9_$\.] {
-	frontend_verilog_yylval.string = new std::string(yytext);
-	auto &str = *frontend_verilog_yylval.string;
-	std::string keyword;
-	int cursor = 0;
-
-	while (1) {
-		if (cursor == GetSize(str)) {
-			keyword = str;
-			delete frontend_verilog_yylval.string;
-			frontend_verilog_yylval.string = nullptr;
-			goto sva_without_label;
-		}
-		char c = str[cursor];
-		if (c != ' ' && c != '\t' && c != '\r' && c != '\n' && c != ':') {
-			cursor++;
-			continue;
-		}
-
-		keyword = str.substr(cursor);
-		str = "\\" + str.substr(0, cursor);
-		break;
-	}
-
-	cursor = 0;
-	while (1) {
-		log_assert(cursor < GetSize(keyword));
-		char c = keyword[cursor];
-		if (c != ' ' && c != '\t' && c != '\r' && c != '\n' && c != ':') {
-			keyword = keyword.substr(cursor);
-			break;
-		}
-		cursor++;
-	}
-
-	if      (keyword == "assert")     { return TOK_ASSERT;   }
-	else if (keyword == "assume")     { return TOK_ASSUME;   }
-	else if (keyword == "cover")      { return TOK_COVER;    }
-	else if (keyword == "restrict")   { return TOK_RESTRICT; }
-	else log_abort();
-
-sva_without_label:
-	if      (keyword == "assert")     { if (formal_mode) return TOK_ASSERT;   SV_KEYWORD(TOK_ASSERT);   }
-	else if (keyword == "assume")     { if (formal_mode) return TOK_ASSUME;   SV_KEYWORD(TOK_ASSUME);   }
-	else if (keyword == "cover")      { if (formal_mode) return TOK_COVER;    SV_KEYWORD(TOK_COVER);    }
-	else if (keyword == "restrict")   { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
-	else log_abort();
+ /* use special token for labels on assert, assume, cover, and restrict because it's insanley complex
+    to fix parsing of cells otherwise. (the current cell parser forces a reduce very early to update some
+    global state.. its a mess) */
+[a-zA-Z_$][a-zA-Z0-9_$]*/[ \t\r\n]*:[ \t\r\n]*(assert|assume|cover|restrict)[^a-zA-Z0-9_$\.] {
+	frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext);
+	return TOK_SVA_LABEL;
 }
 
+"assert"     { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
+"assume"     { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
+"cover"      { if (formal_mode) return TOK_COVER; SV_KEYWORD(TOK_COVER); }
+"restrict"   { if (formal_mode) return TOK_RESTRICT; SV_KEYWORD(TOK_RESTRICT); }
 "property"   { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
 "rand"       { if (formal_mode) return TOK_RAND; SV_KEYWORD(TOK_RAND); }
 "const"      { if (formal_mode) return TOK_CONST; SV_KEYWORD(TOK_CONST); }
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 649dd384f..52685f637 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -105,8 +105,8 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 	bool boolean;
 }
 
-%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE
-%token <string> TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
+%token <string> TOK_STRING TOK_ID TOK_CONSTVAL TOK_REALVAL TOK_PRIMITIVE TOK_SVA_LABEL
+%token TOK_ASSERT TOK_ASSUME TOK_RESTRICT TOK_COVER
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
@@ -126,7 +126,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 
 %type <ast> range range_or_multirange  non_opt_range non_opt_multirange range_or_signed_int
 %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
-%type <string> opt_label tok_prim_wrapper hierarchical_id
+%type <string> opt_label opt_sva_label tok_prim_wrapper hierarchical_id
 %type <boolean> opt_signed opt_property unique_case_attr
 %type <al> attr case_attr
 
@@ -1329,6 +1329,14 @@ opt_label:
 		$$ = NULL;
 	};
 
+opt_sva_label:
+	TOK_SVA_LABEL ':' {
+		$$ = $1;
+	} |
+	/* empty */ {
+		$$ = NULL;
+	};
+
 opt_property:
 	TOK_PROPERTY {
 		$$ = true;
@@ -1373,35 +1381,11 @@ modport_type_token:
     TOK_INPUT {current_modport_input = 1; current_modport_output = 0;} | TOK_OUTPUT {current_modport_input = 0; current_modport_output = 1;}
 
 assert:
-	TOK_ASSERT opt_property '(' expr ')' ';' {
-		if (noassert_mode) {
-			delete $4;
-		} else {
-			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4);
-			if ($1 != nullptr)
-				node->str = *$1;
-			ast_stack.back()->children.push_back(node);
-		}
-		if ($1 != nullptr)
-			delete $1;
-	} |
-	TOK_ASSUME opt_property '(' expr ')' ';' {
-		if (noassume_mode) {
-			delete $4;
-		} else {
-			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $4);
-			if ($1 != nullptr)
-				node->str = *$1;
-			ast_stack.back()->children.push_back(node);
-		}
-		if ($1 != nullptr)
-			delete $1;
-	} |
-	TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+	opt_sva_label TOK_ASSERT opt_property '(' expr ')' ';' {
 		if (noassert_mode) {
 			delete $5;
 		} else {
-			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5);
+			AstNode *node = new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1409,11 +1393,11 @@ assert:
 		if ($1 != nullptr)
 			delete $1;
 	} |
-	TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+	opt_sva_label TOK_ASSUME opt_property '(' expr ')' ';' {
 		if (noassume_mode) {
 			delete $5;
 		} else {
-			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $5);
+			AstNode *node = new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
@@ -1421,15 +1405,39 @@ assert:
 		if ($1 != nullptr)
 			delete $1;
 	} |
-	TOK_COVER opt_property '(' expr ')' ';' {
-		AstNode *node = new AstNode(AST_COVER, $4);
+	opt_sva_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+		if (noassert_mode) {
+			delete $6;
+		} else {
+			AstNode *node = new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
+	} |
+	opt_sva_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+		if (noassume_mode) {
+			delete $6;
+		} else {
+			AstNode *node = new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6);
+			if ($1 != nullptr)
+				node->str = *$1;
+			ast_stack.back()->children.push_back(node);
+		}
+		if ($1 != nullptr)
+			delete $1;
+	} |
+	opt_sva_label TOK_COVER opt_property '(' expr ')' ';' {
+		AstNode *node = new AstNode(AST_COVER, $5);
 		if ($1 != nullptr) {
 			node->str = *$1;
 			delete $1;
 		}
 		ast_stack.back()->children.push_back(node);
 	} |
-	TOK_COVER opt_property '(' ')' ';' {
+	opt_sva_label TOK_COVER opt_property '(' ')' ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
 		if ($1 != nullptr) {
 			node->str = *$1;
@@ -1437,7 +1445,7 @@ assert:
 		}
 		ast_stack.back()->children.push_back(node);
 	} |
-	TOK_COVER ';' {
+	opt_sva_label TOK_COVER ';' {
 		AstNode *node = new AstNode(AST_COVER, AstNode::mkconst_int(1, false));
 		if ($1 != nullptr) {
 			node->str = *$1;
@@ -1445,87 +1453,87 @@ assert:
 		}
 		ast_stack.back()->children.push_back(node);
 	} |
-	TOK_RESTRICT opt_property '(' expr ')' ';' {
+	opt_sva_label TOK_RESTRICT opt_property '(' expr ')' ';' {
 		if (norestrict_mode) {
-			delete $4;
+			delete $5;
 		} else {
-			AstNode *node = new AstNode(AST_ASSUME, $4);
+			AstNode *node = new AstNode(AST_ASSUME, $5);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
 		}
-		if (!$2)
+		if (!$3)
 			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
 		if ($1 != nullptr)
 			delete $1;
 	} |
-	TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
+	opt_sva_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
 		if (norestrict_mode) {
-			delete $5;
+			delete $6;
 		} else {
-			AstNode *node = new AstNode(AST_FAIR, $5);
+			AstNode *node = new AstNode(AST_FAIR, $6);
 			if ($1 != nullptr)
 				node->str = *$1;
 			ast_stack.back()->children.push_back(node);
 		}
-		if (!$2)
+		if (!$3)
 			log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
 		if ($1 != nullptr)
 			delete $1;
 	};
 
 assert_property:
-	TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $4));
+	opt_sva_label TOK_ASSERT TOK_PROPERTY '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
-	TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+	opt_sva_label TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
-	TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $5));
+	opt_sva_label TOK_ASSERT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
-	TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+	opt_sva_label TOK_ASSUME TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
-	TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
-		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $4));
+	opt_sva_label TOK_COVER TOK_PROPERTY '(' expr ')' ';' {
+		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));
 		if ($1 != nullptr) {
 			ast_stack.back()->children.back()->str = *$1;
 			delete $1;
 		}
 	} |
-	TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
+	opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' expr ')' ';' {
 		if (norestrict_mode) {
-			delete $4;
+			delete $5;
 		} else {
-			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
+			ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
 			if ($1 != nullptr) {
 				ast_stack.back()->children.back()->str = *$1;
 				delete $1;
 			}
 		}
 	} |
-	TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
+	opt_sva_label TOK_RESTRICT TOK_PROPERTY '(' TOK_EVENTUALLY expr ')' ';' {
 		if (norestrict_mode) {
-			delete $5;
+			delete $6;
 		} else {
-			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $5));
+			ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
 			if ($1 != nullptr) {
 				ast_stack.back()->children.back()->str = *$1;
 				delete $1;
@@ -1748,6 +1756,11 @@ case_expr_list:
 	TOK_DEFAULT {
 		ast_stack.back()->children.push_back(new AstNode(AST_DEFAULT));
 	} |
+	TOK_SVA_LABEL {
+		ast_stack.back()->children.push_back(new AstNode(AST_IDENTIFIER));
+		ast_stack.back()->children.back()->str = *$1;
+		delete $1;
+	} |
 	expr {
 		ast_stack.back()->children.push_back($1);
 	} |

From d9bb5f3637634ea214194b612aee4bb0c62d7a5c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 11 Mar 2019 01:08:36 -0700
Subject: [PATCH 473/528] Add ENABLE_GLOB Makefile switch

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile        | 5 +++++
 kernel/yosys.cc | 8 +++++---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/Makefile b/Makefile
index 8e93cd285..b8fbcc040 100644
--- a/Makefile
+++ b/Makefile
@@ -10,6 +10,7 @@ CONFIG := clang
 # features (the more the better)
 ENABLE_TCL := 1
 ENABLE_ABC := 1
+ENABLE_GLOB := 1
 ENABLE_PLUGINS := 1
 ENABLE_READLINE := 1
 ENABLE_EDITLINE := 0
@@ -298,6 +299,10 @@ LDLIBS += -ldl
 endif
 endif
 
+ifeq ($(ENABLE_GLOB),1)
+CXXFLAGS += -DYOSYS_ENABLE_GLOB
+endif
+
 ifeq ($(ENABLE_TCL),1)
 TCL_VERSION ?= tcl$(shell bash -c "tclsh <(echo 'puts [info tclversion]')")
 ifeq ($(OS), FreeBSD)
diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 2ed0f4db4..6fd53f85e 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -33,7 +33,7 @@
 #  include <dlfcn.h>
 #endif
 
-#ifdef _WIN32
+#if defined(_WIN32)
 #  include <windows.h>
 #  include <io.h>
 #elif defined(__APPLE__)
@@ -41,13 +41,15 @@
 #  include <unistd.h>
 #  include <dirent.h>
 #  include <sys/stat.h>
-#  include <glob.h>
 #else
 #  include <unistd.h>
 #  include <dirent.h>
 #  include <sys/types.h>
 #  include <sys/wait.h>
 #  include <sys/stat.h>
+#endif
+
+#if !defined(_WIN32) && defined(YOSYS_ENABLE_GLOB)
 #  include <glob.h>
 #endif
 
@@ -564,7 +566,7 @@ std::vector<std::string> glob_filename(const std::string &filename_pattern)
 {
 	std::vector<std::string> results;
 
-#ifdef _WIN32
+#if defined(_WIN32) || !defined(YOSYS_ENABLE_GLOB)
 	results.push_back(filename_pattern);
 #else
 	glob_t globbuf;

From 20c6a8c9b0abb384517c4cc6f58cd29a90bda6ff Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 11 Mar 2019 20:12:28 +0100
Subject: [PATCH 474/528] Improve determinism of IdString DB for similar
 scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/verilog/verilog_backend.cc |  4 ++
 kernel/log.cc                       |  4 ++
 kernel/register.cc                  |  2 +
 kernel/rtlil.cc                     |  2 +
 kernel/rtlil.h                      | 64 ++++++++++++++++++++++++++---
 5 files changed, 71 insertions(+), 5 deletions(-)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 6818edb7a..83d83f488 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1673,6 +1673,8 @@ struct VerilogBackend : public Backend {
 		bool blackboxes = false;
 		bool selected = false;
 
+		auto_name_map.clear();
+		reg_wires.clear();
 		reg_ct.clear();
 
 		reg_ct.insert("$dff");
@@ -1779,6 +1781,8 @@ struct VerilogBackend : public Backend {
 			dump_module(*f, "", it->second);
 		}
 
+		auto_name_map.clear();
+		reg_wires.clear();
 		reg_ct.clear();
 	}
 } VerilogBackend;
diff --git a/kernel/log.cc b/kernel/log.cc
index 0ee2170a0..400a549dd 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -196,7 +196,11 @@ void logv_header(RTLIL::Design *design, const char *format, va_list ap)
 	if (log_hdump.count(header_id) && design != nullptr)
 		for (auto &filename : log_hdump.at(header_id)) {
 			log("Dumping current design to '%s'.\n", filename.c_str());
+			if (yosys_xtrace)
+				IdString::xtrace_db_dump();
 			Pass::call(design, {"dump", "-o", filename});
+			if (yosys_xtrace)
+				log("#X# -- end of dump --\n");
 		}
 
 	if (pop_errfile)
diff --git a/kernel/register.cc b/kernel/register.cc
index 402a5b3ea..64956401f 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -86,6 +86,8 @@ Pass::pre_post_exec_state_t Pass::pre_execute()
 
 void Pass::post_execute(Pass::pre_post_exec_state_t state)
 {
+	IdString::checkpoint();
+
 	int64_t time_ns = PerformanceTimer::query() - state.begin_ns;
 	runtime_ns += time_ns;
 	current_pass = state.parent_pass;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d4aebcda9..7f1816190 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -33,6 +33,8 @@ std::vector<int> RTLIL::IdString::global_refcount_storage_;
 std::vector<char*> RTLIL::IdString::global_id_storage_;
 dict<char*, int, hash_cstr_ops> RTLIL::IdString::global_id_index_;
 std::vector<int> RTLIL::IdString::global_free_idx_list_;
+int RTLIL::IdString::last_created_idx_[8];
+int RTLIL::IdString::last_created_idx_ptr_;
 
 RTLIL::Const::Const()
 {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index f877622aa..01323d112 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -76,6 +76,9 @@ namespace RTLIL
 
 	struct IdString
 	{
+		#undef YOSYS_XTRACE_GET_PUT
+		#undef YOSYS_SORT_ID_FREE_LIST
+
 		// the global id string cache
 
 		static struct destruct_guard_t {
@@ -89,9 +92,43 @@ namespace RTLIL
 		static dict<char*, int, hash_cstr_ops> global_id_index_;
 		static std::vector<int> global_free_idx_list_;
 
+		static int last_created_idx_ptr_;
+		static int last_created_idx_[8];
+
+		static inline void xtrace_db_dump()
+		{
+		#ifdef YOSYS_XTRACE_GET_PUT
+			for (int idx = 0; idx < GetSize(global_id_storage_); idx++)
+			{
+				if (global_id_storage_.at(idx) == nullptr)
+					log("#X# DB-DUMP index %d: FREE\n", idx);
+				else
+					log("#X# DB-DUMP index %d: '%s' (ref %d)\n", idx, global_id_storage_.at(idx), global_refcount_storage_.at(idx));
+			}
+		#endif
+		}
+
+		static inline void checkpoint()
+		{
+			last_created_idx_ptr_ = 0;
+			for (int i = 0; i < 8; i++) {
+				if (last_created_idx_[i])
+					put_reference(last_created_idx_[i]);
+				last_created_idx_[i] = 0;
+			}
+		#ifdef YOSYS_SORT_ID_FREE_LIST
+			std::sort(global_free_idx_list_.begin(), global_free_idx_list_.end(), std::greater<int>());
+		#endif
+		}
+
 		static inline int get_reference(int idx)
 		{
 			global_refcount_storage_.at(idx)++;
+		#ifdef YOSYS_XTRACE_GET_PUT
+			if (yosys_xtrace) {
+				log("#X# GET-BY-INDEX '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));
+			}
+		#endif
 			return idx;
 		}
 
@@ -107,6 +144,11 @@ namespace RTLIL
 			auto it = global_id_index_.find((char*)p);
 			if (it != global_id_index_.end()) {
 				global_refcount_storage_.at(it->second)++;
+		#ifdef YOSYS_XTRACE_GET_PUT
+				if (yosys_xtrace) {
+					log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(it->second), it->second, global_refcount_storage_.at(it->second));
+				}
+		#endif
 				return it->second;
 			}
 
@@ -124,16 +166,22 @@ namespace RTLIL
 			global_refcount_storage_.at(idx)++;
 
 			// Avoid Create->Delete->Create pattern
-			static IdString last_created_id;
-			put_reference(last_created_id.index_);
-			last_created_id.index_ = idx;
-			get_reference(last_created_id.index_);
+			if (last_created_idx_[last_created_idx_ptr_])
+				put_reference(last_created_idx_[last_created_idx_ptr_]);
+			last_created_idx_[last_created_idx_ptr_] = idx;
+			get_reference(last_created_idx_[last_created_idx_ptr_]);
+			last_created_idx_ptr_ = (last_created_idx_ptr_ + 1) & 7;
 
 			if (yosys_xtrace) {
 				log("#X# New IdString '%s' with index %d.\n", p, idx);
 				log_backtrace("-X- ", yosys_xtrace-1);
 			}
 
+		#ifdef YOSYS_XTRACE_GET_PUT
+			if (yosys_xtrace) {
+				log("#X# GET-BY-NAME '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));
+			}
+		#endif
 			return idx;
 		}
 
@@ -144,6 +192,12 @@ namespace RTLIL
 			if (!destruct_guard.ok)
 				return;
 
+		#ifdef YOSYS_XTRACE_GET_PUT
+			if (yosys_xtrace) {
+				log("#X# PUT '%s' (index %d, refcount %d)\n", global_id_storage_.at(idx), idx, global_refcount_storage_.at(idx));
+			}
+		#endif
+
 			log_assert(global_refcount_storage_.at(idx) > 0);
 
 			if (--global_refcount_storage_.at(idx) != 0)
@@ -1282,7 +1336,7 @@ inline bool RTLIL::SigBit::operator<(const RTLIL::SigBit &other) const {
 		return wire ? (offset < other.offset) : (data < other.data);
 	if (wire != nullptr && other.wire != nullptr)
 		return wire->name < other.wire->name;
-	return wire < other.wire;
+	return (wire != nullptr) < (other.wire != nullptr);
 }
 
 inline bool RTLIL::SigBit::operator==(const RTLIL::SigBit &other) const {

From ab5b50ae3c9e63fe3da3ae0451500c1cb5be1743 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 20:09:47 +0100
Subject: [PATCH 475/528] Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for
 non-init writes, fixes #867

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index ae7dec88d..f747a07cd 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2954,12 +2954,14 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 				proc_flags[mem] |= AstNode::MEM2REG_FL_EQ1;
 			}
 
-			// remember if this is a constant index or not
-			if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) {
-				if (children[0]->children[0]->children[0]->type == AST_CONSTANT)
-					mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS;
-				else
-					mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS;
+			// for proper (non-init) writes: remember if this is a constant index or not
+			if ((flags & MEM2REG_FL_INIT) == 0) {
+				if (children[0]->children.size() && children[0]->children[0]->type == AST_RANGE && children[0]->children[0]->children.size()) {
+					if (children[0]->children[0]->children[0]->type == AST_CONSTANT)
+						mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_CONST_LHS;
+					else
+						mem2reg_candidates[mem] |= AstNode::MEM2REG_FL_VAR_LHS;
+				}
 			}
 
 			// remember where this is

From a4ddc569b4c0e51e89317ade8c4183f41acc1cb5 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 20:10:55 +0100
Subject: [PATCH 476/528] Remove outdated "blocking assignment to memory"
 warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f747a07cd..de300bbce 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -50,7 +50,6 @@ using namespace AST_INTERNAL;
 bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, int width_hint, bool sign_hint, bool in_param)
 {
 	static int recursion_counter = 0;
-	static pair<string, int> last_blocking_assignment_warn;
 	static bool deep_recursion_warning = false;
 
 	if (recursion_counter++ == 1000 && deep_recursion_warning) {
@@ -72,7 +71,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (stage == 0)
 	{
 		log_assert(type == AST_MODULE || type == AST_INTERFACE);
-		last_blocking_assignment_warn = pair<string, int>();
 
 		deep_recursion_warning = true;
 		while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
@@ -1592,14 +1590,6 @@ skip_dynamic_range_lvalue_expansion:;
 		sstr << "$memwr$" << children[0]->str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 		std::string id_addr = sstr.str() + "_ADDR", id_data = sstr.str() + "_DATA", id_en = sstr.str() + "_EN";
 
-		if (type == AST_ASSIGN_EQ) {
-			pair<string, int> this_blocking_assignment_warn(filename, linenum);
-			if (this_blocking_assignment_warn != last_blocking_assignment_warn)
-				log_warning("Blocking assignment to memory in line %s:%d is handled like a non-blocking assignment.\n",
-						filename.c_str(), linenum);
-			last_blocking_assignment_warn = this_blocking_assignment_warn;
-		}
-
 		int mem_width, mem_size, addr_bits;
 		bool mem_signed = children[0]->id2ast->is_signed;
 		children[0]->id2ast->meminfo(mem_width, mem_size, addr_bits);

From d25a0c8adeb421246732539b19738a8e68fc1315 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 20:12:02 +0100
Subject: [PATCH 477/528] Improve handling of memories used in mem index
 expressions on LHS of an assignment

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index de300bbce..1c9932ee0 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2918,7 +2918,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 		dict<AstNode*, uint32_t> &mem2reg_candidates, dict<AstNode*, uint32_t> &proc_flags, uint32_t &flags)
 {
 	uint32_t children_flags = 0;
-	int ignore_children_counter = 0;
+	int lhs_children_counter = 0;
 
 	if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ)
 	{
@@ -2966,7 +2966,7 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 			}
 		}
 
-		ignore_children_counter = 1;
+		lhs_children_counter = 1;
 	}
 
 	if (type == AST_IDENTIFIER && id2ast && id2ast->type == AST_MEMORY)
@@ -3009,12 +3009,23 @@ void AstNode::mem2reg_as_needed_pass1(dict<AstNode*, pool<std::string>> &mem2reg
 	log_assert((flags & ~0x000000ff) == 0);
 
 	for (auto child : children)
-		if (ignore_children_counter > 0)
-			ignore_children_counter--;
-		else if (proc_flags_p)
+	{
+		if (lhs_children_counter > 0) {
+			lhs_children_counter--;
+			if (child->children.size() && child->children[0]->type == AST_RANGE && child->children[0]->children.size()) {
+				for (auto c : child->children[0]->children) {
+					if (proc_flags_p)
+						c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
+					else
+						c->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
+				}
+			}
+		} else
+		if (proc_flags_p)
 			child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, *proc_flags_p, flags);
 		else
 			child->mem2reg_as_needed_pass1(mem2reg_places, mem2reg_candidates, proc_flags, flags);
+	}
 
 	flags &= ~children_flags | backup_flags;
 

From 9284cf92b8dcb510a2a9511965e587e42944c543 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 20:14:18 +0100
Subject: [PATCH 478/528] Remove ice40/cells_sim.v hack to avoid warning for
 blocking memory writes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/ice40/cells_sim.v | 19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index bc36cdd14..62a28364b 100644
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -414,24 +414,6 @@ module SB_RAM40_4K (
 			$readmemh(INIT_FILE, memory);
 		else
 			for (i=0; i<16; i=i+1) begin
-`ifdef YOSYS
-				memory[ 0*16 + i] <= INIT_0[16*i +: 16];
-				memory[ 1*16 + i] <= INIT_1[16*i +: 16];
-				memory[ 2*16 + i] <= INIT_2[16*i +: 16];
-				memory[ 3*16 + i] <= INIT_3[16*i +: 16];
-				memory[ 4*16 + i] <= INIT_4[16*i +: 16];
-				memory[ 5*16 + i] <= INIT_5[16*i +: 16];
-				memory[ 6*16 + i] <= INIT_6[16*i +: 16];
-				memory[ 7*16 + i] <= INIT_7[16*i +: 16];
-				memory[ 8*16 + i] <= INIT_8[16*i +: 16];
-				memory[ 9*16 + i] <= INIT_9[16*i +: 16];
-				memory[10*16 + i] <= INIT_A[16*i +: 16];
-				memory[11*16 + i] <= INIT_B[16*i +: 16];
-				memory[12*16 + i] <= INIT_C[16*i +: 16];
-				memory[13*16 + i] <= INIT_D[16*i +: 16];
-				memory[14*16 + i] <= INIT_E[16*i +: 16];
-				memory[15*16 + i] <= INIT_F[16*i +: 16];
-`else
 				memory[ 0*16 + i] = INIT_0[16*i +: 16];
 				memory[ 1*16 + i] = INIT_1[16*i +: 16];
 				memory[ 2*16 + i] = INIT_2[16*i +: 16];
@@ -448,7 +430,6 @@ module SB_RAM40_4K (
 				memory[13*16 + i] = INIT_D[16*i +: 16];
 				memory[14*16 + i] = INIT_E[16*i +: 16];
 				memory[15*16 + i] = INIT_F[16*i +: 16];
-`endif
 			end
 	end
 

From 1cd04a68389671c91dddb56cc3d2f9032f9b44e3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 21:14:50 +0100
Subject: [PATCH 479/528] Fix a bug in handling quotes in multi-cmd lines in
 Yosys scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/yosys.cc | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6fd53f85e..450e4e4cf 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -218,12 +218,18 @@ std::string next_token(std::string &text, const char *sep, bool long_strings)
 
 	if (long_strings && pos_begin != text.size() && text[pos_begin] == '"') {
 		string sep_string = sep;
-		for (size_t i = pos_begin+1; i < text.size(); i++)
+		for (size_t i = pos_begin+1; i < text.size(); i++) {
 			if (text[i] == '"' && (i+1 == text.size() || sep_string.find(text[i+1]) != std::string::npos)) {
 				std::string token = text.substr(pos_begin, i-pos_begin+1);
 				text = text.substr(i+1);
 				return token;
 			}
+			if (i+1 < text.size() && text[i] == '"' && text[i+1] == ';' && (i+2 == text.size() || sep_string.find(text[i+2]) != std::string::npos)) {
+				std::string token = text.substr(pos_begin, i-pos_begin+1);
+				text = text.substr(i+2);
+				return token + ";";
+			}
+		}
 	}
 
 	size_t pos_end = text.find_first_of(sep, pos_begin);

From ff15cf9b1f8208d8c6e22beb9aebedc8bdae213f Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Tue, 12 Mar 2019 17:55:47 -0400
Subject: [PATCH 480/528] Install launcher executable when running yosys-smtbmc
 on Windows.

Signed-off-by: William D. Jones <thor0505@comcast.net>
---
 .gitignore                 |   2 +
 backends/smt2/Makefile.inc |  18 +-
 misc/launcher.c            | 358 +++++++++++++++++++++++++++++++++++++
 3 files changed, 377 insertions(+), 1 deletion(-)
 create mode 100644 misc/launcher.c

diff --git a/.gitignore b/.gitignore
index 48ce458c7..e24f7975a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -24,6 +24,8 @@
 /yosys-abc.exe
 /yosys-config
 /yosys-smtbmc
+/yosys-smtbmc.exe
+/yosys-smtbmc-script.py
 /yosys-filterlib
 /yosys-filterlib.exe
 /kernel/version_*.cc
diff --git a/backends/smt2/Makefile.inc b/backends/smt2/Makefile.inc
index dce82f01a..92941d4cf 100644
--- a/backends/smt2/Makefile.inc
+++ b/backends/smt2/Makefile.inc
@@ -3,14 +3,30 @@ OBJS += backends/smt2/smt2.o
 
 ifneq ($(CONFIG),mxe)
 ifneq ($(CONFIG),emcc)
+
+# MSYS targets support yosys-smtbmc, but require a launcher script
+ifeq ($(CONFIG),$(filter $(CONFIG),msys2 msys2-64))
+TARGETS += yosys-smtbmc.exe yosys-smtbmc-script.py
+# Needed to find the Python interpreter for yosys-smtbmc scripts.
+# Override if necessary, it is only used for msys2 targets.
+PYTHON := $(shell cygpath -w -m $(PREFIX)/bin/python3)
+
+yosys-smtbmc-script.py: backends/smt2/smtbmc.py
+	$(P) sed -e 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' \
+		-e "s|#!/usr/bin/env python3|#!$(PYTHON)|" < $< > $@
+
+yosys-smtbmc.exe: misc/launcher.c yosys-smtbmc-script.py
+	$(P) gcc -DGUI=0 -O -s -o $@ $<
+# Other targets
+else
 TARGETS += yosys-smtbmc
 
 yosys-smtbmc: backends/smt2/smtbmc.py
 	$(P) sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < $< > $@.new
 	$(Q) chmod +x $@.new
 	$(Q) mv $@.new $@
+endif
 
 $(eval $(call add_share_file,share/python3,backends/smt2/smtio.py))
 endif
 endif
-
diff --git a/misc/launcher.c b/misc/launcher.c
new file mode 100644
index 000000000..157d68cf3
--- /dev/null
+++ b/misc/launcher.c
@@ -0,0 +1,358 @@
+/* This file comes from the PyPA Setuptools repository, commit 16e452a:
+https://github.com/pypa/setuptools
+Modifications include this comment and inline inclusion of the LICENSE text. */
+
+/* Copyright (C) 2016 Jason R Coombs <jaraco@jaraco.com>
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE. */
+
+/*  Setuptools Script Launcher for Windows
+
+    This is a stub executable for Windows that functions somewhat like
+    Effbot's "exemaker", in that it runs a script with the same name but
+    a .py extension, using information from a #! line.  It differs in that
+    it spawns the actual Python executable, rather than attempting to
+    hook into the Python DLL.  This means that the script will run with
+    sys.executable set to the Python executable, where exemaker ends up with
+    sys.executable pointing to itself.  (Which means it won't work if you try
+    to run another Python process using sys.executable.)
+
+    To build/rebuild with mingw32, do this in the setuptools project directory:
+
+       gcc -DGUI=0           -mno-cygwin -O -s -o setuptools/cli.exe launcher.c
+       gcc -DGUI=1 -mwindows -mno-cygwin -O -s -o setuptools/gui.exe launcher.c
+
+    To build for Windows RT, install both Visual Studio Express for Windows 8
+    and for Windows Desktop (both freeware), create "win32" application using
+    "Windows Desktop" version, create new "ARM" target via
+    "Configuration Manager" menu and modify ".vcxproj" file by adding
+    "<WindowsSDKDesktopARMSupport>true</WindowsSDKDesktopARMSupport>" tag
+    as child of "PropertyGroup" tags that has "Debug|ARM" and "Release|ARM"
+    properties.
+
+    It links to msvcrt.dll, but this shouldn't be a problem since it doesn't
+    actually run Python in the same process.  Note that using 'exec' instead
+    of 'spawn' doesn't work, because on Windows this leads to the Python
+    executable running in the *background*, attached to the same console
+    window, meaning you get a command prompt back *before* Python even finishes
+    starting.  So, we have to use spawnv() and wait for Python to exit before
+    continuing.  :(
+*/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <windows.h>
+#include <tchar.h>
+#include <fcntl.h>
+
+int child_pid=0;
+
+int fail(char *format, char *data) {
+    /* Print error message to stderr and return 2 */
+    fprintf(stderr, format, data);
+    return 2;
+}
+
+char *quoted(char *data) {
+    int i, ln = strlen(data), nb;
+
+    /* We allocate twice as much space as needed to deal with worse-case
+       of having to escape everything. */
+    char *result = calloc(ln*2+3, sizeof(char));
+    char *presult = result;
+
+    *presult++ = '"';
+    for (nb=0, i=0; i < ln; i++)
+      {
+        if (data[i] == '\\')
+          nb += 1;
+        else if (data[i] == '"')
+          {
+            for (; nb > 0; nb--)
+              *presult++ = '\\';
+            *presult++ = '\\';
+          }
+        else
+          nb = 0;
+        *presult++ = data[i];
+      }
+
+    for (; nb > 0; nb--)        /* Deal w trailing slashes */
+      *presult++ = '\\';
+
+    *presult++ = '"';
+    *presult++ = 0;
+    return result;
+}
+
+
+
+
+
+
+
+
+
+
+char *loadable_exe(char *exename) {
+    /* HINSTANCE hPython;  DLL handle for python executable */
+    char *result;
+
+    /* hPython = LoadLibraryEx(exename, NULL, LOAD_WITH_ALTERED_SEARCH_PATH);
+    if (!hPython) return NULL; */
+
+    /* Return the absolute filename for spawnv */
+    result = calloc(MAX_PATH, sizeof(char));
+    strncpy(result, exename, MAX_PATH);
+    /*if (result) GetModuleFileNameA(hPython, result, MAX_PATH);
+
+    FreeLibrary(hPython); */
+    return result;
+}
+
+
+char *find_exe(char *exename, char *script) {
+    char drive[_MAX_DRIVE], dir[_MAX_DIR], fname[_MAX_FNAME], ext[_MAX_EXT];
+    char path[_MAX_PATH], c, *result;
+
+    /* convert slashes to backslashes for uniform search below */
+    result = exename;
+    while (c = *result++) if (c=='/') result[-1] = '\\';
+
+    _splitpath(exename, drive, dir, fname, ext);
+    if (drive[0] || dir[0]=='\\') {
+        return loadable_exe(exename);   /* absolute path, use directly */
+    }
+    /* Use the script's parent directory, which should be the Python home
+       (This should only be used for bdist_wininst-installed scripts, because
+        easy_install-ed scripts use the absolute path to python[w].exe
+    */
+    _splitpath(script, drive, dir, fname, ext);
+    result = dir + strlen(dir) -1;
+    if (*result == '\\') result--;
+    while (*result != '\\' && result>=dir) *result-- = 0;
+    _makepath(path, drive, dir, exename, NULL);
+    return loadable_exe(path);
+}
+
+
+char **parse_argv(char *cmdline, int *argc)
+{
+    /* Parse a command line in-place using MS C rules */
+
+    char **result = calloc(strlen(cmdline), sizeof(char *));
+    char *output = cmdline;
+    char c;
+    int nb = 0;
+    int iq = 0;
+    *argc = 0;
+
+    result[0] = output;
+    while (isspace(*cmdline)) cmdline++;   /* skip leading spaces */
+
+    do {
+        c = *cmdline++;
+        if (!c || (isspace(c) && !iq)) {
+            while (nb) {*output++ = '\\'; nb--; }
+            *output++ = 0;
+            result[++*argc] = output;
+            if (!c) return result;
+            while (isspace(*cmdline)) cmdline++;  /* skip leading spaces */
+            if (!*cmdline) return result;  /* avoid empty arg if trailing ws */
+            continue;
+        }
+        if (c == '\\')
+            ++nb;   /* count \'s */
+        else {
+            if (c == '"') {
+                if (!(nb & 1)) { iq = !iq; c = 0; }  /* skip " unless odd # of \ */
+                nb = nb >> 1;   /* cut \'s in half */
+            }
+            while (nb) {*output++ = '\\'; nb--; }
+            if (c) *output++ = c;
+        }
+    } while (1);
+}
+
+void pass_control_to_child(DWORD control_type) {
+    /*
+     * distribute-issue207
+     * passes the control event to child process (Python)
+     */
+    if (!child_pid) {
+        return;
+    }
+    GenerateConsoleCtrlEvent(child_pid,0);
+}
+
+BOOL control_handler(DWORD control_type) {
+    /*
+     * distribute-issue207
+     * control event handler callback function
+     */
+    switch (control_type) {
+        case CTRL_C_EVENT:
+            pass_control_to_child(0);
+            break;
+    }
+    return TRUE;
+}
+
+int create_and_wait_for_subprocess(char* command) {
+    /*
+     * distribute-issue207
+     * launches child process (Python)
+     */
+    DWORD return_value = 0;
+    LPSTR commandline = command;
+    STARTUPINFOA s_info;
+    PROCESS_INFORMATION p_info;
+    ZeroMemory(&p_info, sizeof(p_info));
+    ZeroMemory(&s_info, sizeof(s_info));
+    s_info.cb = sizeof(STARTUPINFO);
+    // set-up control handler callback funciotn
+    SetConsoleCtrlHandler((PHANDLER_ROUTINE) control_handler, TRUE);
+    if (!CreateProcessA(NULL, commandline, NULL, NULL, TRUE, 0, NULL, NULL, &s_info, &p_info)) {
+        fprintf(stderr, "failed to create process.\n");
+        return 0;
+    }
+    child_pid = p_info.dwProcessId;
+    // wait for Python to exit
+    WaitForSingleObject(p_info.hProcess, INFINITE);
+    if (!GetExitCodeProcess(p_info.hProcess, &return_value)) {
+        fprintf(stderr, "failed to get exit code from process.\n");
+        return 0;
+    }
+    return return_value;
+}
+
+char* join_executable_and_args(char *executable, char **args, int argc)
+{
+    /*
+     * distribute-issue207
+     * CreateProcess needs a long string of the executable and command-line arguments,
+     * so we need to convert it from the args that was built
+     */
+    int len,counter;
+    char* cmdline;
+
+    len=strlen(executable)+2;
+    for (counter=1; counter<argc; counter++) {
+        len+=strlen(args[counter])+1;
+    }
+
+    cmdline = (char*)calloc(len, sizeof(char));
+    sprintf(cmdline, "%s", executable);
+    len=strlen(executable);
+    for (counter=1; counter<argc; counter++) {
+        sprintf(cmdline+len, " %s", args[counter]);
+        len+=strlen(args[counter])+1;
+    }
+    return cmdline;
+}
+
+int run(int argc, char **argv, int is_gui) {
+
+    char python[256];   /* python executable's filename*/
+    char *pyopt;        /* Python option */
+    char script[256];   /* the script's filename */
+
+    int scriptf;        /* file descriptor for script file */
+
+    char **newargs, **newargsp, **parsedargs; /* argument array for exec */
+    char *ptr, *end;    /* working pointers for string manipulation */
+    char *cmdline;
+    int i, parsedargc;              /* loop counter */
+
+    /* compute script name from our .exe name*/
+    GetModuleFileNameA(NULL, script, sizeof(script));
+    end = script + strlen(script);
+    while( end>script && *end != '.')
+        *end-- = '\0';
+    *end-- = '\0';
+    strcat(script, (GUI ? "-script.pyw" : "-script.py"));
+
+    /* figure out the target python executable */
+
+    scriptf = open(script, O_RDONLY);
+    if (scriptf == -1) {
+        return fail("Cannot open %s\n", script);
+    }
+    end = python + read(scriptf, python, sizeof(python));
+    close(scriptf);
+
+    ptr = python-1;
+    while(++ptr < end && *ptr && *ptr!='\n' && *ptr!='\r') {;}
+
+    *ptr-- = '\0';
+
+    if (strncmp(python, "#!", 2)) {
+        /* default to python.exe if no #! header */
+        strcpy(python, "#!python.exe");
+    }
+
+    parsedargs = parse_argv(python+2, &parsedargc);
+
+    /* Using spawnv() can fail strangely if you e.g. find the Cygwin
+       Python, so we'll make sure Windows can find and load it */
+
+    ptr = find_exe(parsedargs[0], script);
+    if (!ptr) {
+        return fail("Cannot find Python executable %s\n", parsedargs[0]);
+    }
+
+    /* printf("Python executable: %s\n", ptr); */
+
+    /* Argument array needs to be
+       parsedargc + argc, plus 1 for null sentinel */
+
+    newargs = (char **)calloc(parsedargc + argc + 1, sizeof(char *));
+    newargsp = newargs;
+
+    *newargsp++ = quoted(ptr);
+    for (i = 1; i<parsedargc; i++) *newargsp++ = quoted(parsedargs[i]);
+
+    *newargsp++ = quoted(script);
+    for (i = 1; i < argc; i++)     *newargsp++ = quoted(argv[i]);
+
+    *newargsp++ = NULL;
+
+    /* printf("args 0: %s\nargs 1: %s\n", newargs[0], newargs[1]); */
+
+    if (is_gui) {
+        /* Use exec, we don't need to wait for the GUI to finish */
+        execv(ptr, (const char * const *)(newargs));
+        return fail("Could not exec %s", ptr);   /* shouldn't get here! */
+    }
+
+    /*
+     * distribute-issue207: using CreateProcessA instead of spawnv
+     */
+    cmdline = join_executable_and_args(ptr, newargs, parsedargc + argc);
+    return create_and_wait_for_subprocess(cmdline);
+}
+
+int WINAPI WinMain(HINSTANCE hI, HINSTANCE hP, LPSTR lpCmd, int nShow) {
+    return run(__argc, __argv, GUI);
+}
+
+int main(int argc, char** argv) {
+    return run(argc, argv, GUI);
+}

From 04e920337b1b984929d3d69fb2ab1f8b1e92f032 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 17:50:20 +0100
Subject: [PATCH 481/528] Fix a syntax bug in ilang backend related to process
 case statements

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/ilang/ilang_backend.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 4c58ea087..dc39e5e08 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -204,7 +204,7 @@ void ILANG_BACKEND::dump_proc_switch(std::ostream &f, std::string indent, const
 		f << stringf("%s  case ", indent.c_str());
 		for (size_t i = 0; i < (*it)->compare.size(); i++) {
 			if (i > 0)
-				f << stringf(", ");
+				f << stringf(" , ");
 			dump_sigspec(f, (*it)->compare[i]);
 		}
 		f << stringf("\n");

From 17caaa3fa898e39d1dbcfd8b92750a9d713a24af Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 17:51:21 +0100
Subject: [PATCH 482/528] Improve handling of "full_case" attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/genrtlil.cc | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index d7da6fb40..b3a2a84be 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -525,7 +525,16 @@ struct AST_INTERNAL::ProcessGenerator
 				}
 
 				if (last_generated_case != NULL && ast->get_bool_attribute("\\full_case") && default_case == NULL) {
+			#if 0
+					// this is a valid transformation, but as optimization it is premature.
+					// better: add a default case that assigns 'x' to everything, and let later
+					// optimizations take care of the rest
 					last_generated_case->compare.clear();
+			#else
+					default_case = new RTLIL::CaseRule;
+					addChunkActions(default_case->actions, this_case_eq_ltemp, SigSpec(State::Sx, GetSize(this_case_eq_rvalue)));
+					sw->cases.push_back(default_case);
+			#endif
 				} else {
 					if (default_case == NULL) {
 						default_case = new RTLIL::CaseRule;

From f806b95ed6a2f2c1a0e5c8884676fd384e510143 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 20:35:15 +0100
Subject: [PATCH 483/528] Improve handling of and-with-1 and or-with-0 in
 opt_expr, fixes #327

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/opt_expr.cc | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 26a3ca7bc..a05db2a4f 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -155,6 +155,13 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
 			new_b.append_bit(it.first.second);
 		}
 
+		if (cell->type.in("$and", "$or") && i == GRP_CONST_A) {
+			log("  Direct Connection: %s (%s with %s)\n", log_signal(new_b), log_id(cell->type), log_signal(new_a));
+			module->connect(new_y, new_b);
+			module->connect(new_conn);
+			continue;
+		}
+
 		RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
 
 		c->setPort("\\A", new_a);

From ea8ee2414053101bae26cfc2a537d42daf57f5e0 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Mar 2019 17:01:59 +0100
Subject: [PATCH 484/528] Add basic "mutate -list N" framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/Makefile.inc |   1 +
 passes/sat/mutate.cc    | 229 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 230 insertions(+)
 create mode 100644 passes/sat/mutate.cc

diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc
index 6cb1ea644..e91df1eb0 100644
--- a/passes/sat/Makefile.inc
+++ b/passes/sat/Makefile.inc
@@ -9,4 +9,5 @@ OBJS += passes/sat/assertpmux.o
 OBJS += passes/sat/clk2fflogic.o
 OBJS += passes/sat/async2sync.o
 OBJS += passes/sat/supercover.o
+OBJS += passes/sat/mutate.o
 
diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
new file mode 100644
index 000000000..5fd89b7d0
--- /dev/null
+++ b/passes/sat/mutate.cc
@@ -0,0 +1,229 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct mutate_t {
+	std::string mode, src;
+	IdString modname, cellname, celltype, cellport;
+	SigBit outsigbit;
+	int portbit = -1;
+};
+
+struct mutate_opts_t {
+	std::string mode;
+	IdString module, cell, port;
+	int bit = -1;
+};
+
+void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, const mutate_t &entry)
+{
+	if (!opts.module.empty() && opts.module != entry.modname)
+		return;
+
+	if (!opts.cell.empty() && opts.cell != entry.cellname)
+		return;
+
+	if (!opts.port.empty() && opts.port != entry.cellport)
+		return;
+
+	if (opts.bit >= 0 && opts.bit != entry.portbit)
+		return;
+
+	database.push_back(entry);
+}
+
+void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N)
+{
+}
+
+struct MutatePass : public Pass {
+	MutatePass() : Pass("mutate", "generate or apply design mutations") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    mutate -list N [options] [selection]\n");
+		log("\n");
+		log("Create a list of N mutations using an even sampling.\n");
+		log("\n");
+		log("    -o filename\n");
+		log("        Write list to this file instead of console output\n");
+		log("\n");
+		log("\n");
+		log("    mutate -mode MODE [options]\n");
+		log("\n");
+		log("Apply the given mutation.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		mutate_opts_t opts;
+		string filename;
+		int N = -1;
+
+		log_header(design, "Executing MUTATE pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-list" && argidx+1 < args.size()) {
+				N = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-o" && argidx+1 < args.size()) {
+				filename = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-mode" && argidx+1 < args.size()) {
+				opts.mode = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-module" && argidx+1 < args.size()) {
+				opts.module = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-cell" && argidx+1 < args.size()) {
+				opts.cell = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-port" && argidx+1 < args.size()) {
+				opts.port = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-bit" && argidx+1 < args.size()) {
+				opts.bit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (N >= 0)
+		{
+			std::vector<mutate_t> database;
+
+			for (auto module : design->selected_modules())
+			{
+				if (!opts.module.empty() && module->name != opts.module)
+					continue;
+
+				SigMap sigmap(module);
+
+				for (auto wire : module->selected_wires())
+				{
+					for (SigBit bit : SigSpec(wire))
+					{
+						SigBit sigbit = sigmap(bit);
+
+						if (bit.wire == nullptr || sigbit.wire == nullptr)
+							continue;
+
+						if (!bit.wire->port_id != !sigbit.wire->port_id) {
+							if (bit.wire->port_id)
+								sigmap.add(bit);
+							continue;
+						}
+
+						if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
+							if (bit.wire->name[0] == '\\')
+								sigmap.add(bit);
+							continue;
+						}
+					}
+				}
+
+				for (auto cell : module->selected_cells())
+				{
+					if (!opts.cell.empty() && cell->name != opts.cell)
+						continue;
+
+					for (auto &conn : cell->connections())
+					{
+						for (int i = 0; i < GetSize(conn.second); i++) {
+							mutate_t entry;
+							entry.mode = "inv";
+							entry.src = cell->get_src_attribute();
+							entry.modname = module->name;
+							entry.cellname = cell->name;
+							entry.celltype = cell->type;
+							entry.cellport = conn.first;
+							entry.portbit = i;
+
+							if (cell->output(conn.first)) {
+								SigBit bit = sigmap(conn.second[i]);
+								if (bit.wire && bit.wire->name[0] == '\\')
+									entry.outsigbit = bit;
+							}
+
+							database_add(database, opts, entry);
+						}
+					}
+				}
+			}
+
+			log("Raw database size: %d\n", GetSize(database));
+			if (N != 0) {
+				database_reduce(database, opts, N);
+				log("Reduced database size: %d\n", GetSize(database));
+			}
+
+			std::ofstream fout;
+
+			if (!filename.empty()) {
+				fout.open(filename, std::ios::out | std::ios::trunc);
+				if (!fout.is_open())
+					log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
+			}
+
+			for (auto &entry : database) {
+				string str = stringf("mutate -mode %s", entry.mode.c_str());
+				if (!entry.modname.empty())
+					str += stringf(" -module %s", log_id(entry.modname));
+				if (!entry.cellname.empty())
+					str += stringf(" -cell %s", log_id(entry.cellname));
+				if (!entry.cellport.empty())
+					str += stringf(" -port %s", log_id(entry.cellport));
+				if (entry.portbit >= 0)
+					str += stringf(" -bit %d", entry.portbit);
+				if (entry.outsigbit.wire || !entry.src.empty()) {
+					str += " #";
+					if (!entry.src.empty())
+						str += stringf(" %s", entry.src.c_str());
+					if (entry.outsigbit.wire)
+						str += stringf(" %s", log_signal(entry.outsigbit));
+				}
+				if (filename.empty())
+					log("%s\n", str.c_str());
+				else
+					fout << str << std::endl;
+			}
+
+			return;
+		}
+
+		log_cmd_error("Invalid mode: %s\n", opts.mode.c_str());
+	}
+} MutatePass;
+
+PRIVATE_NAMESPACE_END

From 8e6b69d7bba21dd3fa01064ee698dcd409b5dcc8 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 13 Mar 2019 16:09:47 +0100
Subject: [PATCH 485/528] Add "mutate -mode inv", various other mutate
 improvements

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 312 +++++++++++++++++++++++++++++--------------
 1 file changed, 213 insertions(+), 99 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 5fd89b7d0..04aebd897 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -34,10 +34,16 @@ struct mutate_opts_t {
 	std::string mode;
 	IdString module, cell, port;
 	int bit = -1;
+
+	IdString ctrl_name;
+	int ctrl_width, ctrl_value;
 };
 
 void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, const mutate_t &entry)
 {
+	if (!opts.mode.empty() && opts.mode != entry.mode)
+		return;
+
 	if (!opts.module.empty() && opts.module != entry.modname)
 		return;
 
@@ -57,6 +63,183 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 {
 }
 
+void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)
+{
+	std::vector<mutate_t> database;
+
+	for (auto module : design->selected_modules())
+	{
+		if (!opts.module.empty() && module->name != opts.module)
+			continue;
+
+		SigMap sigmap(module);
+
+		for (auto wire : module->selected_wires())
+		{
+			for (SigBit bit : SigSpec(wire))
+			{
+				SigBit sigbit = sigmap(bit);
+
+				if (bit.wire == nullptr || sigbit.wire == nullptr)
+					continue;
+
+				if (!bit.wire->port_id != !sigbit.wire->port_id) {
+					if (bit.wire->port_id)
+						sigmap.add(bit);
+					continue;
+				}
+
+				if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
+					if (bit.wire->name[0] == '\\')
+						sigmap.add(bit);
+					continue;
+				}
+			}
+		}
+
+		for (auto cell : module->selected_cells())
+		{
+			if (!opts.cell.empty() && cell->name != opts.cell)
+				continue;
+
+			for (auto &conn : cell->connections())
+			{
+				for (int i = 0; i < GetSize(conn.second); i++) {
+					mutate_t entry;
+					entry.mode = "inv";
+					entry.src = cell->get_src_attribute();
+					entry.modname = module->name;
+					entry.cellname = cell->name;
+					entry.celltype = cell->type;
+					entry.cellport = conn.first;
+					entry.portbit = i;
+
+					if (cell->output(conn.first)) {
+						SigBit bit = sigmap(conn.second[i]);
+						if (bit.wire && bit.wire->name[0] == '\\')
+							entry.outsigbit = bit;
+					}
+
+					database_add(database, opts, entry);
+				}
+			}
+		}
+	}
+
+	log("Raw database size: %d\n", GetSize(database));
+	if (N != 0) {
+		database_reduce(database, opts, N);
+		log("Reduced database size: %d\n", GetSize(database));
+	}
+
+	std::ofstream fout;
+
+	if (!filename.empty()) {
+		fout.open(filename, std::ios::out | std::ios::trunc);
+		if (!fout.is_open())
+			log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
+	}
+
+	for (auto &entry : database) {
+		string str = stringf("mutate -mode %s", entry.mode.c_str());
+		if (!entry.modname.empty())
+			str += stringf(" -module %s", log_id(entry.modname));
+		if (!entry.cellname.empty())
+			str += stringf(" -cell %s", log_id(entry.cellname));
+		if (!entry.cellport.empty())
+			str += stringf(" -port %s", log_id(entry.cellport));
+		if (entry.portbit >= 0)
+			str += stringf(" -bit %d", entry.portbit);
+		if (entry.outsigbit.wire || !entry.src.empty()) {
+			str += " #";
+			if (!entry.src.empty())
+				str += stringf(" %s", entry.src.c_str());
+			if (entry.outsigbit.wire)
+				str += stringf(" %s", log_signal(entry.outsigbit));
+		}
+		if (filename.empty())
+			log("%s\n", str.c_str());
+		else
+			fout << str << std::endl;
+	}
+}
+
+SigSpec mutate_ctrl_sig(Module *module, IdString name, int width)
+{
+	Wire *ctrl_wire = module->wire(name);
+
+	if (ctrl_wire == nullptr)
+	{
+		log("Adding ctrl port %s to module %s.\n", log_id(name), log_id(module));
+
+		ctrl_wire = module->addWire(name, width);
+		ctrl_wire->port_input = true;
+		module->fixup_ports();
+
+		for (auto mod : module->design->modules())
+		for (auto cell : mod->cells())
+		{
+			if (cell->type != module->name)
+				continue;
+
+			SigSpec ctrl = mutate_ctrl_sig(mod, name, width);
+
+			log("Connecting ctrl port to cell %s in module %s.\n", log_id(cell), log_id(mod));
+			cell->setPort(name, ctrl);
+		}
+	}
+
+	log_assert(GetSize(ctrl_wire) == width);
+	return ctrl_wire;
+}
+
+SigBit mutate_ctrl(Module *module, const mutate_opts_t &opts)
+{
+	if (opts.ctrl_name.empty())
+		return State::S1;
+
+	SigSpec sig = mutate_ctrl_sig(module, opts.ctrl_name, opts.ctrl_width);
+	return module->Eq(NEW_ID, sig, Const(opts.ctrl_value, GetSize(sig)));
+}
+
+SigSpec mutate_ctrl_mux(Module *module, const mutate_opts_t &opts, SigSpec unchanged_sig, SigSpec changed_sig)
+{
+	SigBit ctrl_bit = mutate_ctrl(module, opts);
+	if (ctrl_bit == State::S0)
+		return unchanged_sig;
+	if (ctrl_bit == State::S1)
+		return changed_sig;
+	return module->Mux(NEW_ID, unchanged_sig, changed_sig, ctrl_bit);
+}
+
+void mutate_inv(Design *design, const mutate_opts_t &opts)
+{
+	Module *module = design->module(opts.module);
+	Cell *cell = module->cell(opts.cell);
+
+	SigBit bit = cell->getPort(opts.port)[opts.bit];
+	SigBit inbit, outbit;
+
+	if (cell->input(opts.port))
+	{
+		log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.bit);
+		SigBit outbit = module->Not(NEW_ID, bit);
+		bit = mutate_ctrl_mux(module, opts, bit, outbit);
+	}
+	else
+	{
+		log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.bit);
+		SigBit inbit = module->addWire(NEW_ID);
+		SigBit outbit = module->Not(NEW_ID, inbit);
+		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
+		bit = inbit;
+	}
+
+	SigSpec s = cell->getPort(opts.port);
+	s[opts.bit] = bit;
+	cell->setPort(opts.port, s);
+}
+
 struct MutatePass : public Pass {
 	MutatePass() : Pass("mutate", "generate or apply design mutations") { }
 	void help() YS_OVERRIDE
@@ -70,11 +253,29 @@ struct MutatePass : public Pass {
 		log("    -o filename\n");
 		log("        Write list to this file instead of console output\n");
 		log("\n");
+		log("    -mode name\n");
+		log("    -module name\n");
+		log("    -cell name\n");
+		log("    -port name\n");
+		log("    -bit int\n");
+		log("        Filter list of mutation candidates to those matching\n");
+		log("        the given parameters.\n");
+		log("\n");
 		log("\n");
 		log("    mutate -mode MODE [options]\n");
 		log("\n");
 		log("Apply the given mutation.\n");
 		log("\n");
+		log("    -ctrl name width value\n");
+		log("        Add a control signal with the given name and width. The mutation is\n");
+		log("        activated if the control signal equals the given value.\n");
+		log("\n");
+		log("    -module name\n");
+		log("    -cell name\n");
+		log("    -port name\n");
+		log("    -bit int\n");
+		log("        Mutation parameters, as generated by 'mutate -list N'.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -99,6 +300,12 @@ struct MutatePass : public Pass {
 				opts.mode = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-ctrl" && argidx+3 < args.size()) {
+				opts.ctrl_name = RTLIL::escape_id(args[++argidx]);
+				opts.ctrl_width = atoi(args[++argidx].c_str());
+				opts.ctrl_value = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-module" && argidx+1 < args.size()) {
 				opts.module = RTLIL::escape_id(args[++argidx]);
 				continue;
@@ -119,106 +326,13 @@ struct MutatePass : public Pass {
 		}
 		extra_args(args, argidx, design);
 
-		if (N >= 0)
-		{
-			std::vector<mutate_t> database;
-
-			for (auto module : design->selected_modules())
-			{
-				if (!opts.module.empty() && module->name != opts.module)
-					continue;
-
-				SigMap sigmap(module);
-
-				for (auto wire : module->selected_wires())
-				{
-					for (SigBit bit : SigSpec(wire))
-					{
-						SigBit sigbit = sigmap(bit);
-
-						if (bit.wire == nullptr || sigbit.wire == nullptr)
-							continue;
-
-						if (!bit.wire->port_id != !sigbit.wire->port_id) {
-							if (bit.wire->port_id)
-								sigmap.add(bit);
-							continue;
-						}
-
-						if (!bit.wire->name[0] != !sigbit.wire->name[0]) {
-							if (bit.wire->name[0] == '\\')
-								sigmap.add(bit);
-							continue;
-						}
-					}
-				}
-
-				for (auto cell : module->selected_cells())
-				{
-					if (!opts.cell.empty() && cell->name != opts.cell)
-						continue;
-
-					for (auto &conn : cell->connections())
-					{
-						for (int i = 0; i < GetSize(conn.second); i++) {
-							mutate_t entry;
-							entry.mode = "inv";
-							entry.src = cell->get_src_attribute();
-							entry.modname = module->name;
-							entry.cellname = cell->name;
-							entry.celltype = cell->type;
-							entry.cellport = conn.first;
-							entry.portbit = i;
-
-							if (cell->output(conn.first)) {
-								SigBit bit = sigmap(conn.second[i]);
-								if (bit.wire && bit.wire->name[0] == '\\')
-									entry.outsigbit = bit;
-							}
-
-							database_add(database, opts, entry);
-						}
-					}
-				}
-			}
-
-			log("Raw database size: %d\n", GetSize(database));
-			if (N != 0) {
-				database_reduce(database, opts, N);
-				log("Reduced database size: %d\n", GetSize(database));
-			}
-
-			std::ofstream fout;
-
-			if (!filename.empty()) {
-				fout.open(filename, std::ios::out | std::ios::trunc);
-				if (!fout.is_open())
-					log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
-			}
-
-			for (auto &entry : database) {
-				string str = stringf("mutate -mode %s", entry.mode.c_str());
-				if (!entry.modname.empty())
-					str += stringf(" -module %s", log_id(entry.modname));
-				if (!entry.cellname.empty())
-					str += stringf(" -cell %s", log_id(entry.cellname));
-				if (!entry.cellport.empty())
-					str += stringf(" -port %s", log_id(entry.cellport));
-				if (entry.portbit >= 0)
-					str += stringf(" -bit %d", entry.portbit);
-				if (entry.outsigbit.wire || !entry.src.empty()) {
-					str += " #";
-					if (!entry.src.empty())
-						str += stringf(" %s", entry.src.c_str());
-					if (entry.outsigbit.wire)
-						str += stringf(" %s", log_signal(entry.outsigbit));
-				}
-				if (filename.empty())
-					log("%s\n", str.c_str());
-				else
-					fout << str << std::endl;
-			}
+		if (N >= 0) {
+			mutate_list(design, opts, filename, N);
+			return;
+		}
 
+		if (opts.mode == "inv") {
+			mutate_inv(design, opts);
 			return;
 		}
 

From 76c9c350e7d0dfc11b609d98bdcd1ea0d845cb06 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 13 Mar 2019 17:36:06 +0100
Subject: [PATCH 486/528] Add hashlib "<container>::element(int n)" methods

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/hashlib.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/kernel/hashlib.h b/kernel/hashlib.h
index df534ec1b..e7cb312ed 100644
--- a/kernel/hashlib.h
+++ b/kernel/hashlib.h
@@ -557,9 +557,11 @@ public:
 	void clear() { hashtable.clear(); entries.clear(); }
 
 	iterator begin() { return iterator(this, int(entries.size())-1); }
+	iterator element(int n) { return iterator(this, int(entries.size())-1-n); }
 	iterator end() { return iterator(nullptr, -1); }
 
 	const_iterator begin() const { return const_iterator(this, int(entries.size())-1); }
+	const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }
 	const_iterator end() const { return const_iterator(nullptr, -1); }
 };
 
@@ -881,9 +883,11 @@ public:
 	void clear() { hashtable.clear(); entries.clear(); }
 
 	iterator begin() { return iterator(this, int(entries.size())-1); }
+	iterator element(int n) { return iterator(this, int(entries.size())-1-n); }
 	iterator end() { return iterator(nullptr, -1); }
 
 	const_iterator begin() const { return const_iterator(this, int(entries.size())-1); }
+	const_iterator element(int n) const { return const_iterator(this, int(entries.size())-1-n); }
 	const_iterator end() const { return const_iterator(nullptr, -1); }
 };
 
@@ -952,6 +956,7 @@ public:
 	void clear() { database.clear(); }
 
 	const_iterator begin() const { return database.begin(); }
+	const_iterator element(int n) const { return database.element(n); }
 	const_iterator end() const { return database.end(); }
 };
 
@@ -1051,6 +1056,7 @@ public:
 	void clear() { database.clear(); parents.clear(); }
 
 	const_iterator begin() const { return database.begin(); }
+	const_iterator element(int n) const { return database.element(n); }
 	const_iterator end() const { return database.end(); }
 };
 

From 6ad5d036c58766b2bd0a705c7adfcbf9af4a7d16 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 13 Mar 2019 17:36:37 +0100
Subject: [PATCH 487/528] Add "mutate" command DB reduce functionality

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 193 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 181 insertions(+), 12 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 04aebd897..3ecb955f0 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -25,16 +25,19 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct mutate_t {
 	std::string mode, src;
-	IdString modname, cellname, celltype, cellport;
+	Module *module;
+	Cell *cell;
+	IdString cellport;
 	SigBit outsigbit;
 	int portbit = -1;
+	bool used = false;
 };
 
 struct mutate_opts_t {
+	int seed = 0;
 	std::string mode;
 	IdString module, cell, port;
 	int bit = -1;
-
 	IdString ctrl_name;
 	int ctrl_width, ctrl_value;
 };
@@ -44,10 +47,10 @@ void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, co
 	if (!opts.mode.empty() && opts.mode != entry.mode)
 		return;
 
-	if (!opts.module.empty() && opts.module != entry.modname)
+	if (!opts.module.empty() && opts.module != entry.module->name)
 		return;
 
-	if (!opts.cell.empty() && opts.cell != entry.cellname)
+	if (!opts.cell.empty() && opts.cell != entry.cell->name)
 		return;
 
 	if (!opts.port.empty() && opts.port != entry.cellport)
@@ -59,8 +62,159 @@ void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, co
 	database.push_back(entry);
 }
 
+struct xs128_t
+{
+	uint32_t x = 123456789;
+	uint32_t y = 0, z = 0, w = 0;
+
+	xs128_t(int seed = 0) : w(seed) {
+		next();
+		next();
+		next();
+	}
+
+	void next() {
+		uint32_t t = x ^ (x << 11);
+		x = y, y = z, z = w;
+		w ^= (w >> 19) ^ t ^ (t >> 8);
+	}
+
+	int operator()() {
+		next();
+		return w & 0x3fffffff;
+	}
+
+	int operator()(int n) {
+		if (n < 2)
+			return 0;
+		while (1) {
+			int k = (*this)(), p = k % n;
+			if ((k - p + n) <= 0x40000000)
+				return p;
+		}
+	}
+};
+
+struct mutate_leaf_queue_t
+{
+	pool<mutate_t*, hash_ptr_ops> db;
+
+	mutate_t *pick(xs128_t &rng) {
+		while (!db.empty()) {
+			int i = rng(GetSize(db));
+			auto it = db.element(i);
+			mutate_t *m = *it;
+			db.erase(it);
+			if (m->used == false) {
+				m->used = true;
+				return m;
+			}
+		}
+		return nullptr;
+	}
+
+	void add(mutate_t *m) {
+		db.insert(m);
+	}
+};
+
+template <typename K, typename T>
+struct mutate_inner_queue_t
+{
+	dict<K, T> db;
+
+	mutate_t *pick(xs128_t &rng) {
+		while (!db.empty()) {
+			int i = rng(GetSize(db));
+			auto it = db.element(i);
+			mutate_t *m = it->second.pick(rng);
+			if (m != nullptr)
+				return m;
+			db.erase(it);
+		}
+		return nullptr;
+	}
+
+	template<typename... Args>
+	void add(mutate_t *m, K key, Args... args) {
+		db[key].add(m, args...);
+	}
+};
+
 void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N)
 {
+	if (N >= GetSize(database))
+		return;
+
+	mutate_inner_queue_t<Wire*, mutate_leaf_queue_t> primary_queue_wire;
+	mutate_inner_queue_t<SigBit, mutate_leaf_queue_t> primary_queue_bit;
+	mutate_inner_queue_t<Cell*, mutate_leaf_queue_t> primary_queue_cell;
+	mutate_inner_queue_t<string, mutate_leaf_queue_t> primary_queue_src;
+
+	mutate_inner_queue_t<Module*, mutate_inner_queue_t<Wire*, mutate_leaf_queue_t>> primary_queue_module_wire;
+	mutate_inner_queue_t<Module*, mutate_inner_queue_t<SigBit, mutate_leaf_queue_t>> primary_queue_module_bit;
+	mutate_inner_queue_t<Module*, mutate_inner_queue_t<Cell*, mutate_leaf_queue_t>> primary_queue_module_cell;
+	mutate_inner_queue_t<Module*, mutate_inner_queue_t<string, mutate_leaf_queue_t>> primary_queue_module_src;
+
+	for (auto &m : database)
+	{
+		if (m.outsigbit.wire) {
+			primary_queue_wire.add(&m, m.outsigbit.wire);
+			primary_queue_bit.add(&m, m.outsigbit);
+			primary_queue_module_wire.add(&m, m.module, m.outsigbit.wire);
+			primary_queue_module_bit.add(&m, m.module, m.outsigbit);
+		}
+
+		primary_queue_cell.add(&m, m.cell);
+		primary_queue_module_cell.add(&m, m.module, m.cell);
+
+		if (!m.src.empty()) {
+			primary_queue_src.add(&m, m.src);
+			primary_queue_module_src.add(&m, m.module, m.src);
+		}
+	}
+
+	int weight_pq_w = 100;
+	int weight_pq_b = 100;
+	int weight_pq_c = 100;
+	int weight_pq_s = 100;
+
+	int weight_pq_mw = 100;
+	int weight_pq_mb = 100;
+	int weight_pq_mc = 100;
+	int weight_pq_ms = 100;
+
+	int total_weight = weight_pq_w + weight_pq_b + weight_pq_c + weight_pq_s;
+	total_weight += weight_pq_mw + weight_pq_mb + weight_pq_mc + weight_pq_ms;
+
+	std::vector<mutate_t> new_database;
+	xs128_t rng(opts.seed);
+
+	while (GetSize(new_database) < N)
+	{
+		int k = rng(total_weight);
+
+#define X(__wght, __queue)                \
+    k -= __wght;                          \
+    if (k < 0) {                          \
+      mutate_t *m = __queue.pick(rng);    \
+      if (m != nullptr)                   \
+        new_database.push_back(*m);       \
+      continue;                           \
+    }
+
+		X(weight_pq_w, primary_queue_wire)
+		X(weight_pq_b, primary_queue_bit)
+		X(weight_pq_c, primary_queue_cell)
+		X(weight_pq_s, primary_queue_src)
+
+		X(weight_pq_mw, primary_queue_module_wire)
+		X(weight_pq_mb, primary_queue_module_bit)
+		X(weight_pq_mc, primary_queue_module_cell)
+		X(weight_pq_ms, primary_queue_module_src)
+	}
+
+	std::swap(new_database, database);
 }
 
 void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)
@@ -108,9 +262,8 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 					mutate_t entry;
 					entry.mode = "inv";
 					entry.src = cell->get_src_attribute();
-					entry.modname = module->name;
-					entry.cellname = cell->name;
-					entry.celltype = cell->type;
+					entry.module = module;
+					entry.cell = cell;
 					entry.cellport = conn.first;
 					entry.portbit = i;
 
@@ -140,12 +293,17 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 			log_error("Could not open file \"%s\" with write access.\n", filename.c_str());
 	}
 
+	int ctrl_value = opts.ctrl_value;
+
 	for (auto &entry : database) {
-		string str = stringf("mutate -mode %s", entry.mode.c_str());
-		if (!entry.modname.empty())
-			str += stringf(" -module %s", log_id(entry.modname));
-		if (!entry.cellname.empty())
-			str += stringf(" -cell %s", log_id(entry.cellname));
+		string str = "mutate";
+		if (!opts.ctrl_name.empty())
+			str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
+		str += stringf(" -mode %s", entry.mode.c_str());
+		if (entry.module)
+			str += stringf(" -module %s", log_id(entry.module));
+		if (entry.cell)
+			str += stringf(" -cell %s", log_id(entry.cell));
 		if (!entry.cellport.empty())
 			str += stringf(" -port %s", log_id(entry.cellport));
 		if (entry.portbit >= 0)
@@ -253,6 +411,13 @@ struct MutatePass : public Pass {
 		log("    -o filename\n");
 		log("        Write list to this file instead of console output\n");
 		log("\n");
+		log("    -seed N\n");
+		log("        RNG seed for selecting mutations\n");
+		log("\n");
+		log("    -ctrl name width value\n");
+		log("        Add -ctrl options to the output. Use 'value' for first mutation, then\n");
+		log("        simply count up from there.\n");
+		log("\n");
 		log("    -mode name\n");
 		log("    -module name\n");
 		log("    -cell name\n");
@@ -296,6 +461,10 @@ struct MutatePass : public Pass {
 				filename = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-seed" && argidx+1 < args.size()) {
+				opts.seed = atoi(args[++argidx].c_str());
+				continue;
+			}
 			if (args[argidx] == "-mode" && argidx+1 < args.size()) {
 				opts.mode = args[++argidx];
 				continue;

From bacca5753775bfabed955a9772a5d86d85007c58 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 13 Mar 2019 19:27:17 +0100
Subject: [PATCH 488/528] Fix smtbmc.py handling of zero appended steps

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/smt2/smtbmc.py | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/backends/smt2/smtbmc.py b/backends/smt2/smtbmc.py
index 94a5e2da0..445a42e0d 100644
--- a/backends/smt2/smtbmc.py
+++ b/backends/smt2/smtbmc.py
@@ -1484,11 +1484,11 @@ else:  # not tempind, covermode
                             smt_assert_antecedent("(|%s_h| s%d)" % (topmod, i))
                             smt_assert_antecedent("(|%s_t| s%d s%d)" % (topmod, i-1, i))
                             smt_assert_consequent(get_constr_expr(constr_assumes, i))
-                    print_msg("Re-solving with appended steps..")
-                    if smt_check_sat() == "unsat":
-                        print("%s Cannot appended steps without violating assumptions!" % smt.timestamp())
-                        retstatus = False
-                        break
+                        print_msg("Re-solving with appended steps..")
+                        if smt_check_sat() == "unsat":
+                            print("%s Cannot appended steps without violating assumptions!" % smt.timestamp())
+                            retstatus = False
+                            break
                     print_anyconsts(step)
                     for i in range(step, last_check_step+1):
                         print_failed_asserts(i)

From 1b4fdbb0d881040220cdf1591f415cd2176481ad Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 19:52:02 +0100
Subject: [PATCH 489/528] Add more mutation types, improve mutation src cover

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 362 ++++++++++++++++++++++++++++++++-----------
 1 file changed, 269 insertions(+), 93 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 3ecb955f0..eac00948a 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -24,20 +24,24 @@ USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
 struct mutate_t {
-	std::string mode, src;
-	Module *module;
-	Cell *cell;
-	IdString cellport;
-	SigBit outsigbit;
+	string mode;
+	pool<string> src;
+	IdString module, cell;
+	IdString port, wire;
 	int portbit = -1;
+	int ctrlbit = -1;
+	int wirebit = -1;
 	bool used = false;
 };
 
 struct mutate_opts_t {
 	int seed = 0;
 	std::string mode;
-	IdString module, cell, port;
-	int bit = -1;
+	pool<string> src;
+	IdString module, cell, port, wire;
+	int portbit = -1;
+	int ctrlbit = -1;
+	int wirebit = -1;
 	IdString ctrl_name;
 	int ctrl_width, ctrl_value;
 };
@@ -47,16 +51,35 @@ void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, co
 	if (!opts.mode.empty() && opts.mode != entry.mode)
 		return;
 
-	if (!opts.module.empty() && opts.module != entry.module->name)
+	if (!opts.src.empty()) {
+		bool found_match = false;
+		for (auto &s : opts.src) {
+			if (entry.src.count(s))
+				found_match = true;
+		}
+		if (!found_match)
+			return;
+	}
+
+	if (!opts.module.empty() && opts.module != entry.module)
 		return;
 
-	if (!opts.cell.empty() && opts.cell != entry.cell->name)
+	if (!opts.cell.empty() && opts.cell != entry.cell)
 		return;
 
-	if (!opts.port.empty() && opts.port != entry.cellport)
+	if (!opts.port.empty() && opts.port != entry.port)
 		return;
 
-	if (opts.bit >= 0 && opts.bit != entry.portbit)
+	if (opts.portbit >= 0 && opts.portbit != entry.portbit)
+		return;
+
+	if (opts.ctrlbit >= 0 && opts.ctrlbit != entry.ctrlbit)
+		return;
+
+	if (!opts.wire.empty() && opts.wire != entry.wire)
+		return;
+
+	if (opts.wirebit >= 0 && opts.wirebit != entry.wirebit)
 		return;
 
 	database.push_back(entry);
@@ -99,18 +122,48 @@ struct mutate_leaf_queue_t
 {
 	pool<mutate_t*, hash_ptr_ops> db;
 
-	mutate_t *pick(xs128_t &rng) {
-		while (!db.empty()) {
-			int i = rng(GetSize(db));
-			auto it = db.element(i);
-			mutate_t *m = *it;
-			db.erase(it);
-			if (m->used == false) {
-				m->used = true;
-				return m;
+	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb) {
+		mutate_t *m = nullptr;
+		if (rng(3)) {
+			vector<mutate_t*> candidates;
+			int best_score = -1;
+			for (auto p : db) {
+				if (p->used || p->src.empty())
+					continue;
+				int this_score = -1;
+				for (auto &s : p->src) {
+					if (this_score == -1 || this_score > coverdb.at(s))
+						this_score = coverdb.at(s);
+				}
+				log_assert(this_score != -1);
+				if (best_score == -1 || this_score < best_score) {
+					candidates.clear();
+					best_score = this_score;
+				}
+				if (best_score == this_score)
+					candidates.push_back(p);
+			}
+			if (!candidates.empty())
+				m = candidates[rng(GetSize(candidates))];
+		}
+		if (m == nullptr) {
+			while (!db.empty()) {
+				int i = rng(GetSize(db));
+				auto it = db.element(i);
+				mutate_t *p = *it;
+				db.erase(it);
+				if (p->used == false) {
+					m = p;
+					break;
+				}
 			}
 		}
-		return nullptr;
+		if (m != nullptr) {
+			m->used = true;
+			for (auto &s : m->src)
+				coverdb[s]++;
+		}
+		return m;
 	}
 
 	void add(mutate_t *m) {
@@ -123,11 +176,11 @@ struct mutate_inner_queue_t
 {
 	dict<K, T> db;
 
-	mutate_t *pick(xs128_t &rng) {
+	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb) {
 		while (!db.empty()) {
 			int i = rng(GetSize(db));
 			auto it = db.element(i);
-			mutate_t *m = it->second.pick(rng);
+			mutate_t *m = it->second.pick(rng, coverdb);
 			if (m != nullptr)
 				return m;
 			db.erase(it);
@@ -141,38 +194,10 @@ struct mutate_inner_queue_t
 	}
 };
 
-void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N)
+void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* opts */, int N, xs128_t &rng)
 {
-	if (N >= GetSize(database))
-		return;
-
-	mutate_inner_queue_t<Wire*, mutate_leaf_queue_t> primary_queue_wire;
-	mutate_inner_queue_t<SigBit, mutate_leaf_queue_t> primary_queue_bit;
-	mutate_inner_queue_t<Cell*, mutate_leaf_queue_t> primary_queue_cell;
-	mutate_inner_queue_t<string, mutate_leaf_queue_t> primary_queue_src;
-
-	mutate_inner_queue_t<Module*, mutate_inner_queue_t<Wire*, mutate_leaf_queue_t>> primary_queue_module_wire;
-	mutate_inner_queue_t<Module*, mutate_inner_queue_t<SigBit, mutate_leaf_queue_t>> primary_queue_module_bit;
-	mutate_inner_queue_t<Module*, mutate_inner_queue_t<Cell*, mutate_leaf_queue_t>> primary_queue_module_cell;
-	mutate_inner_queue_t<Module*, mutate_inner_queue_t<string, mutate_leaf_queue_t>> primary_queue_module_src;
-
-	for (auto &m : database)
-	{
-		if (m.outsigbit.wire) {
-			primary_queue_wire.add(&m, m.outsigbit.wire);
-			primary_queue_bit.add(&m, m.outsigbit);
-			primary_queue_module_wire.add(&m, m.module, m.outsigbit.wire);
-			primary_queue_module_bit.add(&m, m.module, m.outsigbit);
-		}
-
-		primary_queue_cell.add(&m, m.cell);
-		primary_queue_module_cell.add(&m, m.module, m.cell);
-
-		if (!m.src.empty()) {
-			primary_queue_src.add(&m, m.src);
-			primary_queue_module_src.add(&m, m.module, m.src);
-		}
-	}
+	std::vector<mutate_t> new_database;
+	dict<string, int> coverdb;
 
 	int weight_pq_w = 100;
 	int weight_pq_b = 100;
@@ -187,20 +212,49 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 	int total_weight = weight_pq_w + weight_pq_b + weight_pq_c + weight_pq_s;
 	total_weight += weight_pq_mw + weight_pq_mb + weight_pq_mc + weight_pq_ms;
 
-	std::vector<mutate_t> new_database;
-	xs128_t rng(opts.seed);
+	if (N >= GetSize(database))
+		return;
+
+	mutate_inner_queue_t<IdString, mutate_leaf_queue_t> primary_queue_wire;
+	mutate_inner_queue_t<pair<IdString, int>, mutate_leaf_queue_t> primary_queue_bit;
+	mutate_inner_queue_t<IdString, mutate_leaf_queue_t> primary_queue_cell;
+	mutate_inner_queue_t<string, mutate_leaf_queue_t> primary_queue_src;
+
+	mutate_inner_queue_t<IdString, mutate_inner_queue_t<IdString, mutate_leaf_queue_t>> primary_queue_module_wire;
+	mutate_inner_queue_t<IdString, mutate_inner_queue_t<pair<IdString, int>, mutate_leaf_queue_t>> primary_queue_module_bit;
+	mutate_inner_queue_t<IdString, mutate_inner_queue_t<IdString, mutate_leaf_queue_t>> primary_queue_module_cell;
+	mutate_inner_queue_t<IdString, mutate_inner_queue_t<string, mutate_leaf_queue_t>> primary_queue_module_src;
+
+	for (auto &m : database)
+	{
+		if (!m.wire.empty()) {
+			primary_queue_wire.add(&m, m.wire);
+			primary_queue_bit.add(&m, pair<IdString, int>(m.wire, m.wirebit));
+			primary_queue_module_wire.add(&m, m.module, m.wire);
+			primary_queue_module_bit.add(&m, m.module, pair<IdString, int>(m.wire, m.wirebit));
+		}
+
+		primary_queue_cell.add(&m, m.cell);
+		primary_queue_module_cell.add(&m, m.module, m.cell);
+
+		for (auto &s : m.src) {
+			coverdb[s] = 0;
+			primary_queue_src.add(&m, s);
+			primary_queue_module_src.add(&m, m.module, s);
+		}
+	}
 
 	while (GetSize(new_database) < N)
 	{
 		int k = rng(total_weight);
 
-#define X(__wght, __queue)                \
-    k -= __wght;                          \
-    if (k < 0) {                          \
-      mutate_t *m = __queue.pick(rng);    \
-      if (m != nullptr)                   \
-        new_database.push_back(*m);       \
-      continue;                           \
+#define X(__wght, __queue)                         \
+    k -= __wght;                                   \
+    if (k < 0) {                                   \
+      mutate_t *m = __queue.pick(rng, coverdb);    \
+      if (m != nullptr)                            \
+        new_database.push_back(*m);                \
+      continue;                                    \
     }
 
 		X(weight_pq_w, primary_queue_wire)
@@ -215,11 +269,19 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 	}
 
 	std::swap(new_database, database);
+
+	int covered_cnt = 0;
+	for (auto &it : coverdb)
+		if (it.second)
+			covered_cnt++;
+
+	log("Covered %d/%d src attributes (%.2f%%).\n", covered_cnt, GetSize(coverdb), 100.0 * covered_cnt / GetSize(coverdb));
 }
 
 void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)
 {
 	std::vector<mutate_t> database;
+	xs128_t rng(opts.seed);
 
 	for (auto module : design->selected_modules())
 	{
@@ -260,20 +322,40 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 			{
 				for (int i = 0; i < GetSize(conn.second); i++) {
 					mutate_t entry;
-					entry.mode = "inv";
-					entry.src = cell->get_src_attribute();
-					entry.module = module;
-					entry.cell = cell;
-					entry.cellport = conn.first;
+					entry.module = module->name;
+					entry.cell = cell->name;
+					entry.port = conn.first;
 					entry.portbit = i;
 
-					if (cell->output(conn.first)) {
-						SigBit bit = sigmap(conn.second[i]);
-						if (bit.wire && bit.wire->name[0] == '\\')
-							entry.outsigbit = bit;
+					for (auto &s : cell->get_strpool_attribute("\\src"))
+						entry.src.insert(s);
+
+					SigBit bit = sigmap(conn.second[i]);
+					if (bit.wire && bit.wire->name[0] == '\\') {
+						for (auto &s : bit.wire->get_strpool_attribute("\\src"))
+							entry.src.insert(s);
+						entry.wire = bit.wire->name;
+						entry.wirebit = bit.offset;
 					}
 
+					entry.mode = "inv";
 					database_add(database, opts, entry);
+
+					entry.mode = "const0";
+					database_add(database, opts, entry);
+
+					entry.mode = "const1";
+					database_add(database, opts, entry);
+
+					entry.mode = "cnot0";
+					entry.ctrlbit = rng(GetSize(conn.second));
+					if (entry.ctrlbit != entry.portbit && conn.second[entry.ctrlbit].wire)
+						database_add(database, opts, entry);
+
+					entry.mode = "cnot1";
+					entry.ctrlbit = rng(GetSize(conn.second));
+					if (entry.ctrlbit != entry.portbit && conn.second[entry.ctrlbit].wire)
+						database_add(database, opts, entry);
 				}
 			}
 		}
@@ -281,7 +363,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 
 	log("Raw database size: %d\n", GetSize(database));
 	if (N != 0) {
-		database_reduce(database, opts, N);
+		database_reduce(database, opts, N, rng);
 		log("Reduced database size: %d\n", GetSize(database));
 	}
 
@@ -300,21 +382,22 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 		if (!opts.ctrl_name.empty())
 			str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
 		str += stringf(" -mode %s", entry.mode.c_str());
-		if (entry.module)
+		if (!entry.module.empty())
 			str += stringf(" -module %s", log_id(entry.module));
-		if (entry.cell)
+		if (!entry.cell.empty())
 			str += stringf(" -cell %s", log_id(entry.cell));
-		if (!entry.cellport.empty())
-			str += stringf(" -port %s", log_id(entry.cellport));
+		if (!entry.port.empty())
+			str += stringf(" -port %s", log_id(entry.port));
 		if (entry.portbit >= 0)
-			str += stringf(" -bit %d", entry.portbit);
-		if (entry.outsigbit.wire || !entry.src.empty()) {
-			str += " #";
-			if (!entry.src.empty())
-				str += stringf(" %s", entry.src.c_str());
-			if (entry.outsigbit.wire)
-				str += stringf(" %s", log_signal(entry.outsigbit));
-		}
+			str += stringf(" -portbit %d", entry.portbit);
+		if (entry.ctrlbit >= 0)
+			str += stringf(" -ctrlbit %d", entry.ctrlbit);
+		if (!entry.wire.empty())
+			str += stringf(" -wire %s", log_id(entry.wire));
+		if (entry.wirebit >= 0)
+			str += stringf(" -wirebit %d", entry.wirebit);
+		for (auto &s : entry.src)
+			str += stringf(" -src %s", s.c_str());
 		if (filename.empty())
 			log("%s\n", str.c_str());
 		else
@@ -375,18 +458,18 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
 	Module *module = design->module(opts.module);
 	Cell *cell = module->cell(opts.cell);
 
-	SigBit bit = cell->getPort(opts.port)[opts.bit];
+	SigBit bit = cell->getPort(opts.port)[opts.portbit];
 	SigBit inbit, outbit;
 
 	if (cell->input(opts.port))
 	{
-		log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.bit);
+		log("Add input inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
 		SigBit outbit = module->Not(NEW_ID, bit);
 		bit = mutate_ctrl_mux(module, opts, bit, outbit);
 	}
 	else
 	{
-		log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.bit);
+		log("Add output inverter at %s.%s.%s[%d].\n", log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
 		SigBit inbit = module->addWire(NEW_ID);
 		SigBit outbit = module->Not(NEW_ID, inbit);
 		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
@@ -394,7 +477,64 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
 	}
 
 	SigSpec s = cell->getPort(opts.port);
-	s[opts.bit] = bit;
+	s[opts.portbit] = bit;
+	cell->setPort(opts.port, s);
+}
+
+void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
+{
+	Module *module = design->module(opts.module);
+	Cell *cell = module->cell(opts.cell);
+
+	SigBit bit = cell->getPort(opts.port)[opts.portbit];
+	SigBit inbit, outbit;
+
+	if (cell->input(opts.port))
+	{
+		log("Add input constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
+		SigBit outbit = one ? State::S1 : State::S0;
+		bit = mutate_ctrl_mux(module, opts, bit, outbit);
+	}
+	else
+	{
+		log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit);
+		SigBit inbit = module->addWire(NEW_ID);
+		SigBit outbit = one ? State::S1 : State::S0;
+		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
+		bit = inbit;
+	}
+
+	SigSpec s = cell->getPort(opts.port);
+	s[opts.portbit] = bit;
+	cell->setPort(opts.port, s);
+}
+
+void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
+{
+	Module *module = design->module(opts.module);
+	Cell *cell = module->cell(opts.cell);
+
+	SigBit bit = cell->getPort(opts.port)[opts.portbit];
+	SigBit ctrl = cell->getPort(opts.port)[opts.ctrlbit];
+	SigBit inbit, outbit;
+
+	if (cell->input(opts.port))
+	{
+		log("Add input cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
+		SigBit outbit = one ? module->Xor(NEW_ID, bit, ctrl) : module->Xnor(NEW_ID, bit, ctrl);
+		bit = mutate_ctrl_mux(module, opts, bit, outbit);
+	}
+	else
+	{
+		log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, log_id(module), log_id(cell), log_id(opts.port), opts.portbit, opts.ctrlbit);
+		SigBit inbit = module->addWire(NEW_ID);
+		SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
+		module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
+		bit = inbit;
+	}
+
+	SigSpec s = cell->getPort(opts.port);
+	s[opts.portbit] = bit;
 	cell->setPort(opts.port, s);
 }
 
@@ -422,7 +562,11 @@ struct MutatePass : public Pass {
 		log("    -module name\n");
 		log("    -cell name\n");
 		log("    -port name\n");
-		log("    -bit int\n");
+		log("    -portbit int\n");
+		log("    -ctrlbit int\n");
+		log("    -wire name\n");
+		log("    -wirebit int\n");
+		log("    -src string\n");
 		log("        Filter list of mutation candidates to those matching\n");
 		log("        the given parameters.\n");
 		log("\n");
@@ -438,9 +582,15 @@ struct MutatePass : public Pass {
 		log("    -module name\n");
 		log("    -cell name\n");
 		log("    -port name\n");
-		log("    -bit int\n");
+		log("    -portbit int\n");
+		log("    -ctrlbit int\n");
 		log("        Mutation parameters, as generated by 'mutate -list N'.\n");
 		log("\n");
+		log("    -wire name\n");
+		log("    -wirebit int\n");
+		log("    -src string\n");
+		log("        Ignored. (They are generated by -list for documentation purposes.)\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
@@ -487,8 +637,24 @@ struct MutatePass : public Pass {
 				opts.port = RTLIL::escape_id(args[++argidx]);
 				continue;
 			}
-			if (args[argidx] == "-bit" && argidx+1 < args.size()) {
-				opts.bit = atoi(args[++argidx].c_str());
+			if (args[argidx] == "-portbit" && argidx+1 < args.size()) {
+				opts.portbit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-ctrlbit" && argidx+1 < args.size()) {
+				opts.ctrlbit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-wire" && argidx+1 < args.size()) {
+				opts.wire = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-wirebit" && argidx+1 < args.size()) {
+				opts.wirebit = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-src" && argidx+1 < args.size()) {
+				opts.src.insert(args[++argidx]);
 				continue;
 			}
 			break;
@@ -505,6 +671,16 @@ struct MutatePass : public Pass {
 			return;
 		}
 
+		if (opts.mode == "const0" || opts.mode == "const1") {
+			mutate_const(design, opts, opts.mode == "const1");
+			return;
+		}
+
+		if (opts.mode == "cnot0" || opts.mode == "cnot1") {
+			mutate_cnot(design, opts, opts.mode == "cnot1");
+			return;
+		}
+
 		log_cmd_error("Invalid mode: %s\n", opts.mode.c_str());
 	}
 } MutatePass;

From 2a4263a75d0bbbc5b8f2de797b572d6f1d64818b Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 23:01:01 +0100
Subject: [PATCH 490/528] Improve "mutate" wire coverage metric

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index eac00948a..243a1b48a 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -289,6 +289,21 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 			continue;
 
 		SigMap sigmap(module);
+		dict<SigBit, int> bit_user_cnt;
+
+		for (auto wire : module->wires()) {
+			if (wire->name[0] == '\\' && wire->attributes.count("\\src"))
+				sigmap.add(wire);
+		}
+
+		for (auto cell : module->cells()) {
+			for (auto &conn : cell->connections()) {
+				if (cell->output(conn.first))
+					continue;
+				for (auto bit : sigmap(conn.second))
+					bit_user_cnt[bit]++;
+			}
+		}
 
 		for (auto wire : module->selected_wires())
 		{
@@ -331,7 +346,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 						entry.src.insert(s);
 
 					SigBit bit = sigmap(conn.second[i]);
-					if (bit.wire && bit.wire->name[0] == '\\') {
+					if (bit.wire && bit.wire->name[0] == '\\' && (cell->output(conn.first) || bit_user_cnt[bit] == 1)) {
 						for (auto &s : bit.wire->get_strpool_attribute("\\src"))
 							entry.src.insert(s);
 						entry.wire = bit.wire->name;

From 4d304e3da77a571d1febfebca1409f522177af38 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 23:01:55 +0100
Subject: [PATCH 491/528] Add a strictly coverage-driven mutation selection
 strategy

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 71 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 70 insertions(+), 1 deletion(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 243a1b48a..440e8b056 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -199,6 +199,8 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* op
 	std::vector<mutate_t> new_database;
 	dict<string, int> coverdb;
 
+	int weight_cover = 500;
+
 	int weight_pq_w = 100;
 	int weight_pq_b = 100;
 	int weight_pq_c = 100;
@@ -209,7 +211,7 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* op
 	int weight_pq_mc = 100;
 	int weight_pq_ms = 100;
 
-	int total_weight = weight_pq_w + weight_pq_b + weight_pq_c + weight_pq_s;
+	int total_weight = weight_cover + weight_pq_w + weight_pq_b + weight_pq_c + weight_pq_s;
 	total_weight += weight_pq_mw + weight_pq_mb + weight_pq_mc + weight_pq_ms;
 
 	if (N >= GetSize(database))
@@ -244,10 +246,76 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* op
 		}
 	}
 
+	vector<mutate_t*> cover_candidates;
+	int best_cover_score = -1;
+	bool skip_cover = false;
+
 	while (GetSize(new_database) < N)
 	{
 		int k = rng(total_weight);
 
+		k -= weight_cover;
+		if (k < 0) {
+			while (!skip_cover) {
+				if (cover_candidates.empty()) {
+					best_cover_score = -1;
+					for (auto &m : database) {
+						if (m.used || m.src.empty())
+							continue;
+						int this_score = -1;
+						for (auto &s : m.src) {
+							if (this_score == -1 || this_score > coverdb.at(s))
+								this_score = coverdb.at(s);
+						}
+						log_assert(this_score != -1);
+						if (best_cover_score == -1 || this_score < best_cover_score) {
+							cover_candidates.clear();
+							best_cover_score = this_score;
+						}
+						if (best_cover_score == this_score)
+							cover_candidates.push_back(&m);
+					}
+					if (best_cover_score == -1) {
+						skip_cover = true;
+						break;
+					}
+				}
+
+				mutate_t *m = nullptr;
+				while (!cover_candidates.empty())
+				{
+					int idx = rng(GetSize(cover_candidates));
+					mutate_t *p = cover_candidates[idx];
+					cover_candidates[idx] = cover_candidates.back();
+					cover_candidates.pop_back();
+
+					if (p->used)
+						continue;
+
+					int this_score = -1;
+					for (auto &s : p->src) {
+						if (this_score == -1 || this_score > coverdb.at(s))
+							this_score = coverdb.at(s);
+					}
+
+					if (this_score != best_cover_score)
+						continue;
+
+					m = p;
+					break;
+				}
+
+				if (m != nullptr) {
+					m->used = true;
+					for (auto &s : m->src)
+						coverdb[s]++;
+					new_database.push_back(*m);
+					break;
+				}
+			}
+			continue;
+		}
+
 #define X(__wght, __queue)                         \
     k -= __wght;                                   \
     if (k < 0) {                                   \
@@ -266,6 +334,7 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* op
 		X(weight_pq_mb, primary_queue_module_bit)
 		X(weight_pq_mc, primary_queue_module_cell)
 		X(weight_pq_ms, primary_queue_module_src)
+#undef X
 	}
 
 	std::swap(new_database, database);

From 27a5d9c91e44dd04fa45e1e2aeff8c6d1cd50872 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Mar 2019 23:20:41 +0100
Subject: [PATCH 492/528] Add "mutate -cfg", improve pick_cover behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 147 +++++++++++++++++++++++++++++--------------
 1 file changed, 101 insertions(+), 46 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 440e8b056..6b9eb3c04 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -42,8 +42,23 @@ struct mutate_opts_t {
 	int portbit = -1;
 	int ctrlbit = -1;
 	int wirebit = -1;
+
 	IdString ctrl_name;
-	int ctrl_width, ctrl_value;
+	int ctrl_width = -1, ctrl_value = -1;
+
+	int pick_cover_prcnt = 50;
+
+	int weight_cover = 500;
+
+	int weight_pq_w = 100;
+	int weight_pq_b = 100;
+	int weight_pq_c = 100;
+	int weight_pq_s = 100;
+
+	int weight_pq_mw = 100;
+	int weight_pq_mb = 100;
+	int weight_pq_mc = 100;
+	int weight_pq_ms = 100;
 };
 
 void database_add(std::vector<mutate_t> &database, const mutate_opts_t &opts, const mutate_t &entry)
@@ -122,25 +137,19 @@ struct mutate_leaf_queue_t
 {
 	pool<mutate_t*, hash_ptr_ops> db;
 
-	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb) {
+	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb, const mutate_opts_t &opts) {
 		mutate_t *m = nullptr;
-		if (rng(3)) {
+		if (rng(100) < opts.pick_cover_prcnt) {
 			vector<mutate_t*> candidates;
-			int best_score = -1;
 			for (auto p : db) {
 				if (p->used || p->src.empty())
 					continue;
-				int this_score = -1;
+				bool is_covered = false;
 				for (auto &s : p->src) {
-					if (this_score == -1 || this_score > coverdb.at(s))
-						this_score = coverdb.at(s);
+					if (coverdb.at(s))
+						is_covered = true;
 				}
-				log_assert(this_score != -1);
-				if (best_score == -1 || this_score < best_score) {
-					candidates.clear();
-					best_score = this_score;
-				}
-				if (best_score == this_score)
+				if (!is_covered)
 					candidates.push_back(p);
 			}
 			if (!candidates.empty())
@@ -176,11 +185,11 @@ struct mutate_inner_queue_t
 {
 	dict<K, T> db;
 
-	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb) {
+	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb, const mutate_opts_t &opts) {
 		while (!db.empty()) {
 			int i = rng(GetSize(db));
 			auto it = db.element(i);
-			mutate_t *m = it->second.pick(rng, coverdb);
+			mutate_t *m = it->second.pick(rng, coverdb, opts);
 			if (m != nullptr)
 				return m;
 			db.erase(it);
@@ -194,25 +203,13 @@ struct mutate_inner_queue_t
 	}
 };
 
-void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* opts */, int N, xs128_t &rng)
+void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N, xs128_t &rng)
 {
 	std::vector<mutate_t> new_database;
 	dict<string, int> coverdb;
 
-	int weight_cover = 500;
-
-	int weight_pq_w = 100;
-	int weight_pq_b = 100;
-	int weight_pq_c = 100;
-	int weight_pq_s = 100;
-
-	int weight_pq_mw = 100;
-	int weight_pq_mb = 100;
-	int weight_pq_mc = 100;
-	int weight_pq_ms = 100;
-
-	int total_weight = weight_cover + weight_pq_w + weight_pq_b + weight_pq_c + weight_pq_s;
-	total_weight += weight_pq_mw + weight_pq_mb + weight_pq_mc + weight_pq_ms;
+	int total_weight = opts.weight_cover + opts.weight_pq_w + opts.weight_pq_b + opts.weight_pq_c + opts.weight_pq_s;
+	total_weight += opts.weight_pq_mw + opts.weight_pq_mb + opts.weight_pq_mc + opts.weight_pq_ms;
 
 	if (N >= GetSize(database))
 		return;
@@ -254,7 +251,7 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* op
 	{
 		int k = rng(total_weight);
 
-		k -= weight_cover;
+		k -= opts.weight_cover;
 		if (k < 0) {
 			while (!skip_cover) {
 				if (cover_candidates.empty()) {
@@ -316,24 +313,24 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &/* op
 			continue;
 		}
 
-#define X(__wght, __queue)                         \
-    k -= __wght;                                   \
-    if (k < 0) {                                   \
-      mutate_t *m = __queue.pick(rng, coverdb);    \
-      if (m != nullptr)                            \
-        new_database.push_back(*m);                \
-      continue;                                    \
+#define X(__wght, __queue)                               \
+    k -= __wght;                                         \
+    if (k < 0) {                                         \
+      mutate_t *m = __queue.pick(rng, coverdb, opts);    \
+      if (m != nullptr)                                  \
+        new_database.push_back(*m);                      \
+      continue;                                          \
     }
 
-		X(weight_pq_w, primary_queue_wire)
-		X(weight_pq_b, primary_queue_bit)
-		X(weight_pq_c, primary_queue_cell)
-		X(weight_pq_s, primary_queue_src)
+		X(opts.weight_pq_w, primary_queue_wire)
+		X(opts.weight_pq_b, primary_queue_bit)
+		X(opts.weight_pq_c, primary_queue_cell)
+		X(opts.weight_pq_s, primary_queue_src)
 
-		X(weight_pq_mw, primary_queue_module_wire)
-		X(weight_pq_mb, primary_queue_module_bit)
-		X(weight_pq_mc, primary_queue_module_cell)
-		X(weight_pq_ms, primary_queue_module_src)
+		X(opts.weight_pq_mw, primary_queue_module_wire)
+		X(opts.weight_pq_mb, primary_queue_module_bit)
+		X(opts.weight_pq_mc, primary_queue_module_cell)
+		X(opts.weight_pq_ms, primary_queue_module_src)
 #undef X
 	}
 
@@ -654,6 +651,12 @@ struct MutatePass : public Pass {
 		log("        Filter list of mutation candidates to those matching\n");
 		log("        the given parameters.\n");
 		log("\n");
+		log("    -cfg option int\n");
+		log("        Set a configuration option. Options available:\n");
+		log("          weight_pq_w weight_pq_b weight_pq_c weight_pq_s\n");
+		log("          weight_pq_mw weight_pq_mb weight_pq_mc weight_pq_ms\n");
+		log("          weight_cover pick_cover_prcnt\n");
+		log("\n");
 		log("\n");
 		log("    mutate -mode MODE [options]\n");
 		log("\n");
@@ -741,6 +744,58 @@ struct MutatePass : public Pass {
 				opts.src.insert(args[++argidx]);
 				continue;
 			}
+			if (args[argidx] == "-cfg" && argidx+2 < args.size()) {
+				if (args[argidx+1] == "pick_cover_prcnt") {
+					opts.pick_cover_prcnt = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_cover") {
+					opts.weight_cover = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_w") {
+					opts.weight_pq_w = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_b") {
+					opts.weight_pq_b = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_c") {
+					opts.weight_pq_c = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_s") {
+					opts.weight_pq_s = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_mw") {
+					opts.weight_pq_mw = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_mb") {
+					opts.weight_pq_mb = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_mc") {
+					opts.weight_pq_mc = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+				if (args[argidx+1] == "weight_pq_ms") {
+					opts.weight_pq_ms = atoi(args[argidx+2].c_str());
+					argidx += 2;
+					continue;
+				}
+			}
 			break;
 		}
 		extra_args(args, argidx, design);

From d1985f6a223d18e0ae8545a620e4117fd4ca23b3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Mar 2019 00:18:31 +0100
Subject: [PATCH 493/528] Improvements in "mutate" list-reduce algorithm

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 49 ++++++++++++++++++++++++++++++++------------
 1 file changed, 36 insertions(+), 13 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 6b9eb3c04..4c103dcd5 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -133,7 +133,7 @@ struct xs128_t
 	}
 };
 
-struct mutate_leaf_queue_t
+struct mutate_queue_t
 {
 	pool<mutate_t*, hash_ptr_ops> db;
 
@@ -181,7 +181,7 @@ struct mutate_leaf_queue_t
 };
 
 template <typename K, typename T>
-struct mutate_inner_queue_t
+struct mutate_chain_queue_t
 {
 	dict<K, T> db;
 
@@ -203,6 +203,29 @@ struct mutate_inner_queue_t
 	}
 };
 
+template <typename K, typename T>
+struct mutate_once_queue_t
+{
+	dict<K, T> db;
+
+	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb, const mutate_opts_t &opts) {
+		while (!db.empty()) {
+			int i = rng(GetSize(db));
+			auto it = db.element(i);
+			mutate_t *m = it->second.pick(rng, coverdb, opts);
+			db.erase(it);
+			if (m != nullptr)
+				return m;
+		}
+		return nullptr;
+	}
+
+	template<typename... Args>
+	void add(mutate_t *m, K key, Args... args) {
+		db[key].add(m, args...);
+	}
+};
+
 void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N, xs128_t &rng)
 {
 	std::vector<mutate_t> new_database;
@@ -214,26 +237,26 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 	if (N >= GetSize(database))
 		return;
 
-	mutate_inner_queue_t<IdString, mutate_leaf_queue_t> primary_queue_wire;
-	mutate_inner_queue_t<pair<IdString, int>, mutate_leaf_queue_t> primary_queue_bit;
-	mutate_inner_queue_t<IdString, mutate_leaf_queue_t> primary_queue_cell;
-	mutate_inner_queue_t<string, mutate_leaf_queue_t> primary_queue_src;
+	mutate_once_queue_t<tuple<IdString, IdString>, mutate_queue_t> primary_queue_wire;
+	mutate_once_queue_t<tuple<IdString, IdString, int>, mutate_queue_t> primary_queue_bit;
+	mutate_once_queue_t<tuple<IdString, IdString>, mutate_queue_t> primary_queue_cell;
+	mutate_once_queue_t<string, mutate_queue_t> primary_queue_src;
 
-	mutate_inner_queue_t<IdString, mutate_inner_queue_t<IdString, mutate_leaf_queue_t>> primary_queue_module_wire;
-	mutate_inner_queue_t<IdString, mutate_inner_queue_t<pair<IdString, int>, mutate_leaf_queue_t>> primary_queue_module_bit;
-	mutate_inner_queue_t<IdString, mutate_inner_queue_t<IdString, mutate_leaf_queue_t>> primary_queue_module_cell;
-	mutate_inner_queue_t<IdString, mutate_inner_queue_t<string, mutate_leaf_queue_t>> primary_queue_module_src;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<IdString, mutate_queue_t>> primary_queue_module_wire;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<pair<IdString, int>, mutate_queue_t>> primary_queue_module_bit;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<IdString, mutate_queue_t>> primary_queue_module_cell;
+	mutate_chain_queue_t<IdString, mutate_once_queue_t<string, mutate_queue_t>> primary_queue_module_src;
 
 	for (auto &m : database)
 	{
 		if (!m.wire.empty()) {
-			primary_queue_wire.add(&m, m.wire);
-			primary_queue_bit.add(&m, pair<IdString, int>(m.wire, m.wirebit));
+			primary_queue_wire.add(&m, tuple<IdString, IdString>(m.module, m.wire));
+			primary_queue_bit.add(&m, tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit));
 			primary_queue_module_wire.add(&m, m.module, m.wire);
 			primary_queue_module_bit.add(&m, m.module, pair<IdString, int>(m.wire, m.wirebit));
 		}
 
-		primary_queue_cell.add(&m, m.cell);
+		primary_queue_cell.add(&m, tuple<IdString, IdString>(m.module, m.cell));
 		primary_queue_module_cell.add(&m, m.module, m.cell);
 
 		for (auto &s : m.src) {

From 9820ed6531f8bd3e30f44f59ae9c82bdc896f57c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Mar 2019 00:48:23 +0100
Subject: [PATCH 494/528] Disable realmath tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index b8fbcc040..2e4605f8b 100644
--- a/Makefile
+++ b/Makefile
@@ -575,7 +575,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
 	+cd tests/simple && bash run-test.sh $(SEEDOPT)
 	+cd tests/hana && bash run-test.sh $(SEEDOPT)
 	+cd tests/asicworld && bash run-test.sh $(SEEDOPT)
-	+cd tests/realmath && bash run-test.sh $(SEEDOPT)
+	# +cd tests/realmath && bash run-test.sh $(SEEDOPT)
 	+cd tests/share && bash run-test.sh $(SEEDOPT)
 	+cd tests/fsm && bash run-test.sh $(SEEDOPT)
 	+cd tests/techmap && bash run-test.sh

From 370db33a4c347049cb8f66c181d39fd2f2ce5e3a Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Mar 2019 20:18:38 +0100
Subject: [PATCH 495/528] Add fmcombine pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/celltypes.h      |  45 ++++---
 kernel/rtlil.cc         |   4 +-
 passes/sat/Makefile.inc |   1 +
 passes/sat/fmcombine.cc | 292 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 325 insertions(+), 17 deletions(-)
 create mode 100644 passes/sat/fmcombine.cc

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 8b8a56111..ae88f4aaf 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -81,6 +81,27 @@ struct CellTypes
 	}
 
 	void setup_internals()
+	{
+		setup_internals_eval();
+
+		IdString A = "\\A", B = "\\B", EN = "\\EN", Y = "\\Y";
+
+		setup_type("$tribuf", {A, EN}, {Y}, true);
+
+		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
+		setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
+		setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
+		setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
+		setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true);
+		setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true);
+		setup_type("$equiv", {A, B}, {Y}, true);
+	}
+
+	void setup_internals_eval()
 	{
 		std::vector<RTLIL::IdString> unary_ops = {
 			"$not", "$pos", "$neg",
@@ -111,20 +132,6 @@ struct CellTypes
 		setup_type("$lcu", {P, G, CI}, {CO}, true);
 		setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
 		setup_type("$fa", {A, B, C}, {X, Y}, true);
-
-		setup_type("$tribuf", {A, EN}, {Y}, true);
-
-		setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$live", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$fair", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$cover", {A, EN}, pool<RTLIL::IdString>(), true);
-		setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
-		setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
-		setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
-		setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true);
-		setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true);
-		setup_type("$equiv", {A, B}, {Y}, true);
 	}
 
 	void setup_internals_mem()
@@ -153,6 +160,15 @@ struct CellTypes
 	}
 
 	void setup_stdcells()
+	{
+		setup_stdcells_eval();
+
+		IdString A = "\\A", E = "\\E", Y = "\\Y";
+
+		setup_type("$_TBUF_", {A, E}, {Y}, true);
+	}
+
+	void setup_stdcells_eval()
 	{
 		IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D";
 		IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H";
@@ -179,7 +195,6 @@ struct CellTypes
 		setup_type("$_OAI3_", {A, B, C}, {Y}, true);
 		setup_type("$_AOI4_", {A, B, C, D}, {Y}, true);
 		setup_type("$_OAI4_", {A, B, C, D}, {Y}, true);
-		setup_type("$_TBUF_", {A, E}, {Y}, true);
 	}
 
 	void setup_stdcells_mem()
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7f1816190..d0fa88890 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -760,7 +760,7 @@ namespace {
 
 		void check()
 		{
-			if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
+			if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
 					cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
 				return;
 
@@ -2360,7 +2360,7 @@ void RTLIL::Cell::check()
 
 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 {
-	if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
+	if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
 			type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
 		return;
 
diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc
index e91df1eb0..4eced2ff1 100644
--- a/passes/sat/Makefile.inc
+++ b/passes/sat/Makefile.inc
@@ -9,5 +9,6 @@ OBJS += passes/sat/assertpmux.o
 OBJS += passes/sat/clk2fflogic.o
 OBJS += passes/sat/async2sync.o
 OBJS += passes/sat/supercover.o
+OBJS += passes/sat/fmcombine.o
 OBJS += passes/sat/mutate.o
 
diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
new file mode 100644
index 000000000..b8a0e94c8
--- /dev/null
+++ b/passes/sat/fmcombine.cc
@@ -0,0 +1,292 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+#include "kernel/celltypes.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct FmcombineWorker
+{
+	Design *design;
+	Module *original = nullptr;
+	Module *module = nullptr;
+	IdString orig_type, combined_type;
+
+	FmcombineWorker(Design *design, IdString orig_type) :
+			design(design), original(design->module(orig_type)),
+			orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
+	{
+	}
+
+	SigSpec import_sig(SigSpec sig, const string &suffix)
+	{
+		SigSpec newsig;
+		for (auto chunk : sig.chunks()) {
+			if (chunk.wire != nullptr)
+				chunk.wire = module->wire(chunk.wire->name.str() + suffix);
+			newsig.append(chunk);
+		}
+		return newsig;
+	}
+
+	void import_prim_cell(Cell *cell, const string &suffix)
+	{
+		Cell *c = module->addCell(cell->name.str() + suffix, cell->type);
+		c->parameters = cell->parameters;
+		c->attributes = cell->attributes;
+
+		for (auto &conn : cell->connections())
+			c->setPort(conn.first, import_sig(conn.second, suffix));
+	}
+
+	void import_hier_cell(Cell *cell)
+	{
+		if (!cell->parameters.empty())
+			log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", log_id(original), log_id(cell));
+
+		FmcombineWorker sub_worker(design, cell->type);
+		sub_worker.generate();
+
+		Cell *c = module->addCell(cell->name.str() + "_combined", sub_worker.combined_type);
+		// c->parameters = cell->parameters;
+		c->attributes = cell->attributes;
+
+		for (auto &conn : cell->connections()) {
+			c->setPort(conn.first.str() + "_gold", import_sig(conn.second, "_gold"));
+			c->setPort(conn.first.str() + "_gate", import_sig(conn.second, "_gate"));
+		}
+	}
+
+	void generate()
+	{
+		if (design->module(combined_type)) {
+			// log("Combined module %s already exists.\n", log_id(combined_type));
+			return;
+		}
+
+		log("Generating combined module %s from module %s.\n", log_id(combined_type), log_id(orig_type));
+		module = design->addModule(combined_type);
+
+		for (auto wire : original->wires()) {
+			module->addWire(wire->name.str() + "_gold", wire);
+			module->addWire(wire->name.str() + "_gate", wire);
+		}
+		module->fixup_ports();
+
+		for (auto cell : original->cells()) {
+			if (design->module(cell->type) == nullptr) {
+				import_prim_cell(cell, "_gold");
+				import_prim_cell(cell, "_gate");
+			} else {
+				import_hier_cell(cell);
+			}
+		}
+
+		for (auto &conn : original->connections()) {
+			module->connect(import_sig(conn.first, "_gold"), import_sig(conn.second, "_gold"));
+			module->connect(import_sig(conn.first, "_gate"), import_sig(conn.second, "_gate"));
+		}
+
+		CellTypes ct;
+		ct.setup_internals_eval();
+		ct.setup_stdcells_eval();
+
+		SigMap sigmap(module);
+
+		dict<SigBit, SigBit> data_bit_to_eq_net;
+		dict<Cell*, SigSpec> cell_to_eq_nets;
+		dict<SigSpec, SigSpec> reduce_db;
+		dict<SigSpec, SigSpec> invert_db;
+
+		for (auto cell : original->cells())
+		{
+			if (!ct.cell_known(cell->type))
+				continue;
+
+			for (auto &conn : cell->connections())
+			{
+				if (!cell->output(conn.first))
+					continue;
+
+				SigSpec A = import_sig(conn.second, "_gold");
+				SigSpec B = import_sig(conn.second, "_gate");
+				SigBit EQ = module->Eq(NEW_ID, A, B);
+
+				for (auto bit : sigmap({A, B}))
+					data_bit_to_eq_net[bit] = EQ;
+
+				cell_to_eq_nets[cell].append(EQ);
+			}
+		}
+
+		for (auto cell : original->cells())
+		{
+			if (!ct.cell_known(cell->type))
+				continue;
+
+			bool skip_cell = !cell_to_eq_nets.count(cell);
+			pool<SigBit> src_eq_bits;
+
+			for (auto &conn : cell->connections())
+			{
+				if (skip_cell)
+					break;
+
+				if (cell->output(conn.first))
+					continue;
+
+				SigSpec A = import_sig(conn.second, "_gold");
+				SigSpec B = import_sig(conn.second, "_gate");
+
+				for (auto bit : sigmap({A, B})) {
+					if (data_bit_to_eq_net.count(bit))
+						src_eq_bits.insert(data_bit_to_eq_net.at(bit));
+					else
+						skip_cell = true;
+				}
+			}
+
+			if (!skip_cell) {
+				SigSpec antecedent = SigSpec(src_eq_bits);
+				antecedent.sort_and_unify();
+
+				if (GetSize(antecedent) > 1) {
+					if (reduce_db.count(antecedent) == 0)
+						reduce_db[antecedent] = module->ReduceAnd(NEW_ID, antecedent);
+					antecedent = reduce_db.at(antecedent);
+				}
+
+				SigSpec consequent = cell_to_eq_nets.at(cell);
+				consequent.sort_and_unify();
+
+				if (GetSize(consequent) > 1) {
+					if (reduce_db.count(consequent) == 0)
+						reduce_db[consequent] = module->ReduceAnd(NEW_ID, consequent);
+					consequent = reduce_db.at(consequent);
+				}
+
+				module->addAssume(NEW_ID, consequent, antecedent);
+
+				if (invert_db.count(antecedent) == 0)
+					invert_db[antecedent] = module->Not(NEW_ID, antecedent);
+
+				if (invert_db.count(consequent) == 0)
+					invert_db[consequent] = module->Not(NEW_ID, consequent);
+
+				module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
+			}
+		}
+	}
+};
+
+struct FmcombinePass : public Pass {
+	FmcombinePass() : Pass("fmcombine", "combine two instances of a cell into one") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    fmcombine [options] module_name gold_cell gate_cell\n");
+		// log("    fmcombine [options] @gold_cell @gate_cell\n");
+		log("\n");
+		log("This pass takes two cells, which are instances of the same module, and replaces\n");
+		log("them with one instance of a special 'combined' module, that effectively\n");
+		log("contains two copies of the original module, plus some formal properties.\n");
+		log("\n");
+		log("This is useful for formal test benches that check what differences in behavior\n");
+		log("a slight difference in input causes in a module.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		Module *module = nullptr;
+		Cell *gold_cell = nullptr;
+		Cell *gate_cell = nullptr;
+
+		log_header(design, "Executing FMCOMBINE pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-o" && argidx+1 < args.size()) {
+			// 	filename = args[++argidx];
+			// 	continue;
+			// }
+			break;
+		}
+		if (argidx+2 == args.size())
+		{
+			string gold_name = args[argidx++];
+			string gate_name = args[argidx++];
+			log_cmd_error("fmcombine @gold_cell @gate_cell call style is not implemented yet.");
+		}
+		else if (argidx+3 == args.size())
+		{
+			IdString module_name = RTLIL::escape_id(args[argidx++]);
+			IdString gold_name = RTLIL::escape_id(args[argidx++]);
+			IdString gate_name = RTLIL::escape_id(args[argidx++]);
+
+			module = design->module(module_name);
+			if (module == nullptr)
+				log_cmd_error("Module %s not found.\n", log_id(module_name));
+
+			gold_cell = module->cell(gold_name);
+			if (gold_cell == nullptr)
+				log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gold_name), log_id(module));
+
+			gate_cell = module->cell(gate_name);
+			if (gate_cell == nullptr)
+				log_cmd_error("Gold cell %s not found in module %s.\n", log_id(gate_name), log_id(module));
+		}
+		else
+		{
+			log_cmd_error("Invalid number of arguments.\n");
+		}
+		// extra_args(args, argidx, design);
+
+		if (gold_cell->type != gate_cell->type)
+			log_cmd_error("Types of gold and gate cells do not match.\n");
+		if (!gold_cell->parameters.empty())
+			log_cmd_error("Gold cell has unresolved instance parameters.\n");
+		if (!gate_cell->parameters.empty())
+			log_cmd_error("Gold cell has unresolved instance parameters.\n");
+
+		FmcombineWorker worker(design, gold_cell->type);
+		worker.generate();
+		IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", log_id(gold_cell), log_id(gate_cell)));
+
+		Cell *cell = module->addCell(combined_cell_name, worker.combined_type);
+		cell->attributes = gold_cell->attributes;
+		cell->add_strpool_attribute("\\src", gate_cell->get_strpool_attribute("\\src"));
+
+		log("Combining cells %s and %s in module %s into new cell %s.\n", log_id(gold_cell), log_id(gate_cell), log_id(module), log_id(cell));
+
+		for (auto &conn : gold_cell->connections())
+			cell->setPort(conn.first.str() + "_gold", conn.second);
+		module->remove(gold_cell);
+
+		for (auto &conn : gate_cell->connections())
+			cell->setPort(conn.first.str() + "_gate", conn.second);
+		module->remove(gate_cell);
+	}
+} FmcombinePass;
+
+PRIVATE_NAMESPACE_END

From dacaebae35c81b4f4970af3ef8bfdb73691fa215 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 15 Mar 2019 21:45:37 +0100
Subject: [PATCH 496/528] Add "fmcombine -fwd -bwd -nop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/fmcombine.cc | 69 +++++++++++++++++++++++++++++++++++------
 1 file changed, 59 insertions(+), 10 deletions(-)

diff --git a/passes/sat/fmcombine.cc b/passes/sat/fmcombine.cc
index b8a0e94c8..cd75ca860 100644
--- a/passes/sat/fmcombine.cc
+++ b/passes/sat/fmcombine.cc
@@ -24,15 +24,23 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
+struct opts_t
+{
+	bool fwd = false;
+	bool bwd = false;
+	bool nop = false;
+};
+
 struct FmcombineWorker
 {
+	const opts_t &opts;
 	Design *design;
 	Module *original = nullptr;
 	Module *module = nullptr;
 	IdString orig_type, combined_type;
 
-	FmcombineWorker(Design *design, IdString orig_type) :
-			design(design), original(design->module(orig_type)),
+	FmcombineWorker(Design *design, IdString orig_type, const opts_t &opts) :
+			opts(opts), design(design), original(design->module(orig_type)),
 			orig_type(orig_type), combined_type("$fmcombine" + orig_type.str())
 	{
 	}
@@ -63,7 +71,7 @@ struct FmcombineWorker
 		if (!cell->parameters.empty())
 			log_cmd_error("Cell %s.%s has unresolved instance parameters.\n", log_id(original), log_id(cell));
 
-		FmcombineWorker sub_worker(design, cell->type);
+		FmcombineWorker sub_worker(design, cell->type, opts);
 		sub_worker.generate();
 
 		Cell *c = module->addCell(cell->name.str() + "_combined", sub_worker.combined_type);
@@ -106,6 +114,9 @@ struct FmcombineWorker
 			module->connect(import_sig(conn.first, "_gate"), import_sig(conn.second, "_gate"));
 		}
 
+		if (opts.nop)
+			return;
+
 		CellTypes ct;
 		ct.setup_internals_eval();
 		ct.setup_stdcells_eval();
@@ -184,15 +195,19 @@ struct FmcombineWorker
 					consequent = reduce_db.at(consequent);
 				}
 
-				module->addAssume(NEW_ID, consequent, antecedent);
+				if (opts.fwd)
+					module->addAssume(NEW_ID, consequent, antecedent);
 
-				if (invert_db.count(antecedent) == 0)
-					invert_db[antecedent] = module->Not(NEW_ID, antecedent);
+				if (opts.bwd)
+				{
+					if (invert_db.count(antecedent) == 0)
+						invert_db[antecedent] = module->Not(NEW_ID, antecedent);
 
-				if (invert_db.count(consequent) == 0)
-					invert_db[consequent] = module->Not(NEW_ID, consequent);
+					if (invert_db.count(consequent) == 0)
+						invert_db[consequent] = module->Not(NEW_ID, consequent);
 
-				module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
+					module->addAssume(NEW_ID, invert_db.at(antecedent), invert_db.at(consequent));
+				}
 			}
 		}
 	}
@@ -214,9 +229,25 @@ struct FmcombinePass : public Pass {
 		log("This is useful for formal test benches that check what differences in behavior\n");
 		log("a slight difference in input causes in a module.\n");
 		log("\n");
+		log("    -fwd\n");
+		log("        Insert forward hint assumptions into the combined module.\n");
+		log("\n");
+		log("    -bwd\n");
+		log("        Insert backward hint assumptions into the combined module.\n");
+		log("        (Backward hints are logically equivalend to fordward hits, but\n");
+		log("        some solvers are faster with bwd hints, or even both -bwd and -fwd.)\n");
+		log("\n");
+		log("    -nop\n");
+		log("        Don't insert hint assumptions into the combined module.\n");
+		log("        (This should not provide any speedup over the original design, but\n");
+		log("        strangely sometimes it does.)\n");
+		log("\n");
+		log("If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
+		opts_t opts;
 		Module *module = nullptr;
 		Cell *gold_cell = nullptr;
 		Cell *gate_cell = nullptr;
@@ -230,6 +261,18 @@ struct FmcombinePass : public Pass {
 			// 	filename = args[++argidx];
 			// 	continue;
 			// }
+			if (args[argidx] == "-fwd") {
+				opts.fwd = true;
+				continue;
+			}
+			if (args[argidx] == "-bwd") {
+				opts.bwd = true;
+				continue;
+			}
+			if (args[argidx] == "-nop") {
+				opts.nop = true;
+				continue;
+			}
 			break;
 		}
 		if (argidx+2 == args.size())
@@ -262,6 +305,12 @@ struct FmcombinePass : public Pass {
 		}
 		// extra_args(args, argidx, design);
 
+		if (opts.nop && (opts.fwd || opts.bwd))
+			log_cmd_error("Option -nop can not be combined with -fwd and/or -bwd.\n");
+
+		if (!opts.nop && !opts.fwd && !opts.bwd)
+			opts.fwd = true;
+
 		if (gold_cell->type != gate_cell->type)
 			log_cmd_error("Types of gold and gate cells do not match.\n");
 		if (!gold_cell->parameters.empty())
@@ -269,7 +318,7 @@ struct FmcombinePass : public Pass {
 		if (!gate_cell->parameters.empty())
 			log_cmd_error("Gold cell has unresolved instance parameters.\n");
 
-		FmcombineWorker worker(design, gold_cell->type);
+		FmcombineWorker worker(design, gold_cell->type, opts);
 		worker.generate();
 		IdString combined_cell_name = module->uniquify(stringf("\\%s_%s", log_id(gold_cell), log_id(gate_cell)));
 

From aa65d3fe65bd45994f8cb053daef3a5e52b31cd3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 16 Mar 2019 00:55:46 +0100
Subject: [PATCH 497/528] Improve mix of src/wire/wirebit coverage in "mutate
 -list"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 115 ++++++++++++++++++++++++++++++++-----------
 1 file changed, 85 insertions(+), 30 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 4c103dcd5..9621d2855 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -46,7 +46,7 @@ struct mutate_opts_t {
 	IdString ctrl_name;
 	int ctrl_width = -1, ctrl_value = -1;
 
-	int pick_cover_prcnt = 50;
+	int pick_cover_prcnt = 80;
 
 	int weight_cover = 500;
 
@@ -133,25 +133,69 @@ struct xs128_t
 	}
 };
 
+struct coverdb_t
+{
+	dict<string, int> src_db;
+	dict<tuple<IdString, IdString>, int> wire_db;
+	dict<tuple<IdString, IdString, int>, int> wirebit_db;
+
+	void insert(const mutate_t &m) {
+		if (!m.wire.empty()) {
+			wire_db[tuple<IdString, IdString>(m.module, m.wire)] = 0;
+			wirebit_db[tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit)] = 0;
+		}
+		for (auto &s : m.src) {
+			src_db[s] = 0;
+		}
+	}
+
+	void update(const mutate_t &m) {
+		if (!m.wire.empty()) {
+			wire_db.at(tuple<IdString, IdString>(m.module, m.wire))++;
+			wirebit_db.at(tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit))++;
+		}
+		for (auto &s : m.src) {
+			src_db.at(s)++;
+		}
+	}
+
+	int score(const mutate_t &m) {
+		int this_score = m.src.empty() ? 0 : 1;
+		if (!m.wire.empty()) {
+			this_score += wire_db.at(tuple<IdString, IdString>(m.module, m.wire)) ? 0 : 5;
+			this_score += wirebit_db.at(tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit)) ? 0 : 1;
+		}
+		for (auto &s : m.src) {
+			this_score += src_db.at(s) ? 0 : 5;
+		}
+		return this_score;
+	}
+};
+
 struct mutate_queue_t
 {
 	pool<mutate_t*, hash_ptr_ops> db;
 
-	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb, const mutate_opts_t &opts) {
+	mutate_t *pick(xs128_t &rng, coverdb_t &coverdb, const mutate_opts_t &opts) {
 		mutate_t *m = nullptr;
 		if (rng(100) < opts.pick_cover_prcnt) {
-			vector<mutate_t*> candidates;
+			vector<mutate_t*> candidates, rmqueue;
+			int best_score = -1;
 			for (auto p : db) {
-				if (p->used || p->src.empty())
+				if (p->used) {
+					rmqueue.push_back(p);
 					continue;
-				bool is_covered = false;
-				for (auto &s : p->src) {
-					if (coverdb.at(s))
-						is_covered = true;
 				}
-				if (!is_covered)
+				int this_score = coverdb.score(*p);
+				if (this_score > best_score) {
+					best_score = this_score;
+					candidates.clear();
+				}
+				if (best_score == this_score)
 					candidates.push_back(p);
 			}
+			for (auto p : rmqueue)
+				db.erase(p);
 			if (!candidates.empty())
 				m = candidates[rng(GetSize(candidates))];
 		}
@@ -167,11 +211,6 @@ struct mutate_queue_t
 				}
 			}
 		}
-		if (m != nullptr) {
-			m->used = true;
-			for (auto &s : m->src)
-				coverdb[s]++;
-		}
 		return m;
 	}
 
@@ -185,7 +224,7 @@ struct mutate_chain_queue_t
 {
 	dict<K, T> db;
 
-	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb, const mutate_opts_t &opts) {
+	mutate_t *pick(xs128_t &rng, coverdb_t &coverdb, const mutate_opts_t &opts) {
 		while (!db.empty()) {
 			int i = rng(GetSize(db));
 			auto it = db.element(i);
@@ -208,7 +247,7 @@ struct mutate_once_queue_t
 {
 	dict<K, T> db;
 
-	mutate_t *pick(xs128_t &rng, dict<string, int> &coverdb, const mutate_opts_t &opts) {
+	mutate_t *pick(xs128_t &rng, coverdb_t &coverdb, const mutate_opts_t &opts) {
 		while (!db.empty()) {
 			int i = rng(GetSize(db));
 			auto it = db.element(i);
@@ -229,7 +268,7 @@ struct mutate_once_queue_t
 void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts, int N, xs128_t &rng)
 {
 	std::vector<mutate_t> new_database;
-	dict<string, int> coverdb;
+	coverdb_t coverdb;
 
 	int total_weight = opts.weight_cover + opts.weight_pq_w + opts.weight_pq_b + opts.weight_pq_c + opts.weight_pq_s;
 	total_weight += opts.weight_pq_mw + opts.weight_pq_mb + opts.weight_pq_mc + opts.weight_pq_ms;
@@ -249,6 +288,8 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 
 	for (auto &m : database)
 	{
+		coverdb.insert(m);
+
 		if (!m.wire.empty()) {
 			primary_queue_wire.add(&m, tuple<IdString, IdString>(m.module, m.wire));
 			primary_queue_bit.add(&m, tuple<IdString, IdString, int>(m.module, m.wire, m.wirebit));
@@ -260,7 +301,6 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 		primary_queue_module_cell.add(&m, m.module, m.cell);
 
 		for (auto &s : m.src) {
-			coverdb[s] = 0;
 			primary_queue_src.add(&m, s);
 			primary_queue_module_src.add(&m, m.module, s);
 		}
@@ -284,8 +324,8 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 							continue;
 						int this_score = -1;
 						for (auto &s : m.src) {
-							if (this_score == -1 || this_score > coverdb.at(s))
-								this_score = coverdb.at(s);
+							if (this_score == -1 || this_score > coverdb.src_db.at(s))
+								this_score = coverdb.src_db.at(s);
 						}
 						log_assert(this_score != -1);
 						if (best_cover_score == -1 || this_score < best_cover_score) {
@@ -314,8 +354,8 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 
 					int this_score = -1;
 					for (auto &s : p->src) {
-						if (this_score == -1 || this_score > coverdb.at(s))
-							this_score = coverdb.at(s);
+						if (this_score == -1 || this_score > coverdb.src_db.at(s))
+							this_score = coverdb.src_db.at(s);
 					}
 
 					if (this_score != best_cover_score)
@@ -327,8 +367,7 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 
 				if (m != nullptr) {
 					m->used = true;
-					for (auto &s : m->src)
-						coverdb[s]++;
+					coverdb.update(*m);
 					new_database.push_back(*m);
 					break;
 				}
@@ -340,8 +379,11 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
     k -= __wght;                                         \
     if (k < 0) {                                         \
       mutate_t *m = __queue.pick(rng, coverdb, opts);    \
-      if (m != nullptr)                                  \
+      if (m != nullptr) {                                \
+        m->used = true;                                  \
+        coverdb.update(*m);                              \
         new_database.push_back(*m);                      \
+      };                                                 \
       continue;                                          \
     }
 
@@ -359,12 +401,25 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 
 	std::swap(new_database, database);
 
-	int covered_cnt = 0;
-	for (auto &it : coverdb)
-		if (it.second)
-			covered_cnt++;
+	int covered_src_cnt = 0;
+	int covered_wire_cnt = 0;
+	int covered_wirebit_cnt = 0;
 
-	log("Covered %d/%d src attributes (%.2f%%).\n", covered_cnt, GetSize(coverdb), 100.0 * covered_cnt / GetSize(coverdb));
+	for (auto &it : coverdb.src_db)
+		if (it.second)
+			covered_src_cnt++;
+
+	for (auto &it : coverdb.wire_db)
+		if (it.second)
+			covered_wire_cnt++;
+
+	for (auto &it : coverdb.wirebit_db)
+		if (it.second)
+			covered_wirebit_cnt++;
+
+	log("Covered %d/%d src attributes (%.2f%%).\n", covered_src_cnt, GetSize(coverdb.src_db), 100.0 * covered_src_cnt / GetSize(coverdb.src_db));
+	log("Covered %d/%d wires (%.2f%%).\n", covered_wire_cnt, GetSize(coverdb.wire_db), 100.0 * covered_wire_cnt / GetSize(coverdb.wire_db));
+	log("Covered %d/%d wire bits (%.2f%%).\n", covered_wirebit_cnt, GetSize(coverdb.wirebit_db), 100.0 * covered_wirebit_cnt / GetSize(coverdb.wirebit_db));
 }
 
 void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)

From a71c38f163a1972b2da8883b7043b25dd8e2662d Mon Sep 17 00:00:00 2001
From: Felix Vietmeyer <FeViTechLLC@gmail.com>
Date: Sat, 16 Mar 2019 06:20:59 -0600
Subject: [PATCH 498/528] Add note about test requirements in README

---
 README.md | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 9bac468a7..c5cd47707 100644
--- a/README.md
+++ b/README.md
@@ -105,12 +105,15 @@ Makefile.
 To build Yosys simply type 'make' in this directory.
 
 	$ make
-	$ make test
 	$ sudo make install
 
 Note that this also downloads, builds and installs ABC (using yosys-abc
 as executable name).
 
+Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via:
+
+	$ make test
+
 Getting Started
 ===============
 

From 6aae502a3647b50e3f5c0f7d02e8056acf080920 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 17 Mar 2019 12:44:23 +0100
Subject: [PATCH 499/528] Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .github/issue_template.md | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/.github/issue_template.md b/.github/issue_template.md
index 4563a71de..22ad6f839 100644
--- a/.github/issue_template.md
+++ b/.github/issue_template.md
@@ -4,6 +4,14 @@
 all necessary source files. (You can simply drag&drop a .zip file into
 the issue editor.)*
 
+Also, make sure that the issue is actually reproducable in current git
+master of Yosys.
+
+Please do not waste our time with issues that don't contain sufficient
+information to reproduce the issue easily. We will simply close those issues.
+
+Contact https://www.symbioticeda.com/ if you need commercial support for Yosys.
+
 ## Expected behavior
 
 *Please describe the behavior you would have expected from the tool.*

From 90bce0415622a3d7a64bca5914a0fb3abdd3cc5c Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 17 Mar 2019 12:53:47 +0100
Subject: [PATCH 500/528] Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 .github/issue_template.md | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/.github/issue_template.md b/.github/issue_template.md
index 22ad6f839..5a0723c3e 100644
--- a/.github/issue_template.md
+++ b/.github/issue_template.md
@@ -7,8 +7,11 @@ the issue editor.)*
 Also, make sure that the issue is actually reproducable in current git
 master of Yosys.
 
-Please do not waste our time with issues that don't contain sufficient
-information to reproduce the issue easily. We will simply close those issues.
+See https://stackoverflow.com/help/mcve for some information on how to
+create a Minimal, Complete, and Verifiable example (MCVE).
+
+Please do not waste our time with issues that lack sufficient information
+to reproduce the issue easily. We will simply close those issues.
 
 Contact https://www.symbioticeda.com/ if you need commercial support for Yosys.
 
@@ -19,6 +22,3 @@ Contact https://www.symbioticeda.com/ if you need commercial support for Yosys.
 ## Actual behavior
 
 *Please describe how the behavior you see differs from the expected behavior.*
-
-**Important Note:** Nobody will be able to help you and/or fix the issue if you
-do not provide sufficient information for reproducing the problem.

From a5f4b836376e1457847da4946c1e12d2d41dc4f4 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 18 Mar 2019 20:34:21 -0400
Subject: [PATCH 501/528] fix local name resolution in prefix constructs

---
 frontends/ast/simplify.cc |  6 +++-
 tests/simple/generate.v   | 58 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 62 insertions(+), 2 deletions(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 1c9932ee0..d525c6b8a 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2863,7 +2863,11 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
 
 	for (size_t i = 0; i < children.size(); i++) {
 		AstNode *child = children[i];
-		if (child->type != AST_FUNCTION && child->type != AST_TASK && child->type != AST_PREFIX)
+		// AST_PREFIX member names should not be prefixed; a nested AST_PREFIX
+		// still needs to recursed-into
+		if (type == AST_PREFIX && i == 1 && child->type == AST_IDENTIFIER)
+			continue;
+		if (child->type != AST_FUNCTION && child->type != AST_TASK)
 			child->expand_genblock(index_var, prefix, name_map);
 	}
 
diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 24eb4462c..3c55682cb 100644
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -90,5 +90,61 @@ generate
 		endcase
 	end
 endgenerate
-
+endmodule
+
+// ------------------------------------------
+
+module gen_test4(a, b);
+
+input [3:0] a;
+output [3:0] b;
+
+genvar i;
+generate
+	for (i=0; i < 3; i=i+1) begin : foo
+		localparam PREV = i - 1;
+		wire temp;
+		if (i == 0)
+			assign temp = a[0];
+		else
+			assign temp = foo[PREV].temp & a[i];
+		assign b[i] = temp;
+	end
+endgenerate
+endmodule
+
+// ------------------------------------------
+
+module gen_test5(input_bits, out);
+
+parameter WIDTH = 256;
+parameter CHUNK = 4;
+
+input [WIDTH-1:0] input_bits;
+output out;
+
+genvar step, i, j;
+generate
+	for (step = 1; step <= WIDTH; step = step * CHUNK) begin : steps
+		localparam PREV = step / CHUNK;
+		localparam DIM = WIDTH / step;
+		for (i = 0; i < DIM; i = i + 1) begin : outer
+			localparam LAST_START = i * CHUNK;
+			for (j = 0; j < CHUNK; j = j + 1) begin : inner
+				wire temp;
+				if (step == 1)
+					assign temp = input_bits[i];
+				else if (j == 0)
+					assign temp = steps[PREV].outer[LAST_START].val;
+				else
+					assign temp
+						= steps[step].outer[i].inner[j-1].temp
+						& steps[PREV].outer[LAST_START + j].val;
+			end
+			wire val;
+			assign val = steps[step].outer[i].inner[CHUNK - 1].temp;
+		end
+	end
+endgenerate
+assign out = steps[WIDTH].outer[0].val;
 endmodule

From 3e89cf68bdc4e9eeb55bd9450121f421bcdc554a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Tue, 19 Mar 2019 08:52:06 -0700
Subject: [PATCH 502/528] Add author name

---
 frontends/aiger/aigerparse.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/aiger/aigerparse.h b/frontends/aiger/aigerparse.h
index 39a77bd93..c49cd152d 100644
--- a/frontends/aiger/aigerparse.h
+++ b/frontends/aiger/aigerparse.h
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                      Eddie Hung <eddie@fpgeh.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above

From fe1fb1336b44bb073125aa4b42f12baa316e9fea Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 19 Mar 2019 20:29:54 +0100
Subject: [PATCH 503/528] Add Xilinx negedge FFs to synth_xilinx dffinit call,
 fixes #873

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 techlibs/xilinx/synth_xilinx.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index accc7a259..805ae8e6e 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -120,7 +120,8 @@ struct SynthXilinxPass : public Pass
 		log("\n");
 		log("    map_cells:\n");
 		log("        techmap -map +/xilinx/cells_map.v\n");
-		log("        dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT\n");
+		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
+		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
 		log("        clean\n");
 		log("\n");
 		log("    check:\n");
@@ -274,7 +275,8 @@ struct SynthXilinxPass : public Pass
 		if (check_label(active, run_from, run_to, "map_cells"))
 		{
 			Pass::call(design, "techmap -map +/xilinx/cells_map.v");
-			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT");
+			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
 			Pass::call(design, "clean");
 		}
 

From 9b0e7af6d7c84d9b252acbe0fbbf596c75fc1498 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Mar 2019 20:52:29 +0100
Subject: [PATCH 504/528] Improve read_verilog debug output capabilities

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/ast.cc                  | 26 +++++++++++++++---------
 frontends/ast/ast.h                   |  2 +-
 frontends/verilog/verilog_frontend.cc | 29 ++++++++++++++++++++++-----
 3 files changed, 42 insertions(+), 15 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 5a1bae7a7..0442ea0db 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -45,7 +45,7 @@ namespace AST {
 
 // instantiate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
+	bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
 	bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
@@ -562,7 +562,8 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 
 	case AST_CONCAT:
 		fprintf(f, "{");
-		for (auto child : children) {
+		for (int i = GetSize(children)-1; i >= 0; i--) {
+			auto child = children[i];
 			if (!first)
 				fprintf(f, ", ");
 			child->dumpVlog(f, "");
@@ -926,23 +927,28 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 		ast_before_simplify = ast->clone();
 
 	if (flag_dump_ast1) {
-		log("Dumping Verilog AST before simplification:\n");
+		log("Dumping AST before simplification:\n");
 		ast->dumpAst(NULL, "    ");
 		log("--- END OF AST DUMP ---\n");
 	}
+	if (flag_dump_vlog1) {
+		log("Dumping Verilog AST before simplification:\n");
+		ast->dumpVlog(NULL, "    ");
+		log("--- END OF AST DUMP ---\n");
+	}
 
 	if (!defer)
 	{
 		while (ast->simplify(!flag_noopt, false, false, 0, -1, false, false)) { }
 
 		if (flag_dump_ast2) {
-			log("Dumping Verilog AST after simplification:\n");
+			log("Dumping AST after simplification:\n");
 			ast->dumpAst(NULL, "    ");
 			log("--- END OF AST DUMP ---\n");
 		}
 
-		if (flag_dump_vlog) {
-			log("Dumping Verilog AST (as requested by dump_vlog option):\n");
+		if (flag_dump_vlog2) {
+			log("Dumping Verilog AST after simplification:\n");
 			ast->dumpVlog(NULL, "    ");
 			log("--- END OF AST DUMP ---\n");
 		}
@@ -1016,14 +1022,15 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
 		bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
 {
 	current_ast = ast;
 	flag_dump_ast1 = dump_ast1;
 	flag_dump_ast2 = dump_ast2;
 	flag_no_dump_ptr = no_dump_ptr;
-	flag_dump_vlog = dump_vlog;
+	flag_dump_vlog1 = dump_vlog1;
+	flag_dump_vlog2 = dump_vlog2;
 	flag_dump_rtlil = dump_rtlil;
 	flag_nolatches = nolatches;
 	flag_nomeminit = nomeminit;
@@ -1357,7 +1364,8 @@ std::string AstModule::derive_common(RTLIL::Design *design, dict<RTLIL::IdString
 	current_ast = NULL;
 	flag_dump_ast1 = false;
 	flag_dump_ast2 = false;
-	flag_dump_vlog = false;
+	flag_dump_vlog1 = false;
+	flag_dump_vlog2 = false;
 	flag_nolatches = nolatches;
 	flag_nomeminit = nomeminit;
 	flag_nomem2reg = nomem2reg;
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 8b185ff51..ddd59d4be 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -282,7 +282,7 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil, bool nolatches, bool nomeminit,
 			bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index aeea36a2b..504f8b3f3 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -81,6 +81,9 @@ struct VerilogFrontend : public Frontend {
 		log("    -assert-assumes\n");
 		log("        treat all assume() statements like assert() statements\n");
 		log("\n");
+		log("    -debug\n");
+		log("        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug\n");
+		log("\n");
 		log("    -dump_ast1\n");
 		log("        dump abstract syntax tree (before simplification)\n");
 		log("\n");
@@ -90,7 +93,10 @@ struct VerilogFrontend : public Frontend {
 		log("    -no_dump_ptr\n");
 		log("        do not include hex memory addresses in dump (easier to diff dumps)\n");
 		log("\n");
-		log("    -dump_vlog\n");
+		log("    -dump_vlog1\n");
+		log("        dump ast as Verilog code (before simplification)\n");
+		log("\n");
+		log("    -dump_vlog2\n");
 		log("        dump ast as Verilog code (after simplification)\n");
 		log("\n");
 		log("    -dump_rtlil\n");
@@ -197,7 +203,8 @@ struct VerilogFrontend : public Frontend {
 		bool flag_dump_ast1 = false;
 		bool flag_dump_ast2 = false;
 		bool flag_no_dump_ptr = false;
-		bool flag_dump_vlog = false;
+		bool flag_dump_vlog1 = false;
+		bool flag_dump_vlog2 = false;
 		bool flag_dump_rtlil = false;
 		bool flag_nolatches = false;
 		bool flag_nomeminit = false;
@@ -258,6 +265,14 @@ struct VerilogFrontend : public Frontend {
 				assert_assumes_mode = true;
 				continue;
 			}
+			if (arg == "-debug") {
+				flag_dump_ast1 = true;
+				flag_dump_ast2 = true;
+				flag_dump_vlog1 = true;
+				flag_dump_vlog2 = true;
+				frontend_verilog_yydebug = true;
+				continue;
+			}
 			if (arg == "-dump_ast1") {
 				flag_dump_ast1 = true;
 				continue;
@@ -270,8 +285,12 @@ struct VerilogFrontend : public Frontend {
 				flag_no_dump_ptr = true;
 				continue;
 			}
-			if (arg == "-dump_vlog") {
-				flag_dump_vlog = true;
+			if (arg == "-dump_vlog1") {
+				flag_dump_vlog1 = true;
+				continue;
+			}
+			if (arg == "-dump_vlog2") {
+				flag_dump_vlog2 = true;
 				continue;
 			}
 			if (arg == "-dump_rtlil") {
@@ -410,7 +429,7 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;

From da42f10765bafe89892aebdf8eeb672282d7ee34 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Mar 2019 22:20:16 +0100
Subject: [PATCH 505/528] Improve "read_verilog -dump_vlog[12]" handling of
 upto ranges

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/ast.cc | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index 0442ea0db..d48996167 100644
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -431,9 +431,12 @@ void AstNode::dumpVlog(FILE *f, std::string indent) const
 		break;
 
 	case AST_RANGE:
-		if (range_valid)
-			fprintf(f, "[%d:%d]", range_left, range_right);
-		else {
+		if (range_valid) {
+			if (range_swapped)
+				fprintf(f, "[%d:%d]", range_right, range_left);
+			else
+				fprintf(f, "[%d:%d]", range_left, range_right);
+		} else {
 			for (auto child : children) {
 				fprintf(f, "%c", first ? '[' : ':');
 				child->dumpVlog(f, "");

From 638be461c3a6d33aa294700249ee0bc27da69403 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 21 Mar 2019 22:19:17 +0100
Subject: [PATCH 506/528] Fix mem2reg handling of memories with upto data
 ports, fixes #888

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/ast/simplify.cc | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index d525c6b8a..63b71b800 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -138,9 +138,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 				int mem_width, mem_size, addr_bits;
 				node->meminfo(mem_width, mem_size, addr_bits);
 
+				int data_range_left = node->children[0]->range_left;
+				int data_range_right = node->children[0]->range_right;
+
+				if (node->children[0]->range_swapped)
+					std::swap(data_range_left, data_range_right);
+
 				for (int i = 0; i < mem_size; i++) {
 					AstNode *reg = new AstNode(AST_WIRE, new AstNode(AST_RANGE,
-							mkconst_int(mem_width-1, true), mkconst_int(0, true)));
+							mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
 					reg->str = stringf("%s[%d]", node->str.c_str(), i);
 					reg->is_reg = true;
 					reg->is_signed = node->is_signed;
@@ -976,6 +982,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		int data_range_left = id2ast->children[0]->range_left;
 		int data_range_right = id2ast->children[0]->range_right;
 
+		if (id2ast->children[0]->range_swapped)
+			std::swap(data_range_left, data_range_right);
+
 		std::stringstream sstr;
 		sstr << "$mem2bits$" << str << "$" << filename << ":" << linenum << "$" << (autoidx++);
 		std::string wire_id = sstr.str();

From 7cfd83c3415dd3d576539e00b91b6e283997fe52 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 22 Mar 2019 11:42:19 +0100
Subject: [PATCH 507/528] Trim init attributes when resizing FFs in "wreduce",
 fixes #887

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/opt/wreduce.cc | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 1f7222e49..52245ce3e 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -54,6 +54,7 @@ struct WreduceWorker
 	std::set<SigBit> work_queue_bits;
 	pool<SigBit> keep_bits;
 	dict<SigBit, State> init_bits;
+	pool<SigBit> remove_init_bits;
 
 	WreduceWorker(WreduceConfig *config, Module *module) :
 			config(config), module(module), mi(module) { }
@@ -164,6 +165,7 @@ struct WreduceWorker
 		{
 			if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) {
 				module->connect(sig_q[i], State::S0);
+				remove_init_bits.insert(sig_q[i]);
 				sig_d.remove(i);
 				sig_q.remove(i);
 				continue;
@@ -171,6 +173,7 @@ struct WreduceWorker
 
 			if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) {
 				module->connect(sig_q[i], sig_q[i-1]);
+				remove_init_bits.insert(sig_q[i]);
 				sig_d.remove(i);
 				sig_q.remove(i);
 				continue;
@@ -178,6 +181,7 @@ struct WreduceWorker
 
 			auto info = mi.query(sig_q[i]);
 			if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) {
+				remove_init_bits.insert(sig_q[i]);
 				sig_d.remove(i);
 				sig_q.remove(i);
 				zero_ext = false;
@@ -387,13 +391,16 @@ struct WreduceWorker
 
 	void run()
 	{
+		// create a copy as mi.sigmap will be updated as we process the module
+		SigMap init_attr_sigmap = mi.sigmap;
+
 		for (auto w : module->wires()) {
 			if (w->get_bool_attribute("\\keep"))
 				for (auto bit : mi.sigmap(w))
 					keep_bits.insert(bit);
 			if (w->attributes.count("\\init")) {
 				Const initval = w->attributes.at("\\init");
-				SigSpec initsig = mi.sigmap(w);
+				SigSpec initsig = init_attr_sigmap(w);
 				int width = std::min(GetSize(initval), GetSize(initsig));
 				for (int i = 0; i < width; i++)
 					init_bits[initsig[i]] = initval[i];
@@ -446,6 +453,24 @@ struct WreduceWorker
 			module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
 			module->swap_names(w, nw);
 		}
+
+		if (!remove_init_bits.empty()) {
+			for (auto w : module->wires()) {
+				if (w->attributes.count("\\init")) {
+					Const initval = w->attributes.at("\\init");
+					Const new_initval(State::Sx, GetSize(w));
+					SigSpec initsig = init_attr_sigmap(w);
+					int width = std::min(GetSize(initval), GetSize(initsig));
+					for (int i = 0; i < width; i++) {
+						log_dump(initsig[i], remove_init_bits.count(initsig[i]));
+						if (!remove_init_bits.count(initsig[i]))
+							new_initval[i] = initval[i];
+					}
+					w->attributes.at("\\init") = new_initval;
+					log_dump(w->name, initval, new_initval);
+				}
+			}
+		}
 	}
 };
 

From 46f6a60d583d32289d70ed532c27e6cbc5ee47ed Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Fri, 22 Mar 2019 13:57:17 +0000
Subject: [PATCH 508/528] xilinx: Add keep attribute where appropriate

Signed-off-by: David Shah <dave@ds0.me>
---
 techlibs/xilinx/cells_xtra.sh | 13 ++++++-----
 techlibs/xilinx/cells_xtra.v  | 43 +++++++++++++++++++----------------
 2 files changed, 31 insertions(+), 25 deletions(-)

diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 37c3e5480..56520ea10 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -7,6 +7,7 @@ function xtract_cell_decl()
 {
 	for dir in $libdir/xeclib $libdir/retarget; do
 		[ -f $dir/$1.v ] || continue
+		[ -z "$2" ] || echo $2
 		egrep '^\s*((end)?module|parameter|input|inout|output|(end)?function|(end)?task)' $dir/$1.v |
 			sed -re '/UNPLACED/ d; /^\s*function/,/endfunction/ d; /^\s*task/,/endtask/ d;
 			         s,//.*,,; s/#?\(.*/(...);/; s/^(input|output|parameter)/ \1/;
@@ -37,10 +38,10 @@ function xtract_cell_decl()
 	xtract_cell_decl BUFMR
 	xtract_cell_decl BUFMRCE
 	xtract_cell_decl BUFR
-	xtract_cell_decl CAPTUREE2
+	xtract_cell_decl CAPTUREE2 "(* keep *)"
 	# xtract_cell_decl CARRY4
 	xtract_cell_decl CFGLUT5
-	xtract_cell_decl DCIRESET
+	xtract_cell_decl DCIRESET "(* keep *)"
 	xtract_cell_decl DNA_PORT
 	xtract_cell_decl DSP48E1
 	xtract_cell_decl EFUSE_USR
@@ -67,10 +68,10 @@ function xtract_cell_decl()
 	xtract_cell_decl IBUFDS_GTE2
 	xtract_cell_decl IBUFDS_IBUFDISABLE
 	xtract_cell_decl IBUFDS_INTERMDISABLE
-	xtract_cell_decl ICAPE2
+	xtract_cell_decl ICAPE2 "(* keep *)"
 	xtract_cell_decl IDDR
 	xtract_cell_decl IDDR_2CLK
-	xtract_cell_decl IDELAYCTRL
+	xtract_cell_decl IDELAYCTRL "(* keep *)"
 	xtract_cell_decl IDELAYE2
 	xtract_cell_decl IN_FIFO
 	xtract_cell_decl IOBUF
@@ -112,7 +113,7 @@ function xtract_cell_decl()
 	xtract_cell_decl PHY_CONTROL
 	xtract_cell_decl PLLE2_ADV
 	xtract_cell_decl PLLE2_BASE
-	xtract_cell_decl PS7
+	xtract_cell_decl PS7 "(* keep *)"
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
 	xtract_cell_decl RAM128X1D
@@ -136,7 +137,7 @@ function xtract_cell_decl()
 	xtract_cell_decl ROM64X1
 	xtract_cell_decl SRL16E
 	xtract_cell_decl SRLC32E
-	xtract_cell_decl STARTUPE2
+	xtract_cell_decl STARTUPE2 "(* keep *)"
 	xtract_cell_decl USR_ACCESSE2
 	xtract_cell_decl XADC
 } > cells_xtra.new
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index 995d62e18..497518d35 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -114,6 +114,7 @@ module BUFR (...);
     parameter SIM_DEVICE = "7SERIES";
 endmodule
 
+(* keep *)
 module CAPTUREE2 (...);
     parameter ONESHOT = "TRUE";
     input CAP;
@@ -130,6 +131,7 @@ module CFGLUT5 (...);
     input CDI, CE, CLK;
 endmodule
 
+(* keep *)
 module DCIRESET (...);
     output LOCKED;
     input RST;
@@ -2102,6 +2104,7 @@ module IBUFDS_INTERMDISABLE (...);
     input INTERMDISABLE;
 endmodule
 
+(* keep *)
 module ICAPE2 (...);
     parameter [31:0] DEVICE_ID = 32'h04244093;
     parameter ICAP_WIDTH = "X32";
@@ -2149,6 +2152,7 @@ module IDDR_2CLK (...);
     input S;
 endmodule
 
+(* keep *)
 module IDELAYCTRL (...);
     parameter SIM_DEVICE = "7SERIES";
     output RDY;
@@ -3057,6 +3061,7 @@ module PLLE2_BASE (...);
     input RST;
 endmodule
 
+(* keep *)
 module PS7 (...);
     output DMA0DAVALID;
     output DMA0DRREADY;
@@ -3688,6 +3693,17 @@ module PULLUP (...);
     output O;
 endmodule
 
+module RAM128X1D (...);
+    parameter [127:0] INIT = 128'h00000000000000000000000000000000;
+    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+    output DPO, SPO;
+    input [6:0] A;
+    input [6:0] DPRA;
+    input D;
+    input WCLK;
+    input WE;
+endmodule
+
 module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3695,25 +3711,6 @@ module RAM128X1S (...);
     input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
 endmodule
 
-module RAM128X1D (
-  output       DPO, SPO,
-  input        D, WCLK, WE,
-  input  [6:0] A, DPRA
-);
-	parameter [127:0] INIT = 128'bx;
-	parameter IS_WCLK_INVERTED = 0;
-endmodule
-
-module RAM64X1D (
-  output DPO, SPO,
-  input  D, WCLK, WE,
-  input  A0, A1, A2, A3, A4, A5,
-  input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
-);
-	parameter [63:0] INIT = 64'bx;
-	parameter IS_WCLK_INVERTED = 0;
-endmodule
-
 module RAM256X1S (...);
     parameter [255:0] INIT = 256'h0;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3797,6 +3794,13 @@ module RAM64M (...);
     input WE;
 endmodule
 
+module RAM64X1D (...);
+    parameter [63:0] INIT = 64'h0000000000000000;
+    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
+    output DPO, SPO;
+    input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
+endmodule
+
 module RAM64X1S (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3859,6 +3863,7 @@ module SRLC32E (...);
     input CE, CLK, D;
 endmodule
 
+(* keep *)
 module STARTUPE2 (...);
     parameter PROG_USR = "FALSE";
     parameter real SIM_CCLK_FREQ = 0.0;

From 3b796c033cc40a753e24f21b25b2701a30f022f1 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Mar 2019 14:38:48 +0100
Subject: [PATCH 509/528] Add RTLIL::Const::ext[su](), fix
 RTLIL::SigSpec::extend_u0 for 0-size signals

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 kernel/rtlil.cc | 2 +-
 kernel/rtlil.h  | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d0fa88890..b3214579d 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
 		remove(width, width_ - width);
 
 	if (width_ < width) {
-		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
+		RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
 		if (!is_signed)
 			padding = RTLIL::State::S0;
 		while (width_ < width)
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 01323d112..52496e702 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -546,6 +546,14 @@ struct RTLIL::Const
 		return ret;
 	}
 
+	void extu(int width) {
+		bits.resize(width, RTLIL::State::S0);
+	}
+
+	void exts(int width) {
+		bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());
+	}
+
 	inline unsigned int hash() const {
 		unsigned int h = mkhash_init;
 		for (auto b : bits)

From e78f5a3055cae54c44303bab187ad2ef11205ca3 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Mar 2019 14:39:42 +0100
Subject: [PATCH 510/528] Fix BTOR output tags syntax in writye_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/btor/btor.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 53359bd7b..96044e339 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -932,9 +932,8 @@ struct BtorWorker
 
 			btorf_push(stringf("output %s", log_id(wire)));
 
-			int sid = get_bv_sid(GetSize(wire));
 			int nid = get_sig_nid(wire);
-			btorf("%d output %d %d %s\n", next_nid++, sid, nid, log_id(wire));
+			btorf("%d output %d %s\n", next_nid++, nid, log_id(wire));
 
 			btorf_pop(stringf("output %s", log_id(wire)));
 		}

From 1eff8be8f018bd6b94efd14a959d6f1807dd056d Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Mar 2019 14:40:01 +0100
Subject: [PATCH 511/528] Add support for memory initialization to write_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 backends/btor/btor.cc | 53 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 96044e339..55c494996 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -615,6 +615,7 @@ struct BtorWorker
 		{
 			int abits = cell->getParam("\\ABITS").as_int();
 			int width = cell->getParam("\\WIDTH").as_int();
+			int nwords = cell->getParam("\\SIZE").as_int();
 			int rdports = cell->getParam("\\RD_PORTS").as_int();
 			int wrports = cell->getParam("\\WR_PORTS").as_int();
 
@@ -641,6 +642,52 @@ struct BtorWorker
 			int data_sid = get_bv_sid(width);
 			int bool_sid = get_bv_sid(1);
 			int sid = get_mem_sid(abits, width);
+
+			Const initdata = cell->getParam("\\INIT");
+			initdata.exts(nwords*width);
+			int nid_init_val = -1;
+
+			if (!initdata.is_fully_undef())
+			{
+				bool constword = true;
+				Const firstword = initdata.extract(0, width);
+
+				for (int i = 1; i < nwords; i++) {
+					Const thisword = initdata.extract(i*width, width);
+					if (thisword != firstword) {
+						constword = false;
+						break;
+					}
+				}
+
+				if (constword)
+				{
+					if (verbose)
+						btorf("; initval = %s\n", log_signal(firstword));
+					nid_init_val = get_sig_nid(firstword);
+				}
+				else
+				{
+					int nid_init_val = next_nid++;
+					btorf("%d state %d\n", nid_init_val, sid);
+
+					for (int i = 0; i < nwords; i++) {
+						Const thisword = initdata.extract(i*width, width);
+						if (thisword.is_fully_undef())
+							continue;
+						Const thisaddr(i, abits);
+						int nid_thisword = get_sig_nid(thisword);
+						int nid_thisaddr = get_sig_nid(thisaddr);
+						int last_nid_init_val = nid_init_val;
+						nid_init_val = next_nid++;
+						if (verbose)
+							btorf("; initval[%d] = %s\n", i, log_signal(thisword));
+						btorf("%d write %d %d %d %d\n", nid_init_val, sid, last_nid_init_val, nid_thisaddr, nid_thisword);
+					}
+				}
+			}
+
+
 			int nid = next_nid++;
 			int nid_head = nid;
 
@@ -649,6 +696,12 @@ struct BtorWorker
 			else
 				btorf("%d state %d %s\n", nid, sid, log_id(cell));
 
+			if (nid_init_val >= 0)
+			{
+				int nid_init = next_nid++;
+				btorf("%d init %d %d %d\n", nid_init, sid, nid, nid_init_val);
+			}
+
 			if (asyncwr)
 			{
 				for (int port = 0; port < wrports; port++)

From 59c44bb61ab1a69a7ba4cd8d2b6d8d3e3408d9ca Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Mar 2019 17:53:09 +0100
Subject: [PATCH 512/528] Add "mutate -s <filename>"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 9621d2855..7025a7aca 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -422,8 +422,9 @@ void database_reduce(std::vector<mutate_t> &database, const mutate_opts_t &opts,
 	log("Covered %d/%d wire bits (%.2f%%).\n", covered_wirebit_cnt, GetSize(coverdb.wirebit_db), 100.0 * covered_wirebit_cnt / GetSize(coverdb.wirebit_db));
 }
 
-void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, int N)
+void mutate_list(Design *design, const mutate_opts_t &opts, const string &filename, const string &srcsfile, int N)
 {
+	pool<string> sources;
 	std::vector<mutate_t> database;
 	xs128_t rng(opts.seed);
 
@@ -497,6 +498,9 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 						entry.wirebit = bit.offset;
 					}
 
+					if (!srcsfile.empty())
+						sources.insert(entry.src.begin(), entry.src.end());
+
 					entry.mode = "inv";
 					database_add(database, opts, entry);
 
@@ -526,6 +530,16 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 		log("Reduced database size: %d\n", GetSize(database));
 	}
 
+	if (!srcsfile.empty()) {
+		std::ofstream sout;
+		sout.open(srcsfile, std::ios::out | std::ios::trunc);
+		if (!sout.is_open())
+			log_error("Could not open file \"%s\" with write access.\n", srcsfile.c_str());
+		sources.sort();
+		for (auto &s : sources)
+			sout << s << std::endl;
+	}
+
 	std::ofstream fout;
 
 	if (!filename.empty()) {
@@ -710,6 +724,9 @@ struct MutatePass : public Pass {
 		log("    -o filename\n");
 		log("        Write list to this file instead of console output\n");
 		log("\n");
+		log("    -s filename\n");
+		log("        Write a list of all src tags found in the design to the specified file\n");
+		log("\n");
 		log("    -seed N\n");
 		log("        RNG seed for selecting mutations\n");
 		log("\n");
@@ -761,6 +778,7 @@ struct MutatePass : public Pass {
 	{
 		mutate_opts_t opts;
 		string filename;
+		string srcsfile;
 		int N = -1;
 
 		log_header(design, "Executing MUTATE pass.\n");
@@ -776,6 +794,10 @@ struct MutatePass : public Pass {
 				filename = args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-s" && argidx+1 < args.size()) {
+				srcsfile = args[++argidx];
+				continue;
+			}
 			if (args[argidx] == "-seed" && argidx+1 < args.size()) {
 				opts.seed = atoi(args[++argidx].c_str());
 				continue;
@@ -879,7 +901,7 @@ struct MutatePass : public Pass {
 		extra_args(args, argidx, design);
 
 		if (N >= 0) {
-			mutate_list(design, opts, filename, N);
+			mutate_list(design, opts, filename, srcsfile, N);
 			return;
 		}
 

From ccfa2fe01cffcc4d23bc989e558bd33addfea58e Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 23 Mar 2019 20:20:32 +0100
Subject: [PATCH 513/528] Add "mutate -none -mode", "mutate -mode none"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/mutate.cc | 31 ++++++++++++++++++++++++++++++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc
index 7025a7aca..c50678c51 100644
--- a/passes/sat/mutate.cc
+++ b/passes/sat/mutate.cc
@@ -46,6 +46,8 @@ struct mutate_opts_t {
 	IdString ctrl_name;
 	int ctrl_width = -1, ctrl_value = -1;
 
+	bool none = false;
+
 	int pick_cover_prcnt = 80;
 
 	int weight_cover = 500;
@@ -526,7 +528,7 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 
 	log("Raw database size: %d\n", GetSize(database));
 	if (N != 0) {
-		database_reduce(database, opts, N, rng);
+		database_reduce(database, opts, opts.none ? N-1 : N, rng);
 		log("Reduced database size: %d\n", GetSize(database));
 	}
 
@@ -550,6 +552,17 @@ void mutate_list(Design *design, const mutate_opts_t &opts, const string &filena
 
 	int ctrl_value = opts.ctrl_value;
 
+	if (opts.none) {
+		string str = "mutate";
+		if (!opts.ctrl_name.empty())
+			str += stringf(" -ctrl %s %d %d", log_id(opts.ctrl_name), opts.ctrl_width, ctrl_value++);
+		str += " -mode none";
+		if (filename.empty())
+			log("%s\n", str.c_str());
+		else
+			fout << str << std::endl;
+	}
+
 	for (auto &entry : database) {
 		string str = "mutate";
 		if (!opts.ctrl_name.empty())
@@ -730,6 +743,9 @@ struct MutatePass : public Pass {
 		log("    -seed N\n");
 		log("        RNG seed for selecting mutations\n");
 		log("\n");
+		log("    -none\n");
+		log("        Include a \"none\" mutation in the output\n");
+		log("\n");
 		log("    -ctrl name width value\n");
 		log("        Add -ctrl options to the output. Use 'value' for first mutation, then\n");
 		log("        simply count up from there.\n");
@@ -802,6 +818,10 @@ struct MutatePass : public Pass {
 				opts.seed = atoi(args[++argidx].c_str());
 				continue;
 			}
+			if (args[argidx] == "-none") {
+				opts.none = true;
+				continue;
+			}
 			if (args[argidx] == "-mode" && argidx+1 < args.size()) {
 				opts.mode = args[++argidx];
 				continue;
@@ -905,6 +925,15 @@ struct MutatePass : public Pass {
 			return;
 		}
 
+		if (opts.mode == "none") {
+			if (!opts.ctrl_name.empty()) {
+				Module *topmod = opts.module.empty() ? design->top_module() : design->module(opts.module);
+				if (topmod)
+					mutate_ctrl_sig(topmod, opts.ctrl_name, opts.ctrl_width);
+			}
+			return;
+		}
+
 		if (opts.mode == "inv") {
 			mutate_inv(design, opts);
 			return;

From ac6cc88db352938d8dd9f2f9c6d404663674538e Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Sun, 24 Mar 2019 16:21:36 +0000
Subject: [PATCH 514/528] memory_bram: Fix multiclock make_transp

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/memory/memory_bram.cc | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index cf4095d06..c38eabaee 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -542,7 +542,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 	}
 
 	// assign write ports
-
+	pair<SigBit, bool> wr_clkdom;
 	for (int cell_port_i = 0, bram_port_i = 0; cell_port_i < wr_ports; cell_port_i++)
 	{
 		bool clken = wr_clken[cell_port_i] == State::S1;
@@ -552,7 +552,7 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
 		pair<SigBit, bool> clkdom(clksig, clkpol);
 		if (!clken)
 			clkdom = pair<SigBit, bool>(State::S1, false);
-
+		wr_clkdom = clkdom;
 		log("      Write port #%d is in clock domain %s%s.\n",
 				cell_port_i, clkdom.second ? "" : "!",
 				clken ? log_signal(clkdom.first) : "~async~");
@@ -718,7 +718,13 @@ grow_read_ports:;
 				if (read_transp.count(pi.transp) && read_transp.at(pi.transp) != transp) {
 					if (match.make_transp && wr_ports <= 1) {
 						pi.make_transp = true;
-						enable_make_transp = true;
+						if (pi.clocks != 0) {
+							if (wr_ports == 1 && wr_clkdom != clkdom) {								
+								log("        Bram port %c%d.%d cannot have soft transparency logic added as read and write clock domains differ.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
+								goto skip_bram_rport;
+							}
+							enable_make_transp = true;
+						}
 					} else {
 						log("        Bram port %c%d.%d has incompatible read transparency.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
 						goto skip_bram_rport;
@@ -913,17 +919,18 @@ grow_read_ports:;
 				} else {
 					SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits);
 					c->setPort(stringf("\\%sDATA", pf), bram_dout);
-
-					if (pi.make_outreg) {
+					if (pi.make_outreg && pi.make_transp) {
+						log("        Moving output register to address for transparent port %c%d.%d.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
+						SigSpec sig_addr_q = module->addWire(NEW_ID, bram.abits);
+						module->addDff(NEW_ID, pi.sig_clock, sig_addr, sig_addr_q, pi.effective_clkpol);
+						c->setPort(stringf("\\%sADDR", pf), sig_addr_q);
+					} else if (pi.make_outreg) {
 						SigSpec bram_dout_q = module->addWire(NEW_ID, bram.dbits);
 						if (!pi.sig_en.empty())
 							bram_dout = module->Mux(NEW_ID, bram_dout_q, bram_dout, pi.sig_en);
 						module->addDff(NEW_ID, pi.sig_clock, bram_dout, bram_dout_q, pi.effective_clkpol);
 						bram_dout = bram_dout_q;
-					}
-
-					if (pi.make_transp)
-					{
+					} else if (pi.make_transp) {
 						log("        Adding extra logic for transparent port %c%d.%d.\n", pi.group + 'A', pi.index + 1, pi.dupidx + 1);
 
 						SigSpec transp_en_d = module->Mux(NEW_ID, SigSpec(0, make_transp_enbits),

From 3b3b77291a21ed23a2763c79335501beebb10746 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Sun, 24 Mar 2019 22:54:18 +0100
Subject: [PATCH 515/528] Updated the liberty parser to accept [A:B] ranges
 (AST has not been updated). Liberty parser now also accepts key : value pair
 lines that do not end in ';'.

---
 passes/techmap/libparse.cc       |  87 +++++++-
 passes/techmap/libparse.h        |  10 +-
 tests/liberty/.gitignore         |   2 +
 tests/liberty/busdef.lib         |  81 +++++++
 tests/liberty/normal.lib         | 360 +++++++++++++++++++++++++++++++
 tests/liberty/run-test.sh        |  10 +
 tests/liberty/semicolmissing.lib |  72 +++++++
 tests/liberty/small.v            |  16 ++
 8 files changed, 631 insertions(+), 7 deletions(-)
 create mode 100644 tests/liberty/.gitignore
 create mode 100644 tests/liberty/busdef.lib
 create mode 100644 tests/liberty/normal.lib
 create mode 100755 tests/liberty/run-test.sh
 create mode 100644 tests/liberty/semicolmissing.lib
 create mode 100644 tests/liberty/small.v

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 3927a657b..878ca3160 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -24,6 +24,7 @@
 #include <istream>
 #include <fstream>
 #include <iostream>
+#include <sstream>
 
 #ifndef FILTERLIB
 #include "kernel/log.h"
@@ -86,15 +87,17 @@ int LibertyParser::lexer(std::string &str)
 {
 	int c;
 
+    // eat whitespace
 	do {
 		c = f.get();
 	} while (c == ' ' || c == '\t' || c == '\r');
 
-	if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']') {
+    // search for identifiers, numbers, plus or minus.
+	if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') {
 		str = c;
 		while (1) {
 			c = f.get();
-			if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.' || c == '[' || c == ']')
+			if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.')
 				str += c;
 			else
 				break;
@@ -111,6 +114,8 @@ int LibertyParser::lexer(std::string &str)
 		}
 	}
 
+    // if it wasn't an identifer, number of array range,
+    // maybe it's a string?
 	if (c == '"') {
 		str = "";
 		while (1) {
@@ -125,9 +130,10 @@ int LibertyParser::lexer(std::string &str)
 		return 'v';
 	}
 
+    // if it wasn't a string, perhaps it's a comment or a forward slash?
 	if (c == '/') {
 		c = f.get();
-		if (c == '*') {
+		if (c == '*') {         // start of '/*' block comment
 			int last_c = 0;
 			while (c > 0 && (last_c != '*' || c != '/')) {
 				last_c = c;
@@ -136,7 +142,7 @@ int LibertyParser::lexer(std::string &str)
 					line++;
 			}
 			return lexer(str);
-		} else if (c == '/') {
+		} else if (c == '/') {  // start of '//' line comment
 			while (c > 0 && c != '\n')
 				c = f.get();
 			line++;
@@ -144,9 +150,10 @@ int LibertyParser::lexer(std::string &str)
 		}
 		f.unget();
 		// fprintf(stderr, "LEX: char >>/<<\n");
-		return '/';
+		return '/';             // a single '/' charater.
 	}
 
+    // check for a backslash
 	if (c == '\\') {
 		c = f.get();
 		if (c == '\r')
@@ -157,11 +164,15 @@ int LibertyParser::lexer(std::string &str)
 		return '\\';
 	}
 
+    // check for a new line
 	if (c == '\n') {
 		line++;
 		return 'n';
 	}
 
+    // anything else, such as ';' will get passed
+    // through as literal items.
+
 	// if (c >= 32 && c < 255)
 	// 	fprintf(stderr, "LEX: char >>%c<<\n", c);
 	// else
@@ -210,7 +221,12 @@ LibertyAst *LibertyParser::parse()
 				ast->value += str;
 				tok = lexer(str);
 			}
-			if (tok == ';')
+            
+            // In a liberty file, all key : value pairs should end in ';'
+            // However, there are some liberty files in the wild that
+            // just have a newline. We'll be kind and accept a newline
+            // instead of the ';' too..
+			if ((tok == ';') || (tok == 'n'))
 				break;
 			else
 				error();
@@ -225,6 +241,48 @@ LibertyAst *LibertyParser::parse()
 					continue;
 				if (tok == ')')
 					break;
+                
+                // FIXME: the AST needs to be extended to store
+                //        these vector ranges.
+                if (tok == '[')
+                {
+                    // parse vector range [A] or [A:B]
+                    std::string arg;
+                    tok = lexer(arg);
+                    if (tok != 'v')
+                    {
+                        // expected a vector array index
+                        error("Expected a number.");
+                    }
+                    else
+                    {
+                        // fixme: check for number A
+                    }
+                    tok = lexer(arg);
+                    // optionally check for : in case of [A:B]
+                    // if it isn't we just expect ']'
+                    // as we have [A]
+                    if (tok == ':')
+                    {
+                        tok = lexer(arg);
+                        if (tok != 'v')
+                        {
+                            // expected a vector array index
+                            error("Expected a number.");
+                        }
+                        else
+                        {
+                            // fixme: check for number B
+                            tok = lexer(arg);                            
+                        }
+                    }
+                    // expect a closing bracket of array range
+                    if (tok != ']')
+                    {
+                        error("Expected ']' on array range.");
+                    }
+                    continue;           
+                }
 				if (tok != 'v')
 					error();
 				ast->args.push_back(arg);
@@ -255,6 +313,14 @@ void LibertyParser::error()
 	log_error("Syntax error in liberty file on line %d.\n", line);
 }
 
+void LibertyParser::error(const std::string &str)
+{
+    std::stringstream ss;
+    ss << "Syntax error in liberty file on line " << line << ".\n";
+    ss << "  " << str << "\n";
+    log_error("%s", ss.str().c_str());
+}
+
 #else
 
 void LibertyParser::error()
@@ -263,6 +329,15 @@ void LibertyParser::error()
 	exit(1);
 }
 
+void LibertyParser::error(const std::string &str)
+{
+    std::stringstream ss;
+    ss << "Syntax error in liberty file on line " << line << ".\n";
+    ss << "  " << str << "\n";
+    printf("%s", ss.str().c_str());
+    exit(1);
+}
+
 /**** BEGIN: http://svn.clifford.at/tools/trunk/examples/check.h ****/
 
 #define CHECK_NV(result, check)                                      \
diff --git a/passes/techmap/libparse.h b/passes/techmap/libparse.h
index cf6325570..c9ebd06c5 100644
--- a/passes/techmap/libparse.h
+++ b/passes/techmap/libparse.h
@@ -46,9 +46,17 @@ namespace Yosys
 		LibertyAst *ast;
 		LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
 		~LibertyParser() { if (ast) delete ast; }
+        
+        /* lexer return values:
+           'v': identifier, string, array range [...] -> str holds the token string
+           'n': newline
+           anything else is a single character.
+        */
 		int lexer(std::string &str);
-		LibertyAst *parse();
+		
+        LibertyAst *parse();
 		void error();
+        void error(const std::string &str);
 	};
 }
 
diff --git a/tests/liberty/.gitignore b/tests/liberty/.gitignore
new file mode 100644
index 000000000..e6ec49c4a
--- /dev/null
+++ b/tests/liberty/.gitignore
@@ -0,0 +1,2 @@
+*.log
+test.ys
diff --git a/tests/liberty/busdef.lib b/tests/liberty/busdef.lib
new file mode 100644
index 000000000..b5e3d50b9
--- /dev/null
+++ b/tests/liberty/busdef.lib
@@ -0,0 +1,81 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 02-11-2018                      */
+/* Version: 1.0                             */
+/*                                          */
+/********************************************/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+    type( IO_bus_3_to_0 ) {
+        base_type : array ;
+        data_type : bit ;
+        bit_width : 4;
+        bit_from : 3 ;
+        bit_to : 0 ;
+        downto : true ;
+    }
+
+    cell (SRAM) {
+        area : 1 ;
+        memory() {
+            type : ram;
+            address_width : 4;
+            word_width : 4;
+        }
+        pin(CE1) {
+            direction : input;
+            capacitance : 0.021;
+            max_transition : 1.024;
+            switch_pin : true;
+        }
+        bus(I1)  {
+            bus_type : IO_bus_3_to_0 ;
+            direction : input;
+            pin (I1[3:0]) {
+                timing() {
+                    related_pin :   "CE1" ;
+                    timing_type : setup_rising ;
+                    rise_constraint (scalar) {
+                        values("0.0507786");
+                    }
+                    fall_constraint (scalar) {
+                        values("0.0507786");
+                    }
+                }
+            }
+        }
+    }
+
+} /* end */
diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib
new file mode 100644
index 000000000..1474e2b59
--- /dev/null
+++ b/tests/liberty/normal.lib
@@ -0,0 +1,360 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 02-11-2018                      */
+/* Version: 1.0                             */
+/*                                          */
+/********************************************/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+  /* Inverter */
+  cell (inv) {
+    area : 1;
+    pin(A) {
+      direction : input;
+    }
+    
+    pin(Y) {
+      direction : output;
+      function : "A'";
+    }
+  }
+  
+  /* tri-state inverter */
+  cell (tri_inv) {
+    area : 4;
+    pin(A) {
+      direction : input;    
+    }
+    pin(S) {
+      direction : input;
+    }
+    pin(Z) {
+      direction : output;
+      function  : "A'";
+      three_State : "S'";
+    }
+  }
+  
+  cell (buffer) {
+    area : 5;
+    pin(A) {
+      direction : input;
+    }
+    pin(Y) {
+      direction : output;
+      function : "A";
+    }
+  }  
+  
+  /* 2-input NAND gate */
+  cell (nand2) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(Y) {
+      direction: output;
+      function : "(A * B)'";
+    }
+  }
+  
+  /* 2-input NOR gate */
+  cell (nor2) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(Y) {
+      direction: output;
+      function : "(A + B)'";
+    }
+  }
+  
+  /* 2-input XOR */
+  cell (xor2) {
+    area : 6;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(Y) {
+      direction: output;
+      function : "(A *B') + (A' * B)";
+    }
+  }
+  
+  /* 2-input inverting MUX */
+  cell (imux2) {
+    area : 5;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(S) {
+      direction : input;
+    } 
+    pin(Y) {
+      direction: output;
+      function : "( (A * S) + (B * S') )'";
+    }
+  }
+  
+  /* D-type flip-flop with asynchronous reset and preset */
+  cell (dff) 
+  {
+    area : 6;
+    ff("IQ", "IQN") {
+      next_state : "D";
+      clocked_on : "CLK";
+      clear      : "RESET";
+      preset     : "PRESET";
+      clear_preset_var1 : L;
+      clear_preset_var2 : L;
+    } 
+    pin(D) {
+      direction : input;
+    }
+    pin(CLK) {
+      direction : input;
+    }
+    pin(RESET) {
+      direction : input;
+    }
+    pin(PRESET) {
+      direction : input;
+    }
+    pin(Q) {
+      direction: output;
+      function : "IQ";
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0; 
+        related_pin : "CLK";
+      }
+      timing () {
+        timing_type : clear;
+        timing_sense : positive_unate;
+        intrinsic_fall : 75;
+        related_pin : "RESET";
+      }
+      timing () {
+        timing_type : preset;
+        timing_sense : negative_unate;
+        intrinsic_rise : 75;
+        related_pin : "PRESET";
+      }      
+    }
+    pin(QN) {
+      direction: output;
+      function : "IQN";
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0; 
+        related_pin : "CLK";
+      }
+      timing () {
+        timing_type : preset;
+        timing_sense : negative_unate;
+        intrinsic_rise : 75;
+        related_pin : "RESET";
+      }
+      timing () {
+        timing_type : clear;
+        timing_sense : positive_unate;
+        intrinsic_fall : 75;
+        related_pin : "PRESET";
+      }      
+    } 
+  }
+
+  /* Latch */
+  cell(latch) {
+    area : 5;
+    latch ("IQ","IQN") {
+      enable : "G";
+      data_in : "D";
+    }
+
+    pin(D) {
+      direction : input;
+    }
+    pin(G) {
+      direction : input;
+    }
+ 
+    pin(Q) {
+      direction : output;
+      function : "IQ";
+      internal_node : "Q";
+      
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "G";
+      }
+      
+      timing() {
+        timing_sense : positive_unate;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "D";
+      }
+    }
+    
+    pin(QN) {
+      direction : output;
+      function : "IQN";
+      internal_node : "QN";
+      
+      timing() {
+        timing_type : rising_edge;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "G";
+      }
+      
+      timing() {
+        timing_sense : negative_unate;
+        intrinsic_rise : 65;
+        intrinsic_fall : 65;
+        rise_resistance : 0;
+        fall_resistance : 0;
+        related_pin : "D";
+      }
+    }
+  }
+
+  /* 3 input AND-OR-INVERT gate */
+  cell (aoi211) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(C) {
+      direction : input;
+    }    
+    pin(Y) {
+      direction: output;
+      function : "((A * B) + C)'";
+    }
+  }
+
+
+  /* 3 input OR-AND-INVERT gate */
+  cell (oai211) {
+    area : 3;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(C) {
+      direction : input;
+    }    
+    pin(Y) {
+      direction: output;
+      function : "((A + B) * C)'";
+    }
+  }
+
+  /* half adder */
+  cell (halfadder) {
+    area : 5;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(C) {
+      direction : output;
+      function  : "(A * B)";
+    }    
+    pin(Y) {
+      direction: output;
+      function : "(A *B') + (A' * B)";
+    }    
+  }
+
+  /* full adder */
+  cell (fulladder) {
+    area : 8;
+    pin(A) {
+      direction : input;
+    }
+    pin(B) {
+      direction : input;
+    }
+    pin(CI) {
+      direction : input;
+    }    
+    pin(CO) {
+      direction : output;
+      function : "(((A * B)+(B * CI))+(CI * A))";
+    }
+    pin(Y) {
+      direction: output;
+      function : "((A^B)^CI)";
+    }    
+  }
+
+} /* end */
diff --git a/tests/liberty/run-test.sh b/tests/liberty/run-test.sh
new file mode 100755
index 000000000..7e2ed2370
--- /dev/null
+++ b/tests/liberty/run-test.sh
@@ -0,0 +1,10 @@
+#!/bin/bash
+set -e
+
+for x in *.lib; do
+	echo "Running $x.."
+    echo "read_verilog small.v" > test.ys
+    echo "synth -top small" >> test.ys
+    echo "dfflibmap -liberty ${x}" >> test.ys
+	../../yosys -ql ${x%.lib}.log -s test.ys
+done
diff --git a/tests/liberty/semicolmissing.lib b/tests/liberty/semicolmissing.lib
new file mode 100644
index 000000000..f7c20750a
--- /dev/null
+++ b/tests/liberty/semicolmissing.lib
@@ -0,0 +1,72 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 24-03-2019                      */
+/* Version: 1.0                             */
+/* Version: 1.1 - Removed semicolons in     */
+/*                full adder                */
+/*                                          */
+/********************************************/
+
+/* 
+    semi colon is missing in full-adder specification
+    some TSMC liberty files are formatted this way..
+*/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+  
+  time_unit                     : "1ps";
+  pulling_resistance_unit       : "1kohm";  
+  voltage_unit                  : "1V";
+  current_unit                  : "1uA";  
+  
+  capacitive_load_unit(1,ff);
+  
+  default_inout_pin_cap         :  7.0;
+  default_input_pin_cap         :  7.0;
+  default_output_pin_cap        :  0.0;
+  default_fanout_load           :  1.0;
+
+  default_wire_load_capacitance : 0.1;
+  default_wire_load_resistance  : 1.0e-3;
+  default_wire_load_area        : 0.0;
+
+  nom_process                   :  1.0;
+  nom_temperature               : 25.0;
+  nom_voltage                   :  1.2;
+  
+  delay_model                   : generic_cmos;
+  
+  /* full adder */
+  cell (fulladder) {
+    area : 8
+    pin(A) {
+      direction : input
+    }
+    pin(B) {
+      direction : input
+    }
+    pin(CI) {
+      direction : input
+    }    
+    pin(CO) {
+      direction : output
+      function : "(((A * B)+(B * CI))+(CI * A))"
+    }
+    pin(Y) {
+      direction: output
+      function : "((A^B)^CI)"
+    }    
+  }
+
+} /* end */
+
+
diff --git a/tests/liberty/small.v b/tests/liberty/small.v
new file mode 100644
index 000000000..bd94be4fc
--- /dev/null
+++ b/tests/liberty/small.v
@@ -0,0 +1,16 @@
+/** small, meaningless design to test loading of liberty files */
+
+module small
+(
+    input clk,
+    output reg[7:0] count
+);
+
+initial count = 0;
+
+always @ (posedge clk) 
+begin
+    count <= count + 1'b1;
+end
+
+endmodule

From 9d9cc8a3140cdbc2d976a5b06b5a057845da739a Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Mon, 25 Mar 2019 12:15:10 +0100
Subject: [PATCH 516/528] EOL is now accepted as ';' replacement on lines that
 look like: feature_xyz(option)

---
 passes/techmap/libparse.cc | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 878ca3160..9dc3e96ab 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -202,12 +202,11 @@ LibertyAst *LibertyParser::parse()
 	{
 		tok = lexer(str);
 
-		if (tok == ';')
+        // allow both ';' and new lines to 
+        // terminate a statement.
+		if ((tok == ';') || (tok == 'n'))
 			break;
 
-		if (tok == 'n')
-			continue;
-
 		if (tok == ':' && ast->value.empty()) {
 			tok = lexer(ast->value);
 			if (tok != 'v')

From 1f7f54e68eb201976ddd42cb906492bf9e611030 Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Mon, 25 Mar 2019 14:12:04 +0100
Subject: [PATCH 517/528] spaces -> tabs

---
 passes/techmap/libparse.cc | 156 ++++++++++++++++++-------------------
 1 file changed, 78 insertions(+), 78 deletions(-)

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 9dc3e96ab..8eadd8735 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -87,12 +87,12 @@ int LibertyParser::lexer(std::string &str)
 {
 	int c;
 
-    // eat whitespace
+	// eat whitespace
 	do {
 		c = f.get();
 	} while (c == ' ' || c == '\t' || c == '\r');
 
-    // search for identifiers, numbers, plus or minus.
+	// search for identifiers, numbers, plus or minus.
 	if (('a' <= c && c <= 'z') || ('A' <= c && c <= 'Z') || ('0' <= c && c <= '9') || c == '_' || c == '-' || c == '+' || c == '.') {
 		str = c;
 		while (1) {
@@ -114,8 +114,8 @@ int LibertyParser::lexer(std::string &str)
 		}
 	}
 
-    // if it wasn't an identifer, number of array range,
-    // maybe it's a string?
+	// if it wasn't an identifer, number of array range,
+	// maybe it's a string?
 	if (c == '"') {
 		str = "";
 		while (1) {
@@ -130,7 +130,7 @@ int LibertyParser::lexer(std::string &str)
 		return 'v';
 	}
 
-    // if it wasn't a string, perhaps it's a comment or a forward slash?
+	// if it wasn't a string, perhaps it's a comment or a forward slash?
 	if (c == '/') {
 		c = f.get();
 		if (c == '*') {         // start of '/*' block comment
@@ -153,7 +153,7 @@ int LibertyParser::lexer(std::string &str)
 		return '/';             // a single '/' charater.
 	}
 
-    // check for a backslash
+	// check for a backslash
 	if (c == '\\') {
 		c = f.get();
 		if (c == '\r')
@@ -164,14 +164,14 @@ int LibertyParser::lexer(std::string &str)
 		return '\\';
 	}
 
-    // check for a new line
+	// check for a new line
 	if (c == '\n') {
 		line++;
 		return 'n';
 	}
 
-    // anything else, such as ';' will get passed
-    // through as literal items.
+	// anything else, such as ';' will get passed
+	// through as literal items.
 
 	// if (c >= 32 && c < 255)
 	// 	fprintf(stderr, "LEX: char >>%c<<\n", c);
@@ -202,8 +202,8 @@ LibertyAst *LibertyParser::parse()
 	{
 		tok = lexer(str);
 
-        // allow both ';' and new lines to 
-        // terminate a statement.
+		// allow both ';' and new lines to 
+		// terminate a statement.
 		if ((tok == ';') || (tok == 'n'))
 			break;
 
@@ -220,11 +220,11 @@ LibertyAst *LibertyParser::parse()
 				ast->value += str;
 				tok = lexer(str);
 			}
-            
-            // In a liberty file, all key : value pairs should end in ';'
-            // However, there are some liberty files in the wild that
-            // just have a newline. We'll be kind and accept a newline
-            // instead of the ';' too..
+			
+			// In a liberty file, all key : value pairs should end in ';'
+			// However, there are some liberty files in the wild that
+			// just have a newline. We'll be kind and accept a newline
+			// instead of the ';' too..
 			if ((tok == ';') || (tok == 'n'))
 				break;
 			else
@@ -240,48 +240,48 @@ LibertyAst *LibertyParser::parse()
 					continue;
 				if (tok == ')')
 					break;
-                
-                // FIXME: the AST needs to be extended to store
-                //        these vector ranges.
-                if (tok == '[')
-                {
-                    // parse vector range [A] or [A:B]
-                    std::string arg;
-                    tok = lexer(arg);
-                    if (tok != 'v')
-                    {
-                        // expected a vector array index
-                        error("Expected a number.");
-                    }
-                    else
-                    {
-                        // fixme: check for number A
-                    }
-                    tok = lexer(arg);
-                    // optionally check for : in case of [A:B]
-                    // if it isn't we just expect ']'
-                    // as we have [A]
-                    if (tok == ':')
-                    {
-                        tok = lexer(arg);
-                        if (tok != 'v')
-                        {
-                            // expected a vector array index
-                            error("Expected a number.");
-                        }
-                        else
-                        {
-                            // fixme: check for number B
-                            tok = lexer(arg);                            
-                        }
-                    }
-                    // expect a closing bracket of array range
-                    if (tok != ']')
-                    {
-                        error("Expected ']' on array range.");
-                    }
-                    continue;           
-                }
+				
+				// FIXME: the AST needs to be extended to store
+				//        these vector ranges.
+				if (tok == '[')
+				{
+					// parse vector range [A] or [A:B]
+					std::string arg;
+					tok = lexer(arg);
+					if (tok != 'v')
+					{
+						// expected a vector array index
+						error("Expected a number.");
+					}
+					else
+					{
+						// fixme: check for number A
+					}
+					tok = lexer(arg);
+					// optionally check for : in case of [A:B]
+					// if it isn't we just expect ']'
+					// as we have [A]
+					if (tok == ':')
+					{
+						tok = lexer(arg);
+						if (tok != 'v')
+						{
+							// expected a vector array index
+							error("Expected a number.");
+						}
+						else
+						{
+							// fixme: check for number B
+							tok = lexer(arg);                            
+						}
+					}
+					// expect a closing bracket of array range
+					if (tok != ']')
+					{
+						error("Expected ']' on array range.");
+					}
+					continue;           
+				}
 				if (tok != 'v')
 					error();
 				ast->args.push_back(arg);
@@ -314,10 +314,10 @@ void LibertyParser::error()
 
 void LibertyParser::error(const std::string &str)
 {
-    std::stringstream ss;
-    ss << "Syntax error in liberty file on line " << line << ".\n";
-    ss << "  " << str << "\n";
-    log_error("%s", ss.str().c_str());
+	std::stringstream ss;
+	ss << "Syntax error in liberty file on line " << line << ".\n";
+	ss << "  " << str << "\n";
+	log_error("%s", ss.str().c_str());
 }
 
 #else
@@ -330,32 +330,32 @@ void LibertyParser::error()
 
 void LibertyParser::error(const std::string &str)
 {
-    std::stringstream ss;
-    ss << "Syntax error in liberty file on line " << line << ".\n";
-    ss << "  " << str << "\n";
-    printf("%s", ss.str().c_str());
-    exit(1);
+	std::stringstream ss;
+	ss << "Syntax error in liberty file on line " << line << ".\n";
+	ss << "  " << str << "\n";
+	printf("%s", ss.str().c_str());
+	exit(1);
 }
 
 /**** BEGIN: http://svn.clifford.at/tools/trunk/examples/check.h ****/
 
 #define CHECK_NV(result, check)                                      \
    do {                                                              \
-     auto _R = (result);                                             \
-     if (!(_R check)) {                                              \
-       fprintf(stderr, "Error from '%s' (%ld %s) in %s:%d.\n",       \
-               #result, (long int)_R, #check, __FILE__, __LINE__);   \
-       abort();                                                      \
-     }                                                               \
+	 auto _R = (result);                                             \
+	 if (!(_R check)) {                                              \
+	   fprintf(stderr, "Error from '%s' (%ld %s) in %s:%d.\n",       \
+			   #result, (long int)_R, #check, __FILE__, __LINE__);   \
+	   abort();                                                      \
+	 }                                                               \
    } while(0)
 
 #define CHECK_COND(result)                                           \
    do {                                                              \
-     if (!(result)) {                                                \
-       fprintf(stderr, "Error from '%s' in %s:%d.\n",                \
-               #result, __FILE__, __LINE__);                         \
-       abort();                                                      \
-     }                                                               \
+	 if (!(result)) {                                                \
+	   fprintf(stderr, "Error from '%s' in %s:%d.\n",                \
+			   #result, __FILE__, __LINE__);                         \
+	   abort();                                                      \
+	 }                                                               \
    } while(0)
 
 /**** END: http://svn.clifford.at/tools/trunk/examples/check.h ****/

From ddc1a4488e9fc10f557e4260df0becbc1cf43f72 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 25 Mar 2019 19:49:00 +0100
Subject: [PATCH 518/528] Add "cutpoint" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/Makefile.inc |   1 +
 passes/sat/cutpoint.cc  | 164 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 165 insertions(+)
 create mode 100644 passes/sat/cutpoint.cc

diff --git a/passes/sat/Makefile.inc b/passes/sat/Makefile.inc
index 4eced2ff1..fc3ac879e 100644
--- a/passes/sat/Makefile.inc
+++ b/passes/sat/Makefile.inc
@@ -11,4 +11,5 @@ OBJS += passes/sat/async2sync.o
 OBJS += passes/sat/supercover.o
 OBJS += passes/sat/fmcombine.o
 OBJS += passes/sat/mutate.o
+OBJS += passes/sat/cutpoint.o
 
diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
new file mode 100644
index 000000000..3a38ebac0
--- /dev/null
+++ b/passes/sat/cutpoint.cc
@@ -0,0 +1,164 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct CutpointPass : public Pass {
+	CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { }
+	void help() YS_OVERRIDE
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    cutpoint [options] [selection]\n");
+		log("\n");
+		log("This command adds formal cut points to the design.\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	{
+		// bool flag_noinit = false;
+
+		log_header(design, "Executing CUTPOINT pass.\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-noinit") {
+			// 	flag_noinit = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			if (design->selected_whole_module(module->name)) {
+				log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
+				module->new_connections(std::vector<RTLIL::SigSig>());
+				for (auto cell : vector<Cell*>(module->cells()))
+					module->remove(cell);
+				vector<Wire*> output_wires;
+				for (auto wire : module->wires())
+					if (wire->port_output)
+						output_wires.push_back(wire);
+				for (auto wire : output_wires)
+					module->connect(wire, module->Anyseq(NEW_ID, GetSize(wire)));
+				continue;
+			}
+
+			SigMap sigmap(module);
+			pool<SigBit> cutpoint_bits;
+
+			for (auto cell : module->selected_cells()) {
+				if (cell->type == "$anyseq")
+					continue;
+				log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
+				for (auto &conn : cell->connections()) {
+					if (cell->output(conn.first))
+						module->connect(conn.second, module->Anyseq(NEW_ID, GetSize(conn.second)));
+				}
+				module->remove(cell);
+			}
+
+			for (auto wire : module->selected_wires()) {
+				if (wire->port_output) {
+					log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
+					Wire *new_wire = module->addWire(NEW_ID, wire);
+					module->swap_names(wire, new_wire);
+					module->connect(new_wire, module->Anyseq(NEW_ID, GetSize(new_wire)));
+					wire->port_id = 0;
+					wire->port_input = false;
+					wire->port_output = false;
+					continue;
+				}
+				log("Making wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
+				for (auto bit : sigmap(wire))
+					cutpoint_bits.insert(bit);
+			}
+
+			if (!cutpoint_bits.empty())
+			{
+				for (auto cell : module->cells()) {
+					for (auto &conn : cell->connections()) {
+						if (!cell->output(conn.first))
+							continue;
+						SigSpec sig = sigmap(conn.second);
+						int bit_count = 0;
+						for (auto &bit : sig) {
+							if (cutpoint_bits.count(bit))
+								bit_count++;
+						}
+						if (bit_count == 0)
+							continue;
+						SigSpec dummy = module->addWire(NEW_ID, bit_count);
+						bit_count = 0;
+						for (auto &bit : sig) {
+							if (cutpoint_bits.count(bit))
+								bit = dummy[bit_count++];
+						}
+						cell->setPort(conn.first, sig);
+					}
+				}
+
+				vector<Wire*> rewrite_wires;
+				for (auto wire : module->wires()) {
+					if (!wire->port_input)
+						continue;
+					int bit_count = 0;
+					for (auto &bit : sigmap(wire))
+						if (cutpoint_bits.count(bit))
+							bit_count++;
+					if (bit_count)
+						rewrite_wires.push_back(wire);
+				}
+
+				for (auto wire : rewrite_wires) {
+					Wire *new_wire = module->addWire(NEW_ID, wire);
+					SigSpec lhs, rhs, sig = sigmap(wire);
+					for (int i = 0; i < GetSize(sig); i++)
+						if (!cutpoint_bits.count(sig[i])) {
+							lhs.append(SigBit(wire, i));
+							rhs.append(SigBit(new_wire, i));
+						}
+					if (GetSize(lhs))
+					module->connect(lhs, rhs);
+					module->swap_names(wire, new_wire);
+					wire->port_id = 0;
+					wire->port_input = false;
+					wire->port_output = false;
+				}
+
+				SigSpec sig(cutpoint_bits);
+				sig.sort_and_unify();
+
+				for (auto chunk : sig.chunks()) {
+					SigSpec s(chunk);
+					module->connect(s, module->Anyseq(NEW_ID, GetSize(s)));
+				}
+			}
+		}
+	}
+} CutpointPass;
+
+PRIVATE_NAMESPACE_END

From c863796e9ff91c76f0f8679b6871b8ffcb75edb6 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2019 14:17:46 +0100
Subject: [PATCH 519/528] Fix "verific -extnets" for more complex situations

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 86 +++++++++++++++++++++++++++++-------
 tests/sva/extnets.sv         | 22 +++++++++
 2 files changed, 93 insertions(+), 15 deletions(-)
 create mode 100644 tests/sva/extnets.sv

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index c412cd3a3..95b7d3586 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1619,30 +1619,35 @@ struct VerificExtNets
 	int portname_cnt = 0;
 
 	// a map from Net to the same Net one level up in the design hierarchy
-	std::map<Net*, Net*> net_level_up;
+	std::map<Net*, Net*> net_level_up_drive_up;
+	std::map<Net*, Net*> net_level_up_drive_down;
 
-	Net *get_net_level_up(Net *net)
+	Net *route_up(Net *net, bool drive_up, Net *final_net = nullptr)
 	{
+		auto &net_level_up = drive_up ? net_level_up_drive_up : net_level_up_drive_down;
+
 		if (net_level_up.count(net) == 0)
 		{
 			Netlist *nl = net->Owner();
 
 			// Simply return if Netlist is not unique
-			if (nl->NumOfRefs() != 1)
-				return net;
+			log_assert(nl->NumOfRefs() == 1);
 
 			Instance *up_inst = (Instance*)nl->GetReferences()->GetLast();
 			Netlist *up_nl = up_inst->Owner();
 
 			// create new Port
 			string name = stringf("___extnets_%d", portname_cnt++);
-			Port *new_port = new Port(name.c_str(), DIR_OUT);
+			Port *new_port = new Port(name.c_str(), drive_up ? DIR_OUT : DIR_IN);
 			nl->Add(new_port);
 			net->Connect(new_port);
 
 			// create new Net in up Netlist
-			Net *new_net = new Net(name.c_str());
-			up_nl->Add(new_net);
+			Net *new_net = final_net;
+			if (new_net == nullptr || new_net->Owner() != up_nl) {
+				new_net = new Net(name.c_str());
+				up_nl->Add(new_net);
+			}
 			up_inst->Connect(new_port, new_net);
 
 			net_level_up[net] = new_net;
@@ -1651,6 +1656,39 @@ struct VerificExtNets
 		return net_level_up.at(net);
 	}
 
+	Net *route_up(Net *net, bool drive_up, Netlist *dest, Net *final_net = nullptr)
+	{
+		while (net->Owner() != dest)
+			net = route_up(net, drive_up, final_net);
+		if (final_net != nullptr)
+			log_assert(net == final_net);
+		return net;
+	}
+
+	Netlist *find_common_ancestor(Netlist *A, Netlist *B)
+	{
+		std::set<Netlist*> ancestors_of_A;
+
+		Netlist *cursor = A;
+		while (1) {
+			ancestors_of_A.insert(cursor);
+			if (cursor->NumOfRefs() != 1)
+				break;
+			cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
+		}
+
+		cursor = B;
+		while (1) {
+			if (ancestors_of_A.count(cursor))
+				return cursor;
+			if (cursor->NumOfRefs() != 1)
+				break;
+			cursor = ((Instance*)cursor->GetReferences()->GetLast())->Owner();
+		}
+
+		log_error("No common ancestor found between %s and %s.\n", get_full_netlist_name(A).c_str(), get_full_netlist_name(B).c_str());
+	}
+
 	void run(Netlist *nl)
 	{
 		MapIter mi, mi2;
@@ -1674,19 +1712,37 @@ struct VerificExtNets
 			if (verific_verbose)
 				log("Fixing external net reference on port %s.%s.%s:\n", get_full_netlist_name(nl).c_str(), inst->Name(), port->Name());
 
-			while (net->IsExternalTo(nl))
-			{
-				Net *newnet = get_net_level_up(net);
-				if (newnet == net) break;
+			Netlist *ext_nl = net->Owner();
 
+			if (verific_verbose)
+				log(" external net owner: %s\n", get_full_netlist_name(ext_nl).c_str());
+
+			Netlist *ca_nl = find_common_ancestor(nl, ext_nl);
+
+			if (verific_verbose)
+				log(" common ancestor: %s\n", get_full_netlist_name(ca_nl).c_str());
+
+			Net *ca_net = route_up(net, !port->IsOutput(), ca_nl);
+			Net *new_net = ca_net;
+
+			if (ca_nl != nl)
+			{
 				if (verific_verbose)
-					log("  external net: %s.%s\n", get_full_netlist_name(net->Owner()).c_str(), net->Name());
-				net = newnet;
+					log(" net in common ancestor: %s\n", ca_net->Name());
+
+				string name = stringf("___extnets_%d", portname_cnt++);
+				new_net = new Net(name.c_str());
+				nl->Add(new_net);
+
+				Net *n = route_up(new_net, port->IsOutput(), ca_nl, ca_net);
+				log_assert(n == ca_net);
 			}
 
 			if (verific_verbose)
-				log("  final net: %s.%s%s\n", get_full_netlist_name(net->Owner()).c_str(), net->Name(), net->IsExternalTo(nl) ? " (external)" : "");
-			todo_connect.push_back(tuple<Instance*, Port*, Net*>(inst, port, net));
+				log(" new local net: %s\n", new_net->Name());
+
+			log_assert(!new_net->IsExternalTo(nl));
+			todo_connect.push_back(tuple<Instance*, Port*, Net*>(inst, port, new_net));
 		}
 
 		for (auto it : todo_connect) {
diff --git a/tests/sva/extnets.sv b/tests/sva/extnets.sv
new file mode 100644
index 000000000..47312de7a
--- /dev/null
+++ b/tests/sva/extnets.sv
@@ -0,0 +1,22 @@
+module top(input i, output o);
+	A A();
+	B B();
+	assign A.i = i;
+	assign o = B.o;
+	always @* assert(o == i);
+endmodule
+
+module A;
+	wire i, y;
+`ifdef FAIL
+	assign B.x = i;
+`else
+	assign B.x = !i;
+`endif
+	assign y = !B.y;
+endmodule
+
+module B;
+	wire x, y, o;
+	assign y = x, o = A.y;
+endmodule

From d0b9b1bece9866fd7b0e153c991fc7e9b57a1efc Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2019 14:51:35 +0100
Subject: [PATCH 520/528] Add "hdlname" attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 README.md                    | 3 +++
 passes/hierarchy/uniquify.cc | 2 ++
 2 files changed, 5 insertions(+)

diff --git a/README.md b/README.md
index c5cd47707..4048ecbc7 100644
--- a/README.md
+++ b/README.md
@@ -315,6 +315,9 @@ Verilog Attributes and non-standard features
 - The ``dynports'' attribute is used by the Verilog front-end to mark modules
   that have ports with a width that depends on a parameter.
 
+- The ``hdlname'' attribute is used by some passes to document the original
+  (HDL) name of a module when renaming a module.
+
 - The ``keep`` attribute on cells and wires is used to mark objects that should
   never be removed by the optimizer. This is used for example for cells that
   have hidden connections that are not part of the netlist, such as IO pads.
diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
index c88ecd82e..e6154e94f 100644
--- a/passes/hierarchy/uniquify.cc
+++ b/passes/hierarchy/uniquify.cc
@@ -87,6 +87,8 @@ struct UniquifyPass : public Pass {
 					smod->name = newname;
 					cell->type = newname;
 					smod->set_bool_attribute("\\unique");
+					if (smod->attributes.count("\\hdlname") == 0)
+						smod->attributes["\\hdlname"] = string(log_id(tmod->name));
 					design->add(smod);
 
 					did_something = true;

From 38b3fbd3f0bbdace11a3ab7b3d153b1a05059378 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 26 Mar 2019 16:01:14 +0100
Subject: [PATCH 521/528] Add "cutpoint -undef"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/sat/cutpoint.cc | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

diff --git a/passes/sat/cutpoint.cc b/passes/sat/cutpoint.cc
index 3a38ebac0..048aec7f3 100644
--- a/passes/sat/cutpoint.cc
+++ b/passes/sat/cutpoint.cc
@@ -33,20 +33,24 @@ struct CutpointPass : public Pass {
 		log("\n");
 		log("This command adds formal cut points to the design.\n");
 		log("\n");
+		log("    -undef\n");
+		log("        set cupoint nets to undef (x). the default behavior is to create a\n");
+		log("        $anyseq cell and drive the cutpoint net from that\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		// bool flag_noinit = false;
+		 bool flag_undef = false;
 
 		log_header(design, "Executing CUTPOINT pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
-			// if (args[argidx] == "-noinit") {
-			// 	flag_noinit = true;
-			// 	continue;
-			// }
+			if (args[argidx] == "-undef") {
+				flag_undef = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -63,7 +67,7 @@ struct CutpointPass : public Pass {
 					if (wire->port_output)
 						output_wires.push_back(wire);
 				for (auto wire : output_wires)
-					module->connect(wire, module->Anyseq(NEW_ID, GetSize(wire)));
+					module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
 				continue;
 			}
 
@@ -76,7 +80,7 @@ struct CutpointPass : public Pass {
 				log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
 				for (auto &conn : cell->connections()) {
 					if (cell->output(conn.first))
-						module->connect(conn.second, module->Anyseq(NEW_ID, GetSize(conn.second)));
+						module->connect(conn.second, flag_undef ? Const(State::Sx, GetSize(conn.second)) : module->Anyseq(NEW_ID, GetSize(conn.second)));
 				}
 				module->remove(cell);
 			}
@@ -86,7 +90,7 @@ struct CutpointPass : public Pass {
 					log("Making output wire %s.%s a cutpoint.\n", log_id(module), log_id(wire));
 					Wire *new_wire = module->addWire(NEW_ID, wire);
 					module->swap_names(wire, new_wire);
-					module->connect(new_wire, module->Anyseq(NEW_ID, GetSize(new_wire)));
+					module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire)));
 					wire->port_id = 0;
 					wire->port_input = false;
 					wire->port_output = false;
@@ -142,7 +146,7 @@ struct CutpointPass : public Pass {
 							rhs.append(SigBit(new_wire, i));
 						}
 					if (GetSize(lhs))
-					module->connect(lhs, rhs);
+						module->connect(lhs, rhs);
 					module->swap_names(wire, new_wire);
 					wire->port_id = 0;
 					wire->port_input = false;
@@ -154,7 +158,7 @@ struct CutpointPass : public Pass {
 
 				for (auto chunk : sig.chunks()) {
 					SigSpec s(chunk);
-					module->connect(s, module->Anyseq(NEW_ID, GetSize(s)));
+					module->connect(s, flag_undef ? Const(State::Sx, GetSize(s)) : module->Anyseq(NEW_ID, GetSize(s)));
 				}
 			}
 		}

From d351b7cb99efe8c412ef7fa8bc0b99b72bc56726 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Mar 2019 13:33:26 +0100
Subject: [PATCH 522/528] Improve "rename" help message

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/cmds/rename.cc | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 698ce7235..466a5da53 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -108,15 +108,19 @@ struct RenamePass : public Pass {
 		log("Rename the specified object. Note that selection patterns are not supported\n");
 		log("by this command.\n");
 		log("\n");
+		log("\n");
 		log("    rename -src [selection]\n");
 		log("\n");
 		log("Assign names auto-generated from the src attribute to all selected wires and\n");
 		log("cells with private names.\n");
 		log("\n");
+		log("\n");
 		log("    rename -wire [selection]\n");
+		log("\n");
 		log("Assign auto-generated names based on the wires they drive to all selected\n");
 		log("cells with private names. Ignores cells driving privatly named wires.\n");
 		log("\n");
+		log("\n");
 		log("    rename -enumerate [-pattern <pattern>] [selection]\n");
 		log("\n");
 		log("Assign short auto-generated names to all selected wires and cells with private\n");
@@ -124,11 +128,13 @@ struct RenamePass : public Pass {
 		log("The character %% in the pattern is replaced with a integer number. The default\n");
 		log("pattern is '_%%_'.\n");
 		log("\n");
+		log("\n");
 		log("    rename -hide [selection]\n");
 		log("\n");
 		log("Assign private names (the ones with $-prefix) to all selected wires and cells\n");
 		log("with public names. This ignores all selected ports.\n");
 		log("\n");
+		log("\n");
 		log("    rename -top new_name\n");
 		log("\n");
 		log("Rename top module.\n");

From 2c7fe42ad158a9859895399bdd876f5dbb2c7376 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Mar 2019 13:47:42 +0100
Subject: [PATCH 523/528] Add "rename -output"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 passes/cmds/rename.cc | 26 +++++++++++++++++++++++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 466a5da53..9b1830b7b 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -24,7 +24,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
+static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name, bool flag_output)
 {
 	from_name = RTLIL::escape_id(from_name);
 	to_name = RTLIL::escape_id(to_name);
@@ -37,13 +37,18 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 			Wire *w = it.second;
 			log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module));
 			module->rename(w, to_name);
-			if (w->port_id)
+			if (w->port_id || flag_output) {
+				if (flag_output)
+					w->port_output = true;
 				module->fixup_ports();
+			}
 			return;
 		}
 
 	for (auto &it : module->cells_)
 		if (it.first == from_name) {
+			if (flag_output)
+				log_cmd_error("Called with -output but the specified object is a cell.\n");
 			log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
 			module->rename(it.second, to_name);
 			return;
@@ -109,6 +114,13 @@ struct RenamePass : public Pass {
 		log("by this command.\n");
 		log("\n");
 		log("\n");
+		log("\n");
+		log("    rename -output old_name new_name\n");
+		log("\n");
+		log("Like above, but also make the wire an output. This will fail if the object is\n");
+		log("not a wire.\n");
+		log("\n");
+		log("\n");
 		log("    rename -src [selection]\n");
 		log("\n");
 		log("Assign names auto-generated from the src attribute to all selected wires and\n");
@@ -148,6 +160,7 @@ struct RenamePass : public Pass {
 		bool flag_enumerate = false;
 		bool flag_hide = false;
 		bool flag_top = false;
+		bool flag_output = false;
 		bool got_mode = false;
 
 		size_t argidx;
@@ -159,6 +172,11 @@ struct RenamePass : public Pass {
 				got_mode = true;
 				continue;
 			}
+			if (arg == "-output" && !got_mode) {
+				flag_output = true;
+				got_mode = true;
+				continue;
+			}
 			if (arg == "-wire" && !got_mode) {
 				flag_wire = true;
 				got_mode = true;
@@ -328,10 +346,12 @@ struct RenamePass : public Pass {
 			if (!design->selected_active_module.empty())
 			{
 				if (design->modules_.count(design->selected_active_module) > 0)
-					rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name);
+					rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name, flag_output);
 			}
 			else
 			{
+				if (flag_output)
+					log_cmd_error("Mode -output requires that there is an active module selected.\n");
 				for (auto &mod : design->modules_) {
 					if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
 						to_name = RTLIL::escape_id(to_name);

From 7682629b79fd59f5ed49fb35a3a2441a405bfd63 Mon Sep 17 00:00:00 2001
From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 27 Mar 2019 14:03:35 +0100
Subject: [PATCH 524/528] Add "read -verific" and "read -noverific"

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---
 frontends/verific/verific.cc | 34 ++++++++++++++++++++++++++++------
 1 file changed, 28 insertions(+), 6 deletions(-)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 95b7d3586..ed9727b88 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2386,21 +2386,43 @@ struct ReadPass : public Pass {
 		log("\n");
 		log("Add directory to global Verilog/SystemVerilog include directories.\n");
 		log("\n");
+		log("\n");
+		log("    read -verific\n");
+		log("    read -noverific\n");
+		log("\n");
+		log("Subsequent calls to 'read' will either use or not use Verific. Calling 'read'\n");
+		log("with -verific will result in an error on Yosys binaries that are built without\n");
+		log("Verific support. The default is to use Verific if it is available.\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
+#ifdef YOSYS_ENABLE_VERIFIC
+		static bool verific_available = !check_noverific_env();
+#else
+		static bool verific_available = false;
+#endif
+		static bool use_verific = verific_available;
+
 		if (args.size() < 2 || args[1][0] != '-')
 			log_cmd_error("Missing mode parameter.\n");
 
+		if (args[1] == "-verific" || args[1] == "-noverific") {
+			if (args.size() != 2)
+				log_cmd_error("Additional arguments to -verific/-noverific.\n");
+			if (args[1] == "-verific") {
+				if (!verific_available)
+					log_cmd_error("This version of Yosys is built without Verific support.\n");
+				use_verific = true;
+			} else {
+				use_verific = false;
+			}
+			return;
+		}
+
 		if (args.size() < 3)
 			log_cmd_error("Missing file name parameter.\n");
 
-#ifdef YOSYS_ENABLE_VERIFIC
-		bool use_verific = !check_noverific_env();
-#else
-		bool use_verific = false;
-#endif
-
 		if (args[1] == "-vlog95" || args[1] == "-vlog2k") {
 			if (use_verific) {
 				args[0] = "verific";

From 487cb45b87ce1cbcc8c2b8127e37d85dd192dceb Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Wed, 27 Mar 2019 15:15:53 +0100
Subject: [PATCH 525/528] Liberty file parser now accepts superfluous ;

---
 passes/techmap/libparse.cc     | 61 ++++++++++++++++++++++++++++++----
 tests/liberty/normal.lib       |  3 +-
 tests/liberty/processdefs.lib  | 48 ++++++++++++++++++++++++++
 tests/liberty/semicolextra.lib | 48 ++++++++++++++++++++++++++
 4 files changed, 151 insertions(+), 9 deletions(-)
 create mode 100644 tests/liberty/processdefs.lib
 create mode 100644 tests/liberty/semicolextra.lib

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 8eadd8735..510a24c24 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -155,11 +155,13 @@ int LibertyParser::lexer(std::string &str)
 
 	// check for a backslash
 	if (c == '\\') {
-		c = f.get();
+		c = f.get();		
 		if (c == '\r')
 			c = f.get();
-		if (c == '\n')
+		if (c == '\n') {
+			line++;
 			return lexer(str);
+		}
 		f.unget();
 		return '\\';
 	}
@@ -186,14 +188,39 @@ LibertyAst *LibertyParser::parse()
 
 	int tok = lexer(str);
 
-	while (tok == 'n')
+	// there are liberty files in the while that
+	// have superfluous ';' at the end of
+	// a  { ... }. We simply ignore a ';' here.
+	// and get to the next statement.
+
+	while ((tok == 'n') || (tok == ';'))
 		tok = lexer(str);
 
 	if (tok == '}' || tok < 0)
 		return NULL;
 
-	if (tok != 'v')
-		error();
+	if (tok != 'v') {
+		std::string eReport;
+		switch(tok)
+		{
+		case 'n':
+			error("Unexpected newline.");
+			break;
+		case '[':
+		case ']':
+		case '}':
+		case '{':
+		case '\"':
+		case ':':
+			eReport = "Unexpected '";
+			eReport += static_cast<char>(tok);
+			eReport += "'.";
+			error(eReport);
+			break;
+		default:
+			error();
+		}
+	}
 
 	LibertyAst *ast = new LibertyAst;
 	ast->id = str;
@@ -282,8 +309,28 @@ LibertyAst *LibertyParser::parse()
 					}
 					continue;           
 				}
-				if (tok != 'v')
-					error();
+				if (tok != 'v') {
+					std::string eReport;
+					switch(tok)
+					{
+					case 'n':
+						error("Unexpected newline.");
+						break;
+					case '[':
+					case ']':
+					case '}':
+					case '{':
+					case '\"':
+					case ':':
+						eReport = "Unexpected '";
+						eReport += static_cast<char>(tok);
+						eReport += "'.";
+						error(eReport);
+						break;
+					default:
+						error();
+					}
+				}
 				ast->args.push_back(arg);
 			}
 			continue;
diff --git a/tests/liberty/normal.lib b/tests/liberty/normal.lib
index 1474e2b59..4621194dd 100644
--- a/tests/liberty/normal.lib
+++ b/tests/liberty/normal.lib
@@ -142,8 +142,7 @@ library(supergate) {
   }
   
   /* D-type flip-flop with asynchronous reset and preset */
-  cell (dff) 
-  {
+  cell (dff) {
     area : 6;
     ff("IQ", "IQN") {
       next_state : "D";
diff --git a/tests/liberty/processdefs.lib b/tests/liberty/processdefs.lib
new file mode 100644
index 000000000..37a6bbaf8
--- /dev/null
+++ b/tests/liberty/processdefs.lib
@@ -0,0 +1,48 @@
+/********************************************/
+/*                                          */
+/* Supergate cell library for Bench marking */
+/*                                          */
+/* Symbiotic EDA GmbH / Moseley Instruments */
+/* Niels A. Moseley                         */
+/*                                          */
+/* Process: none                            */
+/*                                          */
+/* Date   : 25-03-2019                      */
+/* Version: 1.0                             */
+/*                                          */
+/********************************************/
+
+library(processdefs) {
+    technology (cmos);
+    revision : 1.0;
+
+    time_unit                     : "1ps";
+    pulling_resistance_unit       : "1kohm";  
+    voltage_unit                  : "1V";
+    current_unit                  : "1uA";  
+
+    capacitive_load_unit(1,ff);
+
+    default_inout_pin_cap         :  7.0;
+    default_input_pin_cap         :  7.0;
+    default_output_pin_cap        :  0.0;
+    default_fanout_load           :  1.0;
+
+    default_wire_load_capacitance : 0.1;
+    default_wire_load_resistance  : 1.0e-3;
+    default_wire_load_area        : 0.0;
+
+    nom_process                   :  1.0;
+    nom_temperature               : 25.0;
+    nom_voltage                   :  1.2;
+
+    delay_model                   : generic_cmos;
+    
+    define_cell_area(bond_pads,pad_slots)
+    input_voltage(cmos) {
+        vil : 0.3 * VDD ;
+        vih : 0.7 * VDD ;
+        vimin : -0.5 ;
+        vimax : VDD + 0.5 ;
+    }
+}
diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib
new file mode 100644
index 000000000..0144fa3ac
--- /dev/null
+++ b/tests/liberty/semicolextra.lib
@@ -0,0 +1,48 @@
+/*
+
+	Test case for https://www.reddit.com/r/yosys/comments/b5texg/yosys_fails_to_parse_apparentlycorrect_liberty/
+
+	fall_constraint (SETUP_HOLD) formatting.
+
+*/
+
+library(supergate) {
+  technology (cmos);
+  revision : 1.0;
+
+    cell (DFF) {
+        cell_footprint : dff;
+        area : 50;
+        pin(D) {
+            direction : input;
+            capacitance : 0.002;
+            timing() {
+                related_pin : "CK";
+                timing_type : setup_rising;
+
+                fall_constraint (SETUP_HOLD) { values ("0.4000, 0.3000, 0.2000, 0.1000, 0.0000", \
+                    "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
+                    "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
+                    "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
+                    "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ;
+            }
+        }	
+
+        pin(CK) {
+            direction : input;
+            clock : true;
+            capacitance : 0.00290;
+        }
+
+        ff(IQ,IQN) {
+            clocked_on : "CK";
+            next_state : "D";
+        }
+        pin(Q) {
+            direction : output;
+            capacitance : 0.003;
+            max_capacitance : 0.3;
+        }
+        cell_leakage_power : 0.3;
+    }
+}

From ee130f67cdd2ea40defa873e9a6511329850bf8e Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Wed, 27 Mar 2019 15:16:19 +0100
Subject: [PATCH 526/528] Liberty file parser now accepts superfluous ;

---
 tests/liberty/semicolextra.lib | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/liberty/semicolextra.lib b/tests/liberty/semicolextra.lib
index 0144fa3ac..6a7fa77cc 100644
--- a/tests/liberty/semicolextra.lib
+++ b/tests/liberty/semicolextra.lib
@@ -24,7 +24,7 @@ library(supergate) {
                     "0.4000, 0.3000, 0.2000, 0.1000, 0.000", \
                     "0.5000, 0.4000, 0.3000, 0.2000, 0.0000", \
                     "0.7000, 0.6000, 0.5000, 0.4000, 0.2000", \
-                    "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); } ;
+                    "1.0000, 1.0000, 0.9000, 0.8000, 0.6000"); };
             }
         }	
 

From 263ab60b43f3994e83bfa46b793669147d765bcc Mon Sep 17 00:00:00 2001
From: Niels Moseley <n.a.moseley@moseleyinstruments.com>
Date: Wed, 27 Mar 2019 15:17:58 +0100
Subject: [PATCH 527/528] Liberty file parser now accepts superfluous ;

---
 passes/techmap/libparse.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 510a24c24..991cc4498 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -188,7 +188,7 @@ LibertyAst *LibertyParser::parse()
 
 	int tok = lexer(str);
 
-	// there are liberty files in the while that
+	// there are liberty files in the wild that
 	// have superfluous ';' at the end of
 	// a  { ... }. We simply ignore a ';' here.
 	// and get to the next statement.

From 60594ad40cb51f6cf8a5e6ce61377b3405b873a8 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Wed, 27 Mar 2019 17:19:14 +0000
Subject: [PATCH 528/528] memory_bram: Reset make_transp when growing read
 ports

Signed-off-by: David Shah <dave@ds0.me>
---
 passes/memory/memory_bram.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/memory/memory_bram.cc b/passes/memory/memory_bram.cc
index c38eabaee..85ed1c053 100644
--- a/passes/memory/memory_bram.cc
+++ b/passes/memory/memory_bram.cc
@@ -641,6 +641,7 @@ grow_read_ports:;
 				pi.sig_data = SigSpec();
 				pi.sig_en = SigSpec();
 				pi.make_outreg = false;
+				pi.make_transp = false;
 			}
 			new_portinfos.push_back(pi);
 			if (pi.dupidx == dup_count-1) {