mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-10 09:48:06 +00:00
Code Activity

analogdevices: Native LUTRAM primitives

Browse source
This commit is contained in:
Krystine Sherwin 2025-10-08 14:08:41 +13:00 • committed by Lofty
parent b1bc39bca4
commit 009bc900fb
3 changed files with 13 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/analogdevices/cells_sim.v
View file

@ -604,6 +604,8 @@ module RAMS64X1 (
endspecify endspecify
endmodule endmodule
// Dual port.
(* abc9_box, lib_whitebox *) (* abc9_box, lib_whitebox *)
module RAMD32X1 ( module RAMD32X1 (
output DPO, SPO, output DPO, SPO,

12
techlibs/analogdevices/lutrams.txt
View file

@ -1,37 +1,39 @@
# Single-port RAMs. # Single-port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_SP_ { ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
cost 1;
option "ABITS" 5 { option "ABITS" 5 {
cost 1;
abits 5; abits 5;
} }
option "ABITS" 6 { option "ABITS" 6 {
cost 2;
abits 6; abits 6;
} }
width 1; width 1;
init no_undef; init no_undef;
prune_rom; prune_rom;
port arsw "RW" { port arsw "RW" {
clock posedge; clock anyedge;
} }
} }
# Dual-port RAMs. # Dual-port RAMs.
ram distributed $__ANALOGDEVICES_LUTRAM_DP_ { ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
cost 1;
option "ABITS" 5 { option "ABITS" 5 {
cost 2;
abits 5; abits 5;
} }
option "ABITS" 6 { option "ABITS" 6 {
cost 4;
abits 6; abits 6;
} }
width 1; width 1;
init no_undef; init no_undef;
prune_rom; prune_rom;
port ar "R" {
}
port arsw "RW" { port arsw "RW" {
clock posedge; clock posedge;
} }
port ar "R" {
}
} }

9
techlibs/analogdevices/lutrams_map.v
View file

@ -28,7 +28,7 @@ case(OPTION_ABITS)
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN) .WE(PORT_RW_WR_EN)
); );
6: begin 6:
RAMS64X1 RAMS64X1
#( #(
.INIT(INIT) .INIT(INIT)
@ -46,9 +46,8 @@ case(OPTION_ABITS)
.WCLK(PORT_RW_CLK), .WCLK(PORT_RW_CLK),
.WE(PORT_RW_WR_EN) .WE(PORT_RW_WR_EN)
); );
end
default: default:
$error("invalid OPTION_ABITS/WIDTH combination"); $error("invalid OPTION_ABITS");
endcase endcase
endgenerate endgenerate
@ -78,8 +77,8 @@ case (OPTION_ABITS)
) )
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
( (
.SPO(PORT_RW_RD_DATA),
.DPO(PORT_R_RD_DATA), .DPO(PORT_R_RD_DATA),
.SPO(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]), .A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]), .A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]), .A2(PORT_RW_ADDR[2]),
@ -101,8 +100,8 @@ case (OPTION_ABITS)
) )
_TECHMAP_REPLACE_ _TECHMAP_REPLACE_
( (
.SPO(PORT_RW_RD_DATA),
.DPO(PORT_R_RD_DATA), .DPO(PORT_R_RD_DATA),
.SPO(PORT_RW_RD_DATA),
.A0(PORT_RW_ADDR[0]), .A0(PORT_RW_ADDR[0]),
.A1(PORT_RW_ADDR[1]), .A1(PORT_RW_ADDR[1]),
.A2(PORT_RW_ADDR[2]), .A2(PORT_RW_ADDR[2]),