From 009bc900fb039c7b7d4239d254b5740cf57b96cc Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Wed, 8 Oct 2025 14:08:41 +1300
Subject: [PATCH] analogdevices: Native LUTRAM primitives

---
 techlibs/analogdevices/cells_sim.v   |  2 ++
 techlibs/analogdevices/lutrams.txt   | 12 +++++++-----
 techlibs/analogdevices/lutrams_map.v |  9 ++++-----
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v
index c49a54e79..4f9af79c5 100644
--- a/techlibs/analogdevices/cells_sim.v
+++ b/techlibs/analogdevices/cells_sim.v
@@ -604,6 +604,8 @@ module RAMS64X1 (
   endspecify
 endmodule
 
+// Dual port.
+
 (* abc9_box, lib_whitebox *)
 module RAMD32X1 (
   output DPO, SPO,
diff --git a/techlibs/analogdevices/lutrams.txt b/techlibs/analogdevices/lutrams.txt
index fbfd530c3..c342eaede 100644
--- a/techlibs/analogdevices/lutrams.txt
+++ b/techlibs/analogdevices/lutrams.txt
@@ -1,37 +1,39 @@
 # Single-port RAMs.
 
 ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
-	cost 1;
 	option "ABITS" 5 {
+		cost 1;
 		abits 5;
 	}
 	option "ABITS" 6 {
+		cost 2;
 		abits 6;
 	}
 	width 1;
 	init no_undef;
 	prune_rom;
 	port arsw "RW" {
-		clock posedge;
+		clock anyedge;
 	}
 }
 
 # Dual-port RAMs.
 
 ram distributed $__ANALOGDEVICES_LUTRAM_DP_ {
-	cost 1;
 	option "ABITS" 5 {
+		cost 2;
 		abits 5;
 	}
 	option "ABITS" 6 {
+		cost 4;
 		abits 6;
 	}
 	width 1;
 	init no_undef;
 	prune_rom;
-	port ar "R" {
-	}
 	port arsw "RW" {
 		clock posedge;
 	}
+	port ar "R" {
+	}
 }
diff --git a/techlibs/analogdevices/lutrams_map.v b/techlibs/analogdevices/lutrams_map.v
index cb148f56c..7962e616c 100644
--- a/techlibs/analogdevices/lutrams_map.v
+++ b/techlibs/analogdevices/lutrams_map.v
@@ -28,7 +28,7 @@ case(OPTION_ABITS)
 		.WCLK(PORT_RW_CLK),
 		.WE(PORT_RW_WR_EN)
 	);
-6: begin
+6:
 	RAMS64X1
 	#(
 		.INIT(INIT)
@@ -46,9 +46,8 @@ case(OPTION_ABITS)
 		.WCLK(PORT_RW_CLK),
 		.WE(PORT_RW_WR_EN)
 	);
-end
 default:
-	$error("invalid OPTION_ABITS/WIDTH combination");
+	$error("invalid OPTION_ABITS");
 endcase
 endgenerate
 
@@ -78,8 +77,8 @@ case (OPTION_ABITS)
 	)
 	_TECHMAP_REPLACE_
 	(
-		.SPO(PORT_RW_RD_DATA),
 		.DPO(PORT_R_RD_DATA),
+		.SPO(PORT_RW_RD_DATA),
 		.A0(PORT_RW_ADDR[0]),
 		.A1(PORT_RW_ADDR[1]),
 		.A2(PORT_RW_ADDR[2]),
@@ -101,8 +100,8 @@ case (OPTION_ABITS)
 	)
 	_TECHMAP_REPLACE_
 	(
-		.SPO(PORT_RW_RD_DATA),
 		.DPO(PORT_R_RD_DATA),
+		.SPO(PORT_RW_RD_DATA),
 		.A0(PORT_RW_ADDR[0]),
 		.A1(PORT_RW_ADDR[1]),
 		.A2(PORT_RW_ADDR[2]),