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Demonstrate binding SVA properties to a VHDL design. Mention example code (with snippets) in section on Verific.
33 lines
904 B
VHDL
33 lines
904 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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entity updowncount is
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port (
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rst, clk : in std_logic ;
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up, down : in std_logic ;
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o: out std_logic_vector(0 to 3)
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);
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end updowncount;
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architecture rtl of updowncount is
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signal count : std_logic_vector(0 to 3) := "0000";
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begin
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process(clk)
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begin
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if (rising_edge(clk)) then
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if (rst = '1') then
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count <= "0000";
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else
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if (up = '1' and count <= "1010") then
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count <= count + "0001";
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end if;
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if (down = '1' and count > "0000") then
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count <= count - "0001";
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end if;
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end if;
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end if;
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end process;
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o <= count;
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end rtl;
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