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37 lines
1.5 KiB
ReStructuredText
37 lines
1.5 KiB
ReStructuredText
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Getting started
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===============
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.. note:: This tutorial assumes sby installation as per the :ref:`install-doc`.
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It is also recommended to install
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`GTKWave <http://gtkwave.sourceforge.net/>`_, an open source VCD viewer.
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First In, First Out (FIFO) buffer
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********************************
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From `Wikipedia <https://en.wikipedia.org/wiki/FIFO_(computing_and_electronics)>`_,
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a FIFO is
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a method for organizing the manipulation of a data structure (often,
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specifically a data buffer) where the oldest (first) entry, or "head" of the
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queue, is processed first.
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Such processing is analogous to servicing people in a queue area on a
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first-come, first-served (FCFS) basis, i.e. in the same sequence in which
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they arrive at the queue's tail.
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In hardware we can create such a construct by providing two addresses into a
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register file. See the Verilog code below for the two main modules of an
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example implementation.
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.. literalinclude:: ../examples/fifo/fifo.sv
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:language: systemverilog
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Notice that this register design includes a synchronous write and asynchronous
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read. Each word is 8 bits, and up to 16 words can be stored in the buffer. The
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address generator module will be instantiated twice; once for the write address
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and once for the read address. In both cases, the address will start at and
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reset to 0, and will increment by 1 when an enable signal is received. When the
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address pointers increment from the maximum storage value they reset back to 0,
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providing a circular queue.
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