mirror of
https://github.com/YosysHQ/sby.git
synced 2025-04-13 16:48:44 +00:00
12 lines
227 B
Verilog
12 lines
227 B
Verilog
module primegen;
|
|
wire [31:0] prime = $anyconst;
|
|
wire [15:0] factor = $allconst;
|
|
|
|
always @* begin
|
|
if (1 < factor && factor < prime)
|
|
assume((prime % factor) != 0);
|
|
assume(prime > 1000000000);
|
|
cover(1);
|
|
end
|
|
endmodule
|