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2d3d96478a
This also changes the test Makefile to run `.check.py` files after running the corresponding `.sby` file to allow more precise testing of the keep going feature.
18 lines
236 B
Systemverilog
18 lines
236 B
Systemverilog
module test (
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input clk, a
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);
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reg [7:0] counter = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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end
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always @(posedge clk) begin
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if (counter == 3) begin
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assert(a);
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assert(!a);
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assert(0);
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end
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end
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endmodule
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