mirror of
https://github.com/YosysHQ/sby.git
synced 2025-04-07 14:45:18 +00:00
2d3d96478a
This also changes the test Makefile to run `.check.py` files after running the corresponding `.sby` file to allow more precise testing of the keep going feature.
23 lines
360 B
Systemverilog
23 lines
360 B
Systemverilog
module test (
|
|
input clk, a
|
|
);
|
|
reg [7:0] counter = 0;
|
|
|
|
always @(posedge clk) begin
|
|
counter <= counter + 1;
|
|
end
|
|
|
|
always @(posedge clk) begin
|
|
assert(0);
|
|
if (counter == 3 || counter == 7) begin
|
|
assert(a); // step 3,7
|
|
end
|
|
if (counter == 5) begin
|
|
assert(a); // step 5
|
|
end
|
|
if (counter == 7) begin
|
|
assert(a); // step 7
|
|
end
|
|
end
|
|
endmodule
|