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Organize tests into subdirectories and use a new makefile that scans .sby files and allows selecting tests by mode, engine, solver and/or subdirectory. Automatically skips tests that use engines/solvers that are not found in the PATH. See `cd tests; make help` for a description of supported make targets.
74 lines
1.9 KiB
Verilog
74 lines
1.9 KiB
Verilog
module prv32fmcmp (
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input clock,
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input resetn,
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output mem_valid_a, mem_valid_b,
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output mem_instr_a, mem_instr_b,
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input mem_ready_a, mem_ready_b,
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output [31:0] mem_addr_a, mem_addr_b,
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output [31:0] mem_wdata_a, mem_wdata_b,
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output [ 3:0] mem_wstrb_a, mem_wstrb_b,
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input [31:0] mem_rdata_a, mem_rdata_b
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);
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picorv32 #(
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.REGS_INIT_ZERO(1),
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.COMPRESSED_ISA(1)
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) prv32_a (
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.clk (clock ),
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.resetn (resetn ),
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.mem_valid (mem_valid_a),
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.mem_instr (mem_instr_a),
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.mem_ready (mem_ready_a),
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.mem_addr (mem_addr_a ),
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.mem_wdata (mem_wdata_a),
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.mem_wstrb (mem_wstrb_a),
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.mem_rdata (mem_rdata_a)
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);
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picorv32 #(
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.REGS_INIT_ZERO(1),
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.COMPRESSED_ISA(1)
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) prv32_b (
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.clk (clock ),
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.resetn (resetn ),
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.mem_valid (mem_valid_b),
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.mem_instr (mem_instr_b),
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.mem_ready (mem_ready_b),
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.mem_addr (mem_addr_b ),
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.mem_wdata (mem_wdata_b),
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.mem_wstrb (mem_wstrb_b),
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.mem_rdata (mem_rdata_b)
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);
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reg [31:0] rom [0:255];
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integer mem_access_cnt_a = 0;
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integer mem_access_cnt_b = 0;
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always @* begin
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assume(resetn == !$initstate);
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if (resetn) begin
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// only consider programs without data memory read/write
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if (mem_valid_a) assume(mem_instr_a);
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if (mem_valid_b) assume(mem_instr_b);
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// when the access cnt matches, the addresses must match
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if (mem_valid_a && mem_valid_b && mem_access_cnt_a == mem_access_cnt_b) begin
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assert(mem_addr_a == mem_addr_b);
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end
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// hook up to memory
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assume(mem_rdata_a == rom[mem_addr_a[9:2]]);
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assume(mem_rdata_b == rom[mem_addr_b[9:2]]);
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end
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// it will pass when this is enabled
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//assume(mem_ready_a == mem_ready_b);
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end
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always @(posedge clock) begin
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mem_access_cnt_a <= mem_access_cnt_a + (resetn && mem_valid_a && mem_ready_a);
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mem_access_cnt_b <= mem_access_cnt_b + (resetn && mem_valid_b && mem_ready_b);
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end
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endmodule
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