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40 lines
748 B
Plaintext
40 lines
748 B
Plaintext
[options]
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mode bmc
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[engines]
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smtbmc boolector
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[script]
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read_verilog -formal ff_xinit_opt.sv
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prep -flatten -top top
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opt -fast -keepdc
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[file ff_xinit_opt.sv]
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module top(
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input clk,
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input [7:0] d
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);
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(* keep *)
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wire [7:0] some_const = $anyconst;
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wire [7:0] q1;
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wire [7:0] q2;
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ff ff1(.clk(clk), .d(q1), .q(q1));
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ff ff2(.clk(1'b0), .d(d), .q(q2));
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initial assume (some_const == q1);
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initial assume (some_const == q2);
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initial assume (q1 != 0);
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initial assume (q2 != 0);
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always @(posedge clk) assert(some_const == q1);
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always @(posedge clk) assert(some_const == q2);
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endmodule
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module ff(input clk, input [7:0] d, (* keep *) output reg [7:0] q);
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always @(posedge clk) q <= d;
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endmodule
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