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24 lines
373 B
Systemverilog
24 lines
373 B
Systemverilog
module test (
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input clk, a
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);
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reg [7:0] counter = 0;
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always @(posedge clk) begin
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counter <= counter + 1;
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end
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always @(posedge clk) begin
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assert(0);
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if (counter == 3 || counter == 7) begin
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assert(a); // step 3,7
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end
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if (counter == 5) begin
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assert(a); // step 5
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end
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if (counter == 7) begin
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assert(a); // step 7
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end
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assert(1);
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end
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endmodule
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