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27 lines
602 B
Systemverilog
27 lines
602 B
Systemverilog
module primegen;
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(* anyconst *) reg [31:0] prime;
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(* allconst *) reg [15:0] factor;
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always @* begin
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if (1 < factor && factor < prime)
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assume ((prime % factor) != 0);
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assume (prime > 1000000000);
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cover (1);
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end
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endmodule
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module primes;
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parameter [8:0] offset = 500;
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(* anyconst *) reg [8:0] prime1;
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wire [9:0] prime2 = prime1 + offset;
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(* allconst *) reg [4:0] factor;
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always @* begin
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if (1 < factor && factor < prime1)
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assume ((prime1 % factor) != 0);
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if (1 < factor && factor < prime2)
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assume ((prime2 % factor) != 0);
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assume (1 < prime1);
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cover (1);
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end
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endmodule
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