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sby/sbysrc/demo1.sby
Claire Wolf 494f84b0ab Include verilog source files for demo1.sby
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-07-21 13:01:36 +02:00

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[options]
mode bmc
depth 10
wait on
[engines]
smtbmc yices
smtbmc boolector -ack
smtbmc --nomem z3
abc bmc3
[script]
read_verilog -formal -norestrict -assume-asserts picorv32.v
read_verilog -formal axicheck.v
prep -top testbench
[files]
picorv32.v ../extern/picorv32.v
axicheck.v ../extern/axicheck.v