Jannis Harder 6d3b5aa960 Unified trace generation using yosys's sim across all engines ... Currently opt-in using the `fst` or `vcd_sim` options.		2023-01-10 18:42:26 +01:00
..
2props1trace.sby
allconst.sby	Test designs using $allconst	2022-06-03 16:55:06 +02:00
blackbox.sby	switch to using hierarchy -smtcheck for smtlib2 solvers, allowing smtlib2_module modules.	2022-06-22 21:17:29 -07:00
bmc_len.sby	aiger: check supported modes and aigbmc fixes	2022-06-14 17:41:06 +02:00
both_ex.sby
both_ex.v
btor_meminit.sby	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
cover.sby
cover.sv
cover_fail.sby
cover_unreachable.sby	Unified trace generation using yosys's sim across all engines	2023-01-10 18:42:26 +01:00
demo.sby	Test that cvc4 and cvc5 can be used	2022-06-08 13:33:12 +02:00
demo.sv
floor_divmod.sby	add depth 1	2022-05-25 03:35:21 -07:00
Makefile
memory.sby
memory.sv
mixed.sby
mixed.v	Refactor flow to use a common prep model	2022-08-05 16:31:15 +02:00
multi_assert.sby
no_vcd.sby	Add vcd option to make VCD writing optional	2022-09-05 15:42:24 +02:00
preunsat.sby
prv32fmcmp.sby
prv32fmcmp.v
redxor.sby
redxor.v
smtlib2_module.sby	switch to using hierarchy -smtcheck for smtlib2 solvers, allowing smtlib2_module modules.	2022-06-22 21:17:29 -07:00
stopfirst.sby
submod_props.sby