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19 lines
294 B
Systemverilog
19 lines
294 B
Systemverilog
module demo (
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input clk,
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output reg [5:0] counter
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);
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initial counter = 0;
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always @(posedge clk) begin
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if (counter == 15)
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counter <= 0;
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else
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counter <= counter + 1;
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end
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`ifdef FORMAL
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always @(posedge clk) begin
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assert (counter < 32);
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end
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`endif
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endmodule
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