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107 lines
2.9 KiB
ReStructuredText
107 lines
2.9 KiB
ReStructuredText
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Getting Started
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===============
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Installing
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----------
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TBD
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Until I find the time to write this section this links must be sufficient:
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* Yosys: http://www.clifford.at/yosys/
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* SymbiYosys: https://github.com/cliffordwolf/SymbiYosys
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* Z3: https://github.com/Z3Prover/z3
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* Yices2: http://yices.csl.sri.com/
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* Boolector: http://fmv.jku.at/boolector/
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* super_prove: http://downloads.bvsrc.org/super_prove/
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(Yosys, SymbiYosys, and Z3 are non-optional. The other packages are only
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required for some engine configurations.)
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First step: A simple BMC example
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--------------------------------
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Here is a simple example design with a safety property (assertion).
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.. code-block:: systemverilog
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module demo (
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input clk,
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output [5:0] counter
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);
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reg [5:0] counter = 0;
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always @(posedge clk) begin
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if (counter == 15)
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counter <= 0;
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else
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counter <= counter + 1;
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end
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assert property (counter < 32);
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endmodule
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The property in this example is true. We'd like to verify this using a bounded
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model check (BMC) that is 100 cycles deep.
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SymbiYosys is controlled by ``.sby`` files. The following file can be used to
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configure SymbiYosys to run a BMC for 100 cycles on the design:
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.. code-block:: text
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[options]
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mode bmc
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depth 100
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[engines]
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smtbmc
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[script]
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read_verilog -formal demo.v
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prep -top demo
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[files]
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demo.v
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Simply create a text file ``demo.v`` with the example design and another text
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file ``demo.sby`` with the SymbiYosys configuration. Then run::
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sby demo.sby
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This will run a bounded model check for 100 cycles. The last few lines of the
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output should look something like this:
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.. code-block:: text
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SBY [demo] engine_0: ## 0 0:00:00 Checking asserts in step 96..
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SBY [demo] engine_0: ## 0 0:00:00 Checking asserts in step 97..
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SBY [demo] engine_0: ## 0 0:00:00 Checking asserts in step 98..
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SBY [demo] engine_0: ## 0 0:00:00 Checking asserts in step 99..
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SBY [demo] engine_0: ## 0 0:00:00 Status: PASSED
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SBY [demo] engine_0: Status returned by engine: PASS
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SBY [demo] engine_0: finished (returncode=0)
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SBY [demo] summary: Elapsed clock time [H:MM:SS (secs)]: 0:00:00 (0)
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SBY [demo] summary: Elapsed process time [H:MM:SS (secs)]: 0:00:00 (0)
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SBY [demo] summary: engine_0 (smtbmc) returned PASS
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SBY [demo] DONE (PASS)
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This will also create a ``demo/`` directory tree with all relevant information,
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such as a copy of the design source, various log files, and trace data in case
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the proof fails.
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(Use ``sby -f demo.sby`` to re-run the proof. Without ``-f`` the command will
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fail because the output directory ``demo/`` already exists.)
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Time for a simple exercise: Modify the design so that the property is false
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and the offending state is reachable within 100 cycles. Re-run ``sby`` with
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the modified design and see if the proof now fails.
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Going beyond bounded model checks
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---------------------------------
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TBD
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