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22 lines
383 B
Plaintext
22 lines
383 B
Plaintext
[options]
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mode prove
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wait on
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[engines]
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aiger suprove
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aiger avy
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[script]
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read_verilog -formal demo.v
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prep -top top
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[file demo.v]
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module top(input clk, input up, down);
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reg [4:0] counter = 0;
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always @(posedge clk) begin
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if (up && counter != 10) counter <= counter + 1;
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if (down && counter != 0) counter <= counter - 1;
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end
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assert property (counter != 15);
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endmodule
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